DOCSLIB.ORG

Automating the Application Data Placement in Hybrid Memory Systems

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Automating the Application Data Placement in Hybrid Memory Systems Automating the Application Data Placement in Hybrid Memory Systems Harald Servat∗, Antonio J. Pena˜ y, German´ Llorty, Estanislao Mercadaly, Hans-Christian Hoppe∗ and Jesus´ Labartayz ∗Intel Corporation yBarcelona Supercomputing Center (BSC) zUniversitat Politecnica` de Catalunya (UPC) Abstract—Multi-tiered memory systems, such as those based Tools like EVOP [2], ADAMANT [3], MACPO [4] and on Intel R Xeon PhiTMprocessors, are equipped with several mem- Intel R Advisor [5] solely rely on instruction-level instrumen- ory tiers with different characteristics including, among others, tation to monitor the data object allocation and their respective capacity, access latency, bandwidth, energy consumption, and volatility. The proper distribution of the application data objects accesses to advise the user about the most accessed variables into the available memory layers is key to shorten the time– and even their access patterns. These metrics are valuable to to–solution, but the way developers and end-users determine understand the application behavior, but the imposed over- the most appropriate memory tier to place the application data head limit their relevance because they alter the application objects has not been properly addressed to date. performance and generate a daunting amount of data for in- In this paper we present a novel methodology to build an extensible framework to automatically identify and place the production application runs, leading to long analysis times. application’s most relevant memory objects into the Intel Xeon To overcome these limitations, processor manufacturers Phi fast on-package memory. Our proposal works on top of in- have augmented their performance monitoring unit with sam- production binaries by first exploring the application behavior pling mechanisms to provide rich information, including and then substituting the dynamic memory allocations. This the referenced memory address. Precise-Event Based Sam- makes this proposal valuable even for end-users who do not have the possibility of modifying the application source code. We pling (PEBS) is the implementation of such a feature in demonstrate the value of a framework based in our methodology recent Intel processors [6]. Performance analysis tools such for several relevant HPC applications using different allocation as HPCToolkit [7], MemAxes [8], Extrae [9], and Intel R strategies to help end-users improve performance with minimal VtuneTMAmplifier [10] use a hybrid approach combining intervention. The results of our evaluation reveal that our instrumentation to track data allocation and PEBS to mon- proposal is able to identify the key objects to be promoted into fast on-package memory in order to optimize performance, itor the application data references. This approach enables leading to even surpassing hardware-based solutions. exploring in-production executions with a reduced overhead at Index Terms—heterogeneous memory, hybrid memory, high- the cost of providing statistical approximations, even though bandwidth memory, performance analysis, PEBS, sampling, in- approximations for long runs resemble the actual results. strumentation These tools typically identify the data structures that are associated to metrics like high-latency loads or high number I. INTRODUCTION of cache misses but leave the tedious work of substituting Hybrid memory systems (HM)1 accommodate memories the memory allocation calls to the application developer. This featuring different characteristics such as capacity, bandwidth, paper advances the current state of the art by introducing a latency, energy consumption, or volatility. A recent example novel framework design to help end-users, application devel- of an HM-processor is the Intel R Xeon PhiTM, containing opers and processor architects understand the usage of HM two memory systems: DDR and on-package Multi-Channel systems, and to automatically promote the critical data to the DRAM (MCDRAM) [1]. While HM systems present oppor- appropriate memory layer. The framework design consists of tunities in different fields, the efficient usage of these systems four stages: (1) low-overhead data collection using hardware- requires prior application knowledge because developers need based sampling mechanisms; (2) attribution of a cost based to determine which data objects to place in which of the on Last-Level Cache (LLC) misses to each data object; (3) available memory tiers. A common objective is to shorten the distribution of data objects for a given memory configuration; application time–to–solution and this translates into placing and (4) re-execution of the application binary automatically the appropriate data objects on the fastest memory. However, promoting the different data objects to the proper memory tier. fast memory is a scarce resource and the application working The two first stages rely on an unmodified open-source tools, set may not fit. Consequently, it is important to characterize the while the third stage is a derivative from an already existing application behavior to identify the (critical) data that benefits tool and the fourth stage relies newly developed interposition the most from being hosted into fast memory and, if not library. sufficient, keep the non-critical data away in slower memory. The contributions of this paper include: 1) the design of an extensible framework to automatically 1Also known as heterogeneous or multi-tiered memory systems. distribute the data objects of in-production binaries in 1 HM systems targeting performance, and implementing references to a memory simulator that calculates statistics it for Intel Xeon Phi processors; such as cache hits and misses for a given cache organization. 2) an exploration of several strategies to help determine SLO [13] suggests locality optimizations by analyzing the which application variables to place on which memory application reuse paths to find the root causes of poor data tier in HM systems; locality. This tool extends the GCC compiler2 to capture the 3) the evaluation of the proposed distribution approaches application’s memory accesses, function calls and loops to on a set of well-known benchmarks using the presented track data reuses, and then it analyzes the reused paths to framework methodology, including a comparison with suggest code loop transformations. MACPO captures memory already existing hardware and software solutions; and traces and computes metrics for the memory access behavior 4) the proposal of a novel metric to report the efficient use of source-level data structures. The tool uses PerfExpert [14] to of the fast on-package memory by applications. identify code regions with memory-related inefficiencies, then This paper follows contextualizing the work we present with it employs the LLVM compiler3 to instrument the memory already existing state–of–the–art tools and methodologies in references, and finally it calculates several reuse factors and Section II. Section III describes in detail the framework and the number of data streams in a loop nest. Intel Advisor is a its components. In Section IV we put the framework in use performance analysis tool that focuses on the thread and vector through several benchmarks and applications while analyzing performance, and it also explores the memory locality charac- the obtained results. Finally, Section V draws conclusions and teristics of a user-given code. The tool relies on PIN [15] to discusses possible future research directions. instrument binaries at instruction-level allowing correlation of the instructions and the memory access patterns. Tareador [16] II. RELATED WORK is a tool that estimates the amount of parallelism that can There exist several alternatives for taking advantage of the be extracted from a serial application using a task-based MCDRAM on Intel Xeon Phi processors. The user can benefit data-flow programming model. The tool employs dynamic from the fast on-package memory transparently by using it as instrumentation to monitor the memory accesses of delimited a direct-mapped LLC. However, if MCDRAM is configured regions of code to determine whether they can simultaneously in flat mode (i.e. sits on a different part of the address space), run without data race conditions, and then it simulates the then the easiest alternative for the user is to rely on the application execution based on this outcome. EVOP is an numactl command to place as much application data as emulator-based data-oriented profiling tool to analyze actual possible into the fast memory. Another alternative is to use program executions in a system equipped only with a DRAM- the autohbw library provided by the memkind package [11]. based memory [17]. EVOP uses dynamic instrumentation This library is injected into the application before process to monitor the memory references in order to detect which execution and it forwards dynamic allocations into MCDRAM memory structures are the most referenced and then estimate if the requested memory is within a user-given size range the CPU stall cycles incurred by the different memory objects (as long as it fits). The most tedious situation requires the to decide their optimal object placement in a heterogeneous developer to learn (somehow) about the application behavior memory system by means of the dmem advisor tool [2]. with respect to main memory accesses and manually change ADAMANT uses the PEBIL instrumentation package [18] the memory allocations so that they reside on MCDRAM using and includes tools to characterize application data objects, memkind. Even
Load more

Recommended publications
  • インテル® Parallel Studio XE 2020 リリースノート
    インテル® Parallel Studio XE 2020 2019 年 12 月 5 日 内容 1 概要 ..................................................................................................................................................... 2 2 製品の内容 ........................................................................................................................................ 3 2.1 インテルが提供するデバッグ・ソリューションの追加情報 ..................................................... 5 2.2 Microsoft* Visual Studio* Shell の提供終了 ........................................................................ 5 2.3 インテル® Software Manager .................................................................................................... 5 2.4 サポートするバージョンとサポートしないバージョン ............................................................ 5 3 新機能 ................................................................................................................................................ 6 3.1 インテル® Xeon Phi™ 製品ファミリーのアップデート ......................................................... 12 4 動作環境 .......................................................................................................................................... 13 4.1 プロセッサーの要件 ...................................................................................................................... 13 4.2 ディスク空き容量の要件 .............................................................................................................. 13 4.3 オペレーティング・システムの要件 ............................................................................................. 13
    [Show full text]
  • Introduction to High Performance Computing
    Introduction to High Performance Computing Shaohao Chen Research Computing Services (RCS) Boston University Outline • What is HPC? Why computer cluster? • Basic structure of a computer cluster • Computer performance and the top 500 list • HPC for scientific research and parallel computing • National-wide HPC resources: XSEDE • BU SCC and RCS tutorials What is HPC? • High Performance Computing (HPC) refers to the practice of aggregating computing power in order to solve large problems in science, engineering, or business. • Purpose of HPC: accelerates computer programs, and thus accelerates work process. • Computer cluster: A set of connected computers that work together. They can be viewed as a single system. • Similar terminologies: supercomputing, parallel computing. • Parallel computing: many computations are carried out simultaneously, typically computed on a computer cluster. • Related terminologies: grid computing, cloud computing. Computing power of a single CPU chip • Moore‘s law is the observation that the computing power of CPU doubles approximately every two years. • Nowadays the multi-core technique is the key to keep up with Moore's law. Why computer cluster? • Drawbacks of increasing CPU clock frequency: --- Electric power consumption is proportional to the cubic of CPU clock frequency (ν3). --- Generates more heat. • A drawback of increasing the number of cores within one CPU chip: --- Difficult for heat dissipation. • Computer cluster: connect many computers with high- speed networks. • Currently computer cluster is the best solution to scale up computer power. • Consequently software/programs need to be designed in the manner of parallel computing. Basic structure of a computer cluster • Cluster – a collection of many computers/nodes. • Rack – a closet to hold a bunch of nodes.
    [Show full text]
  • Applying the Roofline Performance Model to the Intel Xeon Phi Knights Landing Processor
    Applying the Roofline Performance Model to the Intel Xeon Phi Knights Landing Processor Douglas Doerfler, Jack Deslippe, Samuel Williams, Leonid Oliker, Brandon Cook, Thorsten Kurth, Mathieu Lobet, Tareq Malas, Jean-Luc Vay, and Henri Vincenti Lawrence Berkeley National Laboratory {dwdoerf, jrdeslippe, swwilliams, loliker, bgcook, tkurth, mlobet, tmalas, jlvay, hvincenti}@lbl.gov Abstract The Roofline Performance Model is a visually intuitive method used to bound the sustained peak floating-point performance of any given arithmetic kernel on any given processor architecture. In the Roofline, performance is nominally measured in floating-point operations per second as a function of arithmetic intensity (operations per byte of data). In this study we determine the Roofline for the Intel Knights Landing (KNL) processor, determining the sustained peak memory bandwidth and floating-point performance for all levels of the memory hierarchy, in all the different KNL cluster modes. We then determine arithmetic intensity and performance for a suite of application kernels being targeted for the KNL based supercomputer Cori, and make comparisons to current Intel Xeon processors. Cori is the National Energy Research Scientific Computing Center’s (NERSC) next generation supercomputer. Scheduled for deployment mid-2016, it will be one of the earliest and largest KNL deployments in the world. 1 Introduction Moving an application to a new architecture is a challenge, not only in porting of the code, but in tuning and extracting maximum performance. This is especially true with the introduction of the latest manycore and GPU-accelerated architec- tures, as they expose much finer levels of parallelism that can be a challenge for applications to exploit in their current form.
    [Show full text]
  • Introduction to Intel Xeon Phi (“Knights Landing”) on Cori
    Introduction to Intel Xeon Phi (“Knights Landing”) on Cori" Brandon Cook! Brian Friesen" 2017 June 9 - 1 - Knights Landing is here!" • KNL nodes installed in Cori in 2016 • “Pre-produc=on” for ~ 1 year – No charge for using KNL nodes – Limited access (un7l now!) – Intermi=ent down7me – Frequent so@ware changes • KNL nodes on Cori will soon enter produc=on – Charging Begins 2017 July 1 - 2 - Knights Landing overview" Knights Landing: Next Intel® Xeon Phi™ Processor Intel® Many-Core Processor targeted for HPC and Supercomputing First self-boot Intel® Xeon Phi™ processor that is binary compatible with main line IA. Boots standard OS. Significant improvement in scalar and vector performance Integration of Memory on package: innovative memory architecture for high bandwidth and high capacity Integration of Fabric on package Three products KNL Self-Boot KNL Self-Boot w/ Fabric KNL Card (Baseline) (Fabric Integrated) (PCIe-Card) Potential future options subject to change without notice. All timeframes, features, products and dates are preliminary forecasts and subject to change without further notification. - 3 - Knights Landing overview TILE CHA 2 VPU 2 VPU Knights Landing Overview 1MB L2 Core Core 2 x16 X4 MCDRAM MCDRAM 1 x4 DMI MCDRAM MCDRAM Chip: 36 Tiles interconnected by 2D Mesh Tile: 2 Cores + 2 VPU/core + 1 MB L2 EDC EDC PCIe D EDC EDC M Gen 3 3 I 3 Memory: MCDRAM: 16 GB on-package; High BW D Tile D D D DDR4: 6 channels @ 2400 up to 384GB R R 4 36 Tiles 4 IO: 36 lanes PCIe Gen3. 4 lanes of DMI for chipset C DDR MC connected by DDR MC C Node: 1-Socket only H H A 2D Mesh A Fabric: Omni-Path on-package (not shown) N Interconnect N N N E E L L Vector Peak Perf: 3+TF DP and 6+TF SP Flops S S Scalar Perf: ~3x over Knights Corner EDC EDC misc EDC EDC Streams Triad (GB/s): MCDRAM : 400+; DDR: 90+ Source Intel: All products, computer systems, dates and figures specified are preliminary based on current expectations, and are subject to change without notice.
    [Show full text]
  • Intel® Parallel Studio XE 2020 Update 2 Release Notes
    Intel® Parallel StudIo Xe 2020 uPdate 2 15 July 2020 Contents 1 Introduction ................................................................................................................................................... 2 2 Product Contents ......................................................................................................................................... 3 2.1 Additional Information for Intel-provided Debug Solutions ..................................................... 4 2.2 Microsoft Visual Studio Shell Deprecation ....................................................................................... 4 2.3 Intel® Software Manager ........................................................................................................................... 5 2.4 Supported and Unsupported Versions .............................................................................................. 5 3 What’s New ..................................................................................................................................................... 5 3.1 Intel® Xeon Phi™ Product Family Updates ...................................................................................... 12 4 System Requirements ............................................................................................................................. 13 4.1 Processor Requirements........................................................................................................................ 13 4.2 Disk Space Requirements .....................................................................................................................
    [Show full text]
  • Effectively Using NERSC
    Effectively Using NERSC Richard Gerber Senior Science Advisor HPC Department Head (Acting) NERSC: the Mission HPC Facility for DOE Office of Science Research Largest funder of physical science research in U.S. Bio Energy, Environment Computing Materials, Chemistry, Geophysics Particle Physics, Astrophysics Nuclear Physics Fusion Energy, Plasma Physics 6,000 users, 48 states, 40 countries, universities & national labs Current Production Systems Edison 5,560 Ivy Bridge Nodes / 24 cores/node 133 K cores, 64 GB memory/node Cray XC30 / Aries Dragonfly interconnect 6 PB Lustre Cray Sonexion scratch FS Cori Phase 1 1,630 Haswell Nodes / 32 cores/node 52 K cores, 128 GB memory/node Cray XC40 / Aries Dragonfly interconnect 24 PB Lustre Cray Sonexion scratch FS 1.5 PB Burst Buffer 3 Cori Phase 2 – Being installed now! Cray XC40 system with 9,300 Intel Data Intensive Science Support Knights Landing compute nodes 10 Haswell processor cabinets (Phase 1) 68 cores / 96 GB DRAM / 16 GB HBM NVRAM Burst Buffer 1.5 PB, 1.5 TB/sec Support the entire Office of Science 30 PB of disk, >700 GB/sec I/O bandwidth research community Integrate with Cori Phase 1 on Aries Begin to transition workload to energy network for data / simulation / analysis on one system efficient architectures 4 NERSC Allocation of Computing Time NERSC hours in 300 millions DOE Mission Science 80% 300 Distributed by DOE SC program managers ALCC 10% Competitive awards run by DOE ASCR 2,400 Directors Discretionary 10% Strategic awards from NERSC 5 NERSC has ~100% utilization Important to get support PI Allocation (Hrs) Program and allocation from DOE program manager (L.
    [Show full text]
  • Intel® Xeon Phi™ Processor: Your Path to Deeper Insight
    PRODUCT BRIEF Intel® Xeon Phi™ Processor: Your Path to Deeper Insight Intel Inside®. Breakthroughs Outside. Unlock deeper insights to solve your biggest challenges faster with the Intel® Xeon Phi™ processor, a foundational element of Intel® Scalable System Framework (Intel® SSF) What if you could gain deeper insight to pursue new discoveries, drive business innovation or shape the future using advanced analytics? Breakthroughs in computational capability, data accessibility and algorithmic innovation are driving amazing new possibilities. One key to unlocking these deeper insights is the new Intel® Xeon Phi™ processor – Intel’s first processor to deliver the performance of an accelerator with the benefits of a standard host CPU. Designed to help solve your biggest challenges faster and with greater efficiency, the Intel® Xeon Phi™ processor enables machines to rapidly learn without being explicitly programmed, in addition to helping drive new breakthroughs using high performance modeling and simulation, visualization and data analytics. And beyond computation, as a foundational element of Intel® Scalable System Framework (Intel® SSF), the Intel® Xeon Phi™ processor is part of a solution that brings together key technologies for easy-to-deploy and high performance clusters. Solve Your Biggest Challenges Faster1 Designed from the ground up to eliminate bottlenecks, the Intel® Xeon Phi™ processor is Intel’s first bootable host processor specifically designed for highly parallel workloads, and the first to integrate both memory and fabric technologies. Featuring up to 72 powerful and efficient cores with ultra-wide vector capabilities (Intel® Advanced Vector Extensions or AVX-512), the Intel® Xeon Phi™ processor raises the bar for highly parallel computing.
    [Show full text]
  • HPC Software Cluster Solution
    Architetture innovative per il calcolo e l'analisi dati Marco Briscolini Workshop di CCR La Biodola, Maggio 16-20. 2016 2015 Lenovo All rights reserved. Agenda . Cooling the infrastructure . Managing the infrastructure . Software stack 2015 Lenovo 2 Target Segments - Key Requirements Data Center Cloud Computing Infrastructure Key Requirements: Key Requirements: • Low-bin processors (low • Mid-high bin EP cost) processors High Performance • Smaller memory (low • Lots of memory cost) Computing (>256GB/node) for • 1Gb Ethernet virtualization Key Requirements: • 2 Hot Swap • 1Gb / 10Gb Ethernet drives(reliability) • 1-2 SS drives for boot • High bin EP processors for maximum performance Virtual Data • High performing memory Desktop Analytics • Infiniband Key Requirements: • 4 HDD capacity Key Requirements: • Mid-high bin EP processors • GPU support • Lots of memory (> • Lots of memory (>256GB per 256GB per node) for node) virtualization • 1Gb / 10Gb Ethernet • GPU support • 1-2 SS drives for boot 3 A LOOK AT THE X86 MARKET BY USE . HPC is ~6.6 B$ growing 8% annually thru 2017 4 Some recent “HPC” EMEA Lenovo 2015 Client wins 5 This year wins and installations in Europe 1152 nx360M5 DWC 1512 nx360M5 BRW EDR 3600 Xeon KNL 252 nx360M5 nodes 392 nx360M5 nodes GPFS, GSS 10 PB IB FDR14, Fat Tree IB FDR14 3D Torus OPA GPFS, 150 TB, 3 GB/s GPFS 36 nx360M5 nodes 312 nx360M5 DWC 6 nx360M5 with GPU 1 x 3850X6 GPFS, IB FDR14, 2 IB FDR, GPFS GSS24 6 2 X 3 PFlops SuperMUC systems at LRZ Phase 1 and Phase 2 Phase 1 Ranked 20 and 21 in Top500 June 2015 • Fastest Computer in Europe on Top 500, June 2012 – 9324 Nodes with 2 Intel Sandy Bridge EP CPUs – HPL = 2.9 PetaFLOP/s – Infiniband FDR10 Interconnect – Large File Space for multiple purpose • 10 PetaByte File Space based on IBM GPFS with 200GigaByte/s I/O bw Phase 2 • Innovative Technology for Energy Effective .
    [Show full text]
  • Performance Optimization of Deep Learning Frameworks Caffe* and Tensorflow* for Xeon Phi Cluster
    Performance Optimization of Deep Learning Frameworks on Modern Intel Architectures ElMoustapha Ould-Ahmed-Vall, AG Ramesh, Vamsi Sripathi and Karthik Raman Representing the work of many at Intel Agenda • Op#mizaon maers on modern architectures • Intel’s recent Xeon and Xeon Phi products • Introduc#on to Deep Learning • Op#mizing DL frameworks on IA • Key challenges • Op#mizaon techniques • Performance data • DL scaling Moore’s Law Goes on! Increasing clock speeds -> more cores + wider SIMD (Hierarchical parallelism) Combined Amdahl’s Law for Vector Mul<cores* �������=(​1/​������↓���� +​1−​������↓���� /�������� )∗(​1/​������↓���� +​1−​������↓���� /������������ ) Goal: Reduce Serial Fraction and Reduce Scalar Fraction of Code Ideal Speedup: NumCores*VectorLength (requires zero scalar, zero serial work) Peak “Compute” Gflops/s Compute Bound Performance Most kernels of ML codes are compute bound i.e. raw FLOPS matter Peak “Compute” Gflops/s without SIMD Roofline Model Gflops/s = min (Peak Gflops/s, Stream BW * flops/byte) A+ainable Gflops/s Compute intensity (flops/byte) Overview of Current Generation of Intel Xeon and Xeon Phi Products Current Intel® Xeon PlaBorms 45nm Process 14nm Process Technology 32nm Process Technology 22nm Process Technology Technology Nehalem Westmere Sandy Bridge Ivy Bridge Haswell Broadwell NEW Intel® Intel NEW Intel Intel NEW Intel Intel Microarchitecture Microarchitecture Microarchitecture Microarchitecture Microarchitecture Microarchitecture (Nehalem) (Nehalem) (Sandy Bridge) (Sandy Bridge) (Haswell) (Haswell) TOCK
    [Show full text]
  • HPCG on Intel Xeon Phi 2Nd Generation, Knights Landing
    HPCG on Intel Xeon Phi 2nd Generation, Knights Landing Alexander Kleymenov and Jongsoo Park Intel Corporation SC16, HPCG BoF 1 Outline • KNL results • Our other work related to HPCG 2 ~47 GF/s per KNL ~10 GF/s per HSW 3 Single-Node KNL Perf. (GFLOP/s) 72c Xeon Phi 7290 51.3 (flat mode) 68c Xeon Phi 7250 49.4 (flat mode), 13.8 (DDR) 64c Xeon Phi 7210 46.7 (flat mode) Cache mode provides a similar performance (~3% drop) MCDRAM provides >3.5x performance than DDR Easier to use than KNC Less reliance on software prefetching 2 threads per core is enough to get the best performance Smaller gap between SpMV using CSR and SELLPACK for U of Florida Matrix Collection n=192 usually gives the best results. All results are measured with quad cluster mode and code from https://software.intel.com/en-us/articles/intel-mkl-benchmarks-suite 4 Multi-Node KNL Each node in flat/quad mode connected with Omni-Path fabric (OPA) 5 Outline • IA result updates • Our other work related to HPCG 6 Related Work (1) – Library MKL inspector-executor sparse BLAS routines https://software.intel.com/en-us/articles/intel-math-kernel-library- inspector-executor-sparse-blas-routines SpMP open source library (https://github.com/jspark1105/SpMP ) BFS/RCM reordering, task graph construction of SpTrSv and ILU, … Optimizing AMG in HYPRE library Included from HYPRE 2.11.0 7 Related Work (2) – Compiler Automating Wavefront Parallelization for Sparse Matrix Computations, Venkat et al., SC’16 12-core Xeon E5-2695 v2, ILU0 pre-conditioner, speedups include inspection overhead time 8 Related Work (3) – Script Language Sparso: Context-driven Optimizations of Sparse Linear Algebra, Rong et al., PACT’16, https://github.com/IntelLabs/Sparso 14-core Xeon E5-2697 v3, Julia with Sparso package 9 Notice and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS.
    [Show full text]
  • Knights Landing Intel® Xeon Phi™ CPU: Path to Parallelism With
    Knights Landing Intel® Xeon Phi™ CPU: Path to Parallelism with General Purpose Programming Avinash Sodani Knights Landing Chief Architect Senior Principal Engineer, Intel Corp. Legal INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice.
    [Show full text]
  • Coprocessors: Failures and Successes
    COPROCESSORS : FAILURES AND SUCCESSES APREPRINT Daniel Etiemble Paris Sud University, Computer Science Laboratory (LRI) 91405 Orsay - France [email protected] July 25, 2019 English version of the paper presented in the French Conference COMPAS 2019. ABSTRACT The appearance and disappearance of coprocessors by integration into the CPU, the success or failure of coprocessors are examined by summarizing their characteristics from the mainframes of the 1960s. The coprocessors most particularly reviewed are the IBM 360 and CDC-6600 I/O processors, the Intel 8087 math coprocessor, the Cell processor, the Intel Xeon Phi coprocessors, the GPUs, the FPGAs, and the coprocessors of manycores SW26010 and Pezy SC-2 used in high-ranked supercomputers in the TOP500 or Green500. The conditions for a coprocessor to be viable in the medium or long-term are defined. Keywords Coprocessor · 8087 · Cell · Xeon Phi · GPU 1 Introduction Since the early days of computers, coprocessors have been used to relieve the main processor (CPU) of certain “ancillary” tasks. These coprocessors have been or are being used for different tasks: • I/O coprocessors • Floating-point coprocessors • Graphic coprocessors arXiv:1907.06948v1 [cs.AR] 16 Jul 2019 • Coprocessors for accelerating computation The history of these coprocessors is diverse. Some have disappeared in the medium or short-term, following a technological breakthrough such as the invention of semiconductors, or the evolution of integrated circuit density. This is particularly the case of I/O coprocessors or floating-point coprocessors. Others like graphic coprocessors have a tumultuous history depending on their use for graphics or for high-performance computing or artificial intelligence.
    [Show full text]