The DRAM Story with Articles by Dennard, Itoh, Koyanagi, Sunami, Foss and Isaac Sscs Nlwinter08 1/8/08 10:37 AM Page 2

Total Page:16

File Type:pdf, Size:1020Kb

The DRAM Story with Articles by Dennard, Itoh, Koyanagi, Sunami, Foss and Isaac Sscs Nlwinter08 1/8/08 10:37 AM Page 2 sscs_NLwinter08 1/8/08 10:37 AM Page 1 SSCSSSSCSSSSCCSS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS Winter 2008 Vol. 13, No. 1 www.ieee.org/sscs-news The DRAM Story with articles by Dennard, Itoh, Koyanagi, Sunami, Foss and Isaac sscs_NLwinter08 1/8/08 10:37 AM Page 2 Editor’s Column elcome to The goal of each issue is to be a Dennard, Itoh, Sunami, Koyanagi, the Winter, self-contained resource with back- Isaac and Foss," discussing the evo- 2008, issue ground articles (that is, the 'original lution and current status of DRAM: W sources') and new articles by (1) "Revisting ‘Evolution of the of the Solid-State Cir- cuits Society News- experts who describe the current MOSFET Dynamic RAM-A Per- letter! We appreciate state of affairs in technology in view sonal View’" by Robert Dennard all of your feedback of the impact of the original papers (IBM); on our first year of and/or patents. (2) "The History of DRAM Circuit issues presenting The Technical This issue contains one Education Designs - At the Forefront of Impact of Moore's Law, The Impact Highlights article: DRAM Development" by Kiyoo of Dennard’s Scaling Theory, The "Turning Students On to Circuits," Itoh (Hitachi Ltd); 40th Anniversary of Amdahl's Law, by Yannis Tsividis of Columbia Uni- (3) "Stacked Capacitor DRAM Cell and Barrie Gilbert: The Gears of versity in New York City, NY. and Three-Dimensional Memo- Genius. Thank you for supporting The theme of the issue is "The ry" by Mitsumasa Koyanagi our efforts! DRAM Story with new articles by (Tohoku University); (4) "The Role of the Trench Capaci- tor in DRAM Innovation" by IEEE Solid-State Circuits Society AdCom Hideo Sunami (Hiroshima Uni- President: Elected AdCom Members at Large versity); Willy Sansen Terms to 31 Dec. 08: K. U. Leuven Wanda K. Gass (5) "The Remarkable Story of the Leuven, Belgium Ali Hajimiri DRAM Industry" by Randy Isaac, [email protected] Paul J. Hurst retired Vice President (IBM); Fax: +32 16 321975 Akira Matsuzawa (6) "DRAM - A Personal View" by R. Vice President: Ian Young C. Foss, retired Chairman of the Bernhard Boser Terms to 31 Dec. 09: University of California John J. Corcoran Board and Founder (MOSAID Berkeley, CA Kevin Kornegay Technologies Incorporated). Secretary: Hae-Seung (Harry) Lee In addition, the issue includes David A. Johns Thomas H. Lee reprints of two original papers and University of Toronto Jan Van der Spiegel Toronto, Ontario, Canada Terms to 31 Dec. 10: an original patent: Treasurer: Terri S. Fiez (1) R. H. Dennard, "Evolution of the Rakesh Kumar Tadahiro Kuroda MOSFET Dynamic RAM - A Per- Technology Connexions Bram Nauta sonal View," IEEE Transactions Poway, CA Jan Sevenhans on Electron Devices, vol. ED-31, Mehmet Soyuer Past President: No. 11, November, 1984, pp. Richard C. Jaeger Alabama Microelectronics Center Region 8 Representative: 1549-1555. Auburn University, AL Jan Sevenhans (2) R. H. Dennard, "Field-Effect Transistor Memory," Patent Other Representatives: Region 10 Representative: Representative to Sensors Council C.K. Wang 3,387,286, June 4, 1968. Darrin Young (3) K. Itoh, "In Quest of the Joy of Representative from CAS to SSCS Chairs of Standing Committees: Creation," in "Innovate the Domine Leenaerts Awards John J. Corcoran Representative to CAS from SSCS Future," 2005 Hitachi Hyoron Chapters Jan Van der Spiegel Un-Ku Moon Education C.K. Ken Yang Special Edition, pp. 34-39, Newsletter Editor: Meetings Bill Bidermann Hitachi Hyoronsha, Tokyo, Mary Y. Lanzerotti Membership Bruce Hecht Japan. IBM T.J. Watson Research Center Nominations Stephen H. Lewis [email protected] Publications Bernhard Boser Fax: +1 914 945 1358 Thank you for taking the time to For detailed contact information, see the Soci- read the SSCS News. We appreciate Associate Editor for Europe/Africa: ety e-News: www.ieee.org/portal/site/sscs Tony Harker all of your comments and feedback! ISLI Alba Centre Alba Campus Please send comments to Livingston Scotland EH54 7EG [email protected]. [email protected] For questions regarding Society business, contact the SSCS Executive Office. Contributions for the Spring 2008 issue of the Newsletter must be received by 8 February 2008 at the SSCS Executive Office. A complete media kit for advertisers is available at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS. Anne O’Neill, Executive Director Katherine Olstein, SSCS Administrator IEEE SSCS IEEE SSCS SSCS-West: 1500 SW 11th Ave. #1801 445 Hoes Lane, Portland, OR 97201 Piscataway, NJ 08854 Tel: +1 732 981 3400 Tel: +1 732 981 3410 Fax: +1 732 981 3401 Fax: +1 732 981 3401 Email: [email protected] Email: [email protected] 2 IEEE SSCS NEWS Winter 2008 sscs_NLwinter08 1/8/08 10:38 AM Page 3 Photo by Michiko Sunami. From left, Kiyoo Itoh, Hideo Sunami, Robert H. Dennard, Mitsumasa Koyanagi. Winter 2008 Volume 13, Number 1 Editor’s Column . .2 President’s Message . .4 Introducing Tony Harker, Associate Editor for Europe/Africa . .4 Letters to the Editor . .81 Corrections . .81 EDUCATION HIGHLIGHTS Turning Students On to Circuits, Yannis Tsividis . .6 TECHNICAL LITERATURE Revisiting “Evolution of the MOSFET Dynamic RAM – A Personal View,” Robert H. Dennard, reprinted from IEEE Transactions on Electron Devices, 31(11):1549-1555, November 1984 . .10 Field-Effect Transistor Memory (U.S. Patent No. 3,387,286) R. H. Dennard, 1968 . 17 The History of DRAM Circuit Designs – At the Forefront of DRAM Development, Kiyoo Itoh . .27 40 In Quest of the Joy of Creation, Kiyoo Itoh, reprinted from “Innovate the Future,” 2005 Hitachi Hyoron Special Edition . .31 The Stacked-Capacitor DRAM Cell and Three-Dimensional Memory, Mitsumasa Koyanagi, . .37 The Role of the Trench Capacitor in DRAM Innovation, Hideo Sunami . .42 The Remarkable Story of the DRAM Industry, Randy Isaac . .45 DRAM - A Personal View, R. C. Foss . .50 PEOPLE Asad Abidi Recognized for Work in RF-CMOS, Anne O’Neill . .57 R. Jacob Baker Honored at FIE Conference in October . .59 60 Van der Spiegel Acclaimed for Educational Innovation at IEEE EAB Meeting, Katherine Olstein . .60 Lanzerotti Applauded for Editorship of LEOS Newsletter . .62 SSCS Distinguished Lecturers Visit Athens and Varna . .62 Betty Prince Talks in Brazil . .64 New Senior Members . .64 Call for Fellow Nominations . .64 Tools: How to Write Readable Reports and Winning Proposals: Part 5, Peter and Cheryl Reimold . .65 62 CONFERENCES ISSCC 2008 to Focus on System Integration for Life and Style, Bill Bowhill . .66 Invitation from the ISSCC 2008 Technical Program Chair, Yoshiaki Hagihara . .68 VLSI-TSA and VLSI-DAT to Convene on 21-25 April in Hsinchu, Taiwan, Clara Wu . .69 Mm-Wave CMOS Applications: A Report from a CSICS Panel, Anne O’Neill . .70 CHAPTER NEWS SSCS-Germany Cosponsors SAMOS 2007, Holger Blume . .71 Sakurai and Razavi Visit SSCS-Seoul . .72 18th VLSI Design/CAD Symposium Cosponsored by IEEE Taipei & Tainan, C. C. Wang .72 75 Murmann and Razavi Visit SSCS-Taipei . .74 230 Papers Represent Intennational Community at ASICON 2007 . .75 Ian Galton Speaks on Fractional-N PPLS at SSCS-CAS/Atlanta, Gabriel Rincon-Mora . .76 Academia and Industry Interact in Ireland, Peter Kennedy . .78 Eight Technical Meetings in Fort Collins, Alvin Loke . .80 SSCS Far East Chapters Meet in Jeju, Korea . .81 NEWS Fiez, Kuroda, Nauta, Sevenhans & Soyuer Elected to AdCom . .82 CEDA Celebrates Second Anniversary . .85 81 Keep Your Professional Edge with Innovative Courses from IEEE . .88 Winter 2008 IEEE SSCS NEWS 3 sscs_NLwinter08 1/8/08 10:38 AM Page 4 President’s Message Richard C. Jaeger, Auburn University, [email protected] y two-year term as President exceptional efforts of Anne O’Neill, Sansen, Professor at KU Leuven, of the IEEE Solid-State Cir- Executive Director of the Society, Belgium, and Director of ESAT- cuits Society is nearly at an and Katherine Olstein, SSCS Admin- MICAS, becomes SSCS President. M istrator, who ensure smooth day-to- Professor Sansen is well known end. Thanks to the efforts of our membership, staff, and volunteers, day operation of the society and sup- internationally for his work in ana- the Society continues to strengthen port the President in ways that are log circuits and has been involved and expand its international activities. too many to enumerate. I thank Past with a wide range of SSCS activities Our conferences are attracting record President Steve Lewis for his always including Society Vice President and numbers of paper submissions and considered advice and insight, and I Chair of the 2002 ISSCC. attendees. The Journal of Solid-State also want to acknowledge the many Our Society will be in good hands Circuits sees strong submissions, and contributions of the members of our under Willy’s leadership. the Journal’s papers continue to have Administrative Committee and Sub- some of the highest download rates committees. Finally, the past two Richard C. Jaeger from IEEE Xplore. The number of years have seen outstanding devel- SSCS chapters and their activities are opment of the content of the at a record level. By the end of 2007, Newsletter through the hard work of SSCS financial reserves are also pro- Anne, Katherine and technical Editor, jected to be at a record level. Mary Lanzerotti. We all should be thankful for the As of January 1, 2008, Willy Outgoing President New Recruit to the SSCS Editorial Team Tony Harker, ISLI Alba Centre, [email protected] Hello Everyone support, supervise and deliver Mas- Such phenomena are not simply ter’s and PhD--level programmes at UK or Europe-wide. The constant As the newest recruit to the SSCS our campus in Livingston. drive for cost-effective develop- News Editorial team, I’d like to ISLI also has its own research ment, the quest for competitive introduce myself and give you some group specialising in integrated sili- margins, the need to maintain inno- ideas about the subject areas I will con MEMS, and a design group, vation, and the availability of a high- be addressing in future issues.
Recommended publications
  • 2129710142200313CSE312 Amir Adel Salah.Pdf
    استمارة جقييم الزسائل البحثيت ملقزر دراس ي اوﻻ : بياهاث جمل بمعزفت الطالب اسم الطالبـــــــــــ :أم ري عادل صﻻح عبد العظيم كلية : الهندســــه القسم: الحاسبات و النظم الفرقة/المستوى : الثالثة الشعبة : اسم المقرر :بنية الحاسب كود المقرر : CSE312 استاذ المقرر : د.طارق مراد جمعة ر ال رييد اﻻلكيون [email protected] : للطالب عنوان الرسالة البحثية : Modern Computers Memory ثاهيا: بياهاث جمل بمعزفت لجىت املمتحىيين هل الزسالت البحثيت املقدمت متشابت جشئيا او كليا ☐ وعم ☐ ﻻ فى حالت الاجابت بىعم ﻻ يتم جقييم املشزوع البحثى ويعتبر غير مجاس جقييم املشزوع البحثى م عىاصز التقييم الوسن التقييم اليسبى 1 الشكل العام للزسالت البحثيت 2 جحقق املتطلباث العلميت املطلوبت 3 يذكز املزاجع واملصادر العلميت 4 الصياغت اللغويت واسلوب الكتابت جيد هتيجت التقييم النهائى 100/ ☐ هاجح ☐ راسب جوقيع لجىت التقييم 1. .2 .3 .4 .5 جزفق هذه الاستمارة كغﻻف للمشزوع البحثى بعد استكمال البياهاث بمعزفت الطالب وعلى ان ﻻ جشيد عً صفحت واحدة Computers Memory Introduction At the beginning of the age of technology , A new term name called Memory has appeared .The memory is the most important thing in Computer . it is the main item which is responsible for data storage. The memories were designed by different ways and through multiple stages. At the beginning of memory manufacturing, the memory was produced by vacuum tubes from 1946 to 1959 .Vacuum tubes were basic components which was used to make the first generation of memories . Also the vacuum tubes used to make circuitry of CPU (Central Processing unit).In this generation ,the basic programming language was machine code which used in computers used vacuum tubes in the memory.
    [Show full text]
  • Random Access Memory (Ram)
    www.studymafia.org A Seminar report On RANDOM ACCESS MEMORY (RAM) Submitted in partial fulfillment of the requirement for the award of degree of Bachelor of Technology in Computer Science SUBMITTED TO: SUBMITTED BY: www.studymafia.org www.studymafia.org www.studymafia.org Acknowledgement I would like to thank respected Mr…….. and Mr. ……..for giving me such a wonderful opportunity to expand my knowledge for my own branch and giving me guidelines to present a seminar report. It helped me a lot to realize of what we study for. Secondly, I would like to thank my parents who patiently helped me as i went through my work and helped to modify and eliminate some of the irrelevant or un-necessary stuffs. Thirdly, I would like to thank my friends who helped me to make my work more organized and well-stacked till the end. Next, I would thank Microsoft for developing such a wonderful tool like MS Word. It helped my work a lot to remain error-free. Last but clearly not the least, I would thank The Almighty for giving me strength to complete my report on time. www.studymafia.org Preface I have made this report file on the topic RANDOM ACCESS MEMORY (RAM); I have tried my best to elucidate all the relevant detail to the topic to be included in the report. While in the beginning I have tried to give a general view about this topic. My efforts and wholehearted co-corporation of each and everyone has ended on a successful note. I express my sincere gratitude to …………..who assisting me throughout the preparation of this topic.
    [Show full text]
  • CS 152 Computer Architecture and Engineering Lecture 6
    CS 152 Computer Architecture and Engineering Lecture 6 - Memory Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory http://inst.eecs.berkeley.edu/~cs152 2/8/2016 CS152, Spring 2016 CS152 Administritivia . PS 1 due on Wednesday’s class . Lab 1 also due at the same time . Hand paper reports or email . PS 2 will be released on Wendesday . Lab 2 Wednesday or Thursday . Quiz next week Wednesday (17th) . Discussion section on Thursday to cover lab 2 and PS 1 2/8/2016 CS152, Spring 2016 2 Question of the Day . Can a cache worsen performance, latency, bandwidth compared to a system with DRAM and no caches? 2/8/2016 CS152, Spring 2016 3 Last time in Lecture 5 . Control hazards (branches, interrupts) are most difficult to handle as they change which instruction should be executed next . Branch delay slots make control hazard visible to software, but not portable to more advanced µarchs . Speculation commonly used to reduce effect of control hazards (predict sequential fetch, predict no exceptions, branch prediction) . Precise exceptions: stop cleanly on one instruction, all previous instructions completed, no following instructions have changed architectural state . To implement precise exceptions in pipeline, shift faulting instructions down pipeline to “commit” point, where exceptions are handled in program order 2/8/2016 CS152, Spring 2016 4 Early Read-Only Memory Technologies Punched cards, From early 1700s through Jaquard Loom, Punched paper tape, Babbage, and then IBM instruction
    [Show full text]
  • CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 5 – Memory
    CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 5 – Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs152 Last me in Lecture 4 § Handling excep>ons in pipelined machines by passing excep>ons down pipeline un>l instruc>ons cross commit point in order § Can use values before commit through bypass network § Pipeline hazards can be avoided through soDware techniques: scheduling, loop unrolling § Decoupled architectures use queues between “access” and “execute” pipelines to tolerate long memory latency § Regularizing all func>onal units to have same latency simplifies more complex pipeline design by avoiding structural hazards, can be expanded to in-order superscalar designs 2 Early Read-Only Memory Technologies Punched cards, From early 1700s through Jaquard Loom, Punched paper tape, Babbage, and then IBM instruc>on stream in Harvard Mk 1 Diode Matrix, EDSAC-2 µcode store IBM Balanced Capacitor ROS IBM Card Capacitor ROS 3 Early Read/Write Main Memory Technologies Babbage, 1800s: Digits stored on mechanical wheels Williams Tube, Manchester Mark 1, 1947 Mercury Delay Line, Univac 1, 1951 Also, regenerave capacitor memory on Atanasoff-Berry computer, and rotang magne>c drum memory on IBM 650 4 MIT Whirlwind Core Memory 5 Core Memory § Core memory was first large scale reliable main memory – invented by Forrester in late 40s/early 50s at MIT for Whirlwind project § Bits stored as magne>zaon
    [Show full text]
  • Computer Conservation Society
    Issue Number 76 Winter 2016/7 Computer Conservation Society Aims and objectives The Computer Conservation Society (CCS) is a co-operative venture between BCS, The Chartered Institute for IT; the Science Museum of London; and the Museum of Science and Industry (MSI) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of BCS. The aims of the CCS are: To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future, To develop awareness of the importance of historic computers, To develop expertise in the conservation and restoration of historic computers, To represent the interests of Computer Conservation Society members with other bodies, To promote the study of historic computers, their use and the history of the computer industry, To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by voluntary subscriptions from members, a grant from BCS, fees from corporate membership, donations and by the free use of the facilities of our founding museums. Some charges may be made for publications and attendance at seminars and conferences. There are a number of active projects on specific computer restorations and early computer technologies and software. Younger people are especially encouraged to take part in order to achieve skills transfer. The CCS also enjoys a close relationship with the National Museum of Computing.
    [Show full text]
  • Computer Oral History Collection, 1969-1973, 1977
    Computer Oral History Collection, 1969-1973, 1977 Interviewee: Robert Everett Interviewer: Henry S. Tropp Date: August 3, 1972 Repository: Archives Center, National Museum of American History EVERETT: We really got started getting into the control analyzer in '44, and at that time we were talking about an analog. There was a tendency, so I recall, for MIT to sort of be identified with analog computers, as opposed to Aiken's work at Harvard. I remember when the first announcements came out about Aiken's work, I talked to some people in the computing business at MIT, and they all said: "Oh, well that's just a big adding machine. The differential analyzer, that's the way to go." So, when we started working on it, we started working on an analog computer, and it presented very serious problems. And as I recall, it was in 1945 when we'd built amplifiers and servomechanisms and multipliers, and done a lot of planning work and so on, and had run into very serious difficulties in making a machine which would solve that elaborate set of equations. Jay would be a far better man to talk to about this, but he'd heard about the digital business, so he started. He got the thing converted from an analog machine to a digital machine in 1945. TROPP: So, it was kind of Jay's impetus and pressure that— EVERETT: Well, he--I guess I've forgotten now who it was that talked to him. But anyway, he got invited to a very select meeting about digital computers at MIT, and came convinced that the way to go was the digital computer, which was a very sound improvement on his part.
    [Show full text]
  • United States Court of Appeals for the Federal Circuit
    United States Court of Appeals for the Federal Circuit 01-1449, -1583, -1604, -1641, 02-1174, -1192 RAMBUS INC., Plaintiff-Appellant, v. INFINEON TECHNOLOGIES AG, INFINEON TECHNOLOGIES NORTH AMERICA CORP., and INFINEON TECHNOLOGIES HOLDING NORTH AMERICA INC., Defendants-Cross Appellants. Richard G. Taranto, Farr & Taranto, of Washington, DC, argued for plaintiff- appellant. With him on the brief were William K. West, Jr., Cecilia H. Gonzalez, Joseph P. Lavelle, and Celine T. Callahan, of Howrey Simon Arnold & White, LLP, of Washington, DC; Of counsel on the brief were Michael J. Schaengold, Patton Boggs LLP, of Washington, DC; Robert Kramer, Rambus, Inc., of Los Altos, California; Gregory P. Stone, Kristin Linsley Myles, Paul J. Watford, and Aaron M. May, Munger Tolles & Olson LLP, of Los Angeles, California. Of counsel was Craig Thomas Merritt, Christian & Barton, L.L.P, of Richmond, Virginia. Kenneth W. Starr, Kirkland & Ellis, of Washington, DC, argued for defendants-cross appellants. With him on the brief were Christopher Landau, Kannon K. Shanmugam, Grant M. Dixton. Of counsel on the brief were John M. Desmarais, Gregory S. Arovas, Thomas D. Pease, Meghan Frei, and Michael P. Stadnick, Kirkland & Ellis, of New York, New York. Of counsel was Brian C. Riopelle, McGuire Woods LLP, of Richmond, Virginia. Appealed from: United States District Court for the Eastern District of Virginia Judge Robert E. Payne United States Court of Appeals for the Federal Circuit 01-1449, -1583, -1604, -1641, 02-1174, -1192 RAMBUS INC., Plaintiff-Appellant, v. INFINEON TECHNOLOGIES AG, INFINEON TECHNOLOGIES NORTH AMERICA CORP., and INFINEON TECHNOLOGIES HOLDING NORTH AMERICA INC., Defendants-Cross Appellants.
    [Show full text]
  • Dynamic Rams from Asynchrounos to DDR4
    Dynamic RAMs From Asynchrounos to DDR4 PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sun, 10 Feb 2013 17:59:42 UTC Contents Articles Dynamic random-access memory 1 Synchronous dynamic random-access memory 14 DDR SDRAM 27 DDR2 SDRAM 33 DDR3 SDRAM 37 DDR4 SDRAM 43 References Article Sources and Contributors 48 Image Sources, Licenses and Contributors 49 Article Licenses License 50 Dynamic random-access memory 1 Dynamic random-access memory Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. The main memory (the "RAM") in personal computers is dynamic RAM (DRAM). It is the RAM in laptop and workstation computers as well as some of the RAM of video game consoles. The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities. Unlike flash memory, DRAM is volatile memory (cf. non-volatile memory), since it loses its data quickly when power is removed. The transistors and capacitors used are extremely small; billions can fit on a single memory chip.
    [Show full text]
  • Random Access Memory (RAM)
    P-2 Digital Design & Applications Semiconductor Memory (Unit-V) By: A K Verma SOS in Electronics & Photonics Pt. Ravishankar Shukla University, Raipur (C.G.) 1 What is Memory? • In computing, memory refers to the physical devices used to store programs (sequences of instructions) or data (e.g. program state information) on a temporary or permanent basis for use in a computer or other digital electronic device. The term primary memory is used for the information in physical systems which function at high-speed (i.e. RAM), as a distinction from secondary memory, which are physical devices for program and data storage which are slow to access but offer higher memory capacity. If needed, primary memory can be stored in secondary memory, through a memory management technique called "virtual memory“.[1] 2 History • In the early 1940s, memory technology mostly permitted a capacity of a few bytes. The first electronic programmable digital computer, the ENIAC, using thousands of octal-base radio vacuum tubes, could perform simple calculations involving 20 numbers of ten decimal digits which were held in the vacuum tube accumulators. • The next significant advance in computer memory came with acoustic delay line memory, developed by J. Presper Eckert in the early 1940s. Through the construction of a glass tube filled with mercury and plugged at each end with a quartz crystal, delay lines could store bits of information within the quartz and transfer it through sound waves propagating through mercury. Delay line memory would be limited to a capacity of up to a few hundred thousand bits to remain efficient.
    [Show full text]
  • Cache Memory  Cache Performance  Summary
    EITF20: Computer Architecture Part4.1.1: Cache - 1 Liang Liu [email protected] 1 Lund University / EITF20/ Liang Liu 2016 Outline Reiteration Memory hierarchy Cache memory Cache performance Summary 2 Lund University / EITF20/ Liang Liu 2016 Dynamic scheduling, speculation summary Tomasulo, CDB, ROB Register renaming Out-of-order execution, completion Tolerates unpredictable delays Compile for one pipeline - run effectively on another Allows speculation • multiple branches • in-order commit • precise exceptions • time, energy; recovery Significant increase in HW complexity 3 Lund University / EITF20/ Liang Liu 2016 CPU performance equation 4 Lund University / EITF20/ Liang Liu 2016 Summary pipeline - implementation 5 Lund University / EITF20/ Liang Liu 2016 Intel core-2 chip 7 Lund University / EITF20/ Liang Liu 2016 Intel core-2 chip 8 Lund University / EITF20/ Liang Liu 2016 News 9 Lund University / EITF20/ Liang Liu 2016 Fairchild 10 Lund University / EITF20/ Liang Liu 2016 Fairchild: History “Traitorous 8”: Gordon Moore, C. Sheldon Roberts, Eugene Kleiner, Robert Noyce, Victor Grinich, Julius Blank, Jean Hoerni, Jay Last 1956 Shockley Semiconductor 1957 Fairchild Semiconductor, silicon valley 1959 Kilby, TI and Noyce 1969 Jerry Sanders and First IC 7 other Fairchild colleagues 1968 Noyce, Moore, Rock 11 Lund University / EITF20/ Liang Liu 2016 Fairchild: History The 92 public companies that can be traced back to Fairchild are now worth about $2.1 trillion, which is more than the annual GDP of Canada, India, or Spain.
    [Show full text]
  • Comparative Study of Technology in Semiconductor Memories-A Review
    International Journal of Computer Applications (0975 – 8887) National Conference on Latest Initiatives& Innovations in Communication and Electronics (IICE 2016) Comparative Study of Technology in Semiconductor Memories-A Review Aman Kumar Bobbinpreet Kaur Student Assistant Professor Electronics and communication department Electronics and communication department Chandigarh University Chandigarh University Gharuan, India Gharuan, India ABSTRACT scattering and leakage current are the essential issues of quick In this paper we will present a review on the development of SRAM cells since this undesirable power leakage diminishes the semiconductor Memories through the most recent decade. battery life of adaptable devices. So it is required to have a Starting demands of low power devices is extending therefore; SRAM cell arrangement, having both low static and component this is the reason for scaling of CMOS advancement. In view of power leakage. Supply voltage is scaled to keep up the power the scaling, size of the chip diminishments and number of utilize within most distant point. Nevertheless, scaling of supply transistor in structure on chip increases. Generally the amount of voltage is confined by the prevalent need. Accordingly, the transistors utilized as a piece of chip to store data so, in future scaling of supply voltage just may not be satisfactory to keep up the need of low power memories is growing. The extended the power thickness within purpose of repression, which is enthusiasm for mobile phones has incited amazing examination required for power fragile applications. Circuit methodologies attempts in the setup and progression of low power circuits. and structure level strategies are moreover required close by Memories are the critical section in present day for automated supply voltage scaling to fulfill low power plot.
    [Show full text]
  • FORM 10-Q (Mark One) X QUARTERLY REPORT PURSUANT to SECTION 13 OR 15(D) of the SECURITIES EXCHANGE ACT of 1934
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-Q (Mark One) x QUARTERLY REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the quarterly period ended May 31, 2007 OR o TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number 1-10658 Micron Technology, Inc. (Exact name of registrant as specified in its charter) Delaware 75-1618004 (State or other jurisdiction of (IRS Employer incorporation or organization) Identification No.) 8000 S. Federal Way, Boise, Idaho 83716-9632 (Address of principal executive offices) (Zip Code) Registrant’s telephone number, including area code (208) 368-4000 Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes x No o Indicate by check mark whether the registrant is a large accelerated filer, an accelerated filer, or a non-accelerated filer. See definition of “accelerated filer and large accelerated filer” in Rule 12b-2 of the Exchange Act. (Check one): Large Accelerated Filer x Accelerated Filer o Non-Accelerated Filer o Indicate by check mark whether the registrant is a shell company (as defined in Rule 12b-2 of the Exchange Act). Yes o No x The number of outstanding shares of the registrant’s common stock as of July 3, 2007 was 756,870,527.
    [Show full text]