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Analysis and modeling methods for predicting functional robustness of integrated circuits during fast transient events Remi Bèges To cite this version: Remi Bèges. Analysis and modeling methods for predicting functional robustness of integrated circuits during fast transient events. Electromagnetism. Université Paul Sabatier - Toulouse III, 2017. English. NNT : 2017TOU30046. tel-01811079 HAL Id: tel-01811079 https://tel.archives-ouvertes.fr/tel-01811079 Submitted on 8 Jun 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSETHÈSE En vue de l’obtention du DOCTORAT DE L’UNIVERSITÉ DE TOULOUSE Délivré par : l’Université Toulouse 3 Paul Sabatier (UT3 Paul Sabatier) Thèse CIFRE présentée et soutenue le 2 juin 2017 par : Rémi Bèges Analysis and modeling methods for predicting functional robustness of integrated circuits during fast transient events JURY Geneviève Duchamp Professeur d’Université Membre du Jury Pascal Nouet Professeur d’Université Membre du Jury Alain Sauvage Docteur Membre du Jury Frederic Lafon Docteur Membre du Jury Fabrice Caignet Maitre de Conférence Membre du Jury Patrice Besse Docteur Membre du Jury Marise Bafleur Professeur d’Université Membre du Jury Patrick Austin Professeur d’Université Membre du Jury École doctorale et spécialité : GEET : Électromagnétisme et Systèmes Haute Fréquence Unité de Recherche : Laboratoire d’Analyse et d’Architecture des Systèmes (LAAS-CNRS - UPR 8001) Entreprise CIFRE : NXP Semiconductors Toulouse Directeurs de Thèse : Fabrice Caignet, Patrice Besse et Marise Bafleur Rapporteurs : Mme. Geneviève Duchamp et Mr. Pascal Nouet 2 Contents Introduction 7 1 Review of ESD testing and functional analysis 13 1.1 Context . 13 1.1.1 Electrostatic discharge . 13 1.1.2 Impact of ESD on electronic devices . 14 1.1.3 ESD protection . 17 1.2 Review of ESD testing . 20 1.2.1 Transmission Line Pulsing (TLP) . 20 1.2.2 ESD Gun (IEC 61000-4-2 / ISO 10605) . 24 1.2.3 ISO 7637-2 . 26 1.2.4 IEC 61000-4-4 . 30 1.2.5 IEC 62215 standard . 31 1.3 Review of soft-failure silicon-level investigation . 33 1.3.1 Case studies . 33 1.3.2 Observation methods . 36 1.3.3 Modeling methods of soft-failures for integrated circuits . 40 2 Development of investigation tools 43 2.1 System-level ESD modeling method . 43 2.1.1 Transmission line . 44 2.1.2 Passive devices . 50 2.1.3 ESD protections . 52 2.1.4 Common mode filter . 56 2.1.5 Ferrite beads . 56 2.2 Modeling method application to a TLP generator . 58 2.3 Development of a new injection tool . 62 2.3.1 Motivation . 62 2.3.2 Principle of operation of the TLP-HMM . 64 2.3.3 Validation of TLP-HMM models and standard compliance . 67 2.3.4 Conclusion, limitations and future improvements . 72 2.4 Near-field sensor post-processing . 72 2.4.1 Time-domain integration method . 72 3 2.4.2 Frequency-domain reconstruction method . 74 2.4.3 Conclusion on near-field post-processing . 77 2.5 Conclusion . 78 3 Study of soft-failures at silicon-level 81 3.1 Study of a real product . 81 3.1.1 Product description . 81 3.1.2 Functional failure study . 84 3.2 Test vehicle . 87 3.2.1 Test vehicle description . 87 3.2.2 Voltage monitoring . 88 3.2.3 Communication system . 90 3.2.4 On-chip near-field current sensors . 93 3.2.5 Topcell . 95 3.2.6 Test boards . 96 3.2.7 Test vehicle verification and testing after manufacturing . 97 4 Modeling methods for functional robustness prediction 101 4.1 Intra-chip block modeling . 103 4.1.1 Block failure characterization and modeling method . 103 4.1.2 Block models chaining . 107 4.1.3 Application to the test vehicle . 109 4.1.4 Limitations . 114 4.1.5 Proposed workaround . 117 4.1.6 Final conclusion and follow-up work . 122 4.2 Black box modeling approach . 123 4.2.1 Function failure model . 124 4.2.2 Electrical pin models . 125 4.2.3 Conclusion on black-box modeling . 132 Conclusion 135 Appendices 141 A TLP modeling 143 A.1 Validation curves . 143 B Bottom-up block characterization and modeling 147 B.1 Characterizations . 147 B.2 Improved model chain versus reference . 150 C Black box modelling 153 C.1 Additional validations . 153 Bibliography 155 4 Acronyms 165 5 6 Introduction Integrated circuits miniaturization is still ongoing nowadays allowing increasingly mas- sive integration of electronic functions. An integrated technology is the definition of the dimensions and processes required to manufacture an integrated circuit and its funda- mental conception bricks. The main characteristic of a technology is the feature size called l that represents the smallest dimension for a transistor gate. Size reduction of integrated circuit is mainly accomplished by decreasing this feature size. All other di- mensions of the technology are defined as an integer multiplication factor of l. The value of l determines the size, power consumption, switching speed, performance and many other properties of a chip. So far, Moore’s law successfully predicted that technology dimensions will be reduced by a factor of two every 18 months. The automotive world follows this trend as well, moving recently to 16 nm technology nodes (see Fig. 1) [1] that are normally employed in less demanding applications. Reduction of l results in more massive integration on a given silicon surface. The area occupied by a function on silicon is the main cost factor. Reducing this area allows to diminish the unit manufacturing cost resulting in increased profits and margins. For the same area, integrated circuits in more recent technologies can pack more functionalities with higher performances. Weight reduction of electronic modules in automotive or aerospace lowers fuel consumption, and reduces the impact on the environment. 90 nm 45 nm 28 nm 16 nm Figure 1: Recent evolution of NXP’s automotive technology nodes [1] 7 The decrease of l results in reduction of insulating material’s thickness. Transistor gate oxide becomes thinner, tolerating lower electrical fields before breakdown. After breakdown, the oxide starts leaking significant amount of currents and the transistor becomes unusable. As a result, the technology provides more sensitive conception bricks and a larger silicon area must be dedicated to protecting the core circuitry [1]. New major trends are also emerging in the automotive field. The development of fully autonomous driving is seeing tremendous progress. This class of functionalities take decisions and perform critical actions such as braking or steering the wheel. Those features are developed to offer increased safety for the user. A side consequence is that electronic modules now have very high responsibilities. The real-time constraint is particularly important, meaning that electronic circuits must perform their duties without delay and operate correctly all the time. For instance, an airbag system must always be ready to trigger in case of car accident without any delay. Electric cars raise new challenges for safety as well, such as battery management. Those features require more computing power, more sensing capabilities and more data to exchange. As a consequence, the amount of Engine Control Unit (ECU)s and electronic modules in a car is growing quickly. Communication buses like the Controller Area Network (CAN) [2] or Local Interconnect Network (LIN) [3] are shared by multiple systems and new standards appear for supporting higher bandwidths. The CAN bus with Flexible Data rate (CAN-FD) is an example of this trend. The automotive environment is quite harsh for electronic devices and equipments are exposed to a wide range of stresses. A running engine generates plenty of vibrations and mechanical stress. A lot of heat and thermal cycling is produced when the engine is on, and a vehicle is exposed to large temperature variations during its lifetime. Electrical contacts, solder joints and connections suffer from these stresses, and must be designed to withstand them. Electronic system are also exposed to a wide range of electrical stresses especially in the automotive field. Transient disturbances can be generated by natural phenomena or by the vehicle itself. When the engine is turned on, the battery voltage can drop very low due to the amount of current drawn by the ignition. This voltage drop can affect electronic systems and damage them. Another major source of electrical stress is called the Electro-Static Discharge (ESD). An electrostatic discharge is the sudden flow of electricity between two objects of different charge. It is the result of a local accumulation of electrostatic potential. When a large enough potential difference is reached, a very rapid and large discharge occurs. It is common to record amplitudes in the range of thousands of volts and tens of amperes. A study by Renault car manufacturer [4] estimates that electronic devices are exposed 10000 times to ESDs during their lifetime. It has always been considered a very serious threat for electronic systems. In terms of architecture, a vehicle is constituted by a multitude of electronic mod- ules interconnected by cables. Interconnected electronic systems need to share a good ground reference for them to communicate and work properly. The car’s metallic body is the ground reference for all electronic modules, because a good connection to Earth is impossible inside a vehicle.

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