Fall 2000 XcellXcelljournaljournal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS

PRODUCTS New Virtex Development Board New HDLC and ADPCM Cores

APPLICATIONS Using Block-level Incremental Synthesis

SOFTWARE New WebPack Integrated Synthesis Environment

NEWS IBM and Xilinx Partnership— PowerPC Processors in Virtex-II FPGAs Cover Story Synplicity Chief Technology Officer

Ken McElvain Talks About the R Future of Programmable Logic LETTER FROM THE EDITOR The Partnership Model...

rogrammable logic technology is advancing at a phenomenal rate; our industry is booming, busi- P ness has never been better, and Xilinx is growing faster than we ever imagined. Our devices are bigger, faster, easier to use, and less expensive than ever before, and there are many new development tools, support products, and services being offered by a growing number of companies. In addition, as we add new features, increase performance, and lower prices, many new types of applications are opening for our products-and that fuels even more growth and more innovation. The phenomenal growth of programmable logic technologies is the result of teamwork; we didn’t do it alone. As you can read in the article on page 4 from our CEO, Wim Roelandts, Xilinx is based on a partnership model that includes our technology partners, our stock holders, and you, our customers. Clearly, our sustained success is very dependent on the success of those who work with us. That’s one reason why we work closely with our technology partners and support their development of new prod- ucts and services. It’s also why we work closely with you, to make sure we are creating the right prod- ucts for your current and future needs. It’s also why we publish this journal. EDITOR Carlis Collins [email protected] Communication is Key 408-879-4519

SENIOR DESIGNER Andy Larg Communication is necessary to sustain a healthy partnership, and effective communication requires a two-way process. This journal intends to bring you the latest information about programmable logic BOARD OF ADVISORS Dave Stieg Mike Seither technologies and how to use them. It also brings you the insights of industry insiders about the trends Peter Alfke and developments that will affect you in the future, so you can make informed decisions today. We are always striving to include articles that make a positive difference for you, and present those articles in a format that is interesting and easy to read. journal Xcell Your feedback is important because we want to continue bringing you the types of articles that matter

Xilinx, Inc. most to you. After all, this is your journal; it exists only for your benefit. So, let me know what you think 2100 Logic Drive about our new Xcell Journal; your suggestions for improvement are always welcome. San Jose, CA 95124-3450 Phone: 408-559-7778 FAX: 408-879-4780 Write for Xcell ©1999 Xilinx Inc. All rights reserved. If you have a novel solution to a common design problem or if you have developed a unique design,

Xcell is published quarterly. XILINX, the Xilinx why not share it with your peers? Writing technical articles for Xcell is easy, it can gain you a modest logo, and CoolRunner are registered trademarks amount of fame and fortune, and it’s a great way to promote your company. Send me an e-mail with of Xilinx, Inc. Virtex, LogiCORE, IRL, Spartan, SpartanXL, Alliance Series, Foundation Series, your article ideas, and I’ll send you more details. CORE Generator, IP Internet Capture, IP Remote Interface, MultiLinx, QPRO, Selecti /0, Select 1/0+, True Dual-Port, WebFITTER, WebPACK, Thanks for your continued support of this journal. I hope you like the new design. ChipViewer, Select RAM, Block Ram, Xilinx Online, and all XC-prefix products are trade- marks, and The Programmable Logic Company is a service mark of Xilinx, Inc. Other brand or product names are trademarks or registered trademarks of their respective owners.

The articles, information, and other materials included in this issue are provided soley for the Carlis Collins convenience of our readers. Xilinx makes no warranties, express, implied, statutory, or other- Editor wise, and accepts no liability with respect to any such articles, information, or other materials or their use, and any use thereof is solely at the risk of the user. Any person or entity using such information in any way releases and waives any claim it might have against Xilinx for any loss, damage, or expense caused thereby. Cover Story Page 8 Contents Fall 2000

Design Technology Advances Unleash The Xilinx Business “Ecosystem” ...... 4 Powerful New FPGA Capabilities Design Technology Advances Unleash Powerful The Chief Technology Officer at Synplicity talks about New FPGA Capabilities ...... 8 the trends that are shaping the FPGA industry. Maximizing FPGA Design Performance Using Amplify from Synplicity ...... 11 PowerPC Processors in Virtex-II FPGAs ...... 13

Products The MathWorks and Xilinx take FPGAs into Mainstream DSP . .14 Page 28 Xilinx DSP ...... 16 New HDLC and ADPCM Cores IRL Makes Console Switching Faster and More Reliable . . . . .18 A strategic partnership with ISS produces advanced communications products. LavaCORE - A Configurable Java Processor ...... 20 Inferring Read Only Memory in FPGA Compiler II and FPGA Express ...... 22 Page 46 Using Block-Level Incremental Synthesis in New Virtex XSV Development FPGA Compiler II and FPGA Express ...... 24 Board for Creating Intellectual Property Lucent Technologies Gets a Time-to-market Advantage ...... 27 The XSV Board, designed for the SIP developer community, New HDLC and ADPCM Cores ...... 28 provides a flexible, low-cost platform that supports a large set of interesting applications. Moving the M8051Ewarp ASIC Core to a Virtex FPGA ...... 30 Xilinx WebPACK Software Now Includes ModelSim ...... 33 New WebPACK Integrated Synthesis Environment (ISE) . . . . .34

Applications Page 24 Low Power CoolRunner CPLDs ...... 36 PLDs-Your Competitive Edge for High Volume Production . . . . .38 Using Block-Level Incremental Design Reuse Strategy for FPGAs ...... 40 Synthesis in FPGA Compiler II Year 2000 Worldwide Xilinx Event Schedules ...... 42 and FPGA ExpressBlock-Level CoolRunner CPLDs - Your Best Choice for Battery Operation . . .43 Incremental Synthesis allows you to modify a subset of a design and then Choices, Choices, and Opinions ...... 44 re-synthesize just the modified subset. New Virtex XSV Development Board for Creating Intellectual Property ...... 46 Strathnuey - The Xilinx Technologies Integrator ...... 48 Software Page 34 Tektronix Logic Analyzers - 800 Mbit/sec Using Virtex FPGAs . . .50 New WebPack Integrated Synthesis McData Uses Xilinx FPGAs for Fibre-channel Switch ...... 52 Environment The “Flancter” ...... 54 Free, comprehensive design environment for CPLDs Distribution Adds Value: Intel StrongARM Supported available over the Web. with Xilinx Spartan-II FPGAs ...... 57 Product Reference ...... 58 News Page 13 Xcell journal IBM and Xilinx Partnership– PowerPC Processors in Virtex-II FPGAs For a Free Subscription to the Xcell Journal IBM and Xilinx combine cutting edge technologies E-mail your request to: [email protected]. to create a revolutionary new product. Please include: 1. Your full name and mailing address. 2. Your job title. 3. Your e-mail address. 4. Your company name. 5. Is this a new subscription or a renewal? Viefromw the top

The Xilinx Business “Ecosystem”

by Wim Roelandts, more specialized in their jobs, taking a its shareholders will profit and will contin- CEO, Xilinx more narrow focus, because there is so ue to support the company through stock much to master. That’s why it has become purchases—a key factor in the economic In today’s fast imperative that high technology compa- health of the company. paced high tech- nies, such as Xilinx, focus on the key nology business This partnership between companies, spe- aspects of their business, to become excel- climate, the keys cialized partners, customers, and share- lent at their core technology and business to success are holders is like an ecosystem where each processes, while partnering with other complex and part depends on the others, and the companies that are also the best in what they change constantly. It’s difficult for any boundaries between each are blurred as they do. one company to master all of the necessary they work closely together. For each part of functions of business management, prod- Well managed companies must also learn this ecosystem to survive and to thrive, all uct design, manufacturing, marketing, to partner with their customers to develop parts must work well together, in balance, sales, and customer support. And, as the the insight and the processes that ensure and this must become the primary objec- breadth of required knowledge and expert- the success of each new generation of tech- tive of the company management—if any ise expands, people are becoming much nology. And, if the company is successful, part of the ecosystem fails, all will suffer.

4 View from the top

The Five Habitats • Have a Chief Executive Officer who is a • Advanced information about new prod- coach, not the “quarterback.” Because ucts and new technologies coming from The Xilinx business “ecosystem,” as I see the company so they can be prepared. it, is composed of five main “habitats,” or the business “game” is dynamic, the coach must have competent managers overlapping systems: • Cooperation from the company for and trust them to fulfill their specific product development and marketing. • The Company - People who focus on the responsibilities. primary business goals; the direct • Constant communication with the employees and managers of the company to share information company. about trends, and to maintain • Customers - People who not only overall balance. buy products and services but also • A working relationship that helps influence the design of new prod- them manage their business more ucts. effectively and be more successful. • Partners - People who support the • Training. ecosystem through supplying need- ed services to the company (such as When partners are prosperous and manufacturing and sales, intellectu- growing, customers receive better al property and design support). service and a broader range of sup- port products and services. • Investors - People who own the company and support it through The Investor Habitat their continued investment. For investors to prosper and grow • Government - People who have an they need: impact on the overall business envi- • The company to be well managed ronment by making laws and regu- and provide good return on invest- lations that can affect the company. ment. Each of these habitats must be healthy • To have a good understanding of and prosperous for the overall ecosys- the company’s strategy and busi- tem to be healthy and prosperous. ness practices. The Company Habitat The Customer Habitat • To have timely and unbiased informa- For a company to prosper and grow, it For customers to prosper and grow, they tion about the company’s results. must create and maintain a balanced need: In many cases, employees, customers, and ecosystem. Therefore the company must: • A continuous flow of innovation from partners are also company stockholders, • Determine the core competencies the company to help them create lead- and therefore they are doubly motivated to required for long term success and ing edge products and remain competi- maintain a healthy environment that sup- become excellent in those key areas. tive in their markets. ports the long term growth of the compa- • Determine which functions can best be ny. This is important because the compa- • Easy access to all of the company’s handled by other companies (partners), ny’s ability to borrow money and therefore intellectual property. and manage those relationships well. its flexibility and adaptability are directly • Open channels of communication with affected by the company’s worth on the • Work closely with customers to develop the company to: stock market. the right products and to provide spe- cialized services. - help it create the right products The Government Habitat and services, and become a better • Become a learning organization, adapt- To ensure that government supports the company ing to the dynamics of the marketplace. company and to ensure that the company - receive the latest technical and is a good corporate citizen, the company • Be dynamic, adaptive, and free to inno- must: vate, with room to make mistakes. marketing information The Partner Habitat • Educate the government about the com- • Take good care of its employees by pro- pany and its products. viding a rewarding, satisfying, and For partners to prosper and grow, they friendly work environment. need: • Give feedback on proposed laws and 5 View from the top

policies that can an impact on the com- Customer Support ners are manufacturing and sales. So, Xilinx has no fabrication facilities or direct pany and its industry. To create superior technology, and make sales force. These are two of the most the world aware of it, goes a long way • Build a partnership with local govern- expensive functions in any company, and toward the success of any company. ment to improve the local community the costs are not fixed. In a cyclic industry, However, without effective and consis- and to reach common goals. such as our own, we gain a significant cost tent customer support, it’s not enough. advantage by outsourcing these functions How the Xilinx Ecosystem Works Our technology is complex, and to use it to partners who have made it their busi- effectively requires an in-depth and con- Our primary responsibility must be to ness to be the best; plus we gain added stantly evolving expertise. That’s why we develop, manage, and balance our business flexibility that helps us weather the created our in-house staff of highly- ecosystem if we are to remain the leader in inevitable down turns without having to trained support engineers and design lay off employees or suffer heavy losses. our industry. So, our first task was to services professionals who can quickly Therefore, within Xilinx, we have dedicat- decide what key competencies we needed help you meet any challenge. within Xilinx and which we could entrust ed people to manage these relationships Sometimes the difference between our to outside partners. with our 3rd party manufacturing and products and our services blur. For exam- sales partners. In addition, we also have We have defined four core competencies ple, our in-house development tools and dedicated marketing people who manage that we must keep within our relationships Xilinx: with our develop- ment tool partners, • Product design and tech- helping them define nology development. and market their • Marketing. products to our cus- tomers. • Customer support. For manufacturing, • Partner relationship we have partnered management. with UMC in Taiwan and Seiko- By focusing on these core Epson in Japan. functions, we can put our UMC has created resources to best use. one of the world’s Product Design leading IC fabrica- tion facilities, with Product design is our pri- the very latest equip- mary focus because inno- ment and process vation is the lifeblood of technologies. And, any high technology company; we spend intellectual property are products, but because it is their business to manufacture more money on research and development their sole purpose is to assist you in cre- semiconductors, they are always on the than any of our competitors. We continu- ating the best possible designs with the cutting edge of process technology. ously strive to create leading edge devices least time and effort. So, though most of We work very closely with UMC to devel- and support tools that meet the specific our revenue comes from the sale of op new manufacturing technologies and to needs of our customers. FPGAs and CPLDs, we must also make ensure that our designs can make best use sure the best tools and services are avail- Marketing of the highest performance, and least able too. expensive, process technologies. Through It’s not enough to create “dream” products We also work with many third-party con- this partnership, we have moved from 0.5µ with more and more features. Excellent sultants to provide training, design serv- technology to 0.15µ in less than five years; products must consistently meet the needs ices, IP development, tool development, and 0.13µ technology is soon to be in use. of our customers and our customers must and so on. This fast-paced process migration has be fully aware of what we offer. It is the helped us to quickly reduce costs and sig- Partner Relationship Management function of marketing to make sure that nificantly increase density, which means we are in full communication with our Two of the most important competencies you get faster, less expensive devices, soon- marketplace, in both directions. that we decided to entrust to outside part- er. We could not have progressed this

6 View from the top

quickly with an in house fabrication facili- The Xilinx Value System Conclusion ty—the costs would have been far too Values are what holds any organization Many companies—even successful ones— high. This partnership has benefited both together and define the boundaries within view themselves as adversaries with their companies, as well as our customers. which its employees can efficiently func- customers and with their marketplace, For sales, we use our distributors and inde- tion. Too often a company’s values are often using military tactics and focusing pendent sales representatives. Sales is obvi- undefined however and this leads to errat- on winning at all cost. We think there is a ously a critical function in any company, ic results and confusion. better way. and is very expensive. We chose to partner To help us manage and balance the Xilinx To become successful, and remain com- with our distributors because Xilinx prod- business ecosystem, we developed a clear petitive, high technology companies must ucts are a key source of revenue for them, and consistent set of values that we live by. view themselves as part of a synergistic often providing more revenue than any In part, these values are the boundaries whole that includes customers, strategic other product line. Therefore our distribu- that allow our managers the room to inno- partners, employees, investors, and gov- tors have a lot of incentive to focus on our vate and to take ownership of their func- ernment. At Xilinx, our role is to maintain products and to use their extensive sales tions. Our values also help to make Xilinx the dynamic balance of this system, and to force to focus on Xilinx. This is another a great place to work which inevitably keep it growing and expanding in a way win-win partnership that helps both com- leads to better products, happier cus- that makes everyone more whole and panies adapt to the inevitable ups and tomers, and increased profits. prosperous. downs of the business cycles. Our cus- tomers also benefit from the broad range Our values are contained within the When you work with Xilinx, you’ll see what of services provided by our distributors. acronym “CREATIVE” which stands for: a positive difference our “ecosystem” atti- tude can bring to your long term success. At Xilinx, average revenue per employee is $600K; many companies with in-house Customer Focused. We exist only because our sales teams are fortunate to have C customers are satisfied and want to do busi- $200,000/year/employee. By keeping our ness with us... and we never forget it! sales costs low, we can put more resources into research and development which Respect. We value all people, treating them keeps us on the leading edge of technolo- R with dignity at all times. gy, and makes our customers and our investors very happy.

For software support, we partner with the Excellence. We strive for “Best in Class” in E industry’s leading software and develop- everything we do. ment tool suppliers to make sure that you have access to the broadest range of tools Accountability. We do what we say we will do and support. We work very closely with A the leading software suppliers to make sure and expect the same from others. that our tools work well together. Though we have a massive in-house effort for soft- Teamwork. We believe that cooperative action ware development we also know how T important it is to provide you with the produces superior results. new tools and processes that are constant- ly being created in the marketplace. Integrity. We are honest with ourselves, each For research, we partner with universities I other, our customers, our partners, and our and research centers around the world to shareholders. access the latest developments. Plus, the “Very” Open Communication. We share infor- Xilinx University Program is helping train V mation, ask for feedback, acknowledge good engineering students in the use of pro- work, and encourage diverse ideas. grammable logic devices by providing donations, discounted products, and serv- Enjoying Our Work. We work hard, are ices. Today there are over 1200 universities E rewarded for it; and we maintain a good sense using Xilinx in class labs; about 15% of all of perspective, humor, and enthusiasm. of the engineering universities worldwide.

7 Cover Story Synplicity

DesignDesign Technology Advances TheThe ChiefChief TechnologyTechnology OfficerOfficer atat SynplicitySynplicity talkstalks UnleashUnleash Powerful aboutabout thethe trendstrends thatthat areare NewNew FPGA Capabilities shapingshaping thethe FPGAFPGA industry.industry.

by Ken McElvain Chief Technology Officer, Synplicity, Inc. In today’s marketplace there is enormous pressure to create increasingly com- plex systems and get those systems to market as quickly as possible. To chal- lenge these efforts, there is a lack of qualified engineers, industry stan- dards are constantly changing, ASIC development costs are skyrock- eting, and new technologies are quickly making yesterday’s meth- ods obsolete. These problems are intensified with the fierce competition for lucrative emerging markets. The risks are significant; one equipment vendor estimates the cost of missing a market window to be more than $1 million a day. However, there is also good news. Today’s multi-million gate FPGAs offer great promise for designers confounded by the limitations of tradition- al ASIC implementation. Indeed, the increased

8 Cover Story Synplicity

time-to-market demands and lower devel- Fortunately, just such an approach exists in that is possible through the emergence of opment cost of FPGAs, combined with RTL prototyping, a methodology being fast, dense FPGAs such as the Xilinx today’s FPGA capacities well in excess of a adopted widely by both ASIC vendors and Virtex FPGAs and synthesis technologies million gates, are yielding a profound system houses. that can translate ASIC RTL into multi- increase in the number of applications ple FPGAs. By building a version of their In contrast to conventional ASIC designers being realized in programmable form. design in hardware using multiple who tend to focus on the functions within From networking and telecommunications FPGAs, designers can use RTL prototyp- their chips, SoC designers must give much designers grappling with narrow market ing to leapfrog all of the limitations of more consideration to the system-level windows and evolving standards, to a software simulation. nature of the device’s inputs and outputs. broad scope of designers seeking low-risk rapid prototyping, the number of people turning to FPGA solutions is quickly expanding. Today’s multi-million gate FPGAs offer Engineers Designing both FPGAs and ASICs great promise for designers confounded Only six years ago, engineers were divided into two distinct groups: those that by the limitations of traditional designed ASICs and those that designed with FPGAs. The FPGA designers were ASIC implementation. primarily schematic based while the ASIC designers had adopted RTL technologies. -Ken McElvain, Synplicity These two groups didn’t work together.

Today, things have changed. Many design- Software simulation, which checks circuit FPGAs Offer Design Flexibility ers developing FPGAs are also designing functionality against a blast of test vectors, ASICs, often at the same time. In addition, falls short of allowing system I/O to be The Internet’s explosive popularity, and designers are now less concerned about the tested. Other drawbacks of software simu- the resulting surge in demand for band- underlying device technology because the lation are well known; it is too slow and width, has created immense competitive gap between ASIC and FPGA performance can’t reproduce electromechanical interac- pressure for communications equipment is narrowing. However, ASICs will remain tions such as fetching data from a drive. makers. To complicate matters, the com- the technology of choice for certain types Simulation can take as much as 60 percent munications market is a minefield of spec- of applications. If a design must operate at of the design cycle time and require too ifications evolving unpredictably toward the low end of power consumption or at many iterations between RTL and gate- standardization. Schemes for carrying the extreme upper end of performance, or level implementation. Also, it does voice and video over the Internet, or the if you are designing a very high-volume, not allow for co-verification of hardware Internet over cable, or any number of vari- cost-sensitive system, an ASIC is likely the and software. ations on the Internet theme bring with most cost-effective solution. If design flexi- them a multitude of implementation These roadblocks stand in the way of what bility or remote design upgradability are details that often must either be ironed SoCs require. For example, consumer and out by committees or decided by the needed or if engineering time and risk must communication designs (areas of great market. be minimized, an FPGA is a logical choice. promise for SoCs) compete within tight The SoC Opportunity for FPGAs time-to-market windows that suffer when Such last minute unpredictability makes debugging takes many iterations through bringing complex communications equip- The advent of systems on chips (SoCs) is long cycles of simulation and synthesis. In ment to market quickly even more diffi- more than a simple extension of ASIC addition, many chips for these markets cult. Equipment vendors who hope to technology to higher density. With SoCs, must run at high clock rates to verify their ASIC designers have become system exploit the high-density and high-volume correct operation. Inadequate verification designers, and the event-driven simulation economics of ASIC technology risk every- of these designs can mean one or more fab technology traditionally used is no longer thing should a last minute protocol re-spins, which can cost over $1 million per sufficient for verifying functionality. change force a silicon re-spin. Realizing re-spin and take up to six months. Instead, what designers urgently need is a this, increasing numbers of equipment faster, higher-level, hardware-oriented veri- To take fuller advantage of the SoC phe- manufacturers are instead opting for the fication path that accepts actual system nomenon, designers can instead turn to fast turnaround and flexibility offered inputs to yield actual system outputs. RTL prototyping, a new methodology by FPGAs.

9 Cover Story Synplicity

The quick re-configurability of FPGAs car- Evolution of Software mented based upon not only traditional ries other benefits in addition to accommo- timing constraints, but also physical con- Design automation is key to enabling this dating shifting specifications. By exploiting straints. The nature of FPGA architectures new era of FPGA design. Unfortunately, the option for in-system programmability, makes it possible to perform physical opti- simply extending interconnect-aware ASIC companies can easily and affordably make mization techniques during synthesis, for design technology to the FPGA domain field upgrades, correct bugs and add fea- example, moving registers across regional won’t work. The interconnect configura- boundaries to increase performance. tures over the Internet, to name just a few tions and options unique to FPGA archi- possibilities. tectures cannot be comprehended utilizing Physical synthesis offers significant produc- tivity as well as performance advantages to The Impact of FPGA Technology Advances ASIC physical modeling techniques. Instead, new FPGA-targeted design FPGA designers. First, the use of physical FPGA technology used constraints during synthe- to be one or two sis results in more accurate generations behind timing estimation, elimi- ASICs. However, the nating time-consuming increase in FPGA den- and tedious design itera- sity and performance tions common with tradi- has steadily outpaced tional approaches. that of ASICs for some Likewise, physical opti- time. Because of the mization during synthesis increasing NRE costs makes it possible to physi- cally optimize a circuit for of leading-edge ASICs, the best possible perform- the typical ASIC ance. Combined physical design is falling farther synthesis and optimiza- behind the leading tion techniques can have edge of process tech- significant cost benefits, nology, while FPGAs enabling designers in are becoming process many cases to implement drivers. a device in a lower-cost However, taking full speed grade. advantage of state-of- FPGA physical synthesis the-art FPGA technolo- forms the critical link gy today presents new between state-of-the-art and difficult challenges. programmable technology As FPGA process tech- and designers seeking to nology progresses well leverage its unique advan- into the deep submicron realm, intercon- automation technology is needed. Such tages. Such technology opens the door of nect-dominant delay now poses the same technology must address the difficult task opportunity for those faced with today’s difficulties for FPGA designers that previ- of bringing accurate information about the tough market realities. ously plagued their ASIC counterparts. physical interconnection of a programma- Conclusion Traditional schematic or logic synthesis- ble circuit into the design process without Market forces have created a risky environ- based programmable design solutions, sim- extending design cycles. ment where the winners and the losers are ilar to the ASIC methodologies of three to Fortunately, FPGA design technology is often separated by only a small gap of inno- four years ago, lack the ability to adequate- evolving to accommodate the needs of vation. Therefore, it is increasingly impor- ly account for interconnect effects early in designers in the deep submicron era. Of tant to produce next-generation designs on the design cycle. With today’s highly com- particular significance is FPGA-based time and within budget, using limited plex circuits and relentless market pressure, physical synthesis technology. Physical syn- engineering resources. Today’s programma- it is more important than ever that accurate thesis factors a design’s physical characteris- ble logic technology and the development interconnect-related performance informa- tics into the synthesis process. During syn- tools that support them are your keys to tion be integral to early design processes. thesis, a design is optimized and imple- success in this dynamic marketplace.

10 Applications Software Maximizing FPGA Design Performance Using Amplify from Synplicity In very large designs, interconnect delays are becoming more and more predominant. AmplifyTM is the first physical synthesis tool for FPGAs that helps you optimize signal routing delays and achieve timing closure. by Philippe Garrault Technical Marketing Engineer, Xilinx, Inc. [email protected] On the first pass, the project is synthesized then implemented with global timing constraints only (without physical constraints). Amplify is a new product from Synplicity® that allows you to add Figure 1 shows a floorplanned view of the design after the first pass. physical constraints to your design, using the Synplify® PRO syn- Note that the logic is spread over the chip because, without place- thesis engine. It links your RTL code to a floorplan of the target ment constraints, the place and route algorithm has no informa- device. You can assign your RTL code to physical regions by graph- tion about what logic is crucial for grouping into a region (or there ically dropping the logic into these regions. During the synthesis are too many possibilities). The timing constraints were not met, process, Amplify will use a set of rules to optimize the RTL code and the best frequency obtained was 104.6MHz. based on estimated placement and interconnect After this first implementation, we analyzed the delays (into and between regions). post-layout timing report to gather information on Amplify generates an optimized netlist (.edf file) the critical path, such as: and a Xilinx constraint file (.ncf file) based on the • The number of critical paths. specified physical constraints. These files are then used by the Xilinx Alliance Series 3.1i software • The start and end points (single or multiple). tools to implement the design. • The type of critical path (link with I/O or purely Improving Maximum Frequency internal, wire or bus). With Amplify you can iterate the implementation twice. In the • The number of logic levels. first pass, you determine the critical paths after place and route. In • The device resources (flip-flop, combinatorial, block RAM, and the second pass, you assign physical constraints on these critical so on). paths to optimize the netlist. By iterating the second pass, the physical constraints can be refined according to the place and route On the second pass, the different critical paths were assigned in post-layout timing report, until your timing requirements are met. separate regions through the Amplify user interface. Figure 2 shows the physical constraints entered in the synthesis environment for Another approach is to set several regions prior to implementa- our example. tion. These regions could be a representation of the RTL hierar- chy of the design and each could contain one block (or module) The regions are floorplanned according to the required design of the design. resources, such as block RAM and high fanout nets. . By re-syn- thesizing the design with these physical constraints, a new netlist Finally, you could also mix these techniques to get a floorplan that file along with a constraint file were created. The place and route would not only be a hierarchy representation but you could also software uses these optimized files to constrain the logic on these add physical constraints on the critical paths regardless of any hier- particular areas by placing the critical logic together, shortening net archy consideration. This is what we did in the following example. delays to meet the timing requirements. Design Example If the constraints are not met, the Xilinx floorplanner can give use- The following example shows how to interface Amplify with the ful information about the final layout and determine the precise Xilinx place and route tools. The design presented is a network logic utilization within a region, or view the exact placement of application, which is divided into a top module driving nine simi- logic on the critical path. This can help to resize regions, remove lar sub-modules. This code is implementing FIFOs and large constraints on non-critical paths, or re-place regions closer togeth- busses. We targeted a Virtex-E, XCVE1000-7 device. er to drive or share common logic or busses. 11 Applications Software

Figure 3 shows the floorplanned view of the constrained design in our example. Note that the logic is gathered according to the constraint file. The best frequency obtained was 120.1MHz, which is a 12.9% improvement. Using the post-layout tim- ing report and the floorplanner helped us focus on the critical parts of the design, thus saving time by applying more accurate constraints, and reducing the number of iteration needed to meet the timing con- straints. Interfacing Amplify with Xilinx Tools Here are some guidelines to help you get the best performance from these tools: Figure 1 - floorplanned view of the design on the first pass. • Put different critical paths into different regions. This usually gives better results. • If the critical path contains lots of logic, two regions can be overlapped: one small one containing the most critical logic that needs to be placed very close together and a bigger one containing the rest of the critical path. • Amplify does not currently write con- straints for block RAM or black boxes, thus if the critical path includes these objects, use the Constraints Editor and constrain black-boxes and block RAM in the UCF file within or close to the region constraining the rest of the critical path. Use the following command:

INST p1.qram1 LOC = RAMB4_R0C1: RAMB4_R7C1, RAMB4_R*C2; Figure 2 - Physical constraints entered in the synthesis environment. • Applying physical constraints to critical paths is more likely to improve results if the ratio between routing and logic is in favor of routing (this ratio is given by the post-layout timing report). • Slightly moving a region can affect the maximum frequency of your design. Conclusion Synplicity’s Amplify Physical Optimizer in conjunction with the Xilinx Alliance Series 3.1i software can significantly improve your design performance. As a result of the new features and capabilities, you have a more efficient way to visualize and con- strain critical paths of your designs, saving Figure 3 - Floorplanned view of the constrained design. time in multiple iterations while getting better speed performance.

12 News Partnerships PowerPC Processors IBM and Xilinx combine cutting edge technologies to create a in Virtex-II FPGAs revolutionary new product. by Ann Duft Manager of North American PR, Xilinx “This joint effort will bring about a new Roelandts, president and CEO of Xilinx. [email protected] design era combining programmable logic “IBM’s process technology is the most IBM and Xilinx recently announced a part- time-to-market advantages with the cost advanced in the industry and the nership to create a new generation of devices benefits of standard cell technology,” said PowerPC architecture has become the for use in communications, storage, and Andrew Allison, semiconductor industry standard in communications, enabling us consumer applications. Under the agree- analyst. “This is a potent combination.” to deliver the highest performance and ment, we are working together to embed highest density products into the market “IBM and Xilinx are committed to meeting IBM PowerPC processor cores in Xilinx at the leading edge of technology.” each customer’s unique blend of require- VirtexTM-II FPGAs. The pairing of a low- ments for cost, design time, and individual- Under the multi-year agreement, Xilinx cost, high performance PowerPC processor ized function,” said John Kelly, general man- will license IBM’s high-performance core with customizable FPGA circuitry ager, IBM Microelectronics Division. “This PowerPC processor cores and CoreConnect allows you to create custom chips for your requires a variety of chip design options, bus for integration into Xilinx FPGAs. particular application at reduced cost and from standard, off-the-shelf parts IBM and Xilinx will map the resulting to FPGAs to ASICs. This designs to IBM’s advanced chip manufac- agreement creates both turing processes, keeping Xilinx FPGAs on a new approach in chip the leading edge of technology. IBM will design, as well as a unique license IP from Xilinx to quickly move collaboration between leadership process technology to the mar- the world’s leading ASIC ketplace. We also plan to explore other and programmable logic areas of cooperation that could benefit cus- providers.” tomers of both companies. The complementary mar- keting and technology About IBM agreement will enable cus- tomers who choose FPGA IBM Microelectronics is the world’s solutions from Xilinx to leading ASIC supplier and a key more easily migrate to IBM contributor to IBM’s status as a with faster time-to-market. Availability dates ASIC and standard product solutions. premier information technology for the new chips will be announced later Customers will factor performance, cost, provider. IBM Microelectronics this year by Xilinx. time-to-market, and volume requirements develops, manufactures, and markets in making a determination as to the best The new devices will initially be fabricated state-of-the-art semiconductor and option for a given application, while using by IBM for Xilinx using advanced IBM chip interconnect technologies, products, the same industry standard PowerPC and manufacturing technologies, including cop- and services. Its superior integrated IBM’s system-on-a-chip CoreConnect bus per interconnects which adds to their per- solutions can be found in many of technology across all solutions. formance. This will enable Xilinx to broad- the world’s best-known electronic en its manufacturing volume and geograph- “The combination of technologies will lead brands. More information about ic diversity, and leverage common foundry to a new level of performance and flexibility IBM Microelectronics can be found manufacturing processes. in the semiconductor market,” said Wim at www.chips.ibm.com.

13 New Technologies DSP

important for DSP applications, because many system-level design trade-offs are based upon the results of the hardware implemen- The MathWorks tation. Consequently, your development time is significantly reduced, and moreover, even if you are new to FPGAs, you can use the familiar tools from The MathWorks, and Xilinx take along with the Xilinx FPGA development tools, to create FPGA-based DSP applica- tions. This combination not only gives you the ease-of-use and time-to-market advan- tages of FPGAs but also the highest possible FPGAs into performance. The System Generator The System Generator consists of two com- Mainstream DSP ponents to help you proceed from a system model to actual hardware. The Xilinx Block Set (XBS) allows you to embed bit-true and Now you can develop high-performance cycle-true models of FPGA-specific circuitry into a Simulink design, while the System programmable DSP systems with Xilinx FPGAs Generator translation software converts the Simulink model into synthesizable VHDL, using system design and verification tools from with Xilinx FPGA hardware as the target. The MathWorks, Inc. The XBS provides these elements: • Parametric blocks for DSP, arithmetic, and logic functions. • Gateway blocks to communicate with the Simulink environment, where you have by Per Holmberg access to the extensive set of Simulink DSP Sr. Product Marketing Manager, Xilinx System Overview libraries.* [email protected] The Xilinx System Generator automatically • Special tokens to support user-defined Anne Mascarin generates hardware description language black boxes and to invoke the System DSP Market Segment Manager, The MathWorks (HDL) code from a system representation Generator interface to the Xilinx FPGA [email protected] model in Simulink. The HDL design can software. The MathWorks and Xilinx have entered a then be synthesized for implementation in The XBS provides the functionality of: strategic exclusive alliance and joint develop- Xilinx FPGAs using standard hardware syn- ment agreement for the system-level creation thesis software. To maximize predictability, • Simulink S-functions - the Simulink repre- of FPGA-based DSP designs. The first prod- density, and performance, the System sentation of the XBS. uct will be the Xilinx System Generator for Generator automatically maps blocks in the • Synthesizable VHDL - the hardware repre- Simulink(tm) software. Used with The system design into optimized LogiCORE sentation of the XBS, including the use of MathWorks’ popular Simulink system-level algorithms (cores). With only one represen- Xilinx cores where appropriate. design tools, and the Xilinx CORE tation of the design and no manual interven- tion when translating the system-level design Generator and LogiCORE DSP algorithms, The System Generator software token acti- to HDL, a common source of errors is this software is the first to bridge the gap vates the translation software that converts a removed. between system-level DSP design and FPGA Simulink model built from XBS elements implementation, allowing you to easily You can significantly reduce development into synthesizable VHDL. The VHDL gen- design high-performance DSP applications time by quickly iterating between the sys- erated may include cores for appropriate in Xilinx FPGAs. The overall system flow is tem-level model in Simulink and the hard- functions, as well as corresponding simula- illustrated in Figure 1. ware implementation. This is especially tion models. 14 New Technologies DSP

The System Generator graphical user inter- in the hierarchy and creates a VHDL Multi-rate clocking is supported through face (GUI) allows you to customize the description of the design. Where possible, time step information provided during sim- Simulink simulation. For example, it can the mapper uses the Xilinx CORE Generator ulation. Each control logic block is given a hierarchically override fixed-point values to generate optimized LogiCORE imple- default synthesizable behavior which may with doubles. This is particularly useful dur- mentations for specific design elements. require alteration to achieve an efficient ing design and debugging. implementation. When an element or its parameter values Simulink imply functionality unavailable in the The Testbench Generator CORE Generator, the mapper instantiates a You can model a VHDL design using any The testbench generator is an interactive tool reference to a parameterized, synthesizable combination of Simulink blocks. By using that runs in the MATLAB environment, in the XBS black box token, you can then which you capture the input instantiate the design into a generated stimuli and system outputs of VHDL model. The black box customiza- selected simulation runs for con- tion GUI encapsulates the design infor- version to test vectors. The gen- mation necessary for the compiler to erator converts the captured sim- create the correct instantiation ulation data into VHDL code interfaces. This black box support that will exercise the implemented allows the abstraction of com- model and test its outputs against monly used control signals the expected results. and ports, and then infers Logic Synthesis them within the generat- ed VHDL. The Xilinx Foundation Series, or any synthesis compiler supported Working in through the Xilinx Alliance Series Simulink, you cre- software tools, can be used to syn- ate a model of the thesize the control logic and ele- hardware system ments for which no hardware macros as well as one or Figure 1 - Flow diagram. exist, and combine all the pieces into more test envi- a fully realized netlist. The outputs of ronments in which to this back-end process are a bit stream simulate the model. When the model is first entity in a synthesis library or your own sup- and an EDIF structural netlist of the hard- entered, simulation is typically performed plied model.The actual hardware entities ware, annotated with timing information. using floating-point data to verify its theoret- used have additional inputs and outputs for This netlist can be simulated with the test ical performance. You then add the appro- control signals that are not evident at the vectors produced previously from system priate XBS elements, and then convert data level of abstraction used in Simulink. The simulations to verify the performance of the types to the bit-true representations used in mapper inserts the necessary control ports completed FPGA hardware realization. the hardware implementation. Then the and connects them to control logic blocks. model is re-simulated to verify its perform- Conclusion ance with quantized coefficient values and About The MathWorks With the introduction of the Xilinx System limited data bit widths, which can lead to Generator for Simulink, you now have a tool overflow, saturation, and scaling problems. The MathWorks develops technical that makes the job of incorporating FPGAs User-defined black boxes can also be incor- computing software for engineers into your DSP designs easier than ever porated in the modeling and elaboration and scientists in industry and educa- before. Today, Xilinx FPGAs provide you process. When the model has been convert- tion. An extensive family of products, with the world’s highest-performance pro- ed to a form realizable in the FPGA and grammable DSP solution, supporting appli- based on MATLAB and Simulink, its performance meets specification, you cations equivalent to 160 billion MACs. As can invoke the netlist and the test bench provides high-productivity tools for FPGA technology continues to advance, it is generator. solving challenging expected that by the year 2002, you will have The Netlister and Mapper mathematical, access to a ten million gate FPGA offering computational, 0.6 Tera MACS per second. The netlister extracts a hierarchical represen- tation of the model structure annotated with and simulation all the element parameters and signal data problems. For more information see See www.xilinx.com types. A mapper then analyzes the elements www.mathworks.com for more information. 15 Core Solutions Xilinx DSP

The World’s Highest-performance Programmable DSP Solution. A New Paradigm in High Performance Digital Signal Processing...

by Rufino Olay Sr. DSP Product Marketing Engineer, Xilinx [email protected] best speed and area utilization for your Multiple Data Paths and Channels particular needs. Individual arithmetic logic can be linked to Xilinx DSP consists of the Virtex and Parallel Operations separate data paths or mutually coupled to Spartan series FPGAs, a wide range of DSP run parallel operations during individual algorithms, and a comprehensive set of soft- Xilinx DSP helps you create the most robust cycles. This approach is ideal for applications ware tools and prototyping boards. This is a DSP applications by exploiting the paral- consisting of multiple subtasks that need lit- complete DSP solution giving you the high lelism that is inherent in DSP mathematical tle or no interdependency. performance and system integration of models. Using the vast logic resources that ASICs and ASSPs plus the reconfigurability are present in the Virtex FPGAs, you can cre- Logical Operations ate fully parallel structures that give you the and quick turnaround of standard proces- You can easily implement a variety of bit- utmost in computational power. sors. This ultimate combination provides a and byte-wide operations such as barrel shift- comprehensive and robust platform to help Customizable Data Structures ing, comparison, rotation, and accumulation you create the highest performing repro- by instantiating any of our numerous cores Unlike fixed-width processors or ASICs, grammable signal processing applications or by writing your own HDL code to cus- Xilinx FPGAs give you the freedom to cre- imaginable. tomize a particular process. We’ve created a complete The MathWorks Simulink design flow that guides you Algorithm Benchmark Unit of Measure Integration through the conceptual 16-bit 160,000,000,000 MAC/s architectural design, verifi- Xilinx and The MathWorks (the cation, and implementa- 256 Tap FIR 160 MSPS leader in DSP algorithm tools) have created a strategic alliance tion. Design techniques 1024 pt FFT 41 usec such as parallel processing that allows you to build high per- Reed Solomon Decoder 87 MHz and distributed arithmetic, formance DSP systems in Xilinx coupled with industry-lead- JPEG Codec 21 MHz FPGAs using the system design and verification tools with which ing hardware platforms, ADPCM 16 MHz you are already familiar. The increases sampling rates by result is the Xilinx System an order of magnitude over Table 1 - Performance Matrix GeneratorTM tool-set which that of traditional approach- bridges the gap between your conceptual es; there is no faster DSP solution, anywhere. ate custom word lengths for your particular architectural design and the actual transla- Table 1 shows a sample listing of algorithm situations, including different parameters tion and implementation of your FPGA- benchmarks. within the same design. For example some based DSP system. channels in your system might require more bits of precision than others; you can With the Xilinx System Generator you can Fast, Flexible, and Easy easily change the algorithm and the Xilinx easily experiment with various DSP func- With Xilinx DSP you can easily create DSP software will easily accommodate the tions and quickly see the algorithmic trade- customized architectures that give you the new data configuration. offs between performance and silicon area.

16 Core Solutions Xilinx DSP

FPGA-based complex sin- best possible design expertise. In addition, Shorter Design Cycle gle-rate, half-band, Hilbert Xilinx DSP FAEs have extensive design expe- Traditional design methodology transform, and interpolated rience which gives them particular insight filter designs. Design tech- and knowledge to the challenges and intrica- System Design Analysis & Tradeoffs FPGA Design niques such as distributed cies of high performance DSP applications. arithmetic are employed to Cores address the FPGA design phase Third-Party Programs Using Cores optimize filter structures for high-end DSP applications To help you further reduce your develop- System Design Analysis & Tradeoffs such as wireless and xDSL ment time, Xilinx has partnered with various modems, medical imaging, DSP development companies to provide a Using The Xilinx System Generator Only Xilinx addresses and radar signal processing. wide range of services, from algorithm devel- this with The Mathworks! System Design The operational perform- opment to full turnkey operation, giving Development Time ance of the FIR filters, in the you: Virtex family, exceeds 160 Figure 1 - IP and System Generator provide shorter design cycles. • A large and growing selection of system IP billion multiply accumulates from our AllianceCORE partners. (MACs) per second. Then you can easily compare the cost and • Access to the leading DSP experts in vari- The FIR Filter Generator allows you to speed with off-the-shelf DSP devices. ous application areas. choose from millions of parameter combina- Key Features include: tions to match your unique DSP design • Design services and expertise from the • Seamless integration; no manual redesign requirements, from fast, fully parallel systems Xilinx XPERTS partners. to cost-effective designs optimized for lower is required. • A wide range of in-house and third-party sampling rates, as shown in Figure 2. The design expertise and application experi- • No risk of error introduction. available parameters include: ence. • Only one source code to maintain. • From 2 to 1024 taps. In addition, numerous third-party vendors • Floating-point and fixed-point system • From 1 to 32 bit input simulation. data and coefficient pre- cision. • Automatically generates HDL description Xilinx IP Advantage for Xilinx FPGAs. • Signed or unsigned input Comprehensive IP Offering data. Lower cost than DSP Our extensive selection of IP, including fil- • Fully serial, parallel, or a processors combination of serial/par- ters, correlators, transforms, FFTs, FECs, Worlds fastest allel filter implementa- programmable integrators, DDS, and math functions, gives DSP device you the power to build large, complex tions with the ability for PERFORMANCE designs quickly and effortlessly. Plus, our IP multi-clocking of output data. is optimized and parameterized for imple- Area/Cost mentation in our Virtex and Spartan FPGAs • Time multiplexing of Figure 2 - Xilinx FIR Filter Generator only filter algorithm so you get the most efficient and fastest data for multiple channel enabling area/performance tradeoffs. implementation. structures. The intuitive GUI in our CORE Generator Smart-IP Technology such as GV & Associates, Nallatech, and Lyr guides you through the various options to Signal Processing also offer prototyping By employing the Xilinx Smart-IP help you customize the IP for your specific hardware. Technology, the CORE Generator main- design requirements. The features include: tains constant performance over the entire Conclusion • Scalable IP to fit your particular applica- range of FPGA densities; Smart IP gives you With the Xilinx DSP solution, you get faster tion. predictable timing and optimal an imple- DSP designs that are customized for your mentation for area and speed. This pre- • Millions of possible permutations. exact needs. Plus, there are no NRE charges dictability, unique to Xilinx, is essential for or limitations to your creativity. There simply • Minimal learning curve. incorporating entire systems on an FPGA. is no better way to create DSP designs. New FIR Filter Generator In-House Expertise Xilinx recently announced the FIR Filter We’ve gathered together a highly knowledge- Generator, a new tool for creating fully opti- able team of DSP experts to create the best For more information see mized and parameterized algorithms for possible DSP tools and to provide you the www.xilinx.com/dsp

17 Success Story Xilinx IRL

IRL Makes Console Switching Faster and More Reliable.

by Robert Rowe switches to manage and operate multiple also provides flexibility for developing and Product Manager, Apex servers from a single console. This provides rapidly deploying new services and for [email protected] more space for servers, routers, hubs, and remotely reconfiguring data in the console One of the most pressing concerns facing printers by reducing the quantity of key- switch. Information Systems Managers today is boards, monitors, and mice. Faster Time-to-Market managing the volume and diversity of Apex, the market leader in console switches, servers under their authority. As corpora- By populating the console switch with chose Xilinx to provide the FPGAs to create tions increase the number of servers they Xilinx FPGAs, Apex engineers developed their next generation switch. By using Xilinx deploy, the infrastructure needed to support 80% of the base solution to get the system FPGAs and the Xilinx Internet this growth requires more efficient manage- up and running. Then, by the time the Reconfigurable Logic (IRL) technologies, ment of physical space, server information, switches were deployed to customers, the Apex could develop a console switch that and staff time. remaining 20% of the code was completed can be upgraded with new services or func- and transmitted to the systems in the field. Administrators have recognized the impor- tionality, in the field, without having to sup- This gave Apex a lead in deploying the prod- tance of reducing the amount of space occu- ply customers with new boards or EPROM uct to the field before the competition-a real pied by computing and peripheral devices, chips. Not only does this provide conven- time-to-market advantage and a key benefit and as a result, are implementing console ience for their installed base of customers, it for their customers.

18 Success Story Xilinx IRL

Flexibility and High Throughput In most customer environments, the console ...due to the ability to remotely upgrade the design over switch is located in the same facility as the servers, but with the flexibility offered by the Internet, the engineers were able to ship the Xilinx FPGAs, the console can be located anywhere in the world. With the Apex Emerge2000, for remote access server con- product early, with the assurance that any new features trol, you can manage the graphical consoles of your server population from any location. could easily be added in the field. The basic architecture is based on the PCI bus (Figure 1). By using two Xilinx FPGAs in each Emerge2000, one for PCI commu- the design right up to the time of board Conclusion delivery. Once the boards became available, nications that is loaded at power-up and Xilinx FPGAs, along with the Xilinx IRL the engineers could load the FPGA configu- remains loaded, and the other FPGA loaded technologies, allows companies like Apex to ration at the work bench and verify the dynamically at run time, Apex console build flexible, next-generation equipment design. If they had used custom ASICs, it switches never have to break the PCI that can be upgraded over the Internet. The would have required much more time to communication. The time to market advantages are obvious and complete the design. In addition, Xilinx PCI core pro- the unique design possibilities are limited due to the ability to remotely vides up to 33 MHz only by your imagination. operation, is easy to upgrade the design over the use, and is easy to Internet, the engineers were migrate to other PCI able to ship the product cores with higher bus widths early, with the assurance that if the need arises. any new features could easily be added in the field. About Apex Xilinx also provides an easy migration path from low to high density devices allowing Technical Support from Xilinx Apex designs, manufactures and Apex to include more robust features in Support from a supplier is a critical path markets stand-alone electronic their console switch products as their item, often overlooked when designers requirements evolve. view supplier technology. Obtaining the switching systems and integrated Rapid Prototype Development most up-to-date information, in a precise server cabinet solutions for the format, can become a critical factor when By employing Xilinx FPGA technology, the moving at the rapid pace our market client/server computing environ- Apex engineers could continue developing demands. The Xilinx support organization ment. Apex supplies stand-alone is fast and responsive, and delivered the lat- est information to Apex engineering, blur- switching systems to some of the ring the lines of distinction between sup- largest PC manufacturers in the plier and customer. industry for integration into their product offerings, providing switching systems to OEMs (Compaq, Dell, IBM, and Hewlett- Packard) representing 43 percent of all PC servers and 66 percent of all “super” servers shipped world- wide.Go to http://www.apex.com Figure 1 - The Emerge2000 board for more information. 19 New Products Cores LavaCORE - A Configurable Java Processor Create Java-enabled appliances, mobile devices, secure Internet devices, and embedded network computers that can be dynamically configured for application-specific computing.

by Bhaskar Bose, Ph.D. and M. Esen Tuna President, Vice President - R&D, Derivation Systems, Inc. LavaCORE Features Some of the features are highlighted below: [email protected], [email protected] The processor core features a 32-bit archi- • 32-bit direct execution Java processor. LavaCORETM is a 32-bit configurable tecture with 32-bit address and data paths. • Executes Java Virtual Machine bytecode in JavaTM processor core targeted to the Xilinx Our reference design is implemented in a hardware. Virtex FPGA architecture. The processor Virtex XCV300 BG352-4 FPGA. Figure 1 • Stand-alone (system on a chip) or core executes Java bytecode directly in hardware shows a block diagram of the architecture. configuration. eliminating the need for software-based interpreters or code translators. LavaCORE is a clean-room implementation of the Java Virtual Machine and is provided as a syn- thesizable “soft-core” with a suite of tools for parameterized core generation, hard- ware/software co-design, co-verification, and custom Java application development. LavaCORE is a revolutionary product that provides unparalleled flexibility for a wide range of prototyping and embedded appli- cations. Direct Java bytecode execution keeps the runtime to a minimum making the processor ideal for embedded applica- tions that require small memory foot-prints Figure 1 - LavaCORE architecture. and flexible reconfigurable architectures. Both the application and the operating sys- tem code can be developed in Java and A 16x32-bit dual-ported RAM implements • Built-in hardware encryption module. compiled to native code by standard Java the register-file. The instruction register is • Fully synthesizable FPGA core. compilers. composed of three 8-bit registers denoting • Parameterized Core Generator automati- LavaCORE is designed to bring embed- the instruction, byte one, and byte two of cally synthesizes VHDL, Verilog, or EDIF ded Java technology to the reconfigurable the instruction stream. A 32-bit ALU com- gate-level netlists. marketplace. The customizable core and putes arithmetic and logical operations. • Software support includes Parameterized dynamic reconfiguration take full advan- Additional signals include clock, reset, signal Core Generator, LavaOS Runtime tage of the features of programmable interrupt, memory interface, and a set of Environment, Co-Simulation/Verification hardware. observability pins for the state and flags. Tools, and Hardware Debugger.

20 New Products Cores

• The instruction tester. LavaRock Processor • The application simulator. External Memory Register • The hardware testbench for the synthesized ALU core. Floating File Point Local Interrupt The hardware interface provides an imple- Unit Memory Controller mentation debugging bridge for the synthe- Garbage sized hardware. The same debugging envi- Programmable Encryption Collector ronment and user interface are used for the Timers Unit testing of the target hardware.

Figure 2 - LavaCORE system architecture. Conclusion The LavaCORE Configurable Java Processor Parameterized Core Generator executables. In addition, the linker builds the core enables the deployment of Java technol- boot tables, class initialization codes, and The LavaCORE Parameterized Core ogy for a new generation of embedded assigns the interrupt and trap handlers. Generator operates via an intuitive graphical reconfigurable systems. Native execution of interface and includes user selectable param- The executable image incorporates the run- Java bytecode provides reliable hardware exe- eters for a wide range of configurable time environment. It is designed for embed- cution, denser code, and minimum runtime options. Every implementation of ded applications and is small enough to be environment. The LavaCORE parameter- LavaCORE can be application specific, lead- implemented in the internal block RAM. In ized core generator allows you to configure ing to optimal solutions in terms of power, a standalone configuration, the LavaCORE the capabilities of the processor core and syn- speed, and area. system architecture can incorporate the thesize an optimal LavaCORE for your application. Typically, specialized embedded applications entire runtime environment and a Java appli- use only a subset of the full JVM instruction cation within the Virtex block RAM. LavaCORE provides a fast design solution set. By analyzing the application, you can Application Debugging Tools for embedded Java processors targeted to determine which Java bytecode instructions programmable hardware. With our config- can be omitted or moved from hardware to The LavaCore application debugging tool set urable Java processor core and co-design/ver- software, improving various cost criteria. consists of a core simulator and a hardware ification environment this unique IP product interface (Figure 3). The simulator has a will reduce design time leading to faster time Additional options allow you to include built-in debugger that features single step- to market. functional components of the synthesized ping, memory and register file monitors, and architecture such as the built-in encryption conditional break points. The simulator and For more information about Derivation engine, programmable timers, and interrupt the debugger share a graphical user interface Systems, or the LavaCORE products, see controllers. For larger systems, floating point to display and debug the LavaCore execution www.derivation.com and external memory interfaces are defined both at instruction and micro steps. (Figure 2). LavaCORE and LavaOS are trademarks of The LavaCore simulation environment con- Derivation Systems, Inc., JAVA is a registered Once parameterized options are selected, the sists of three separate components that vali- trademark of Sun Microsystems, Inc. LavaCore Generator automatically synthe- date all three aspects of the LavaCore: sizes a gate-level implementation in either VHDL, Verilog, or EDIF netlist formats. Along with this softcore, an HDL testbench and a customized runtime called LavaOSTM are generated. The synthesized core can then be directly input to Xilinx Foundation Series or Alliance Series software for place and route. The HDL testbench is used both to test the hard- core and softcore. Figure 1 depicts the dataflow architecture of a LavaCore instance. Linker/Application Builder Standard Java-class files, generated from third party commercial Java development Figure 3 - LavaCORE design environment. environments, are statically resolved to build 21 Applications Software Inferring Read Only Memory in FPGA Compiler II and FPGA Express

by Alan Ma Senior Corporate Applications Engineer, Synopsys, Inc. [email protected]

Prior to the recent advancements in FPGA Verilog and VHDL, and by using constant General Implementations technology, you had to rely on external arrays in VHDL. RAM or ROM. Now, with the introduc- FCII/FE generally implements ROM using Using CASE Statements LUTs, MUXF5s, and MUXF6s when tar- tion of million-gate FPGAs such as the geting Xilinx Virtex devices. The actual Xilinx Virtex devices, you have access to FCII/FE infers ROM when the inputs to resources used are closely related to the abundant on-chip memory resources. the CASE statement are constant and all width of the address port. If the address has FPGA Compiler II/FPGA Express the states are specified. Figure 1 shows an less than or equal to four bits, then the (FCII/FE) takes advantage of Virtex example of an 8x4 ROM in Verilog. Figure ROM will be implemented using LUTs. If resources such as Look-Up Tables (LUTs) 2 illustrates its VHDL equivalent. the address has five bits, then MUXF5s, MUXF5s, MUXF6s, and on-chip block Using Constant Arrays (which provide multiplexer functions in SelectRAM to provide the highest quality one half of a Virtex Configurable Logic of results for ROM functions. You also have the option of using constant Block), will be used in addition to the arrays in VHDL. Figure 3 describes the Coding Styles LUTs. If the address has between six to coding style for the same 8x4 ROM where nine bits, the ROM will be implemented Version 3.4 of FCII/FE recognizes a ROM CONV_INTEGER is a built-in function that using LUTs, MUXF5s, and MUXF6s description using CASE statements in both converts std_logic_vector to integer. which provide multiplexer functions in a 22 Applications Software

module rom_8x4 ( address, rom_out ); full Virtex CLB. When the address has ten or more bits, FCII/FE

input [2:0] address; implements ROM using on-chip block SelectRAM resources if certain output [3:0] rom_out; conditions are met. reg [3:0] rom_out; Using Block SelectRAM always @(address) case (address) The Virtex series provides dedicated blocks of on-chip, dual port syn- 3’b000 : rom_out <= 4’b0001; 3’b001 : rom_out <= 4’b0010; chronous RAM, with 4096 memory cells (bits). These resources can 3’b010 : rom_out <= 4’b0100; also be used for ROM if certain conditions are met. Our research indi- 3’b011 : rom_out <= 4’b1000; 3’b100 : rom_out <= 4’b1000; cates that when the address of the ROM has ten bits and the data has 3’b101 : rom_out <= 4’b0100; 3’b110 : rom_out <= 4’b0010; more than or equal to three bits, quality of results can be improved by 3’b111 : rom_out <= 4’b0001; mapping the ROM to block SelectRAM if the output of the ROM is endcase endmodule registered. However, if the data has less than or equal to two bits (when the address has ten bits), using LUTs, MUXF5s, and MUXF6s, as Figure 1 - Using CASE statements for ROM in Verilog. described in the previous section, yields better results. For ROM whose address has more than or equal to eleven bits, block SelectRAM will library ieee; always be used if the output is registered. Table 1 summarizes the con- use ieee.std_logic_1164.all; ditions for ROM inference. entity rom_8x4 is port ( address: in std_logic_vector(2 downto 0); To reserve block SelectRAM for user-defined functions, you can use output: out std_logic_vector(3 downto 0) ); the scripting command “set_chip_instantiated_blockram”. For exam- end rom_8x4; ple, the following reserves 4096 bits of block SelectRAM for architecture rtl of rom_8x4 is inferred ROM: begin process (address) begin set_chip_instantiated_blockram 4096 case address is when "000" => output <= "0001"; While set_chip_instantiated_blockram applies to the current project, when "001" => output <= "0010"; when "010" => output <= "0100"; you can use the variable proj_user_instantiated_blockram to reserve when "011" => output <= "1000"; when "100" => output <= "1000"; block SelectRAM globally for all the subsequent projects. For exam- when "101" => output <= "0100"; ple, the following reserves 4096 bits of block SelectRAM for all when "110" => output <= "0010"; when "111" => output <= "0001"; future projects: when others => output <= "0000"; end case; proj_user_instantiated_blockram 4096 end process; end rtl; Conclusion Figure 2 - Using CASE statements for ROM in VHDL. Inferring ROM is easy with FPGA Compiler II and FPGA Express, which take full advantage of the abundant on-chip memory resources library ieee; of the Xilinx Virtex devices. use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; Visit the Synopsys FPGA website at www.synopsys.com/fpga for other entity rom_8x4 is port ( information on the latest FPGA synthesis technologies. address: in std_logic_vector(2 downto 0); output: out std_logic_vector(3 downto 0) ); end rom_8x4; LUT MUXF5 MUXF6 SelectRAM architecture rtl of rom_8x4 is

constant num_word : integer := 8; ADD <= 4 Bits Any Data Width constant num_bit : integer := 4; signal int_add : integer range 0 to 7; type ROMARRAY is array (0 to (num_word-1)) of ADD = 5 Bits Any Data Width std_logic_vector((num_bit-1) downto 0);

constant ROM: ROMARRAY := ( 6 Bits <= ADD <= 9 Bits Any Data Width "0001", "0010", "01 00", ADD = 10 Bits 1 Bit <= DATA <= 2 Bits "1000", "1000", "0100", ADD = 10 Bits* DATA >= 3 Bits* "0010", "0001" ); ADD >= 11 Bits* Any Data Width* begin int_add <= CONV_INTEGER(address); output <= ROM (int_add); Table 1 - LUTs, MUXF5s, MUXF6s, and block SelectRAM utilization. end rtl; * Note that LUTs, MUXF5s, and MUXF6s will be used if the output of the ROM is not registered. Figure 3 - Using constant arrays for ROM in VHDL. 23 Applications Software Using Block-Level Incremental Synthesis in FPGA Compiler II and FPGA Express

Block-Level Incremental Synthesis allows you to modify a subset of a design and then re-synthesize just the modified subset.

by Alan Ma Senior Corporate Applications Engineer, Synopsys, Inc. modified netlists. Not only does this increase design will have three blocks: the likelihood of preserving post place-and- [email protected] • Block 1: TOP, B, F route timing behavior for the unmodified Advancements in the capacity and speed of blocks, overall compilation time for both • Block 2: A, C, D FPGAs have made this technology increas- synthesis and place-and-route is significantly • Block 3: E ingly attractive for million-gate designs. As reduced. the complexity of the designs grows so does Any modifications to any module/ Identifying Blocks the need for advanced synthesis and place- entity/netlist contained in a block cause the and-route tools. One of the highly sought A block is the smallest subset to which BLIS entire block to be re-synthesized. For exam- features is the ability to recompile only the can be applied. It can be a Verilog module, a ple, if F is modified then every member of modified portion of a design after modifica- VHDL entity, an EDIF netlist, or a combi- Block 1 (TOP, B, F) will be re-synthesized tions have been made. Such a feature is need- nation of these, as long as they form a tree even though TOP and B have not been ed not only to reduce compilation time, but within the design hierarchy. The top-level changed. also to preserve the timing behavior of cer- module/entity/netlist of this tree is, by defi- Blocks can be identified in both the tain sections of a design when other sections nition, the block root. The components of a Graphical User Interface (GUI) and the shell of the design are changed. block include the block root and all mod- of FCII/FE. In the GUI, right-click an elab- ules/entities/netlists in its tree of the design To address these requirements, FPGA orated implementation in the Chips window hierarchy that do not include another block Compiler II and FPGA Express (FCII/FE) and select Edit Constraints. Select the Modules version 3.4 introduce Block-Level root. Incremental Synthesis (BLIS) to allow you to For example, the top- Block 1 = Block Root modify a subset of your design and then re- level design “TOP” in TOP synthesize just the modified subset. A design Figure 1 has two subde- can be divided into “blocks,” the smallest signs A and B. A instanti- Block 2 A B subset to which BLIS can be applied. ates C and D. B instanti- FCII/FE generates an optimized netlist for ates E and F. By defini- each block, which does not change unless the tion the top-level design CDE F design associated with that block has been TOP is a block root. If Block 3 modified. The netlist of each block is then you also decide to desig- presented individually to the place-and-route nate A and E as block tool which is capable of recompiling only the roots, then the entire Figure 1 - Example of blocks and block roots

24 Applications Software tab to display the Modules Constraint Table. Error: Cannot set block option on module ‘AND’ for being in the same design source file as A. You can then specify any subdesigns as block The newer time stamp of B causes the entire Furthermore, the concept of block and block roots in the Block Partition column. To Block 1 to be re-synthesized. Needless to say, root only applies when the target architecture remove a block root designation, click the this is not a desired behavior. supports BLIS. Attempting to apply this fea- particular cell and select Remove. Note that ture on an architecture which is not support- It is obvious that BLIS is not useful the top-level design is always identified as the ed by BLIS will result in the fol- in the extreme case where all modules/enti- lowing error message: ties/netlists are described in a single design Error: block assignments are not source file. supported for the target technology Since FCII/FE does not incrementally opti- of this chip mize across block boundaries it is important not to break combinatorial logic into differ- BLIS is currently available for ent blocks. For best QoR, it is recommend- the Xilinx Virtex architecture. ed to observe conventional Register Transfer Design Planning Level (RTL) coding style when partitioning The advancement in synthesis designs. This involves grouping related com- and place-and-route technolo- binatorial logic within a module/entity and gies certainly plays an important registering all outputs of such a module/enti- role in Quality of Results (QoR) ty. but thorough design planning Note that BLIS is most effective when mod- Figure 2 - Modules Constraint Table can never be replaced. In order to ifications are done within a module/entity. take full advantage of BLIS it is important to Changing the partition or the pins of the block root by definition and it cannot be understand that: modules/entities of the design causes the removed. Figure 2 shows the Modules entire design to be re-synthesized. This is Constraint Table. • FCII/FE uses a time stamp to determine if an implementation is out-of-date. If the why thorough planning in the early stage of In the shell, use the command time stamp of any of the analyzed design the design process is vital to success. set_module_block followed by the option source files is newer than the elaborated Implementation Update “true” and the path to the implementation then the elaborated imple- This section describes what needs to be done module/entity/netlist to be specified as the mentation needs to be updated. block root. For example: in the GUI and the shell to update an imple- • A block is the smallest subset to which mentation after a design has been modified. fc2_shell/fe_shell> set_module_block true BLIS can be applied and any changes in It is assumed that blocks have been defined /TOP/A any member of a block cause the entire as described previously, an optimized imple- In the interactive mode, you can remove any block to be re-synthesized. block root designations by using the “false” • A block represents Block 1 = Block Root TOP option. For example: “hard” boundaries which fc2_shell/fe_shell> set_module_block false FCII/FE does not opti- Block 2 /TOP/A mize across. A B In the batch mode, the same can be achieved Therefore it is recommend- ed that each module/enti- simply by removing the set_module_block CDE F commands associated with the block roots to ty/netlist in a design be Block 3 be removed in the fc2_shell or fe_shell scripts. described in its own design source file. Doing so set_mod- Figure 3 - Example of design planning Please refer to the man page of ensures that modifying a ule_block for additional usage and syntax module/entity/netlist will not affect the time mentation has been created, and place-and- information. To access the man page: stamp of other modules/entities/netlists route netlists have also been generated. For fc2_shell/fe_shell> man set_module_block which could potentially be members of those who are not familiar with the synthesis other blocks. Block roots can only be designated on user- process of FCII/FE, please refer to the FPGA created modules/entities/netlists. For exam- In Figure 3, A and B are described in the Compiler II/FPGA Express Getting Started ple, attempting to modify the setting on a same design source file. Modifying A not manual for step-by-step instructions. primitive or the top-level design will result in only causes the entire Block 2 to be re-syn- In the GUI, a red question mark next to a the following error message: thesized, it also affects the time stamp of B design source file in the Design Sources

25 Applications Software

window indicates that the file has been the interactive mode. Please refer to the least two defined blocks, and any change modified. Right-clicking the modified file man pages for complete usage and syntax of block roots. Other operations, such as and selecting Update File reanalyzes the file information. modifying timing constraints, do not for syntax errors. cause block-level incremental re-synthesis Limitations of the implementation. Similarly, a red question mark next to an As mentioned previously, time-stamping is elaborated implementation in the Chips win- Conclusion used to determine if an implementation is dow indicates that the implementation is out-of-date. FCII/FE processes time FPGA Compiler II and FPGA Express ver- out-of-date with respect to its design source stamps in whole seconds. If both analysis sion 3.4 introduce Block-Level Incremental files. Right-clicking the elaborated imple- and elaboration finish within one second, Synthesis allowing you to modify a subset of mentation and selecting Update Chip re-elab- then the analyzed design source files and a design and then re-synthesize just the mod- orates the implementation. the elaborated implementation will have ified subset. They generate an optimized Once the design has been re-elaborated, the same time stamp. When the time netlist for each block and the netlist of a right-clicking the optimized implementation stamp of the elaborated implementation is block does not change unless the design asso- and selecting Update Chip re-optimizes the older than or equal to the analyzed design ciated with that block has been modified. design. If blocks are properly defined as source files, the existing elaborated imple- The place-and-route tools that support described previously, BLIS will be automati- mentation is discarded and re-elaborated block-level incremental place-and-route are cally enabled. In this situation only the upon Update Chip or Update Project. The able to recognize and recompile only the blocks that are associated with modified files new elaborated implementation will then netlists that have been changed. Not only are re-optimized. Note that there has to be at have a newer time stamp than the existing does this increase the likelihood of preserving least two blocks defined to enable BLIS. optimized implementation. This causes post place-and-route timing behavior for the the existing optimized implementation to Instead of individually updating the design unmodified blocks, overall compilation time be discarded and re-optimized when actu- source files, the elaborated implementa- for both synthesis and place-and-route can ally none of the design source files have tions, and the optimized implementations, be significantly reduced. you can update the entire project in one been modified. Because designs in general step by right-clicking the project icon in the take longer than one second to be analyzed Design Sources window and selecting and elaborated, this limitation should not Please visit http://www.synopsys.com/ Update Project. It is important to under- present any problems. products/fpga/ for the latest in FPGA synthesis technology. stand that FCII/FE generates one netlist in Note that BLIS is driven only by the dif- EDIF format for each block defined. The ference in time stamps, the existence of at names of the netlists are the same as the module/entity/netlist name of the respec- create_project TOP tive block roots. Performing an Update Project add_file -library WORK -format VHDL c:/designs/top/TOP.vhd ensures that only the netlists associ- add_file -library WORK -format VHDL c:/designs/top/A.vhd ated with modified blocks are regenerated. add_file -library WORK -format VHDL c:/designs/top/B.vhd Note that explicitly choosing Export Netlist add_file -library WORK -format VHDL c:/designs/top/C.vhd add_file -library WORK -format VHDL c:/designs/top/D.vhd forces all netlists to be regenerated. This add_file -library WORK -format VHDL c:/designs/top/E.vhd step is therefore only recommended when add_file -library WORK -format VHDL c:/designs/top/F.vhd the design is synthesized for the first time. analyze_file

If Export Timing Specifications is selected in create_chip -name TOP -target VIRTEX -device V800FG680 -speed -6 -frequency 50 TOP the Export Netlist dialog box, FCII/FE gen- current_chip TOP erates a Synopsys Constraint File (.scf) to pass timing constraints entered in FCII/FE set_module_block true /TOP/A to the place-and-route tools. Since the set_module_block true /TOP/B/E Xilinx place-and-route tool does not read optimize_chip -name TOP-Optimized .scf directly, the information in this file export_chip -dir . must be transferred to a User Constraint File (.ucf) for timing constraints to be con- # design has been modified sidered during place-and-route. update_project

Figure 4 shows a sequence of equivalent list_message fc2_shell/fe_shell commands to be used in Figure 4 - fc2_shell/fe_shell commands

26 Success Story Virtex FPGAs

or Gigabit Ethernet. This provides net man- agers an obvious migration path. By mid- Lucent Technologies Gets a 2000 even more capable 80-series boards will become available and can be deployed beside the 50-series boards in the same Time-to-market Advantage P880 chassis. The P880’s backplane scales upward from When Lucent Technologies set out to design the Cajun P880 Routing Switch, designers quickly 56 Gigabits per second to 139 Gigabits per determined that a traditional ASIC design would require too much time. second providing the P880 with the capabil- ity of switching or routing from 41 to 106 by Tamara Snowden million packets per send. Designed with no Corporate PR Manager, Xilinx single point of failure, the highly reliable Cajun P880 supports up to 768 10/100 [email protected] tem gates at clock speeds up to 200 Mhz and megabits per second Ethernet ports, up to include many new features that address sys- The Cajun P880 Routing Switch is the 384 fiber Fast Ethernet ports, and up to 128 tem-level design challenges. Fully supported newest member of Lucent’s next-genera- Gigabit Ethernet ports in a fault-tolerant, by the Alliance Series software, the Virtex tion, enterprise data networking solutions modular chassis. that provide network managers with an family offered a complete solution for easy and flexible way to optimize their net- Lucent, ready to meet the design challenges The P880’s switching fabric consists of six work designs; it had an for their groundbreaking switch elements, each using two XCV150 extremely aggressive devel- product. devices for a total of 12 per chassis. The con- troller used a single XCV800 device. The opment schedule. “By going with Xilinx The Software Solution design allows for high redundancy to maxi- “We originally designed the we were able to ship Lucent’s design team chose mize reliability. A second backup controller is P880 with an ASIC at the the P880 months earlier Synopsys FPGA Express for optional with the P880, while a seventh heart of the switching fab- synthesis, VCS for a Verilog switch element can be added for redundancy. ric,” said Brian Ramelson, than we would have with simulator, and Xilinx Alliance Ramelson estimates a typical place and route design manager at Lucent. Series tools for place and for the controller took just about two hours. “We soon realized that if we a traditional ASIC design” route. Ramelson especially Conclusion stuck with an ASIC design, appreciated the ability of the the product would be late Alliance Series software to per- Ramelson notes this was a far different expe- to market.” Ramelson had recently attended form multi-pass timing-driven place-and- rience from the last time he worked with an a Xilinx Virtex series presentation and decid- route. “If a layout initially failed to meet tim- FPGA. “The element that best represents ed to contact Xilinx personnel to find out ing requirements, we let the system work on the success of this program was how fast we more. the problem,” said Ramelson. “In one case were able to complete the design. End to we let the software perform about twenty As a result, a close working relationship end the design process was completed with- successive iterations over a weekend resulting developed between Ramelson and John in six weeks—we had a working model in in two or three workable layouts.” DePapp, Xilinx field applications engineer, about a month.” over the next several weeks. The two spent The Alliance Series provides the flexibility to Because of the breadth of its capabilities, the over 100 hours working together on the select the best EDA design environment for P880 spans both the “internetwork” and project. “The design process went very a specific application. Combining the “wiring-closet” market sectors. This makes smoothly,” said Ramelson “the support pro- advanced implementation technology of the Lucent switch a potent competitor. But vided by DePapp was second-to-none.” Xilinx with the strengths of its partners pro- specs mean little unless you can deliver prod- vides a powerful overall design solution, the Virtex FPGAs - a Test Case uct on time and that was where Xilinx highest clock performance and the highest FPGAs entered the picture. “By going with Ramelson’s team selected the Virtex densities in the industry. Xilinx we were able to ship the P880 months XCV150 and XCV800 FPGAs to supply the The Cajun P880 Switch earlier than we would have with a tradition- functions they needed. “At the time we were al ASIC design,” concluded Ramelson. skeptical that any FPGA could implement The 17-slot Cajun P880 is a major step up these functions,” said Ramelson. “We decid- from Lucent’s P550 7-slot switch, although ed to try Xilinx FPGAs for this project as a the two share a common architecture. The More information on the test case for future designs.” The Virtex series P880 can use any of the company’s existing Cajun P880 can be found at devices range from 50,000 to 1,000,000 sys- 50-series boards for Ethernet, Fast Ethernet, http://www.lucent.com/ins/products/p880/ 27 New Products Cores NewNew HDLCHDLC andand ADPCMADPCM CoresCores A strategic partnership with ISS produces advanced communications products.

by Katie DaCosta IP Product Marketing, Xilinx [email protected] extensive IP portfolio for the latest Xilinx ships provides a perfect environment to devices including Virtex, Virtex-E, and expand the usage of ISS cores in wireless To help our customers reduce design cycles Spartan-II FPGAs, as well as future FPGA and wired communications, and digital and get products to market quickly, Xilinx families. Xilinx will deliver these video and imaging applications. With this and ISS (Integrated Silicon Systems, Ltd.) LogiCORE products using the Xilinx agreement, Xilinx can now fully utilize our have entered into a strategic development expertise in multimedia communications to and OEM agreement to provide versions of provide the highest-performance, ISS multimedia and communications cores off-the-shelf design solutions optimized for Xilinx FPGAs. The IP available in the market.” cores will be available for purchase from Xilinx as LogiCORE products, “ISS has achieved industry-wide downloadable from the Xilinx IP recognition for solving the needs of Center, and optimized for Xilinx the communications and multimedia architectures and design tools. The user community,” said Mark Aaldering, senior director for the IP Solutions Division cores in this program include CORE Generator tool to smoothly inte- at Xilinx. “By partnering with ISS, Xilinx is Single-channel HDLC, 32-channel grate the cores into the Xilinx design flow. HDLC, and 32-channel ADPCM, and are able to address the demand for a one-stop available now. “This agreement broadens our long-term source of high-quality, cost-effective, opti- and successful relationship with Xilinx,” mized FPGA cores. This agreement A Strategic Alliance said James G. Doherty, CEO of ISS. “The expands the successful long-term relation- The deliverables of this agreement are opti- strength of the Xilinx Virtex architecture ship between ISS and Xilinx, which started mized and supported cores from ISS’s coupled with their commitment to partner- with membership in the Xilinx 28 New Products Cores

AllianceCORE third party IP develop- HDLC Cores Conclusion ment program and the co-development The HDLC cores conform to the ITU The strategic partnership between Xilinx partnership for Reed-Solomon Forward Q.921 and X.25 recommendations for full and ISS is already producing optimized Error Correction cores. The agreement duplex, point-to-point and multi-point cores for the communications market, reinforces the Xilinx commitment to pro- operation. The cores function at data rates and many more are on the way. Xilinx con- viding leading-edge IP for multi-million over 40 Mbps and include a direct connec- tinues to provide the most advanced FPGA gate FPGA designs.” tion to pulse code modulation (PCM) net- and IP technologies to help you create the The New Cores works. The HDLC cores are ideal for pub- next generation of high performance equip- The first three cores to result from the lic and private packet switched data net- ment and get your products to market as Xilinx-ISS agreement are focused on accel- works such as Frame Relay switches, cable soon as possible. erating the design cycle of high-density modems, Broadband ISDN, T1/E1, FPGAs in communications applications. T3/E3, Packet-based DSL Access Multiplexers (DSLAMs), Remote/multi- service access concentrators, and Sonet net- ”The strength of the Xilinx Virtex works. About ISS architecture, coupled with their ADPCM Cores Integrated Silicon Systems Ltd. (ISS) is The 32 Channel ADPCM speech codec the leading supplier of application-spe- commitment to partnerships, performs the ITU G.726 conversion of 64 kbit/s A-law or µ-law PCM channels to and cific virtual components (ASVCs) for provides a perfect environment from 40-, 32-, 24- or 16-Kbit channels multimedia and communications using the Adaptive Differential Pulse Code to expand the usage of ISS cores Modulation transcoding technique. The FPGA, ASIC, and System-on-a-Chip core supports up to 32 duplex (SoC) integrated circuits. ISS delivers in wireless and wired communi- encoding/decoding channels or up to 64 encoding and/or decoding channels, and video/image compression, audio com- cations, and digital video and can operate in burst or continuous modes. pression, and channel coding solutions It is on-line configurable for A-law or µ-law for consumer and communications imaging applications.“ PCM encoding as well as various ADPCM compression rates including G.721 or applications. Using proprietary tech- G.723 mode operation. The ADPCM niques for direct-mapped implementa- codec will be used in applications such as The HDLC (High-level Data Link CO DSLAMs, satellite communications, tions of digital signal processing func- Control) protocol controller cores and the digital audio storage, H.323 VoIP gateways, tions and algorithms in hardware, ISS ADPCM (Adaptive Differential Pulse Code access servers, and computer telephony and Modulation) codec core are used in a num- cellular networks where high quality voice delivers solutions that realize 10X to ber of telecom applications ranging from compression is important. 1000X improvements in performance internet routers and switches to VoIP (Voice over Internet Protocol) gateways. Availability compared to conventional implementa- “The Xilinx HDLC and ADPCM The HDLC and ADPCM cores are avail- tions using software-programmable LogiCORE products address the exploding able now. Suggested resale pricing is $7,200 DSP microprocessors. ISS is a private- demand from telecom and network devel- for the 32 Channel HDLC controller core, opers for complex Virtex-based IP for data $3,900 for the Single Channel HDLC con- ly held company with European head- and voice processing,” said Babak Hedayati, troller core, and $14,400 for the 32 Channel quarters in Belfast, Northern Ireland, Director of Marketing and Business ADPCM codec core. Licensing information Development at Xilinx IP Solutions and instructions for downloading the cores, UK and worldwide sales and marketing Division. “The HDLC protocol is proven as and information on all Xilinx LogiCORE operations in San Jose, California. one of the most popular methods of trans- products can be found at the Xilinx mitting data over WAN systems. The avail- IP Center at: www.xilinx.com/ipcenter. More information about ISS and its Information on other Xilinx LogiCORE ability of these cores on the Xilinx IP Center products may be obtained at provides a one stop source to integrate tele- and third-party AllianceCORE products is com IP solutions into Xilinx FPGAs.” also available from the IP Center. http://www.iss-dsp.com 29 New Products Cores

MovingMoving thethe M8051EwarpM8051Ewarp ASICASIC CoreCore toto aa VirtexVirtex FPGAFPGA Mentor Graphics implements their M8051EwarpTM core in a Virtex FPGA.

by Kevin Rowley Design Engineer, Mentor Graphics - IP division [email protected] ASIC gates is to envelope the synthesized The most important point about Figure 1 core in a wrapper which has instantiated all is that all memories are on-chip, which There is an ever increasing demand for the necessary components for simulation of means there are no I/O pads between the digital IP cores that have been proven in the core. These components typically are M8051Ewarp core and its memory mod- FPGAs as well as ASIC test silicon. This is program memory, data memory, and extra ules, and thus delays on inputs and outputs due to the obvious prototyping advantages peripherals. However, after FPGA place and to and from memory are avoided. The test and increasing market share of FPGAs. route the core will have I/O pads on its code for the core is contained in the In this article I explain the strategy we interface. Program ROM. Also shown are the data used and the results we obtained when memory RAM block and the internal data implementing the Mentor Graphics The delays inherent in these pads preclude memory (IRAM). The peripherals are the M8051EwarpTM core, which was originally the usual ASIC test method and a new syn- wait-state generator necessary for the test created for ASIC development, in Xilinx thesizable wrapper is required which, after suite and the External Special Function VirtexTM technology. place and route, will have the M8051Ewarp Registers (ESFRS) also needed by the test core, memories, and required peripherals in Test Strategy suite. a single netlist which can then be simulated. The usual method we use to prove the The synthesizable wrapper we used is illus- Data captured from the wrapper is written functionality of the M8051Ewarp core in trated in Figure 1. to a simulation-listing file for comparison

30 New Products Cores

The CORE Generator then generated an EDIF netlist with this .COE file for the ROM; it also generated EDIF netlists for the RAM modules. The EDIF netlists would be dragged-in later at the place and route stage for the wrapper. Synthesis Strategy

We used Mentor Graphics LeonardoTM for synthesis. The target operating speed of the M8051Ewarp core in the Virtex FPGA was 30 Mhz. Therefore, the synthesis con- straints were setup accordingly. The part we targeted was the XCV200BG352. To syn- thesize the wrapper we first synthesized the M8051Ewarp core separately and then read it in, during the synthesis of the wrapper, as a separate file. Wrapper Synthesis Figure 1 - Test setup for the core. For synthesis, all the memory modules are treated as “black boxes.” In addition to producing an EDIF file of the synthesized wrapper for place and route, synthesis also to reference listings. The test bench is a • .MIF file - Requires a line for each ROM produced an .NCF file which Xilinx place self-checking type which will setup and ini- location but also each byte has to be in and route uses to determine the timing tialize the M8051Ewarp core and then binary format. constraints of the circuit. The timing check the program execution (using the • .COE file - Allows the ROM locations to analysis by Leonardo produced the follow- test program stored in ROM). be specified in hex format. ing results: Memory Requirements Because the .COE format is closer to Intel Successful simulation of the system test hex format we decided to use a .COE file Clock Frequency Report to specify the ROM. First however it was suite required the following memory : Clock : Frequency necessary to write a special program which • 4k bytes of synchronous ROM. ------would take the Intel hex format file for the SCLK : 33.8 MHz • 1k bytes of synchronous single-port test opcodes and convert it into a .COE file CCLK : 33.4 MHz RAM. for the CORE Generator. PCLK : 33.4 MHz • 256 bytes of dual-port synchronous The final COE file looked like the follow- RAM. ing (abridged) : Critical Path Report

The CORE Generator tool from the Xilinx There are no paths that violate user specified 2.1i Alliance Series software suite was used Component_Name=crom; options or constraints to design and generate the memory mod- Data_Width=8; And the expected area utilization report: Depth=4096; ules. ****************************************** Radix=16; Specifying Memory Contents Device Utilization for v200bg352 Default_Data=0; ****************************************** The RAM cores had all their contents ini- Memory_Initialization_Vector = Resource Used Avail Utilization tialized to zero by the CORE Generator, 01, ------80, IOs 97 260 37.31% however the ROM module had to have test Function Generators 3653 4704 77.66% 00, opcodes stored in it for simuation. There CLB Slices 1827 2352 77.68% c2, are two ways of specifying ROM contents Dffs or Latches 653 4704 13.88% with the CORE Generator: a8, ------... 31 New Products Cores

This shows that the wrapper fitted into the in the .NCF file generated from wrapper We found that the maximum speed with XCV200 device and, according to synthesis. Some effort was needed to the netlist was 31.25 Mhz. Above this Leonardo, was expected to run correctly at examine all violating paths from “trce” speed the setup time required for PROGA 30 Mhz. and make sure they were path exceptions. feeding into the ROM was being violated; Place and Route of the Wrapper Because several runs were required to pass static timing during synthesis and place and route, it was necessary to automate the place and route stage using the following script :

ngdbuild -p v200bg352-6 ewarp_f.edf ewarp_f.ngd

map ewarp_f

par -d 1 -ol 5 -pl 5 -rl 5 -w ewarp_f Figure 2 - Waveform view. ewarp_f_out.ncd ewarp_f.pcf

trce ewarp_f_out ewarp_f.pcf -v 3 -o Verification PROGA was becoming valid too late ewarp_f_out before the next clock cycle. Illustrated in Figure 2 is a waveform view ngdanno ewarp_f_out ewarp_f.ngm of the M8051Ewarp core cycling through Conclusion ngd2ver ewarp_f_out -w the test code stored on ROM at 30 Mhz. We successfully placed and routed a com- The file ewarp_f.edf is the EDIF file for Program opcode can be seen coming plete M8051Ewarp core plus memory and into M8051Ewarp core on the PROGDI the wrapper after synthesis. Note “ngdan- peripherals on a Xilinx Virtex device and input. The program address is shown in no” produces the SDF file which must be got it to work at speeds up to 31.25 Mhz. signal PROGA. The test code was setup by back-annotated with the FPGA netlist for The key to our success was using the on- the COE file at ROM generation. gate-level simulation. The “ngd2ver” pro- chip memory of the Xilinx part, and using gram produces a verilog netlist of the Running the complete simulation through the Xilinx CORE Generator software to SimPrims primitives for verilog gate-level 4k bytes of test code results in 12100 vec- design the memories. Synthesis was per- simulation. The FPGA device utilization tors. If the core has simulated correctly, it formed by Leonardo and the post-synthe- figures we achieved are detailed in the out- will finish at PROGA equal to FFF hex. If sis EDIF netlist of the M8051Ewarp put file from the “par” program: there has been a problem then the simula- wrapper was placed and routed by Xilinx tion will not reach program address FFFh 2.1i Alliance Series software. The resulting Device utilization summary: and it will be stuck in a loop at an earlier verilog netlist and SDF file, after place program address and will terminate after a and route, ran through the test suite suc- Number of External GCLKIOBs 3 out of 4 75% certain time-out period. cessfully at the required speed. Number of External IOBs 94 out of 260 36% The output delays on some of the Number of BLOCKRAMs 11 out of 14 78% M8051Ewarp core output ports exceeded Number of SLICEs 2073 out of 2352 88% the strobe period at 30 Mhz. Usually core For more information on the outputs are strobed out to a listing file M8051Ewarp core see the Number of GCLKs 3 out of 4 75% twice per clock cycle, the strobe period Mentor Graphics website at: Number of TBUFs 16 out of 2464 1% being just less that half a clock cycle. www.mentor.com/inventra/ Therefore, since some output delays The “trce” program listed static timing exceeded the strobe period it was not possi- 8051e_warp.html information and constraints applied for ble to do a straight unix “diff” between the place and route. This produced a lot of vio- Virtex netlist simulation listing and the ref- lations on paths which upon closer inspec- erence listing for this test. However inspec- tion turned out to be multi-cycle path tion of the listing file from simulation and References exceptions. This was because multi-cycle comparison with the assember code listing path exceptions setup for the for the test showed the circuit to be func- [1] ASIC/FPGA market share , M8051Ewarp synthesis were not included tioning correctly. www.xilinx.com, June 2000

32 Product Focus Software

Xilinx WebPACK Software A complete design environment, including simulation, for Xilinx Now Includes ModelSim CoolRunner and XC9500 CPLDs... by Anita Schreiber Staff Applications Engineer, Xilinx and CPLD fitter modules of WebPACK and XC9500 CPLDs, leads you through a [email protected] and the MXE backPACK module results in simple and complex design example using Simulation is one of the keys to creating a tight integration between WebPACK’s MXE for both functional and post-route fast compact designs, with the least time Project Navigator design environment and simulations. XAPP338 is available on the and effort. Now you can simulate your MTI’s simulation tools. WebPACK is avail- Xilinx website at: functional and post-route VHDL and able at: www.xilinx.com/products/soft- www.xilinx.com/xapp/xapp338.pdf. Verilog CPLD designs using the Xilinx ware/webpowered.htm. WebPACK software, which includes the MXE Licensing ModelSim software from Model Technology, Inc. (MTI). Licenses are required for MXE and can be obtained at the end of the installation Using the MTI ModelSim simulator gives process or after the product has been you the ability to use HDL testbenches installed. With either method, your Web which allow you to behaviorally describe browser will be directed to an online license the stimulus for your design. Describing request form. Upon completion of this stimulus behaviorally allows the simulation form, the MXE license and instructions for to more accurately represent the system installing the license will be quickly Figure 1 - MXE backPACK Module. conditions and to vary based on the e-mailed to you. response received by the device. HDL test- benches also enable concurrent stimulation Using MXE with the WebPACK of different functions within the design and Project Navigator can be defined to compare the results from Once you have installed MXE, you can the device with expected results, eliminat- import HDL testbenches into design proj- ing the need to inspect waveforms to insure ects in the same manner as other source that the device is functioning properly. files. When an HDL testbench is selected MTI ModelSim Xilinx Edition (MXE) in Project Navigator, the ModelSim Functional and Post-route simulation The inclusion of ModelSim in WebPACK processes are available as shown in Figure 2. is through an exclusive OEM arrangement You can create simulation command files Figure 2 - ModelSim Simulator processes. between MTI and Xilinx. MTI licenses to (ModelSim “.do” files) as Project Navigator Xilinx a special edition of ModelSim called invokes the MXE simulator, or you can the ModelSim Xilinx Edition (MXE). specify existing .do files. MXE Starter is a free trial version available to Xilinx WebPACK customers that allows Execution of either of the simulator you to run up to 500 debuggable lines of processes results in ModelSim simulating code before performance reductions occur. the design and displaying the specified Upgrades to the ModelSim Personal windows as shown in Figure 3. Edition (PE) and the Elite Edition (EE) are Conclusion available from MTI and both upgrades are compatible with WebPACK. With ModelSim and WebPACK you can quickly and easily create CPLD designs Downloading MXE that work perfectly, the first time. MXE is included in the latest backPACK A detailed application note (XAPP338) module of WebPACK as shown in Figure instructing you on the operation of MXE 1. Downloading the required design entry within WebPACK for both CoolRunner Figure 3 - Resulting ModelSim windows. 33 Innovations Software New WebPACK Integrated Synthesis Environment (ISE)

Free, comprehensive design environment for CPLDs available over the Web.

by Larry McKeogh CPLD Software Sr. Technical Marketing Engineer, Xilinx [email protected] extending design flow functionality. The Xilinx WebPACKTM, the popular Internet- first BackPACK modules introduced were enabled Project Navigator-based CPLD ChipViewer and Model Technology’s design environment just got better. The new ModelSim XE Starter Edition. WebPACK WebPACK ISE release extends your produc- ISE includes updates to these two tools as tivity and performance capabilities even fur- well as offering schematic design libraries for ther with an easier to use design interface use with schematic capture. and greater design control. WebPACK ISE also introduces two new The free WebPACK tool modules include: tools developed by Visual Software Solutions (VSS) for inclusion in Xilinx soft- • Design Entry Module - Provides VHDL, ware: StateCad (www.statecad.com) and Verilog, and ABEL HDL support as well HDL Bencher (www.testbench.com). as schematic capture design entry which is new to WebPACK with ISE. StateCad • Fitter - Fitters for either the XC9500 or StateCad automates the state machine CoolRunner families. design process. It automatically looks for common design problems such as stuck-at- • Programming - For device programming state, conflicting state assignment, and inde- control. In addition, the recently introduced BackPACK modules have been augmented for the WebPACK ISE release. New BackPACK Capabilities Xilinx introduced the concept of a WebPACK “BackPACK,” or productivity enhancement module in April 2000. BackPACK modules are not required for CPLD design completion, but are useful in

34 Innovations Software

into four basic areas allowing as much or as little interaction with the design flow as you want.

1 Greater Control 2 In addition to the improved design environ- ment and new tool integration the CPLD tools are augmented with the following new features and improvements: 3 • XC9500XV output banking support auto- 4 matically assigns device outputs based on the desired output voltage standard. • Improved design analysis included in the fitter and timing reports. • Operating code cleanup and efficiency improvements. • The ABEL language was upgraded to ver- sion 7.3 with the following changes: Figure 1 - Project Navigator design environment. - ABEL-XST synthesis. ABEL designers can now choose ABEL-XST synthesis terminate conditions. Its automated error easily modified to simulate the expected for similar synthesis results with analysis insures that designs are logically design performance. Final waveforms may improved software stability consistent which reduces the simulation be exported as a VHDL or Verilog file for - WYSIWYG Support. New option for requirements and improves product reliabil- use in many popular EDA simulators. The ABEL designers who want to assign the ity. StateCAD automatically produces HDL automatic nature of HDL Bencher allows exact design implementation and not code for synthesis and simulation that elim- test benches to be automatically updated as have the synthesis or fitting tools re- inates manual translation efforts and coding your design changes, thus eliminating stale optimize the design errors. It simplifies complex state machine test cases. Use of HDL Bencher ensures that design allowing you to achieve peak hard- your complex hardware designs are more - True bus notation for ABEL designs ware performance with less effort than robust and up-to-date than if coded manu- • Improved design analysis included in fitter before. ally all in a fraction of the time. and timing reports. HDL Bencher Easier to Use Design Interface • Operating code cleanup and efficiency HDL Bencher is an automatic test bench The upgraded Project Navigator design improvements. generator allowing test benches to be creat- environment, shown in Figure 1, has a new Conclusion ed in minutes. A VHDL or Verilog design look and feel. The basic Project Navigator structure is maintained and WebPACK ISE builds on the success of the includes significant new flexi- original WebPACK with improvements to Time (ns) 0100 200 bility enhancements, allowing the Project Navigator design environment you to fully customize the for improved ease of use. The Xilinx CPLD A[3:0] 1 1 2 design environment. design implementation tool update included B[3:0] 0 1 0 in WebPACK ISE provides design control, Other ease of use improve- while the tight integration of new tools such ADD_SUB 1 0 1 ments (as shown in Figure 1) as ECS, HDL Bencher, and StateCad S[3:0] 102include: extend the WebPACK functionality making 1 - HDL editor integration. WebPACK ISE the industry leader in design file can be imported to HDL Bencher either 2 - Synthesis flow switching. environments available over the Internet. manually or through the Project Navigator 3 - Double-click design process property WebPACK ISE is a modular design tool design environment. HDL Bencher analyzes and options access. available for free from the Internet at the design I/O and creates a default stimulus http://www.xilinx.com/products/software/ waveform for each. The waveform may be 4 - Augmented design processes grouped webpowered.htm. 35 Product Focus CoolRunner

The Smart Card Reader One of the fastest growing uses for Smart Cards is to replace the standard credit card; this has lead to a dramatic increase in portable battery powered Smart Card read- ers. These readers can be used in restau- LowLow PowerPower rants for payment at your table, in taxis and buses for payment on the move, and in on- line Web-based or main street stores. Figure 1 shows the basic components of a Smart Card reader. These functions may also be integrated into cash registers, vend- CoolRunnerCoolRunner ing machines, public pay phones, set-top boxes, mobile phones, utility meters, and many other devices that require an authen- tication or secure payment system.

The functional blocks that make up the CPLDsCPLDs system are: • Main data processing - typically a 16- or 32-bit microprocessor (MCU) for com- putational functions. An Ideal Fit for • Memory - to store data (operating sys- tem, variables, data storage) and micro- Smart Card Readers processor boot code. • Security logic - to aid data encryption. • Card reader interface - for both the Smart Card reader (contact and contactless) and the magnetic card reader. • Keypad and keypad decoder - for enter- ing Personal Identification Numbers Coolrunner CPLDs can be used to implement various functions (PINs) and other data, and the associated logic to decode the input. within Smart Card Readers, and are especially beneficial in handheld, • LCD Display driver - for user feedback. lightweight, battery-powered applications. • Modem and modem interface - for inter- facing to wireless, cellular, and radio modems (usually PCMCIA type). by Karen Parnell small denominations of cash, accumulate European Marketing Manager, medical records, be used as security cards, How it Works High Volume Products, Xilinx [email protected] and can greatly ease on-line buying. Their In a typical consumer transaction: applications and acceptance are increasing Smart Cards are becoming a common part of daily; the American Express® Blue Card now • The merchant inserts the Smart Card our every day lives, and new ways to use this comes with a free Smart Card reader that into the card reader and power is applied technology are being developed at a rapid connects to your PC so you can interrogate to the card. pace. Because they hold more than 100 times your account securely on-line, and you don’t • The reader communicates with the Smart the information contained on a standard have to enter your account details every time Card MCU to perform the card authen- magnetic strip card, Smart Cards can store you purchase from a website. tication cycle.

36 Product Focus CoolRunner

• During the initial read function the Smart • When the transaction is complete the Card interface logic passes the data to the card is ejected and removed. The Smart card reader microprocessor via the security Card reader is then ready for the next logic. (The CoolRunner device is a non- transaction. volatile EEPROM CPLD so it is secure CoolRunner Technology is Key 6mm and reliable and thus ideal for implement- ing security logic and MCU decoding.) The Coolrunner family of ultra low power, low cost CPLDs is ideal for this application. • The card reader instructs the user to enter Not only do the CoolRunner devices con- a PIN via a message on the LCD. The user sume less power than any other CPLD but Figure 2 - CoolRunner XPLA3 64-macrocell 56-pin, enters their PIN via the keypad; this is they come in very small form factor pack- 0.5mm pin pitch Chip Scale package. authenticated by the reader MCU. The ages, such as the 56 pin, 0.5mm pitch Chip PIN is verified by the MCU in the card Scale Package device shown in Figure 2. which compares the PIN stored in it’s CoolRunner devices are available in both RAM with the one presented. If the com- Card reader to be updated in the field, thus 3.3V and 5V versions, enabling Smart Card parison is negative the CPU will refuse to increasing the effective system life. By inte- readers to easily accommodate both the new work. The Smart Card keeps track of how grating all of the logic into a small form fac- 3.3V Smart Cards and the older 5V types. many wrong PINs are entered and if it is tor, ultra-low-power CoolRunner CPLD, over a predetermined number, typically you can dramatically reduce the total PCB three attempts, the card blocks itself against area and number of layers required. any future use. Conclusion The Smart Card market is on the brink of realising its full world-wide potential for cashless transactions, store loyalty schemes, access control systems, medical record cards, identity cards, drivers licenses, and many other applications. This year we will see per- sonal computers shipped with Smart Card readers as standard equipment which will unlock widespread world-wide acceptance of multi-application Smart Cards, and hand- held battery powered Smart Card readers in taxis and buses will become common place. Xilinx high-volume CoolRunner CPLD devices provide you with cost effective solu- tions that retain the traditional PLD time to market advantage but with the added benefit of ultra low power operation, very small form factor packages, and a secure, reliable, Figure 1 - Smart Card reader internal functions. non-volatile process technology.

• When the PIN is verified, the purchase CoolRunner CPLDs are perfect for XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL amount is entered by the merchant and performing the interfacing and the Smart Card is interrogated to see if it Macrocells 32 64 128 256 384 decoding functions in the Smart has enough stored value. If so, the Usable Gates 1000 2000 4000 8000 12000 Card reader. The main CoolRunner amount entered is deducted from the tPD (ns) 5 6 6 7.5 7.5 tasks are the memory interfacing, stored value on the card. fSYS (MHz) 200 166 166 133 133 input/output expansion, keypad Packages 44VQ (32) 44VQ (32) • If it is not an SVC (Stored Value Card) decoder logic, LCD interfacing, (Max. User 48CS (32) *48CS (32) I/Os) 56CP (44) transaction then the amount to be modem interfacing, and interfacing 100VQ (64) 100VQ (80) 144TQ (104) 144TQ (104) debited from the bank account will be to the physical card reader itself. 208PQ (160) 280CS (160) 280CS (216) verified using the modem (wireless, Because they are reprogrammable, cellular, or radio). CoolRunner devices allow the Smart Table 1 - The CoolRunner family of CPLDs. 37 Column Market Analyst

As standard, off-the-shelf products, PLDs can be produced inexpensively, in high vol- umes; there is no delay for production ramp PLDs-YourPLDs-Your Competitive up as is often the case with ASICs which often require a long lead time and added risk. We maintain that time to volume is a more critical concern than time to market EdgeEdge for High Volume for electronic equipment designers and manufacturers today. Designing with standard, off-the-shelf pro- grammable logic devices gives you the key ProductionProduction advantage of flexibility, allowing you to immediately address market demands for high volume production; programmable logic has been proven effective for all appli- cations, not just low volume systems and With a compound annual growth rate of over 29% from 1990 prototyping. to 2000 the PLD industry is one of the fastest growing segments Affordability Meets Desirability of the IC industry. Many factors affect whether a product is viewed by the marketplace as being both desirable and affordable. Figure 1 illustrates by Rebecca Burr market potential, which is the junction rep- Reducing their time to market remains a Director, Market Analysis, Xilinx, Inc. resenting those consumers who desire and key focus for competitive companies. This [email protected] can afford a given product. focus is growing in complexity because of According to the Semiconductor Industry virtual manufacturing and because system Consumers must balance the purchasing Association (SIA), the programmable logic designers are increasing their collaboration power of their income with the cost of a market is forecasted to grow by 42.9% in with suppliers and customers–the steps given product. Purchasing power is affected 2000 to $4.1 billion. To place this in per- required for prototyping, design change, by a broad spectrum of factors. For example, spective, in 1990, PLD shipments of $416 quality testing, and change execution are consumers’ income levels, other expenses, million represented roughly 5% of all logic being further compressed. Programmable and inflation play a large part in determin- devices sold. In the year 2000, PLDs will logic has proven itself a very effective solu- ing purchasing power. At the same time, account for more than 14% of all logic tion for dealing with these challenges by they must rationalize the cost of ownership devices sold. This tremendous market helping companies deliver products to of a product (maintenance, and so on) and expansion only further reinforces the market as fast as possible. any ongoing usage costs. Therefore, a prod- growing acceptance and viability of PLDs uct must offer a high level of utility through Time-to-Volume Advantages as a system design standard. Fueling this features and performance. The combination explosive growth are several industries Winning companies must not only devel- of product appeal and practicality equates to whose success was in part enabled by the op new products quickly (time to market), market size. PLD industry. they must also be able to manufacture the A Tale of Two Products product, and quickly ramp production to Time-to-Market Advantages meet customers’ demands. This is called Let’s illustrate how the manufacturing Winning companies have succeeded by “time-to-volume.” Component supply model, and consequently the drive for time getting their products to market before through electronics distributors, and flexi- to volume, has changed over the years by their competition. They meet their cus- ble contract manufacturing, are factors contrasting TVs with DVDs (digital video tomers’ needs quickly and therefore estab- that have enabled companies to respond to disk players). Television entered the US mar- lish a market position that is very difficult soaring customer demand. Furthermore, ket in 1936 with very little market impact, to challenge; this position also gives them PLDs have been a major factor in provid- because there was little content and also lit- a market advantage for subsequent genera- ing an off-the-shelf platform for not only tle disposable income with which to buy the tions of products. This so-called “time-to- prototyping and early production, but also TV sets. By 1945 there were probably less market” paradigm is the watchword for manufacturing through the entire product than ten thousand TV sets in use, yet that many entrepreneurial companies. life cycle. number was destined to grow enormously as

38 Column Market Analyst

post-war incomes rose and broadcast net- sumer products, the 250,000,000 works were able to supply the content that affordability threshold is Population drove demand. By 1950, the number of TV attained when the end 200,000,000 sets in consumer’s hands had grown signifi- equipment price falls 150,000,000 cantly to six million sets, and then to sixty between 1.1 and 1.8 million by 1960. In 1998, according to the weeks of household 100,000,000 Consumer Electronics Manufacturing income. Table 1 presents Association (CEMA), penetration of color US median household 50,000,000 televisions reached 98% of U.S. households. income and correspon- 0

Figure 2 presents television penetration over ding price points for con- 1940 1945 1950 1960 1970 1980 1990 time. sumer goods acceptance. Population Television Ownership

Contrasting the acceptance and penetration Industrial Markets Source: U.S. Census Department, CEMA Consumer Research of television to that of DVD player market The concepts of market illustrates why time to volume has become a Figure 2 - Television penetration time to volume potential apply to non- fundamental market force for designers and consumer, industrial system manufacturers. The DVD market equipment as well. For example, Internet- was in an ideal market position at its incep- some other supplier will step in and take its place based corporations of all sizes must respond tion. The content (movies) was already avail- as the market leader. to their customers’ needs for more Conclusion bandwidth. Both internal cus-

Income tomers for Intranet support, and Programmable logic will continue to outpace Purchasing Ownership Cost Expenses Cost Power Usage Cost Inflation external customers demanding other electronic component market segments faster, more seamless Internet because there is no faster or better way to devel- interfaces, are demanding greater Affordability op and manufacture your products; this applies performance. The result is that to cellular phones, base stations, electronic test Market Potential companies are demanding ever- equipment, medical devices, telephone switch- Desirability increasing performance and more ing systems, and a vast array of consumer and features from their network sys- industrial products. In the year 2000, PLDs

Use s Usability tem suppliers. Those network sup- will account for more than 14% of all logic pliers, in turn, have to respond devices sold. with faster, better, cheaper prod- Programmable logic has proven itself a very Figure 1 - Market potential is the overlap of affordability ucts in much shorter time than effective solution for dealing with the chal- and desirability. ever before. The stakes are colos- lenges of delivering product to market on a sal, because if a network company timely basis. cannot service its customers, then able and the market requirement for high- quality movies to be played on big-screen TVs and home theater systems had already developed. Moreover, the cost to purchase a DVD player and the DVD disks was low Year Total Income Product Affordability Range compared to when TVs were initially intro- 1969 $33,072 $728 to $1,191 duced to the market. The result was explo- sive growth in product demand. Industry 1979 $34,666 $763 to $1,248 prognosticators forecast that the US con- 1983 $32,941 $725 to $1,186 sumers will purchase ten million DVD play- ers in 2000. This will represent an increase 1989 $36,598 $805 to $1,318 in market penetration from 4% to 12% in 1993 $33,660 $741 to $1,212 twelve months. 1996 $35,172 $774 to $1,266 Customer demand has driven this growth of advanced products. TVs were interesting and unique, yet with the lack of disposable Table 1 - Product affordability based on consumer income (in 1996 dollars). income there was not a significant demand for televisions until the 1950s. For con-

39 Perspective Design Reuse Design Reuse Strategy for FPGAs The design productivity gap creates an opportunity for competitive advantage.

by Carol Fields Methodology Manager, Design Solutions Group, Xilinx [email protected]

With today’s technology, you are faced with more usable gates then ever before; that’s both a blessing and a curse. Moore’s law, stating that “the number of transistors per square inch on an integrated circuit doubles every two years”, has been holding true since 1965, allowing a higher level of integration to occur on one piece of silicon. However, you can only take advantage of this expo- nential growth in densities if it is matched by a similar growth in design productivity. Why worry about this gap in productivity? History has shown that on average, for a given product market, the first entrant takes 70% of all sales over the lifetime of the prod- uct, the second takes 15%, and the later ones share the remaining 15%, as illustrated in Figure 1. It pays to be first.

40 Perspective Design Reuse

Design Reuse Fills the Productivity Gap seeing is an increased use of System Level operate at internal speeds far surpassing 200 Integration (SLI). What we are also finding MHz. Many designs that once could only be The most promising way to fill this produc- is more SLI occurring on FPGA devices implemented in an ASIC due to speed, den- tivity gap, and be the first to the market with with many of the same design issues as SoC. sity, or pricing are converting to a much your new product, is to reuse existing designs more flexible and productive FPGA solution. or Virtual Components (VCs). Design reuse The predictions are that by 2003 the bulk is not a new idea; designers have always of the industry revenue growth will be It is a safe bet that more systems will be reused code, scripts, testbenches, and so on. because of SLI. The existing Design Reuse implemented in FPGAs in the future, espe- What is new (from two years ago) is the methodologies today are closely linked to cially given Moore’s law and the ingenuity of growth in intellectual property (IP) infra- SoC. In reality it makes more sense to tie FPGA R&D engineers. The industry ana- structure and the formalization of Design Design Reuse methodology to both SoC lysts predict that in 2003 FPGAs will begin Reuse methodologies. and SLI since a formalized Design Reuse to replace standard cell ASICs in all but very methodology would benefit both SoC and high volume applications. However, there are Design Reuse exists in several levels from “ad SLI designers. many cases where the volume is not high hoc” reuse of a previous proj- enough for Standard Cell technology, ect to purchasing a design Sales such as the adoption of gigabit from a third-party vendor. If Volume Ethernet, and areas where there is a an in-house VC has the Growth Maturity Decline demand for higher performance prod- potential of being reused Profit 1st Entrant ucts to meet increasing traffic flow more than twice, it is wise to Margin from the Internet. put some effort into develop- ing a Design Reuse method- 2nd Entrant Because Design Reuse is about plan- ology. This methodology 3rd Entrant ning for the future, the term Systems- addresses all aspects of the Others on-a-Reprogrammable-Chip (SoRC) process including legal and Product Life Cycle is used for SoC implemented in an business practices, VC specifi- Total FPGA. This term is used to define Revenues cation, designing and coding, both full and partial system-level testing strategies, design stor- designs since the challenges facing age and retrieval, and design Figure 1 - Time-to-market product life cycle. these FPGA designers are almost metrics. identical. Although it is rare to find Systems-On-a-Reprogrammable-Chip entire systems on an FPGA today, there is The amount of effort or lack of effort has a an increasing amount of SLI designs occur- direct effect on the VC’s reusability, especial- FPGAs have changed dramatically since they ring due to the newer FPGA architectures ly if the person reusing the module is not the were first introduced and used as glue logic (such as the Virtex family containing sys- original designer. If a third-party VC is to be just 15 years ago. In the late 1980 and early tem-level features). purchased, it is important to understand the 1990s, FPGAs were primarily used for pro- total cost and actual usability of the VC. totyping and lower volume applications Planning for the Future while custom ASICs were used for high vol- The key to Design Reuse is trust. For an Today most major digital design companies ume, cost sensitive designs. FPGAs had been internally generated VC you need to build-in are in the process of defining (or redefin- too expensive and too slow for many appli- trust, and when purchasing a third party VC ing) their Design Reuse strategy. This gen- cations, let alone for Systems-on-a-Chip. you need to define what makes the VC trust- erally includes the creation of an internal Plus, the development tools were often diffi- worthy. Design Reuse Department, similar in cult to learn and lagged the features found in structure to the existing EDA Department Design Reuse Strategy Today ASIC development systems. used to manage CAD tools. In the late The most popular design reuse methods are Silicon technology now allows us to build 1980’s many major companies had already for ASIC designs. This makes sense because FPGAs consisting of tens of millions of tran- formed their EDA Department to support the abundance of gates provided by Moore’s sistors allowing for more features and capa- the multitude of ASIC EDA tools. At this Law is allowing such a high level of integra- bilities in programmable technology. With point FPGA technology was just emerging tion as to place an entire System-on-a-Chip today’s deep sub-micron technology, it is with designers using either a proprietary (SoC). In 1995 the Dataquest definition of possible to deliver over three million usable EDA tool or a simple schematic capture SoC included a compute engine (micro- system gates in a FPGA. Today’s average tool; these tools hardly required a depart- processor, microcontroller, or digital signal ASIC design operating at 30 to 50MHz can ment to manage them. By the mid-1990s processor), at least 100K of user gates, and be implemented in an FPGA using the same FPGAs were being widely used by these significant on-chip memory. Five years later RTL synthesis design methodology. By the same companies for higher density glue we still do not find an abundance of systems year 2003, a state-of-the-art FPGA will logic and SLI, and FPGA support was on an ASIC chip. However, what we are exceed 10 million system gates, and will retrofitted into the EDA Departments.

41 Perspective Design Reuse Year 2000 Worldwide Xilinx Event Schedules

Gates / designer / day Moore’s Engineering Law Productivity Year 2000 North American Event Schedule Sept 6-7 Embedded Internet Conference 2000 Productivity San Jose, CA Gap 100 Sept 20 SNUG 2000 Boston Design Reuse Boston, MA

10 System Sept 24-28 Embedded Systems Conference 2000 Verification San Jose, CA Logic Synthesis Behavioral 10 Compilers Sept 26-28 MAPLD 2000 Schematic Laurel, MD Capture Oct 16-19 ICSPAT 2000 Dallas, TX 1980 1990 2000 2010 Oct 16-18 NCF / InfoVision 2000 Figure 2 - The productivity gap Chicago, IL Oct 18-21 Frontiers in Education 2000 Today, we have the opportunity to define a Conclusion Kansas City, MI reuse strategy that can not only co-exist for In 1999, the number of ASIC design starts FPGAs and ASICs but can also work seam- Year 2000 European Event Schedule peaked at only 1000 designs, and despite all lessly between the two technologies. The the publicity over the multimillion gates Sept 4-15 Xilinx Roadshow decision to include FPGAs in a Design Throughout Germany designs, most of these design starts were Reuse strategy must be made up-front under 200K transistors. The average FPGA Sept 5-8 EUSIPCO 2000 because it affects almost all phases of the design start in 1999 was between 10K and Tampere, Finland Design Reuse process, from design specifica- 50K gates, with the fastest growing size range Oct 12-13 Nokia Expo tion to verification planning. between 50K and 100K gates. Considering Espoo, Finland Sharing RTL Design Methods that FPGAs are more widely used than ASICs Oct 23-24 IP2000 Europe in digital designs today, it makes sense to Edinburgh, Scotland One of the most exciting outcomes of the include FPGAs in a design reuse strategy. dramatic improvements in FPGA architec- Nov 21-24 Electronica 2000 Munich, Germany tures, pricing, and design tools is that this There are many benefits of sharing a common technology advancement has made it possi- design reuse strategy; one of the most com- Year 2000 South East Asian Event Schedule pelling is the flexibility it gives the designer to ble for ASIC and FPGA designers to share a Sept 27-28 IIC 2000 common RTL design methodology. A com- choose the IC technology late in the design Seoul, Korea mon RTL design methodology is the basis cycle. It provides the flexibility to choose the best method to implement an SLI design Oct 3-4 EDA&T for a common design reuse methodology. Hsinchu,Taiwan without the overhead of retraining the design Though ASICs will continue to provide teams. In this fast pace market it is difficult to Nov 2000 Xilinx Technical Seminar higher levels of design integration, higher predict what features your product will need Sydney, Singapore, Seoul, and Shanghai speeds, and new EDA environments, and what technology you should use. Year 2000 Japanese Event Schedule FPGAs are never far behind. The major FPGA and EDA companies have made a A Design Reuse strategy is more than RTL code Nov 2000 Micon System Tool Fair 2000 Tokyo, Japan conscious decision to keep their design envi- and synthesis. Many companies reusing designs ronments the same, from the end users have found more value in the design and test Nov 2000 Xilinx Technical Seminar point of view, to make it easy for users to specifications than the actual RTL design. If Tokyo, Osaka, Yokohama, and Tachikawa, Japan move from one technology to the another. you are currently an ASIC user, the good news This was illustrated by the wide adoption of is that many of the elements of a good design reuse methodology can easily incorporate RTL synthesis tools and verification tools in For more information about Xilinx Worldwide Events, please contact the mid-1990s. In the case of RTL synthesis, FPGAs with minimal modifications. one of the following Xilinx team members or see our website at: existing ASIC methodology was kept the Xilinx has joined efforts with Qualis Design http://www.xilinx.com/company/tradeshows.htm Corporation to create the first Reuse Design same and the synthesis algorithms where • US Shows: Darby Mason-Merchant at: [email protected] or Guide for FPGA users. This new FPGA Reuse changed to target specific FPGA devices. Jennifer Makin at: [email protected] Field Guide will walk you through the elements Today we are seeing higher-level EDA tools of building a design reuse strategy and is avail- • European Shows: Andrea Fionda at: [email protected]. such as Floorplanners and team-based able, free of charge, from the Xilinx website at: design tools using the Internet. www.xiliinx.com/ipcenter. • Japanese Shows: Renji Mikami at: [email protected] • SouthEast Asian Shows: Mary Leung at: [email protected] 42 42 Comparisons CoolRunner CPLDs CoolRunner CPLDs - Your Best Choice for Battery Operation Recent studies prove that the Xilinx CoolRunner” family gives you far longer battery life than any other CPLD on the market. by John Hubbard CPLD Applications Engineer, Xilinx Conclusion [email protected] CoolRunner CPLDs are clearly the low power leader—for your com- The hand-held consumer electronics market is currently experiencing pany to remain competitive in the rapidly growing portable market, unprecedented growth, and it has become imperative for manufactur- your best choice is Xilinx. ers to maximize battery longevity to enhance their competitive edge. See the articles on page ___ and ___ for more information. You can With the CoolRunner CPLD family you get high performance, find the full story on CoolRunner CPLDs at: extremely low power, and field upgradeability, in a very small http://support.xilinx.com/products/xpla3.htm and http://support.xil- package—clearly the best solution for the next generation of low cost inx.com/products/coolpld.htm portable equipment. CPLD Comparison Your battery-operated design will run much longer with CoolRunner CPLDs. To illustrate the dramatic difference, Figure 1 compares the You can extend your battery life up to 200 impact on battery life using CPLDs from Altera®, Cypress®, Lattice®, times just by using CoolRunner CPLDs. Vantis® and Xilinx. This comparison was implemented with the fol- lowing conditions: 200 180 ® • Two Energizer No. E91 AA 1.5V alkaline batteries were used as the 160 Xilinx XCR3128XL power source. 140 Altera 3000A 120 Altera 7000A 100 Cypress CY37128 • The CPLD was the only device loading the batteries. 80 Lattice ISPLSI2128VE 60 Vantis M4A3 40 • Each CPLD was fully populated with 16 bit binary counters. Vantis M4LV 20 0 • All counters were clocked at 20 MHz. Hours of operation *Low power mode for all competitors. • All outputs were unloaded. Figure 1 - Dynamic CPLD battery life comparison. Dynamic Power Consumption

As you can see from Figure 1, CoolRunner CPLDs extend battery life 6000 far beyond the competition. In fact, the competition was given a 5000 Xilinx XCR3128XL Altera 3000A 4000 power advantage by measuring their CPLDs in low power mode. Altera 7000A However, the competition’s CPLDs run much slower in low power 3000 Cypress CY37128 Lattice ISPLSI2128VE 2000 mode. CoolRunner CPLDs do not need a low power mode and they Vantis M4A3 always operate at full speed. 1000 Vantis M4LV 0 Static Power Consumption Hours of operation *Low power mode for all competitors. Since the CoolRunner CPLD draws 1/1000th the power that the Figure 2 - Static CPLD battery life comparison. competition requires at standby, your power management require- ments will be dramatically reduced or eliminated. As shown in Figure 2, in standby mode, the CoolRunner CPLD can extend battery life up 1000 900 to 390 times that of the competition. 800 700 Total Power Consumption 600 Hours 500 400 By modulating the dynamic operation (full power) with static opera- 300 tion (standby mode), you will considerably extend the battery life of 200 100 your design using CoolRunner CPLDs. Figure 3 illustrates battery 0 5 25 50 75 100 longevity in the form of duty cycle where, for example, a 75% duty Power Duty Cycle cycle represents 75% dynamic and 25% static operation. Figure 3 - CoolRunner duty cycle effect on battery life. 43 Column Getting Started Choices, Choices, and Opinions How to choose the best Xilinx programmable logic technology for your application.

Recommendations Use CPLDs, such as the XC9500XL family, for small designs where “instant-on”, fast and wide decoding, in-system programmability, and design security are important. Use CoolRunner CPLDs when idle-power con- sumption is important, as in battery-operat- ed equipment. Use FPGAs for larger and more complex designs. FPGA Families Xilinx has a wide range of FPGAs to choose from. Here’s an overview of our complete by Peter Alfke even for wide input functions. And, once product line, from the beginning. Applications Engineering, Xilinx programmed, the design can be locked and [email protected] thus made secure. Most CPLD architectures XC2000 and XC6200 are very similar, so it is important to evaluate The Xilinx XC2000 family was introduced Xilinx offers a wide variety of programmable the subtle nuances. logic devices, using different architectures in 1985, and has outlived its useful life. The and technologies. Here is a high-level In-system-programmability (ISP) is a must XC6200 family embodied an innovative overview of the different families and some for today’s designs, and the ability to main- architecture that was popular in academic suggestions for the prospective user. tain pin-outs during design modifications research, but found no commercial use. (“pin-locking”) is crucial. The limited com- These families are no longer available. 5V or 3.3V / 2.5V? plexity (<300 flip-flops) means that most XC3000, XC3100, and XC5200 The standard logic supply for 30 years has CPLDs are used for “glue logic” functions. These families are not recommended for new been 5 volts, but modern processes with For most CPLDs, the relatively high static designs, because several newer families offer smaller geometries demand lower voltages, (idle) power consumption prohibits their use better functionality and performance at a such as 3.3V, 2.5V, 1.8V, and even lower in in battery-operated equipment. Xilinx lower price. The XC3000L is still the FPGA the future. While Xilinx strives to make CoolRunner devices are the notable excep- family with the lowest static (idle) power inputs tolerant to voltages higher than Vcc, tion, offering the lowest static power con- consumption of <100 microamps, and it we discourage you from starting any new sumption (<50 microamps) of any program- offers an on-chip crystal-oscillator driver, not project with 5V devices. mable device. available in any other FPGA family. These Xilinx will continue offering 5V devices for FPGAs offer much higher complexity, up to families stay in production, but are not rec- years to come, but these devices will not ben- 70,000 flip-flops, and their idle power con- ommended for new designs. efit from the traditional performance sumption is reasonably low. Because the con- XC4000 - E, EX, XL, XLA, and EV enhancing and cost-reducing redesigns, and figuration bitstream must be reloaded every process enhancements. To benefit from the time power is re-applied, design security is an Today, this is the industry’s most popular latest technology, do not use 5V devices for issue, but the advantages and opportunities series of FPGA families. The XC4000E is a new designs unless there is a special reason. of dynamic reconfiguration, even in the end- superset of the XC4000 family, with higher user system, are an important advantage. speed, more routing, and edge-triggered syn- CPLDs or FPGAs? FPGAs offer more logic flexibility than chronous write into the LUT-based RAM. CPLDs with their PAL-derived, easy-to- CPLDs, and more sophisticated system-level The XC4000EX extends the XC4000E fam- understand, AND-OR structure offer a sin- features (clock management, on-chip RAM, ily to 3000 flip-flops, and adds a generous gle-chip solution with fast pin-to-pin delays, programmable I/O levels). amount of routing resources. The XC4000,

44 Column Getting Started

XC4000E, and XC4000EX are 5V fami- generally recommended for new designs. The 2.5V Virtex family covers the range lies, and as such are not generally recom- Spartan-XL and XC4000XLA from 1,800 to more than 27,000 flip-flops. mended for new designs, because newer The 2.5V Virtex pins are 5V tolerant, and families offer better performance and lower The Spartan-XL and XC4000XLA families the devices can implement 5V PCI. cost. offer similar features and performance, where Spartan-XL covers the range of 360 The 1.8V Virtex-E family is an enhanced The 3.3V XC4000XLA is an upgrade of to 2000 flip-flops, while XC4000XLA superset of the original Virtex family with the very popular 3.3V XC4000XL family, offers 1,500 to 7,000 flip-flop capacity. two or three times the amount of and the 2.5V XC4000XV extends the fam- These 3.3V families should be used where BlockRAM, as well as support for differen- ily to 18,000 flip-flop capacity. The the more advanced features of the Virtex tial I/O standards such as LVDS, BusLVDS, XC4000XLA devices should be used where series and Spartan-II are not needed (such and LVPECL. At the high end, Virtex-E the more advanced features of the Virtex as BlockRAM, clock management, and ver- offers 73,000 flip-flops (>3 million system series (BlockRAM, clock management, and satile I/O). gates). The enhanced 0.18 micron process versatile I/O) are not needed. Use Virtex-E provides higher performance, but requires instead of XC4000XV for new designs. Virtex, Virtex-E, and Virtex-EM 1.8V for the core. The I/O uses up to 3.3 V, and is not 5V tolerant. Spartan The Virtex family is the biggest design project in Xilinx history and, judging by The 1.8V Virtex-EM family includes two Spartan devices are functionally a subset of the number of early design-wins, is also the devices that are electrically and architec- the XC4000E family, offering up to 2000 most successful. The Virtex architecture is turally identical with Virtex-E, but have flip-flops at a significantly lower price. rooted in XC4000 concepts (4-input look- significantly more BlockRAM (over 1 mil- They are mainly used in cost-sensitive, up tables, usable as synchronous RAM), lion bits in the XCV812E). Virtex-EM is high-volume (consumer) applications. but the design started with a clean slate: also the first FPGA family using copper Spartan FPGAs achieve lower manufactur- interconnect technology for lower inter- ing cost in several ways: • The interconnect structure is generous, and is optimized for short and predictable connect resistance, higher speed, and better • The die are smaller. delays. resistance to metal-migration problems. • The manufacturing flow is streamlined. • DLL-based fully digital clock-manage- The Virtex-E and -EM families are highly • Speed, temperature, and package options ment eliminates on-chip and on-board recommended for new designs, where they are more limited. clock delays. offer not only high speed and high capaci- ty, but also valuable system-level features • Configuration modes are bit-serial only. • The device pins are compatible with such as clock management, a versatile I/O • The pricing structure favors high- many board-level I/O standards. structure, and substantial amounts of dual- volume sales. • Up to several hundred dual-ported ported BlockRAM. Virtex-EM is ideal for Spartan is a 5V family, and as such is not BlockRAMs of 4Kb each. memory-intensive applications. Spartan-II

Virtex-EM Spartan-II extends the advanced features of the Virtex family, with 400 to 4,700 Spartan-II Virtex-E Spartan-XL XC4000XLA flip-flops. Spartan-II uses streamlined Virtex manufacturing methods and limited XC4000XL XC4000XV speed, temperature, and package options to address the cost-sensitive high-volume XC4000EX Spartan (consumer) market. Conclusion XC4000E

XC4000 Xilinx offers many different programma- XC3000(A) XC3000(L) ble logic families to meet the needs of a wide range of applications. Make sure you XC3000(A) are using the right technology today, so

Logic: Vcc=5.0V Vcc=3.3V Vcc=2.5V Vcc=1.8V your designs will continue to be competi- tive tomorrow. I/O: Vcc=5.0V Vcc=3.3V Vcc=1.5...3.3V Vcc=1.5...3.3V XC4000XV: 3.3V only

Figure 1 - Xilinx FPGA Genealogy

45 Innovations IP Development Tools New Virtex XSV Development Board for Creating Intellectual Property

The XSV Board, designed for the SIP developer community, provides a flexible, low-cost platform that supports a large set of interesting applications.

by Dave Vanden Bout Product Manager, XESS Corp. [email protected]

With the advent of large FPGAs such as the Xilinx Virtex series, the semiconductor intellectual property (SIP) market is poised for rapid expansion. Developers of open SIP serve a large segment of this market. With open SIP, the HDL source code and schematics for a functional core are made freely available and the developers generate revenue through service and support. But open SIP developers need an affordable, widely available platform for their cores to run on, just as the PC provided the plat- form for the growth of the open Linux OS. That’s why we created the XSV Development Board XSV Features

The XSV Development Board from XESS Corp., shown in Figure 1, is a general-pur- pose Virtex FPGA development platform with extensions for multimedia I/O and network connectivity. The XSV houses a single Virtex chip in a 240-pin PQFP pack- age, ranging from the XCV50 (50 K gates) up to the XCV800 (800 K gates). The wide range of device sizes in the same low-cost package lets XESS tailor the price of the board to meet the price requirements of

46 Innovations IP Development Tools

open SIP developers and users. Therefore the FPGA. For even higher speeds, an which are loaded into the XSV Board with you can move from smaller to larger Ethernet physical-level interface links the the GXSLOAD utility from XESS. XESS FPGAs on the XSV Board without the FPGA to a network at up to 100 Mbps. also provides utilities to run self-test diag- need to rearrange your pin assignments. The FPGA can also communicate with nostics and to set the frequency of the pro- external systems through two 50-pin I/O grammable oscillator on the XSV Board. Video and Audio Capabilities headers (38 general-purpose I/O, 12 XSV Board users can get example designs The XSV Board surrounds the Virtex chip power/ground). and application notes at www.xess.com and with circuitry that supports many of Configuration can subscribe to an email list of users who today’s important applications. A video provide assistance to one another. decoder chip digitizes NTSC, PAL, and A Xilinx XC95108 CPLD manages the SECAM formats with up to nine bits of configuration of the XSV Board. The Conclusion resolution. The FPGA can process the dig- CPLD accepts bitstreams via the parallel Using the XSV Board, you can easily devel- itized video and store it in one of two inde- port and loads them into the FPGA. Or it op Intellectual Property for Xilinx FPGAs. This flexible, low-cost platform supports a variety of applications and helps you to quickly realize your designs. For developing IP, there is no faster or easier method. For more information contact XESS on- line at: www.xess.com, or send e-mail to: [email protected]

About XESS

XESS Corporation is the leading provider of hybrid programmable logic/microcontroller development boards. Targeted at the

Figure 1 - XSV Development Board block diagram. educational market, XESS boards allow universities and students pendent banks of 512K x 16 SRAM, or it can program the bitstream information to build systems which combine can send the video to a 24-bit RAMDAC into a 16 Mb Flash RAM on the XSV for output on a VGA monitor. Video needs Board. The Flash RAM stores multiple bit- elements of hardware and software sound to go with it, so a 20-bit stereo codec streams that are selectable with a DIP and then quickly explore tradeoffs lets the FPGA input and output two chan- switch. The CPLD configures the FPGA nels of audio. with the selected bitstream upon power-up. between the two. XESS sells its Connectivity Using XSV products directly to customers world- To provide connectivity, the XSV Board The XSV Board is attached to a PC with a wide. Founded in 1990, XESS is has interfaces for the parallel, serial, and commonly available 25-wire parallel port privately held and is headquartered PS/2 keyboard/mouse ports common on cable, and is powered with a standard PC- PCs. There is also a USB port that connects ATX power supply. The Xilinx Foundation in Apex, NC. a wide variety of devices to the XSV Board Series or Alliance Series development soft- at up to 12 Mbps through a USB core in ware is used to generate Virtex bitstreams

47 New Products Development Tools Strathnuey - The Xilinx Technologies Integrator An entry level PCI card with DIME slot capability using Spartan-II FPGAs.

by Derek McAulay Design Engineer, Nallatech Ltd [email protected] The low profile PCI/USB card, Strathnuey, is the latest carrier card to be added to Nallatech’s award winning DIME module product line. The Strathnuey pulls face, along with Spartan-II drivers and together, in a compact form factor, many application software, removing the need of the exciting new technologies being for required expertise in PCI or USB inter- produced by Xilinx for FPGAs. Support is facing. The advanced system-level tools included for the high speed SelectMAP tomize the Strathnuey for your application supplied are those from the established interface (which forms the basis for partial while maintaining the low cost and fea- DIME range, which include plug and play reconfiguration), Chipscope ILA (giving tures of the DIME standard. DIME Select capability and a standard interface which built-in logic analyzer capability), Xilinx modules will include AD/DA conversion, provides transparent migration to the PCI LogiCORE development (for custom Bluetooth, SDRAM, QDR ZBT, and more powerful and scalable DIME plat- application development), and DSP IP Ethernet. forms such as the Ballynuey. core verification. DIME Professional A key component of the tools is the Using two of the latest Spartan-II devices If you require a higher level of perform- integrated high speed configuration the Strathnuey provides a versatile plat- ance and more processing power, the mechanism which allows the on board form for application development. The Virtex-based DIME Professional modules Spartan-II, or other attached FPGAs, to be Spartan-II family is used in diverse appli- can also be mounted onto the Strathnuey. configured directly over the PCI or USB cations such as wireless digital communi- These DIME modules are all populated buses, thus eliminating the need for dedi- cation systems, digital TV, high-speed with the Virtex family and include a wide cated download cabling and PROM pro- DSL, cable modems, and medical imaging range of functions, such as video capture gramming. The configuration of the systems. and display, high speed communications, Spartan-II or Virtex-E FPGA (using the DIME - DSP and Image processing Modules for data capture/generation, and complex DIME slot) can be performed via the Enhanced FPGAs DSP algorithms. Xilinx SelectMap protocol, or alternatively via the JTAG chain, which allows access to The DIME module slot, illustrated in Whether you are using DIME Professional the data and control registers, enabling Figure 1, gives access to the wide range or DIME Select modules, the Strathnuey partial reconfiguration. This feature natu- of DIME modules, which you can use enables you to construct full custom rally provides the mechanism to develop to customize the card to your selected FPGA-based systems using standard off dynamically reconfigurable systems giving application. the shelf products, guaranteeing risk this card the capability of having multiple reduction and a significant reduction in DIME Select personalities. development costs and time to market. To complement the Strathnuey, a new The software tools run on all Windows Configuration Software range of low profile modules, called DIME platforms (95/98/NT/2000) and is one of Select, are now available from Nallatech. The Strathnuey kit comes complete with the first FPGA-based system platforms to These new modules enable you to cus- compiled designs for the PCI/USB inter- be supported under Linux.

48 New Products Development Tools

Communication Interface very elaborate Computer Based Training PCI Development Platform (CBT) courses to be based around the Communication and control of the The Strathnuey can also be used to prove Strathnuey. These can be developed to Strathnuey is provided by two separate your own PCI interface designs when you educate the student in many areas and the mechanisms. Using the universal PCI are using the Xilinx 32-bit PCI integration of technologies such as the interface enables the card to be used inside LogiCORE or an in house PCI core. Xilinx Chipscope ILA allows the student standard PC systems for embedded appli- Support for 3.3V and 5V PCI is incorpo- to have a full debug workbench on his PC cations. Alternatively, for standalone or rated with auto detection circuitry to without the expense of additional test remote applications, the card can use the select the appropriate bit streams from equipment. USB interface allowing it to be connected the flash-based XCV1800 PROMs. These directly to a laptop, for example. The addition of DIME Select Modules PROMs can easily be reconfigured with will ensure that lecturers can educate their IP Core Demonstration Platform the user-specific bit stream. students in many areas including: Conclusion The flexibility and scalability of the • FPGA technology. Strathnuey make its range of applications The Strathnuey gives you a complete plat- wide and varied. In particular, the • DSP theory. form that links the exciting new technolo- Strathnuey is an ideal demonstration envi- gies from Xilinx. In addition, the • Communications theory. ronment for IP core suppliers to show Strathnuey provides an ideal entry-level their cores’ capabilities working “live” with • ADC/DAC principles including aliasing. DIME-based system development plat- real hardware and data. • Control theory. form, which can also be used as a stepping stone to the high performance Ballynuey As an example, IP developers can easily • Hardware and software partitioning. DIME Professional products. send data to and from their cores via the straightforward infrastructure interfaces The new development system is the result such that demonstration GUIs could be of a close collaboration between Nallatech For more information on the Strathnuey constructed to elegantly demonstrate any and the reconfigurable logic group led by or other DIME products, contact special features of their particular cores. Patrick Lysaght at the University of Nallatech at www.nallatech.com. Additionally, if required, a DIME module Strathclyde. The group has a 70-seat labo- can provide the appropriate physical front ratory for teaching undergraduates digital end or back end interface to hook up the design and has been using Xilinx FPGAs core with other systems for a complete since 1989. demonstration system. Integrated Silicon Systems (ISS), the lead- ing multimedia IP core provider, selected DIME to demonstrate the capabilities of its applications-specific virtual compo- nents (ASVCs). “Performance and flexibil- ity were key selection criteria when ISS went looking for a suitable hardware plat- form to demonstrate its multimedia and communications IP cores working in Xilinx Virtex technology.” commented Stephen Farson, Engineering Manager, ISS. “Nallatech’s DIME solution excelled in these areas.” Educational Lab Experiments The Strathnuey provides an excellent edu- cational platform for Electronic Engineering courses, with the ability to go far beyond education in FPGA technology to complete system design. The simplicity of the software interface to the uncommit- Figure 1 - Strathnuey block diagram ted secondary Spartan-II FPGA allows 49 Success Story Virtex FPGAs Tektronix Logic Analyzers 800 Mbit/sec Using Virtex FPGAs

by Tamara Snowden Corporate PR Manager, Xilinx [email protected]

Tektronix chose the Virtex XCV300 Technology leader Tektronix, headquar- tered in Wilsonville, Oregon, recently device specifically for it’s TLA 700 announced its new suite of instruments designed for the most challenging leading- edge digital design applications. The inte- Rambus adapter, based upon its grated tool set is composed of new per- formance-leading instruments: the TLA flexibility and overall performance. 714/720 portable and benchtop logic ana- flexibility and overall performance. lyzers, the TDS694C digital storage oscillo- scope (DSO), and complementary connec- tion devices. The instruments were designed to work together to provide spe- cialized features and optimized perform- ance. An Integrated Solution “A digital design engineer operates in an environment of accelerating technological change under extreme time-to-market con- ditions,” said Steve Jennings, director of marketing of the Tektronix’ Measurement Business Division. “This new integrated solution provides superior measurement and analysis capabilities for even the most challenging design areas like Rambus mem- ory systems and next-generation micro- processors.” Choosing an Upgradable FPGA Solution “The Virtex FPGA provides the flexibility necessary to implement protocol detection and reorganize the data for a delightful pres- entation to the Logic Analyzer and in so doing, delighting the customer,” said Brainard Brauer, a Tektronix design engineer. “An ASIC was not an option in this design. The Virtex FPGA provides field upgradeabli-

50 Success Story Virtex FPGAs

ty of the code, which is critical in this fast A New Family of Logic Analyzers moving, cutting-edge application.” The new family of logic analyzers, the “Virtex FPGAs have allowed Tektronix to TLA 714 and the TLA 720, are replacing About Tektronix de-serialize the Rambus data bus,” said the original TLA 704/711. They offer an Brauer. Virtex devices accept Rambus data industry-leading combination of acquisi- Tektronix is a portfolio of measure- after presampling logic has converted the tion speed, channel width and memory serial channel from 26 bits on both edges at depth, all of which are essential for sup- ment, color printing, and video and 800Mbit/sec to 56 single edge signals to porting next-generation microprocessor networking businesses dedicated to 400Mbits/sec. “Tektronix has been suc- designs. Now offering up to 16M, the cessful at using the Virtex FPGA to accept TLA 714/720 have the deepest memory applying technology excellence to this 400MBits/sec data directly into the configuration in the industry plus an customer challenges. Headquartered Virtex device.” This was achieved by pro- innovative hardware-assisted display sys- viding multi-phase clocks to the device tem to simplify the management of such a in Wilsonville, Oregon, Tektronix (four phases). Each clock was connected to large memory. has operations in 26 countries out- a different global clock input, routed over “High register count is its own internal global side the United States. Founded in a key to our bus route with separate DLL’s decoding implementa- 1946, the company had revenues (Delay Locked Loops). “An ASIC was not an tion, once deserialized “The device achieves a into a wide parallel of $2.1 billion in fiscal 1998. setup/hold specification option in this design. The pipe line architecture. For more information, visit the better than 1.2ns worst The Virtex device pro- case across temperature Virtex FPGA provides field vided the lower power website at www.tek.com. and at any pin of the consumption we device,” said Brauer. “It is upgradeablity of the code, needed with much critical to verify that the which is critical in this higher useable register tools have routed each densities than previ- At the heart of all of the TLA 700 Series data input to an IOB ous devices,” said logic analyzer modules is a breakthrough fast moving, cutting-edge TM (Input/Output Block). In Brauer. called MagniVu acquisition technology, the Tektronix implemen- a super-high-speed sampling architecture application.” The new TLA 700 tation, four input pins that dramatically changes the way logic features an easy-to-use were consumed for each analyzers work and what functionality they Windows 98 user data line. As a result, four offer. All incoming data is oversampled at interface and a PC platform with expand- IOBs were required (one for each clock a 2GHz rate, regardless of how the logic ed openness in response to customers’ phase). The package loading must be care- analyzer is being used. The oversampled strong acceptance of the original TLA fully understood and compensated for to data is then processed in real time to per- 700’s open platform. Tektronix built in avoid signal slew rate issues. form timing acquisition, state acquisition, an industry-standard computer and oper- and triggering without missing the slight- Choosing a Software Solution ating system to provide the user with a est piece of crucial timing information on familiar interface. Because it works just Brauer used the Xilinx Alliance Series soft- any channel. like any other PC-based software, the user ware to design the TMS810 Rambus inter- can focus on the problem, rather than the face adapter, which provides the crucial front tool. Tektronix has also created the end interface between Rambus and the Embedded Systems Tools Partners TLA700 logic analyzer. The Alliance Series Program to deliver development is the industry’s leading open systems soft- and debug solutions for the ware that provides the flexibility to select the TLA 700 Series. The solu- best EDA design environment for a specific tions range from providing application. Combining the advanced software, analysis tools implementation technology of Xilinx with and physical processor the strengths of its partners provides a pow- connections, to disassem- erful overall design solution, the highest bly software that runs on clock performance and the highest densities the logic analyzer. in the industry.

51 Success Story McData

When IBM needs McData Uses state of the art Fibre-Channel hardware, Xilinx FPGAs for it thinks McDATA. When McDATA needs FPGAs, Fibre-channel Switch it thinks Xilinx.

by Tamara Snowden data center and edge servers in large enter- als like disk and tape arrays. IBM came to Corporate PR Manager, Xilinx prise data centers. McDATA also offers McDATA again when the company need- [email protected] design, implementation planning, integra- ed an internal bridge card to manage the McDATA Corporation, headquartered in tion testing, and training services for com- optoelectronic, framing, and format con- Broomfield, CO, is the architect of the panies building enterprise SANs. version from newer, IEEE One Gigabit first enterprise-wide SAN (Storage Area Fibre-Channel connections (or FICON) Designing a Bridge Card Network) solution. McDATA specializes for the 9032 (Shown in Figure 1). in highly available, scalable and centrally In the late 1990s McDATA designed a Originally designed with the 200-Megabit managed enterprise SANs, providing cus- 128-port 9032 Model 5 Director for IBM- ESCON protocol in mind, to the Model 5 tomers with hardware and software that a super switch for interconnecting main- would be the first of IBM’s switches to allow dynamic connection between the frame computers and high speed peripher- support FICON.

52 Success Story McData

Each new bridge card would perform the to use Xilinx FPGAs and design tools not have been possible with an ASIC— work of up to eight ESCON channels. Up rather than develop an ASIC. The team another time saver and another advantage to 16 FICON Bridge cards (equivalent to would take advantage of FPGA repro- of the FPGA approach. 128 ESCON ports or one half of the grammability to design, develop, and McDATA used several different Xilinx Model 5’s capacity) would be supported in debug as they went along. products to implement the bridge card, a single 9032 Model 5 Director. Using multiple FPGAs sped up the effort among them the XC4013XL, XC4028XL, Retrofitting the FICON bridge card would further. McDATA found that by parti- and XC4044XL FPGAs, and an XC9500 allow data centers to use tioning the design into CPLD. The CPLD was used to interface the much higher speed modules, each with its to an Intel i960 processor which down- of FICON without “It was McDATA’s posi- own FPGA, they could loaded the bitmaps into the FPGAs. As replacing the 9032 assign each part to a dif- the design evolved, McDATA started with Directors. It would also tive experience that ferent designer or team relatively large FPGAs, but as they altered give IBM’s customers for easy to manage and and optimized the design, they moved to the ability to optimize made Xilinx the choice faster parallel develop- smaller die sizes especially with respect to for either raw speed or- ment. the XC4013s. McDATA is also moving to of the engineering Xilinx XLA technology FPGAs to “greatly through multiplexing- Xilinx FPGAs were also help with cost reduction, while continu- larger arrays of storage team. They also knew valuable because there ing to minimize program risks,” according devices. Except for the were so many unknowns to Hwang. costs associated of the that they didn’t need to in the project. In fact, bridge card itself, once the decision had The process went so well that McDATA upgrading the Director push Xilinx technology; been made to use is sticking with its original FPGA imple- would be nearly pain- FPGAs, McDATA decid- mentation, especially since this allows for less, and conserve the there was capability ed to optimize the bridge the design to be further refined. As is customer’s investment in reserve.” card architecture around usually the case, McDATA originally in a costly piece of high- them, to get the most out anticipated going to an ASIC to mini- performance hardware- of the programmability. mize costs. But now, production of the the 9032 Model 5 has a This helped minimize FICON Bridge Card is well underway backplane with full-duplex, 1-Gigabit the impact of specification changes, bugs, using Xilinx FPGAs. The cost reductions capacity. and implementation changes. Use of the made using Xilinx XLA-class FPGAs Choosing FPGAs Over ASICs FPGAs drastically cut development risk, have been significant, and consequently, and development moved along far faster there are no immediate plans to switch to Roughing out the block diagram for the than the ASIC approach. a custom chip. new FICON card was straightforward. The bridge card would handle multiplex- “We knew Xilinx’ product philosophy, ing and format conversion; IBM would having been a Xilinx customer for five perform protocol conversion in the main- years, and were very comfortable with it “The risk was too high with the frame. The 1-Gigabit optical input is and with the company’s product,” says steered to an optoelectronic converter, and Hwang . “It was McDATA’s positive expe- ASIC approach. In hindsight, we from there to a 32-bit, 26-Mhz parallel rience that made Xilinx the choice of the bus. Next is a framer, then a Fibre- engineering team. They also knew that made exactly the right decision Channel high-level protocol converter, fol- they didn’t need to push Xilinx technolo- lowed by eight IBM-supplied ESCON gy; there was capability in reserve.” to go with Xilinx FPGAs.” engines the output of which connect to the The Design Process 9032 Director’s backplane. The design process went smoothly using Xilinx FPGAs form the heart of the bridge standard Xilinx Alliance Series( software card’s framer and protocol conversion sec- tools. “We used the scripting capabilities Conclusion tions. Originally, an ASIC had been tar- to the fullest so that we could automate as geted for these roles. But ASIC develop- much of the process as possible,” says Looking back on the development Hwang ment is risky and time consuming and Hwang. In addition, McDATA used the says, “The risk was too high with the ASIC project engineer Paul Hwang needed to Xilinx EPIC FPGA editor to help debug approach. In hindsight, we made exactly minimize risk and get the product to mar- the design by bringing out internal signals the right decision to go with Xilinx ket as quickly as possible. Hwang decided to unused I/O pins, something that would FPGAs.” 53 Applications Circuit Design

TheThe “Flancter”“Flancter” How to set a status flag in one clock domain, clear it in another, and never have to use an asynchronous clear for anything but reset.

by Rob Weinstein Senior Member of Technical Staff, ister that mitigates these problems. It’s called the two clock domains. Also, the output Memec Design Services the “Flancter” (named by my colleague, must be synchronized with additional flip- Mark Long), and is shown in Figure 1. flops to mitigate metastability when cross- There are times when it’s important to gen- ing clock domains (more about this later). erate a status flag that is set by an event in As you can see, it’s made up of two D-type one clock domain and reset by an event in a flip-flops, an inverter, and an exclusive OR How It Works different clock domain. Using a D-type flip- (XOR) gate. Notice that the asynchronous To explain its operation, I like to rearrange flop, where a “1” is clocked in from one reset inputs to the flip-flops are shown the circuit as shown in Figure 2. clock domain and its asynchronous reset is unconnected for clarity only. Normally, pulsed by logic in the second clock domain, these would be tied to the global set/reset This is the same circuit as shown in Figure is the time-honored method to achieve this net in the system. 1, but untwisted so that the two inputs to function. While there is nothing logically the XOR gate are clearly visible. You can Operation of the Flancter is simple; when wrong with this, it introduces other prob- see that the XOR gate’s upper input is FF1 is clocked (rising edge of SET_CLK lems such as combinational logic driving an labeled Q1, while its lower input is labeled while SET_CE is asserted), OUT goes high. asynchronous reset pin, uncertainty in tim- Q2. Also, Q1 and Q2 are the Q outputs of When FF2 is clocked (rising edge of ing constraint boundaries, and muddying FF1 and FF2, respectively. Now for the RESET_CLK while RESET_CE is asserted), the global reset function. trick part of this magic trick: the D input OUT goes low. Note that this circuit must to FF1 comes from an inverter, so whenev- Here, I present an alternative method for be used in an interlocked system where the er FF1 is clocked, Q1 assumes the opposite generating a multiple clock domain flag reg- flip-flops won’t be continuously clocked by state of Q2 and the output of the XOR

54 Applications Circuit Design

There are a few things wrong with the Flancter from the start. One problem is that it uses two flip-flops to create a single flag bit. This is a minor fault when you consider that most FPGAs have an abun- dant supply of flip-flops. A more serious issue is how to use the output. Remember that the output can change synchronously to either clock domain. You need to resyn- chronize the output to whichever clock domain needs to see it; often both clock domains. It is common to use two flip- Figure 1 - Basic Flancter. flops in series as a metastability-resistant synchronizer. However, the most serious drawback to the Flancter is that operating the set and reset flip-flops must be mutually exclusive in time. This means that when logic in clock domain 1 sets the Flancter, it doesn’t attempt to set the Flancter again until it sees that it has been reset. Likewise, the logic in clock domain 2 never attempts to reset the Flancter unless it sees that it has been set. Establishing this kind of inter- locked protocol guarantees that both of the Flancter’s flip-flops won’t be clocked simul- taneously (or within each other’s setup and Figure 2 - Rearranged Flancter hold time windows). Applications of the Flancter There are many applications of the gate will go high. When FF2 is clocked, Q2 value of Q1. Also, OUT goes low because Flancter, but a very common application is becomes the same as Q1, and the output it is the XOR of Q1 and Q2. will go low. In summary, clocking FF1 interfacing a microprocessor to an FPGA. • At point C, Q1 again gets the inverted causes OUT to go high and clocking FF2 Typically, the microprocessor and FPGA value of Q2, causing OUT to go high. causes OUT to go low. logic run on separate clocks. When the • At point D, Q2 goes low because it gets microprocessor writes a control register A timing diagram will help describe the the value of Q1, causing OUT to go low. within the FPGA, the Flancter can be used Flancter’s operation. Figure 3 shows the as a status flag to tell an internal state basic timing diagram. So What’s Wrong With It? machine that new data is available. The basic points of interest in the timing diagram are:

• SET_CLK and RESET_CLK are asynchro- SET_CLK nous to each other. SET_CE Q1

• At point A, the rising edge of SET_CLK A C while SET_CE is high causes Q1 to go RESET_CLK high because it gets the inverted value of RESET_CE Q2. Also, OUT goes high because it is the Q2

XOR of Q1 and Q2. B D • At point B, the rising edge of OUT RESET_CLK while RESET_CE is high Figure 3 - Basic Flancter timing causes Q2 to go high because it gets the 55 Product Focus Circuit Design

Likewise, a state machine within the flops used to filter any metastable logic Things to notice in Figure 5: FPGA can use the Flancter to generate an conditions from propagating into the • The FPGA’s state machine sets the inter- interrupt to the microprocessor that is sub- state machine. rupt request (INT) at point A. sequently cleared by a read or interrupt- • The particular microprocessor used in acknowledge cycle from the microproces- • Sometime later, the microprocessor this example employs metastable resistant sor, as shown in Figure 4. responds to the interrupt by reading a status register, thus resetting the inter- rupt request at point B. Variations on a Flancter While the basic Flancter is very simple, many useful variations are possible. I describe some of the more interesting variations in the Flancter app-note available on our website, http://www.memecdesign.com/ resources/guides/. Some of the variations you’ll find there include the 3-way Flancter, the n-way Flancter, the async-reset emulating Flancter, and the default-to-active-high Flancter. The app-note also has VHDL and Verilog listings for the basic Flancter. Conclusion I turned 37 this year and I got to thinking that all the “greats” did their best work long before they reached my age. As I look back Figure 4 - Flancter used for microprocessor interrupt on my design career, I realize that I haven’t designed any circuits or developed any the- orems that will bear my name like the Pierce Oscillator or Shannon’s Sampling Theorem. The best I can do is to offer the Things to notice in Figure 4: techniques on its INT input. Flancter as my legacy. Perhaps someday, the • The Flancter is made up of FF1, FF2, the • The interrupt sequence is defined such Weinstein-Flancter will be found in the inverter, and the XOR gate. that setting and resetting the interrupt indexes of engineering tomes right between flag cannot occur simultaneously. Watt-Hour and Wien-Bridge. • The state machine, FF1, FF3, and FF4 are all synchronous to SYSCLK. The following timing diagram helps illus- trate the operation: • The microprocessor (µP) runs off its own clock, PCLK.

• The state machine pulses SET_CE for SYSCLK one SYSCLK cycle when it needs to SET_CE request an interrupt. Q1 A • The microprocessor performs a read

cycle from a predefined address to reset RD_L the interrupt. Although not shown, read- ADDRESS Status Address ing from this address may also cause a RESET_CE status register to be driven onto the Q2

microprocessor’s data bus allowing B simultaneous reading of status and reset- INT ting of interrupt. Figure 5 - Flancter interrupt timing diagram • FF3 and FF4 are resynchronizing flip-

56 Column Distribution Distribution Adds Value: Intel StrongARM Supported with Xilinx Spartan-II FPGAs Avnet is a key member of the Xilinx sales force, helping our customers create solid designs using innovative development tools by Russ Sinagra Marketing Manager GPD, Xilinx [email protected] SDRAM control, and the A number of Avnet customers, in various StrongArm interface as a starting locations across North America, were look- point for your specific applica- ing for a simple and flexible way to develop tion. In addition to the IP core, a PCI interface to an Intel StrongARM software is provided to help processor, and several Avnet FAEs (Field develop your embedded appli- Applications Engineers) across the country cation. Applications develop- helped their customers develop unique ment software is also available from Avnet solutions for their individual designs. Then, Design Services or third parties. Avnet during an Avnet FAE design review where Design Services can also provide engineer- the PCI requirements of different cus- ing consulting services, helping you to tomers were discussed, it became apparent A StrongArm SA1110 Processor provides quickly customize your design to further that there were a number of common the processing power and a Xilinx Spartan- speed your time to market. requirements for a PCI interface—and they II XC2S100 implements a glueless inter- realized there was a common solution to face between the SA1110 processor bus The kit sells for $8,995.00 and is available many different problems. and the industry standard PCI bus. Along now from your local Avnet distributor. For with these hardware resources, Avnet more information, visit the Avnet site at: By using Spartan-II FPGAs from Xilinx, the Design Services provides IP cores for PCI, http://www.ads.avnet.com Avnet FAEs knew they had a great opportu- nity to provide an aggressively priced yet flex- ible PCI connection that would meet the needs of many customers. The FAEs knew that this would be a great way to highlight a number of Avnet Design Services (ADS) strengths as well. The CatapultTM StrongARM PCI Development Kit Avnet combined their ADS board-level solution services, their FPGA services, and their ability to create Intellectual Property, to create the Catapult StrongArm PCI Development Kit, a solution that covers many needs (Fig.1). This kit gives you a time-to-market boost by integrating all the key product technologies into a single development environment. Figure 1 - Catapult block diagram

57 Reference Virtex

Virtex and XC4000X Series FPGAs

Each Virtex family has its own unique fea- The XC4000X Series is part of the broad Designed in an advanced 0.25 micron tures to meet different application require- spectrum of Xilinx “XL” products unveiled process, the XC4000X series delivers indus- ments. All devices have both distributed September, 1998. As a result, Xilinx offers try-leading performance while significantly RAM and block RAM, and between four the broadest choice of 3.3 volt and 2.5 volt reducing power consumption. and eight DLLs for efficient clock manage- devices available from a single supplier, with ment. densities ranging from 800 to 500,000 sys- tem gates. With 12 family members ranging See www.xilinx.com • The Virtex family, consisting of devices for more information. from 30,000 to 500,000 system gates, the that range from 50K up to 1 million logic devices feature patented SelectRAM memo- gates, supports 17 I/O standards, and offers ry, with a highly flexible arrangement of 5V PCI compliance. logic, single-port, or dual-port memory. • The Virtex-E family offers the highest logic gate count available for FPGA Product Selection Matrix any FPGA, ranging DENSITY FEATURES from 50K up to 3.2 FPGA Product Selection Matrix million system gates, and supports 20 I/O

standards including DEVICES KEY FEATURES Logic Cells Maximum Logic Gates System Typical Gate Range Max. RAM Bits CLB Matrix CLBs Flip-Flops Max. I/O Output Drive (mA) PCI Compliant 1.8 Volt 2.5 Volt 3 Volt 5 Volt LVPECL, LVDS, and XC4013XLA 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y –––X Bus LVDS differential XC4020XLA 1862 20K 13K-40K 25K 28x28 784 2016 205 12/24 Y –––X XC4028XLAXC4000 Series: 2432 28K 18K-50K 33K 32x32 1024 2560 256 12/24 Y –––X signaling. Density XC4036XLA 3078 36K 22K-65K 42K 36x36 1296 3168 288 12/24 Y –––X Leadership/ • The Virtex-EM XC4044XLAHigh Performance/ 3800 44K 27K-80K 51K 40x40 1600 3840 320 12/24 Y –––X Extended Memory XC4052XLASelectRAM 4598 52K 33K-100K 62K 44x44 1936 4576 352 12/24 Y ––X* Memory family consists of two XC4062XLA 5472 62K 40K-130K 74K 48x48 2304 5376 384 12/24 Y ––X* XC4085XLA 7448 85K 55K-180K 100K 56x56 3136 7168 448 12/24 Y ––X devices that have a * XCV50 1728 21K 34K-58K 56K 16x24 384 1536 180 2/24 Y ––X* high RAM-to-logic XCV100 2700 32K 72K-109K 78K 20x30 600 2400 180 2/24 Y ––X* gate ratio that is target- XCV150Virtex Family: 3888 47K 93K-165K 102K 24x36 864 3456 260 2/24 Y – X I/O * ed for specific applica- Density/ XCV200Performance 5292 64K 146K-237K 130K 28x42 1176 4704 284 2/24 Y – X I/O * tions such as gigabit XCV300Leadership 6912 83K 176K-323K 160K 32x48 1536 6144 316 2/24 Y – X I/O * per second network XCV400BlockRAM 10800 130K 282K-468K 230K 40x60 2400 9600 404 2/24 Y – X I/O * Distributed RAM – X I/O switches and high defi- XCV600SelectI/O 15552 187K 365K-661K 312K 48x72 3456 13824 512 2/24 Y * nition graphics. XCV8004 DLLs 21168 254K 511K-888K 406K 56x84 4704 18816 512 2/24 Y ––X* XCV1000 27648 332K 622K-1,124K 512K 64x96 6144 24576 512 2/24 Y ––X* XCV50E 1728 21K 47K-72K 88K 16x24 384 1536 176 2/24 Y X I/O I/O ** XCV100E 2700 32K 105K-128K 118K 20x30 600 2400 176 2/24 Y X I/O I/O ** XCV200EVirtex-E Family: 5292 64K 215K-306K 186K 28x42 1176 4704 284 2/24 Y X I/O I/O ** Density/ XCV300E 6912 83K 254K-412K 224K 32x48 1536 6144 316 2/24 Y X I/O I/O ** Performance XCV400ELeadership 10800 130K 413K-570K 310K 40x60 2400 9600 404 2/24 Y X I/O I/O ** XCV600EBlockRAM 15552 187K 679K-986K 504K 48x72 3456 13824 512 2/24 Y X I/O I/O ** XCV1000EDistributed RAM 27648 332K 1,146K-1,569K 768K 64x96 6144 24576 660 2/24 Y X I/O I/O ** SelectI/O+ XCV1600E8 DLLs 34992 420K 1,628K-2,189K 1062K 72x108 7776 31104 724 2/24 Y X I/O I/O ** XCV2000ELVDS, BLVDS, 43200 518K 1,857K-2,542K 1240K 80x120 9600 38400 804 2/24 Y X I/O I/O ** XCV2600ELVPECL 57132 686K 2,221K-3,264K 1530K 92x138 12696 50784 804 2/24 Y X I/O I/O ** XCV3200E 73008 876K 2,608K-4,074K 1846K 104x156 16224 64896 804 2/24 Y X I/O I/O ** XCV405EVirtex Extended 10800 130K 1,068K-1,307K 710K 40x60 2400 9600 404 2/24 Y X I/O I/O ** XCV812EMemory Capabilities 21168 254K 2,569K-3,062K 1414K 56x84 4704 18816 556 2/24 Y X I/O I/O ** * I/Os are 5V tolerant ** 5 Volt tolerant I/Os with external resistor X = Core and I/O voltage 58 I/Os = I/O voltage supported Reference Spartan

Robust Feature Set Advantages Over ASICs • Flexible on-chip distributed and • No costly NRE charges. block memory. • No time consuming vector generation • Four digital Delay Locked Loops for needed. Say hello to a new level of performance; the efficient chip-level/board-level clock • All devices are 100% tested by Xilinx. Spartan-II family now includes devices management. with over 200,000 system gates, and you • Field upgradeable (remotely upgrade- • Select I/O Technology for interfacing get 100,000 system gates for under $10, at able, using Xilinx Online technology). speeds of 200Mhz and beyond, giving you with all major bus standards such as design flexibility that’s hard to beat. These HSTL, GTL, SSTL, and so on. • No lengthy prototype or production lead times. low-powered, 2.5-V devices feature I/Os • Full PCI compliance. that operate at up to 3.3V with full 5-V • Priced aggressively against comparable • System speeds over 200 MHz. tolerance. Spartan-II devices also feature ASICs. multiple Delay Locked Loops, on-chip • Power management. RAM (block and distributed), and versatile Extensive Design Support I/O technology that supports over 16 high- For more information see www.xil- performance interface standards. You get • Complete suite of design tools. inx.com/products/spartan2 all this in an FPGA that offers unlimited • Extensive core support. programmability, and can even be upgrad- ed in the field, remotely, over any network. • Compile designs in minutes.

FPGA Product Selection Matrix DENSITY FEATURES FPGA Product Selection Matrix

DEVICES KEY FEATURES Logic Cells Maximum Logic Gates System Typical Gate Range Max. RAM Bits CLB Matrix CLBs Flip-Flops Max. I/O Output Drive (mA) PCI Compliant 1.8 Volt 2.5 Volt 3.3 Volt 5.0 Volt XCS05Spartan Family: 238 3K 2K-5K 3K 10x10 100 360 77 12 Y ––– X XCS10High Volume 466 5K 3K-10K 6K 14x14 196 616 112 12 Y ––– X ASIC XCS20 950 10K 7K-20K 13K 20x20 400 1120 160 12 Y ––– X Replacement/ XCS30High Performance/ 1368 13K 10K-30K 18K 24x24 576 1536 192 12 Y ––– X XCS40SelectRAM Memory 1862 20K 13K-40K 25K 28x28 784 2016 205 12 Y ––– X XCS05XLSpartan-XL Family: 238 3K 2K-5K 3K 10x10 100 360 77 12/24 Y ––X * XCS10XLHigh Volume 466 5K 3K-10K 6K 14x14 196 616 112 12/24 Y ––X * ASIC XCS20XLReplacement/ 950 10K 7K-20K 13K 20x20 400 1120 160 12/24 Y ––X * XCS30XLHigh Performance/ 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y ––X * XCS40XLSelectRAM Memory 1862 20K 13K-40K 25K 28x28 784 2016 224 12/24 Y ––X * XC2S15 432 8K 6K-15K 22K 8x12 96 384 86 2/24 Y – X I/0 * XC2S30Spartan-II Family: 972 17K 13K-30K 36K 12x18 216 864 132 2/24 Y – X I/0 * High Volume XC2S50BlockRAM 1728 30K 23K-50K 56K 16x24 384 1536 176 2/24 Y – X I/0 * XC2S100Distributed RAM 2700 53K 37K-100K 78K 20x30 600 2400 196 2/24 Y – X I/0 * XC2S150SelectI/O 3888 77K 52K-150K 102K 24x36 864 3456 260 2/24 Y – X I/0 * 4 DLLs XC2S200 5292 103K 71K-200K 130K 28x42 1,176 4704 284 2/24 Y – X I/0 * * I/Os are tolerant X = Core and I/O voltage I/Os = I/O voltage supported 59 Reference CPLDs

XC9500 and CoolRunner CPLDs

Whether performing WebPOWERED Software Solutions - Offer modules for ABEL/HDL synthesis and high speed network- you the flexibility to target the XC9500 simulation, device fitting, and JTAG ing-based or power- and CoolRunner Series CPLDs on-line or programming. conscious portable on the desktop, including: Through leading performance, free inter- designs, Xilinx • WebFITTER - an on-line device fitting net-based WebPOWERED software and CPLDs provide you and evaluation tool that accepts HDL, the industry’s lowest power consumption, with a complete ABEL, or netlist files and provides all Xilinx has the right CPLD for every range of value ori- reports, simulation models, and pro- designer’s need. ented products. gramming files, along with price quotes. See www.xilinx.com/products/cpldsolu- • WebPACK - downloadable desktop solu- tions/index.htm for more information XC9500 - Offers industry- tions that offer free CPLD software leading speeds, while giv-

ing you the flexibility of an CPLD Product Selection Matrix Density Features enhanced customer-proven pin-locking architecture along with extensive IEEE

Core Voltage

CPLD Family

Devices

Key Features

Macrocells

Max. I/O

Pin-to-Pin Delay (ns)

System Frequency

Individual OE Ctrl

JTAG

Ultra Low-Power

Philips Std. 1149.1 JTAG Part Number Boundary-Scan support. XC9536XLBest Pin-Locking 36 36 4 200 √√ XC9572XLJTAG w/Clamp 72 72 5 178.6 √√ XC9500XL CoolRunner - Offers the XC95144XLHigh Performance 144 117 5 178.6 √√ High Endurance patented Fast Zero Power XC95288XL 288 192 6 151 √√ (FZP() design technology, XCR3032XL 32 32 5 200 √√ XCR3064XLUltra Low Power 64 64 6 166 √√ combining low power and JTAG XPLA3 XCR3128XL 128 104 6 166 √√ high speed. These devices 3.3 Volt Increased Logic ISP XCR3256XLFlexibility 256 160 7.5 133 √√ offer standby currents of XCR3384XL 384 216 7.5 133 √√ less than 100 microamps, XCR3032A 32 32 6 111 √√PZ3032A XPLA- XCR3064AUltra Low Power 64 64 7.5 95 √√PZ3064A operating currents 50-67% Enhanced JTAG lower than traditional XCR3128A 128 96 7.5 95 √√PZ3128A XCR3320Ultra Low Power 320 192 7.5 100 √√PZ3320C CPLDs, and pin-to-pin XPLA2 XCR3960High Density 960 384 7.5 100 √√PZ3960C speeds of 5.0ns. XC9536 36 34 5 100 √√ XC9572 72 72 7.5 83.3 √√ XC95108Best Pin-Locking 108 108 7.5 83.3 √√ XC9500 JTAG XC95144 144 133 7.5 83.3 √√ High Endurance 5 Volt XC95216 216 166 10 66.7 √√ ISP XC95288 288 192 10 66.7 √√ XCR5032C 32 32 6 111 √√PZ5032C XPLA- XCR5064CUltra Low Power 64 64 7.5 105 √√PZ5064C JTAG Enhanced XCR5128C 128 96 7.5 100 √√PZ5128C

60 Reference PROMs

XC18V FPGA Configurations 3.3V Configuration PROMs JTAG PROM Density PD8 SO20 PC20 PC44 VQ44 ISP XC17V XC1765EL(X) 64Kb XXXX XC17128EL(X) 128Kb X X X XC17256EL(X) 256Kb X X X XC17S XC17512L 512Kb X X X XC1701L 1Mb X X X X XC1702L 2Mb XX XC1704L 4Mb X X XC18V128 128Kb X X X XC18V512 512Kb X X X X XC18V01 1Mb X X X X XC18V02 2Mb X X X Xilinx offers a full range of configuration memo- XC18V04 4Mb X X X Note: XC1700EL parts are marked with an “X” instead of “EL” ries optimized for use with Xilinx FPGAs. Our PROM product lines are designed to meet the same stringent demands as our high-performance 3.3V Configuration PROMs for Spartan-XL/Spartan-II FPGAs and CPLDs, taking full advantage of the FPGA Configuration Bits Family PROM Solution PD8 VO8 SO20 same advanced processing technologies. In addi- XCS05XL 54,544 Spartan XL XC17S05XL X X XCS10XL 95,752 Spartan XL XC17S10XL X X tion, they were developed in close cooperation XC2S15 197,696 Spartan II XC17S15XL X X with Xilinx FPGA designers for optimal perform- XCS20XL 179,160 Spartan XL XC17S20XL X X XCS30XL 249,168 Spartan XL XC17S30XL X X ance and reliability. XC2S30 336,768 Spartan II XC17S30XL X X XCS40XL 330,696 Spartan XL XC17S40XL X X* X XC18V: Our in-system re-programmable family XC2S50 559,232 Spartan II XC17S50XL X X XC2S100 781,248 Spartan II XC17S100XL X X provides a feature-rich, fast configuration solution XC2S150 1,041,128 Spartan II XC17S150XL X X unmatched by any other configuration PROM XC2S200 1,335,872 Spartan II XC17S200XL* X X * In development available today, and provides a cost-effective method for re-programming and storing large Xilinx FPGA bitstreams. This family is JTAG ready and Boundary-Scan enabled for exceptional Configuration PROMs for Virtex-E ease-of-use, system integration, and flexibility. Configuration XC17xx/XC18Vxx PD8 PC20 SO20 PC44 VQ44 FPGA Bits Solution XC17V/XC17S: Our low-cost XC17V and XC17S XCV50E 630,048 01 X** X X X*** XCV100E 863,840 01 X** X X X*** families are an ideal configuration solution for XCV200E 1,442,106 02 X X cost-sensitive applications. XC17V00 PROMs are XCV300E 1,875,648 02 X X XCV400E 2,693,440 04 X X pin-compatible with our 18V family to allow for a XCV405E 3,430,400 04 X X cost-reduction migration path as your production XCV600E 3,961,632 04 X X volumes increase. The XC17S family is specially XCV812E 6,519,648 04+04 or 08* X X XCV1000E 6,587,520 04+04 or 08* XX designed to provide a low-cost, integrated solution XCV1600E 8,308,992 04+04 or 08* XX for our Spartan families of FPGAs. XCV2000E 10,159,648 04+08* or 16* XX XCV2600E 12,922,336 16* X X XCV3200E 16,283,712 16* X X * In development ** Available on XC17xx only *** Available in XC18Vxx only

Configuration PROMs for Virtex FPGA Configuration XC17xx/XC18Vxx PD8 PC20 SO20 PC44 VQ44 Bits Solution XCV50 558,048 01 X* X X X** XCV100 780,064 01 X* X X X** XCV150 1,038,944 01 X* X X X** XCV200 1,334,688 02 XX XCV300 1,750,656 02 X X XCV400 2,544,896 04 X X XCV600 3,606,816 04 X X XCV800 4,714,400 04 + 512 X X XCV1000 6,126,528 04 + 02 X X * Available on XC17xx only ** Available on XC18Vxx only

61 Reference QPRO QPRO QML-Certified FPGAs and PROMs

The Xilinx QPRO family of Radiation The Virtex QPRO family of High because their systems can retain consistent Hardened FPGAs and PROMs are finding Reliability products is experiencing a high form, fit, and function through the use of homes in many new satellite and space degree of success in the defense market. As Virtex QPRO FPGAs. This cannot be applications. Both the XQR4000XL and designers find it more and more difficult to achieved with costly and inflexible ASICs XQVR Virtex products are being designed find components suitable for the harsh or custom logic. into space systems that will utilize reconfig- environments seen by defense systems, they Please visit http://www.xilinx.com/prod- urable technology. Numerous communica- are discovering that they can incorporate ucts/hirel_qml.htm for all the latest infor- tions and GPS satellites, space probe, and the functions of obsolete parts into Virtex mation about these products, including shuttle missions are included on the grow- QPRO products. This has the added long some new applications notes. ing list of programs that will be flying these term advantage of significantly reducing devices. the costs of future re-qualifications,

FPGA Product Selection Matrix DENSITY FEATURES

DEVICES KEY FEATURES Logic Cells Maximum Logic Gates System Typical Gate Range Max. RAM Bits CLB Matrix CLBs Flip-Flops Max. I/O Output Drive (mA) PCI Compliant 1.8 Volt 2.5 Volt 3 Volt 5 Volt XQR/XQ4013XLXC4000 Series: 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y ––X * Density XQR/XQ4036XLLeadership/ 3078 36K 22K-65K 42K 36x36 1296 3168 288 12/24 Y ––X * High Performance/ XQR/XQ4062XLSelectRAM 5472 62K 40K-130K 74K 48x48 2304 5376 384 12/24 Y ––X * XQ4085XLMemory 7448 85K 55K-180K 100K 56x56 3136 7168 448 12/24 Y ––X * Virtex Family: – X I/O * XQV100Density/ 2700 32K 72K-109K 78K 20x30 600 2400 180 2/24 Y **XQVR/XQV300Performance 6912 83K 176K-323K 160K 32x48 1536 6144 316 2/24 Y – X I/O * Leadership **XQVR/XQV600BlockRAM 15552 187K 365K-661K 312K 48x72 3456 13824 512 2/24 Y – X I/O * Distributed RAM **XQVR/XQV1000SelectI/O 4 DLLs 27648 332K 622K-1,124K 512K 64x96 6144 24576 512 2/24 Y – X I/O *

* I/Os are tolerant ** XQR and XQVR devices are Radiation Hardened X = Core and I/O voltage I/Os = I/O voltage supported

(1) All devices specified from -55°C to +125°C (2) Selected XQ4000E/EX devices also available QPRO QML-certified PROMs Package Device Density DD8 SO20 CC44 PC44 XC1736D 36Kb X XC1765D 64Kb X XC17128D 128Kb X XC17256D 256Kb X XQR/XQ 1701L* 1Mb X X XQR/XQ 1704L* 4Mb X X** * XQR devices are Radiation Hardened. ** XQ devices only.

62 Reference Software

Lead Product Feature Comparison Alliance Series Foundation Series ISE Series ALI-STD ALI-ELI FND-EXP FND-ELI FND-BAS FND-BSX ISE-ELI ISE-EXP ISE-BSX Xilinx development systems give you the Design Entry speed you need. With version 3.1i solu- Schematic Entry √√√√√√√ HDL Entry √√√√√√√ tions, Xilinx place and route times are as ABEL Entry √√√√√√√ fast as 2 minutes for our 200,000 gate, HDL Editor √√√√√√√ XC2S200 Spartan(r)-II device, and 30 State Diagram Editor √√√√VSS* VSS* VSS* minutes for our 1 million gate, system-level Environment Operating System PC/UNIX PC/UNIX PC PC PC PC PC PC PC XCV1000E Virtex(tm)-E device. That Simulation makes Xilinx development systems the Gate Level Timing Simulation √√√√ fastest in the industry. HDL Simulation MTI** MTI** MTI** MTI** MTI** MTI** MTI** MTI** MTI** HDL Test Bench Generator VSS* VSS* VSS* And with the push of a button, our timing- Synthesis driven tools are creating designs that sup- Xilinx Synthesis Technology (XST) √√√ FPGA Express √√√√√√√ port I/O speeds in excess of 800 Mbps, and Incremental Synthesis √√√√√√√ internal clock frequencies in excess of 300 System Features ALI-STD ALI-ELI FND-EXP FND-ELI FND-BAS FND-BSX ISE-ELI ISE-EXP ISE-BSX MHz. Constraints editor √√√√√√√√√ Floorplanner √√√√√√√√√ These development solutions combine CPLD ChipViewer √√√√√√√√√ powerful technology with a flexible, easy to Pin Editor √√√√√√√√√ use graphical interface to help you achieve FPGA Editor √√√√√√√√√ Core Generator included √√√√√√√√√ the best possible designs within your proj- Configuration by cable √√√√√√√√√ ect schedule, regardless of your experience Error navigation to Xilinx Web √√√ level. Command line operation √√√ HTML timing reports √√√√√√√√√ Data Book I/O timing √√√√√√√√√ Project archiving √√√√√√√√√ System Interfaces EDIF in √√√√√√ PROM file generation √√√√√√√√√ JTAG download software √√√√√√√√√ IBIS √√√√√√√√√ STAMP √√√√√√√√√ VHDL, Verilog √√√√√√√√√ HDL Simulation libraries √√√√√√√√√

*VSS - Delivered as part of the ALLSTAR program or as a backPACK module in WebPACK

Lead Product Device Support Comparison Alliance Series Foundation Series ISE Series Family Part Number ALI-STD ALI-ELI FND-EXP FND-ELI FND-BAS FND-BSX ISE-ELI ISE-EXP ISE-BSX Virtex XCV50 only √√ √ All devices up to √√√√ √√ XCV1000 Virtex-E XCV50E only √√ √ All devices up to √√√√ √√ XCV1000E All devices up to √√ √ XCV3200E Virtex-EM XCV405EM √√√√ √√ XCV812EM √√√√ √√ XCSxx Spartan √√√√√√√√√ (All devices) XCSxxXL Spartan XL √√√√√√√√√ (All devices) Spartan-II XC2SxxXL (Includes √√√√√√√√√ XC2S200) XC9500 XV/XL √ XC9500 √√√√√√√√ Series (All devices) XC4000E/L/EX √ XC400 √√√√√√√√ Series (All devices) XC4000XL/XLA (All devices up to √√ √ XC4020) XC4000XL/XLA √√√√ √√ (All devices) XC4000XV √√√√ √√ (All devices) XC3x00A/L XC3000 √√√√√√ Series (All devices) XC5200 XC5200 √√√√√√ Series (All devices)

*Note: CoolRunner Series is only available in WebFITTER and WebPACK at this time. 63 You can bet your ASIC on it.

The Spartan®-II family offers a costs, there’s also multiple Delay Locked Loops, on-chip winning combination of perfor- RAM (block and distributed), and our unique SelectI/O™ mance and price. In fact with interface technology. over 200,000 system gates, clock Xilinx IP Center completes speeds beyond 200MHz, and lightning fast the total solution compile times, Spartan-II FPGAs give you the The Xilinx IP Center brings you all the best dollar value in the industry. FPGA cores, reference designs, design Get rid of the risk services and third party support you could Now you’ve got the design flexibility you’ve wish for, all easily available via the web. been waiting for, without any annoying NRE Find out more today by visiting us at costs, strung-out production times, or the design www.xilinx.com/sp1.htm. You’ll soon see risks associated with a typical ASIC. To save system why you can bet your ASIC on us.

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