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Synchronous Ethernet explained
1. FROM ASYNCHRONOUS TO SYNCHRONOUS ETHERNET
Synchronous Ethernet is an ITU-T standard that provides mechanisms to trans- fer frequency over the Ethernet physical layer, which can then be made trace- able to an external source such as a network clock. On this case Ethernet links are part of the synchronization network (see Figure 2). The proposal to specify the transport of a reference clock over Ethernet links was brought by operators to ITU-T Study Group 15 in September 2004. The aim of Synchronous Ethernet is to avoid changes to the existing IEEE Ethernet, but to extend to work as a proper synchronous network.
On many respects the evolution to a synchronous Ethernet network is equiva- lent to the one that occurred from PDH/T-Carrier to SDH/SONET and the causes are similar. The higher bit rates are the most important is to keep transmission synchronized by a unified clock in order to keep clock fluctuations and offsets under control as they are a main cause of errors a poor QoS.
Despite being an IEEE standard, Ethernet architecture has been described in ITU-T G.8010 as a network made up of an ETH layer and a ETY layer. Written in simple terms, the ETY layer corresponds the physical layer as defined in IEEE 802.3, while the ETH layer represents the pure packet layer. Ethernet MAC
Figure 1 ALBEDO Ether.Sync is a field tester for Synchronous Ethernet equipped with all the features to deploy SyncE infrastructures, Precision Time Protocol (PTP / IEEE 1588v2) and Gigabit Ethernet supporting legacy while new test such as eSAM Y.1564
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frames at the ETH layer are carried as a client of the ETY layer. In OSI termi-
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nology, ETY is layer 1, ETH layer 2. Synchronous Ethernet is based on the P
A ITU-T G.8010 description of the Ethernet architecture.
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A key issue in Synchronous is the definition of the mechanisms necessary to
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age. These mechanisms and procedures are found fundamentally in three D
E different recommendations: ITU-T G.8261, G.8262 and G.8264. The aspects
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8 • ITU-T G.8262 defines Synchronous Ethernet clocks compatible with SDH
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3 clocks. Synchronous Ethernet clocks, based on ITU-T G.813 clocks, are de-
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t fined in terms of accuracy, noise transfer, holdover performance, noise tol-
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5 Equipment Slave clocks. While the IEEE 802.3 standard specifies Ethernet
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g clocks to be within ±100 ppm. EECs accuracy must be within ±4.6 ppm. In
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Synchronus Ethernet Synchronus Ethernet Backplane Backplane
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±100 ppm ±100 ppm
Standard Ethernet Standard Ethernet
Figure 2 Synchronous Ethernet Architecture and comparison with conventional Ethernet.
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o • ITU-T G.8264 extends the usability of the ITU-T G.707 Synchronization Status
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, Message (SSM) by Synchronous Ethernet equipment. The SSM contain an in-
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Ethernet Synchronization Messaging Channel
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e l In SDH, the SSM provides traceability of synchronization signals and it is
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A In SDH, the SSM message is carried in fixed locations within the SDH frame. However, in Ethernet there is no equivalent of a fixed frame. The mecha- nisms needed to transport the SSM over Synchronous Ethernet are defined by the ITU-T in G.8264 in cooperation with IEEE. More specifically, the ESMC, defined by the ITU-T is based on the Organization Specific Slow Protocol (OS- SP), currently specified in IEEE 802.3ay.
The ITU-T G.8264 defines a background or heart-beat message to provide a continuous indication of the clock quality level. However, event type mes- sages with a new SSM quality level are generated immediately.
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The ESMC protocol is composed of the standard Ethernet header for a slow
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protocol, an ITU-T specific header, a flag field, and a type length value (TLV) P
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whose meaning is described in ITU-T G.781.
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D 2. HANDS-ON: TESTING SYNCHRONIZATION
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Basic TDM and Packet Test
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A 1 1 A1* A2* J0* A1* A1* A1* A2* A2* A2* J0* X* X* J0: Section Trace A1= 11110110, A2= 00101000: Frame Alignment B1 E1 F1 B1 ^ ^ E1 ^ F1 X X B1: Section Parity Code BIP-8 D1 D2 D3 D1 ^ ^ D2 ^ D3 B2: Bit interleaved parity, D1-D3: 192-kbit/s OA&M data H1 H2 H3 Pointer (s) D4-D12: 576-kbit/s OA&M data E1, E2: 64-kbit/s orderwire channels B2 K1 K2 B2 B2 B2 K1 K2 F1: 64-kbit/s user channel H1, H2, H3: pointer bytes D4 D5 D6 D4 D5 D6 K1, K2: Request /answer APS channels D7 D8 D9 D7 D8 D9 F1: 64-kbit/s user channel M0, M1: Resending of B2 errors D10 D11 D12 D10 D11 D12 Z0: reserved
9 S1 M1 E2 9 S1 M1 E2 X X S1: SSM (Synchronization Status Messages)
Figure 4 Sections overheads in SDH / SONET. Synchronization Status Messages (SSM): This is used to inform the remote multiplexer on the quality of the clock used to generate the signals. 0x: Unknown, 2x: G811, 4x: G.812 transit, 8x: G.812 local, Bx: G.813, Fx: Not used for synchronization.
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TDM Jitter / Wander Measurements
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A range of standards including ITU-T G.823/G.824 specify the performance of
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setups, test pattern, measurement parameters, as well as the limits for net- I
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The ALBEDO Ether.Sync conduct jitter/wander measurements up to GbE in D
E compliance with ITU-T recs.O.171, O.172, and O.173. MTIE and TDEV are key
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parameters for verifying synchronization function. MTIE is useful in captur-
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2 ing the phase transients in a timing signal, because it describes the maximum
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5 phase variation of a timing signal over a period of time. However, MTIE
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mator rather than peak estimator. TDEV tends to remove transients in the
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t The ITU-T specifies requirements for TDM network timing and synchroniza-
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L 1324 5 6 7 8bytes A Slow Protocol Ethertype (0x88-09) 2 Type (0x01) 1 ITU-T G.8264 Slow Protocol Subtype (0x0a) 1 Length (0x00-04) 2 ESMC message ITU-OUI (00-19-a7) 3 Reserved (0x0) SSM code 1
ITU Subtype 2 Version Flg
Reserved 4
TLV 4
Future enhancement TLV 32~1486
FCS 4
Figure 5 Ethernet Synchronization Message Channel (ESMC) protocol data unit rec. ITU-T G.8264.
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3 Figure 6 ALBEDO Ether.Sync and ALBEDO Ether.Genius are testers to test SyncE circuits by decoding and
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A vides reference timing for the network, which is propagated throughout the network via the enhanced physical layer specifications of SyncE circuits. In- formation identifying the qualify level (QL message) of the master clock driv- ing the synchronization chain is passed through the network via sync status messages (SSM) in the Ethernet synchronization messaging channel (ESMC) that are contained in specialized Ethernet frames sent periodically, one per second.
Telecom field experts can verify SyncE circuits by decoding and displaying the SSM, capturing ESMC messages, and measuring the received frequency off- set (ppm). It also can during Ethernet service turn-up test traffic can be gen- erated using an external reference or recovered SyncE timing to ensure proper SyncE traffic propagation (see Figure 6).
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Alternatively engineers may also use ALBEDO Net.Shark which is a is a FPGA
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to Wireshark where they can be decoded (see Figure 7).
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R [1] Sargento S., Valadas R., Gonçalves J., Sousa H., IP-Based Access Networks for Broadband Multimedia Services,
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o IEEE Communications Magazine, February 2003, pp. 146-154.
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T [2] Ferrant J., Gilson M., Jobert S., Mayer M., Ouellette M., Montini L., Rodrigues S., Ruffini S., Synchronous Ethernet:
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D A Method to Transport Synchronization, IEEE Communications Magazine, September 2008, pp. 126-134.
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A [3] Vainshtein A., Stein YJ., Structure-Agnostic Time Division Multiplexing (TDM) over Packet (SAToP), IETF Request For Comments RFC 4553, Jun. 2006. [4] Vainshtein A., Sasson I., Metz E., Frost T., Pate P., Structure-Aware Time Division Multiplexed (TDM) Circuit Emu- lation Service over Packet Switched Network (CESoPSN), IETF Request For Comments RFC 5086, Dec. 2007. [5] ITU-T Rec. Y.1413, TDM-MPLS network interworking - User plane interworking, March 2004. [6] ITU-T Rec. Y.1453, TDM-IP interworking - User plane interworking, March 2006. [7] ITU-T Rec. G.8261, Timing and Synchronization Aspects in Packet Networks, February 2008. [8] ITU-T Rec. G.8262, Timing Characteristics of Synchronous Ethernet Equipment Slave Clock (EEC), August 2007. [9] ITU-T Rec. G.8264, Distribution of Timing Through Packet Networks, February 2008. [10] Metro Ethernet Forum Technical Specification MEF 8, Implementation Agreement for the Emulation of PDH Cir- cuits over Metro Ethernet Networks, October 2004. [11] Metro Ethernet Forum Technical Specification MEF 18, Abstract Test Suite for Circuit Emulation Services over Ethernet based on MEF 8, May 2007.
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