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Multimedia Soc Design Shao-Yi Chien 2 Outline Introduction to SoC, Multimedia Systems, and ESL Shao-Yi Chien 教育部顧問室1 SLD Course Material VLSI教育改進計畫 Outline ◼ Introduction to SoC ◼ Relationship between SoC and multimedia systems ◼ Challenges for SoC Design ◼ SoC design methodologies ◼ New SoC design methodologies: ESL ◼ Modeling issues ◼ Some existing system-level design tools ◼ Conclusion Multimedia SoC Design Shao-Yi Chien 2 Outline ◼ Introduction to SoC ◼ Relationship between SoC and multimedia systems ◼ Challenges for SoC Design ◼ SoC design methodologies ◼ New SoC design methodologies: ESL ◼ Modeling issues ◼ Some existing system-level design tools ◼ Conclusion Multimedia SoC Design Shao-Yi Chien 3 Silicon Evolution Multimedia SoC Design Shao-Yi Chien 4 Why System-on-a-Chip? Design Paradigm Shift Yesterday Today Multimedia SoC Design Shao-Yi Chien 5 Changes in the Nature of IC Design System on a chip Block design system-design tools Design efficiency, gates per Library-based Cell array person-day chip Chip-design tools Transistor Handcrafted custom chips Transistor models (IEEE Spectrum Nov,1996) Multimedia SoC Design Shao-Yi Chien 6 From ASIC to SoC Yesterday Today •HW only •Heterogeneous •Multiple SW stacks •Perfect interconnection •CPU + dedicated HW •Non perfect interconnect MINORITY A B C SW On Cout S S - Chip Communication Network CommunicationChip HW SW CPU Cout SW module counter( HW clk, //Clock signal. reset_n, //Async. reset signal, active low. enable, //Sync. enale signal. The counter won't act without enable==1'b1. CPU HW data //output counter data. ); input clk; //Clock signal. CPU input reset_n; //Async. reset signal, active low. input enable; //Sync. enale signal. The counter won't act without enable==1'b1. output [1:0] data; //output counter data. reg [1:0] data, data_w; ..... always@(posedge clk or negedge reset_n) SW HW begin if(!reset_n) begin data <= #1 2'd0; end else begin CPU data <= #1 data_w; end end endmodule Multimedia SoC Design Shao-Yi Chien 7 Outline ◼ Introduction to SoC ◼ Relationship between SoC and multimedia systems ◼ Challenges for SoC Design ◼ SoC design methodologies ◼ New SoC design methodologies: ESL ◼ Modeling issues ◼ Some existing system-level design tools ◼ Conclusion Multimedia SoC Design Shao-Yi Chien 8 Digital Convergence Personal Consumer Computer Electronics Multimedia Communication Technology Video Systems & Communications Multimedia SoC Design Shao-Yi Chien 9 Multimedia Technology for Human Life ◼ From office to home and the outdoors Any Time ◼ From large devices to portable devices Any Where ◼ From specific people to everybody At Will Multimedia SoC Design Shao-Yi Chien 10 Relationship between SoC and Multimedia Systems ◼ Multimedia systems integrate many subsystems User interface Image/video/audio capturing Image/video/audio displaying Image/video/audio processing and coding Communication and storage ◼ High volume of the consumer electronics ◼ Both the factors make multimedia system a highly possible application for SoC TV/STB, mobile phones, wearable devices, AR/VR, automotive electronics, multimedia players, multimedia portable players, game consoles, … Multimedia SoC Design Shao-Yi Chien 12 SoC Example: Set Top Box Controller Multimedia SoC Design Shao-Yi Chien 13 SoC Example: Multimedia Mobile Phones (1) ◼ Renesas application processor for 3G cellular phones T. Kamei et al., “A resume-standby application processor for 3G cellular phones,” ISSCC Dig. Tech. Papers, pp. 336—337, Feb., 2004. Multimedia SoC Design Shao-Yi Chien 14 SoC Example: Multimedia Mobile Phones (2) T. Kamei et al., “A resume-standby application processor for 3G cellular phones,” ISSCC Dig. Tech. Papers, pp. 336—337, Feb., 2004. Multimedia SoC Design Shao-Yi Chien 15 SoC Example: Smartphone Processor http://event.mediatek.com/_en_octacore/index.html Multimedia SoC Design Shao-Yi Chien 16 SoC Example: Smartphone Processor Multimedia SoC Design Shao-Yi Chien 17 SoC Example: Smartphone Processor ◼ Snapdragon 845 Multimedia SoC Design Shao-Yi Chien 18 SoC Example: Smartphone Processor Multimedia SoC Design Shao-Yi Chien 19 Outline ◼ Introduction to SoC ◼ Relationship between SoC and multimedia systems ◼ Challenges for SoC Design ◼ SoC design methodologies ◼ New SoC design methodologies: ESL ◼ Modeling issues ◼ Some existing system-level design tools ◼ Conclusion Multimedia SoC Design Shao-Yi Chien 20 SoC Dilemmas ❑ While SoC complexity is increasing, the time to market of consumer products is decreasing. ❑ IC designer lacks expertise of system developers. ❑ How to integration of internal virtual components (VC) and external VC? Multimedia SoC Design Shao-Yi Chien 21 Engineering Productivity Gap ❑ Engineering productivity has not been keeping up with silicon gate capacity for several years. ❑ Companies have been using larger design teams, making engineers work longer hours, etc., but clearly the limit is being reached. Multimedia SoC Design Shao-Yi Chien 22 Challenges ❑ Interoperability and Integration IPs (Intellectual properties) present a multitude of interoperability and integration challenges. System- Level Integration IPs may come in several forms: Hard, Soft, Firm Common interface between blocks? Multimedia SoC Design Shao-Yi Chien 23 Challenges (cont.) ❑ EDA Tool Interoperability These data formats may or may not be compatible. Standardizing these diverse data formats. ❑ Testing an SoC An SoC’s complexity requires extensive. It’s necessary to test each VC separately. ❑ Process-Level Portability Soft IP & Firm IP Hard IP Multimedia SoC Design Shao-Yi Chien 24 Outline ◼ Introduction to SoC ◼ Relationship between SoC and multimedia systems ◼ Challenges for SoC Design ◼ SoC design methodologies ◼ New SoC design methodologies: ESL ◼ Modeling issues ◼ Some existing system-level design tools ◼ Conclusion Multimedia SoC Design Shao-Yi Chien 25 Design and Verification Step Specification Design Verification Verification / Design / Validation Refinement Actually, the major problem Implementation is Verification Multimedia SoC Design Shao-Yi Chien 26 Typical SOC design flow ◼ Overlap in specification/architecture phase and RTL-design phase; multiple design changes Architecture design done informally ◼ SW development starting late in the project ◼ Little SW simulation pre-silicon (takes too long) Specification Software Dev. & Architecture Physical Hardware Dev. Design RTL Closure Tape-Out Multimedia SoC Design Shao-Yi Chien 27 SoC Verification Gaps ◼ Different languages are spoken At different levels of abstraction By HW / SW / systems people Problems, bottlenecks, and misunderstandings are detected too late. System RTL / Firmware Chip Multimedia SoC Design Shao-Yi Chien 28 Verification at the Backend Cost to fix a problem Test and Simulations Time Project Project Start End Multimedia SoC Design Shao-Yi Chien 29 SoC Verification Challenges 30% Design 10T 2007 100B 2001 70% 100M 1995 Verification Simulation Simulation Cycles 1M 10M 100M Gates Multimedia SoC Design Shao-Yi Chien 30 System Level Design Matters 65% in 2003 61% of IC designs require one or more Specification re-spins bugs Source: 2002 Collett International RTL bugs Specification and RTL bugs cause re-spins! Multimedia SoC Design Shao-Yi Chien 31 SoC Design Methodologies System-Level IC IP Sourcing IP Integration Chip Chip Fabrication Architecture Implementation •System Architecture •In-house IP •Digital logic •FPGA •3rd party foundry + services •Chip Architecture + •Gate array •Mixed-signal •Technology Selection •3rd party IP •Standard cells •Embedded •Algorithm Develop -Selection •Megacell library -Qualification Memory •Datapath compiler -Licensing •Embedded Micro’s •Memory compiler + •Hand-crafted •In-house tools Note:Shaded area is the conventional ASIC development process (Dr. H. D. Lin in 8th VLSI/CAD workshop ) Multimedia SoC Design Shao-Yi Chien 32 Top-Down Design Flow (RMM) Create System Specification Develop Behavioral Model Characterized Library Refine and Test Behavior Model of Hardware/Software Macros & Interface Determine Hardware/Software Partition Protocols Specify and Develop Specify and Develop IP Simulation Hardware Architecture Prototype Software Model Mode Refine and Test Architecture Model (Hardware/Software Co-simulation) Specify Specify Software Implementation Blocks Multimedia SoC Design Shao-Yi Chien 33 Spiral SOC Design Flow (RMM) System Design and Verification Physical Spec. Timing Spec. Hardware Spec. Software Spec. I/O Timing, Area, Power Algorithm Application Clock Clock Tree Macro Prototype Frequency Block Preliminary Block Timing Prototype selection/ Floorplan Spec Testing design Updated Block Block Application Floorplan Synthesis Verification Development Updated Top-Level Application Floorplan HDL Testing Trial Top-Level Top-Level Application Placement Synthesis Verification Testing Multimedia SoC Design Final PlacementShao-Yi Chien and Route 34 Platform Based Design Multimedia SoC Design Shao-Yi Chien 35 Platform Based Design ◼ Platform An integrated and managed set of common features, upon which a set of products or product family can be built. A platform is a virtual component (VC). ◼ Platform-based design An integration oriented design approach emphasizing systematic reuse, for developing complex products based upon platforms and compatible hardware and software VCs, intended to reduce development risks, costs, and time to market. Multimedia SoC Design Shao-Yi Chien 36 Platform Based Design ◼ More precise definition of platform-based design An organized method to reduce the time required and risk involved in designing and verifying
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