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Virtual Memory and Address Translation

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Virtual Memory and Address Translation Review ! Program addresses are virtual addresses. Ø" Relative offset of program regions can not change during program execution. E.g., heap can not move further from code. Ø" Virtual addresses == physical address inconvenient. " Program location is compiled into the program. ! A single offset register allows the OS to place a process’ virtual Virtual Memory and address space anywhere in physical memory. Address Translation Ø" Virtual address space must be smaller than physical. Ø" Program is swapped out of old location and swapped into new. ! Segmentation creates external fragmentation and requires large regions of contiguous physical memory. Ø" We look to fixed sized units, memory pages, to solve the problem. 1 2 Virtual Memory Realizing Virtual Memory Concept Paging n 2 -1! (fMAX-1,oMAX-1)! ! Key problem: How can one support programs that ! Physical memory partitioned into equal sized require more memory than is physically available? Ø" How can we support programs that do not use all of their page frames memory at once? Ø" Page frames avoid external fragmentation. (f,o)! ! Hide physical size of memory from users n A memory address is a pair (f, o) Ø" Memory is a “large” virtual address space of 2 bytes o Ø" Only portions of VAS are in physical memory at any one Program f — frame number (fmax frames) time (increase memory utilization). o — frame offset (omax bytes/frames) ’ P s Physical address = omax×f + o Physical ! Issues VAS Ø" Placement strategies Memory " Where to place programs in physical memory Ø" Replacement strategies " What to do when there exist more processes than can fit in f memory PA: Ø" Load control strategies 1 " Determining how many processes can be in memory at one log2 (fmax × omax) log2 omax time 0! f o (0,0)! 3 4 Physical Address Specifications Frame/Offset pair v. An absolute index Questions ! Example: A 16-bit address space with (omax =) 512 byte page frames ! The offset is the same in a virtual address and a Ø" Addressing location (3, 6) = 1,542 physical address. (3,6)! 1,542! Ø" A. True o Ø" B. False ! If your level 1 data cache is equal to or smaller than 3 6 Physical 2number of page offset bits then address translation is not Memory necessary for indexing the data cache. PA: 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 Ø" A. True 16 10 9 1 f Ø" B. False 1,542 (0,0)! 0! 5 6 Realizing Virtual Memory Paging Paging Mapping virtual addresses to physical addresses 2n-1 =! (p -1,o -1)! MAX MAX ! Pages map to frames ! A process’s virtual address space is ! Pages are contiguous in a VAS... partitioned into equal sized pages Ø" But pages are arbitrarily located Ø" page = page frame Virtual in physical memory, and (p,o)! Address Ø" Not all pages mapped at all times (f1, o1)! o Space A virtual address is a pair (p, o) p — page number (pmax pages) Virtual o — page offset (o bytes/pages) Physical max Address Virtual address = omax×p + o (p2, o2)! Memory Space p (p1,o1)! (f2, o2)! VA: 1 log2 (pmax×omax) log2 oMAX (0,0)! p o 7 8 Paging Frames and pages Virtual address translation ! A page table maps virtual ! Only mapping virtual pages that are in use does Program (f, o)! what? P pages to physical frames Ø" A. Increases memory utilization. Ø" B. Increases performance for user applications. CPU Ø" C. Allows an OS to run more programs concurrently. Ø" D. Gives the OS freedom to move virtual pages in the virtual P’s p o f o address space. Virtual Physical Address 20 10 9 1 16 10 9 1 ! Address translation and changing address mappings Memory Space are Virtual Addresses Physical Ø" A. Frequent and frequent (p, o)! Addresses Ø" B. Frequent and infrequent f Ø" C. Infrequent and frequent Ø" D. Infrequent and infrequent p Page Table 9 10 Virtual Address Translation Details Virtual Address Translation Details Page table structure Example A system with 16-bit addresses 1 table per process ! Contents: (4,1023)! Ø" 32 KB of physical memory Part of process’s state Ø" Flags — dirty bit, resident bit, clock/ reference bit Ø" 1024 byte pages Ø" Frame number (4,0)! (3,1023)! CPU CPU Physical Addresses p o f o P’s p o f o Virtual Physical 9 9 20 10 9 1 16 10 9 1 Address 15 10 0 14 10 0 Memory Space Virtual Virtual Addresses Addresses Physical Addresses 1 0 0 0 0 0 0 0 PTBR + 0 1 0 f 0 1 1 0 0 1 0 0 p (0,0)! Page Table 11 Page Table 12 Virtual Address Translation Virtual Address Translation Performance Issues Using TLBs to Speedup Address Translation ! Cache recently accessed page-to-frame translations in a TLB Ø For TLB hit, physical page number obtained in 1 cycle ! Problem — VM reference requires 2 memory references! " Ø" For TLB miss, translation is updated in TLB Ø" One access to get the page table entry Ø" Has high hit ratio (why?) Ø" One access to get the data f o Physical ! Page table can be very large; a part of the page table can be on CPU Addresses disk. 16 10 9 1 Ø" For a machine with 64-bit addresses and 1024 byte pages, what is p o the size of a page table? Virtual Addresses 20 10 9 1 ? ! What to do? Ø" Most computing problems are solved by some form of… " Caching Key Value " Indirection p f f TLB p X! 13 Page Table 14 Dealing With Large Page Tables Dealing With Large Page Tables Multi-level paging Multi-level paging ! Add additional levels of indirection to the page table by sub-dividing ! Example: Two-level paging page number into k parts Ø" Create a “tree” of page tables Ø" TLB still used, just not shown Second-Level Ø" The architecture determines the Page Tables CPU Memory number of levels of page table p p o f o 1 2 Virtual Physical Virtual Address Addresses Addresses p2 20 16 10 1 16 10 1 p1 p2 p3 o PTBR + page table + f p3 p1 p2 p1 Third-Level First-Level Page Tables First-Level Second-Level Page Table Page Table Page Table 15 16 The Problem of Large Address Spaces Virtual Address Translation Using Page Registers (aka Hashed/Inverted Page Tables) ! With large address spaces (64-bits) forward mapped page tables ! Each frame is associated with a register containing become cumbersome. Ø" Residence bit: whether or not the frame is occupied Ø" E.g. 5 levels of tables. Ø" Occupier: page number of the page occupying frame Ø" Protection bits ! Instead of making tables proportional to size of virtual address space, make them proportional to the size of physical address ! Page registers: an example space. Ø" Physical memory size: 16 MB Ø" Virtual address space is growing faster than physical. Ø" Page size: 4096 bytes Ø" Number of frames: 4096 ! Use one entry for each physical page with a hash table Ø" Space used for page registers (assuming 8 bytes/register): 32 Ø" Translation table occupies a very small fraction of physical memory Kbytes Ø" Size of translation table is independent of VM size Ø" Percentage overhead introduced by page registers: 0.2% Ø" Size of virtual memory: irrelevant ! Page table has 1 entry per virtual page ! Hashed/Inverted page table has 1 entry per physical frame 17 18 Page Registers Indexing Hashed Page Tables How does a virtual address become a physical address? Using Hash Tables ! Hash page numbers to find corresponding frame number ! CPU generates virtual addresses, where is the Ø" Page frame number is not explicitly stored (1 frame per entry) physical page? Ø" Protection, dirty, used, resident bits also in entry Ø" Hash the virtual address CPU Memory Ø" Must deal with conflicts Virtual ! TLB caches recent translations, so page lookup can p o Address PID f o Physical take several steps running Addresses 20 9 1 16 9 1 Ø" Hash the address Ø" Check the tag of the entry tag check Hash =? =? Ø" Possibly rehash/traverse list of conflicting entries ! TLB is limited in size fmax– 1 Ø" Difficult to make large and accessible in a single cycle. PTBR + PID page 0 1 1 fmax– 2 Ø" They consume a lot of power (27% of on-chip for StrongARM) h(PID, p) 0 Inverted Page Table 19 20 Searching Hahed Page Tables Searching Hashed Page Tables Using Hash Tables Using Hash Tables (Cont’d.) ! Minor complication Ø" Since the number of pages is usually larger than the number of ! Page registers are placed in an array slots in a hash table, two or more items may hash to the same location ! Page i is placed in slot f(i) where f is an agreed-upon hash function ! Two different entries that map to same location are said to collide ! To lookup page i, perform the following: ! Many standard techniques for dealing with collisions Ø" Compute f(i) and use it as an index into the table of page Ø" Use a linked list of items that hash to a particular table entry registers Ø" Rehash index until the key is found or an empty table entry is Ø" Extract the corresponding page register reached (open hashing) Ø" Check if the register tag contains i, if so, we have a hit Ø" Otherwise, we have a miss 21 22 Virtual Memory (Paging) Questions The bigger picture Code Data ! A process’s VAS is its context ! Why use hashed/inverted page tables? Ø" Contains its code, data, and stack Ø" A.
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