CS 152 Computer Architecture and Engineering
Lecture 11 - Virtual Memory and Caches
Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley
http://www.eecs.berkeley.edu/~krste! http://inst.eecs.berkeley.edu/~cs152!
February 25, 2010 CS152, Spring 2010 Today is a review of last two lectures
• Translation/Protection/Virtual Memory • This is complex material - often takes several passes before the concepts sink in • Try to take a different path through concepts today
February 25, 2010 CS152, Spring 2010 2 VM features track historical uses: • Bare machine, only physical addresses – One program owned entire machine • Batch-style multiprogramming – Several programs sharing CPU while waiting for I/O – Base & bound: translation and protection between programs (not virtual memory) – Problem with external fragmentation (holes in memory), needed occasional memory defragmentation as new jobs arrived • Time sharing – More interactive programs, waiting for user. Also, more jobs/second. – Motivated move to fixed-size page translation and protection, no external fragmentation (but now internal fragmentation, wasted bytes in page) – Motivated adoption of virtual memory to allow more jobs to share limited physical memory resources while holding working set in memory • Virtual Machine Monitors – Run multiple operating systems on one machine – Idea from 1970s IBM mainframes, now common on laptops » e.g., run Windows on top of Mac OS X – Hardware support for two levels of translation/protection » Guest OS virtual -> Guest OS physical -> Host machine physical February 25, 2010 CS152, Spring 2010 3 Bare Machine
Physical Physical Address Inst. Address Data Decode PC Cache D E + M Cache W
Physical Physical Address Memory Controller Address
Physical Address Main Memory (DRAM)
• In a bare machine, the only kind of address is a physical address
February 25, 2010 CS152, Spring 2010 4 Base and Bound Scheme
Data Bound Bounds Register ≤ Violation? Mem. Address Logical data Load X Register Address segment Data Base Physical Register + Address
Program
Program Bound Bounds Main Memory Address Register ≤ Violation? Space Program Logical program Counter Address segment Program Base Physical Register + Address
Logical address is what user software sees. Translated to physical address by adding base register.
February 25, 2010 CS152, Spring 2010 5 Base and Bound Machine Prog. Bound Data Bound Register Register Bounds Bounds Logical ≤ Violation? Logical ≤ Violation? Address Address
Inst. Data Decode PC + Cache D E + M + Cache W Physical Physical Address Address Program Base Data Base Register Register Physical Physical Address Address Memory Controller
Physical Address Main Memory (DRAM) [ Can fold addition of base register into (base+offset) calculation using a carry-save adder (sum three numbers with only a few gate delays more than adding two numbers) ]
February 25, 2010 CS152, Spring 2010 6 Memory Fragmentation
Users 4 & 5 Users 2 & 5 free arrive leave OS OS OS Space Space Space 16K user 1 16K user 1 user 1 16K user 2 24K user 2 24K 24K user 4 16K 24K user 4 16K 8K 8K 32K user 3 32K user 3 user 3 32K
24K user 5 24K 24K
As users come and go, the storage is “fragmented”. Therefore, at some stage programs have to be moved around to compact the storage.
February 25, 2010 CS152, Spring 2010 7 Paged Memory Systems
• Processor generated address can be interpreted as a pair
1 0 0 0 1 1 2 2 3 3 3
Address Space Page Table 2 of User-1 of User-1 Page tables make it possible to store the pages of a program non-contiguously.
February 25, 2010 CS152, Spring 2010 8 Private Address Space per User
OS User 1 VA1 pages Page Table Physical Memory
User 2 VA1
Page Table
User 3 VA1
Page Table free
• Each user has a page table • Page table contains an entry for each user page
February 25, 2010 CS152, Spring 2010 9 Linear Page Table
Data Pages • Page Table Entry (PTE) Page Table contains: PPN PPN – A bit to indicate if a page exists DPN – PPN (physical page number) for PPN a memory-resident page Data word – DPN (disk page number) for a Offset page on the disk – Status bits for protection and usage DPN • OS sets the Page Table PPN PPN Base Register whenever DPN active user process DPN changes VPN DPN PPN PPN
PT Base Register VPN Offset Virtual address February 25, 2010 CS152, Spring 2010 10 Page Tables in Physical Memory
PT User 1
VA1 PT User 2 User 1
VA1
User 2
February 25, 2010 CS152, Spring 2010 11 Size of Linear Page Table
With 32-bit addresses, 4-KB pages & 4-byte PTEs: ⇒ 220 PTEs, i.e, 4 MB page table per user ⇒ 4 GB of swap needed to back up full virtual address space
Larger pages? • Internal fragmentation (Not all memory in a page is used) • Larger page fault penalty (more time to read from disk)
What about 64-bit virtual address space??? • Even 1MB pages would require 244 8-byte PTEs (35 TB!) What is the “saving grace” ? sparsity of virtual address usage
February 25, 2010 CS152, Spring 2010 12 Hierarchical (Two-Level) Page Table Virtual Address 31 22 21 12 11 0 p1 p2 offset
10-bit 10-bit L1 index L2 index offset Root of the Current Page Table p2 p1
(Processor Level 1 Register) Page Table
Level 2 page in primary memory Page Tables page in secondary memory
PTE of a nonexistent page Data Pages
February 25, 2010 CS152, Spring 2010 13 Two-Level Page Tables in Physical Memory Physical Virtual Memory Address Spaces Level 1 PT User 1 VA1 Level 1 PT User 1 User 2
User2/VA1 VA1 User1/VA1
User 2 Level 2 PT User 2
February 25, 2010 CS152, Spring 2010 14 Address Translation & Protection
Virtual Address Virtual Page No. (VPN) offset Kernel/User Mode
Read/Write Protection Address Check Translation
Exception? Physical Address Physical Page No. (PPN) offset
• Every instruction and data access needs address translation and protection checks
A good VM design needs to be fast (~ one cycle) and space efficient
February 25, 2010 CS152, Spring 2010 15 Translation Lookaside Buffers Address translation is very expensive! In a two-level page table, each reference becomes several memory accesses Solution: Cache translations in TLB TLB hit ⇒ Single Cycle Translation TLB miss ⇒ Page Table Walk to refill
virtual address VPN offset
V R W D tag PPN (VPN = virtual page number)
(PPN = physical page number)
hit? physical address PPN offset
February 25, 2010 CS152, Spring 2010 16 Handling a TLB Miss
Software (MIPS, Alpha) TLB miss causes an exception and the operating system walks the page tables and reloads TLB. A privileged “untranslated” addressing mode used for walk
Hardware (SPARC v8, x86, PowerPC) A memory management unit (MMU) walks the page tables and reloads the TLB
If a missing (data or PT) page is encountered during the TLB reloading, MMU gives up and signals an exception for the original instruction
February 25, 2010 CS152, Spring 2010 17 Page-Based Virtual Memory Machine (Hardware Page Table Walk) Page Fault? Page Fault? Protection violation? Protection violation? Virtual Virtual Address Physical Address Physical Address Address Inst. Inst. Decode Data Data PC TLB Cache D E + M TLB Cache W
Miss? Miss? Page Table Base Register Hardware Page Table Walker Physical Physical Address Address Memory Controller
Physical Address Main Memory (DRAM) • Assumes page tables held in untranslated physical memory
February 25, 2010 CS152, Spring 2010 18 CS152 Administrivia
• Tuesday Mar 9, Quiz 2 – Cache and virtual memory lectures, L6-L11, PS 2, Lab 2
February 25, 2010 CS152, Spring 2010 19 Virtual Memory
• More than just translation and protection • Use disk to extend apparent size of main memory • Treat DRAM as cache of disk contents • Only need to hold active working set of processes in DRAM, rest of memory image can be swapped to disk • Inactive processes can be completely swapped to disk (except usually the root of the page table) • Combination of hardware and software used to implement this feature • (ATLAS was first implementation of this idea)
February 25, 2010 CS152, Spring 2010 20 Page Fault Handler
• When the referenced page is not in DRAM: – The missing page is located (or created) – It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk – If no free pages are left, a page is swapped out Pseudo-LRU replacement policy • Since it takes a long time to transfer a page (msecs), page faults are handled completely in software by the OS – Untranslated addressing mode is essential to allow kernel to access page tables
February 25, 2010 CS152, Spring 2010 21 Caching vs. Demand Paging
secondary memory
primary primary CPU cache CPU memory memory
Caching Demand paging cache entry page frame cache block (~32 bytes) page (~4K bytes) cache miss rate (1% to 20%) page miss rate (<0.001%) cache hit (~1 cycle) page hit (~100 cycles) cache miss (~100 cycles) page miss (~5M cycles) a miss is handled a miss is handled in hardware mostly in software
February 25, 2010 CS152, Spring 2010 22 Address Translation: putting it all together Virtual Address hardware Restart instruction TLB hardware or software software Lookup miss hit
Page Table Protection Walk Check the page is ∉ memory ∈ memory denied permitted
Page Fault Update TLB Protection Physical (OS loads page) Fault Address (to cache) SEGFAULT
February 25, 2010 CS152, Spring 2010 23 Address Translation in CPU Pipeline
Inst Inst. Data Data Decode PC TLB Cache D E + M TLB Cache W
TLB miss? Page Fault? TLB miss? Page Fault? Protection violation? Protection violation?
• Software handlers need restartable exception on TLB fault • Handling a TLB miss needs a hardware or software mechanism to refill TLB • Need mechanisms to cope with the additional latency of a TLB: – slow down the clock – pipeline the TLB and cache access – virtual address caches – parallel TLB/cache access
February 25, 2010 CS152, Spring 2010 24 Virtual Address Caches
PA VA Physical Primary CPU TLB Cache Memory
Alternative: place the cache before the TLB VA Primary Virtual PA (StrongARM) CPU TLB Memory Cache
• one-step process in case of a hit (+) • cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) • aliasing problems due to the sharing of pages (-) • maintaining cache coherence (-) (see later in course)
February 25, 2010 CS152, Spring 2010 25 Aliasing in Virtual-Address Caches
Page Table Tag Data
VA1 Data Pages VA1 1st Copy of Data at PA
PA VA2 2nd Copy of Data at PA
VA2 Virtual cache can have two copies of same physical data. Two virtual pages share Writes to one copy not visible one physical page to reads of other!
General Solution: Disallow aliases to coexist in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct- mapped cache (early SPARCs)
February 25, 2010 CS152, Spring 2010 26 Concurrent Access to TLB & Cache
Virtual VA VPN L b Index
k Direct-map Cache TLB L 2 blocks 2b-byte block PA PPN Page Offset
Tag = Physical Tag Data hit? Index L is available without consulting the TLB ⇒ cache and TLB accesses can begin simultaneously Tag comparison is made after both accesses are completed
Cases: L + b = k L + b < k L + b > k
February 25, 2010 CS152, Spring 2010 27 Virtual-Index Physical-Tag Caches: Associative Organization
Virtual 2a VA VPN a L = k-b b Index
Direct-map Direct-map TLB k L L 2 blocks 2 blocks Phy. PA PPN Page Offset Tag = = Tag hit? 2a
Data After the PPN is known, 2a physical tags are compared
Is this scheme realistic?
February 25, 2010 CS152, Spring 2010 28 Concurrent Access to TLB & Large L1 The problem with L1 > Page size Virtual Index L1 PA cache VA VPN a Page Offset b Direct-map
VA PPN Data TLB 1 a
VA2 PPNa Data
PA PPN Page Offset b = hit? Tag
Can VA1 and VA2 both map to PA ?
February 25, 2010 CS152, Spring 2010 29 A solution via Second Level Cache
L1 Instruction Memory Cache Unified L2 Memory CPU Cache Memory L1 Data RF Cache Memory
Often, a common L2 cache backs up both Instruction and Data L1 caches
L2 is “inclusive” of both Instruction and Data caches
February 25, 2010 CS152, Spring 2010 30 Anti-Aliasing Using L2: MIPS R10000
Virtual Index L1 PA cache VA VPN a Page Offset b Direct-map
into L2 tag VA1 PPNa Data TLB VA2 PPNa Data
PA PPN Page Offset b PPN = hit? Tag
• Suppose VA1 and VA2 both map to PA and VA1 is already in L1, L2 (VA1 ≠ VA2) PA a Data • After VA2 is resolved to PA, a collision will be 1 detected in L2. • VA1 will be purged from L1 and L2, and VA2 will be Direct-Mapped L2 loaded ⇒ no aliasing !
February 25, 2010 CS152, Spring 2010 31 Virtually-Addressed L1: Anti-Aliasing using L2
Virtual VA VPN Page Offset b Index & Tag
VA1 Data TLB VA2 Data
PA PPN Page Offset b L1 VA Cache
“Virtual Tag Physical Tag” Index & Tag
PA VA1 Data Physically-addressed L2 can also be used to avoid aliases in virtually- L2 PA Cache addressed L1 L2 “contains” L1
February 25, 2010 CS152, Spring 2010 32 Atlas Revisited
• One PAR for each physical page PAR’s • PAR’s contain the VPN’s of the pages resident in primary memory
PPN VPN • Advantage: The size is proportional to the size of the primary memory
• What is the disadvantage ?
February 25, 2010 CS152, Spring 2010 33 Hashed Page Table: Approximating Associative Addressing
VPN d Virtual Address Page Table Offset PA of PTE PID hash +
Base of Table VPN PID PPN • Hashed Page Table is typically 2 to 3 times larger than the number of PPN’s to reduce collision VPN PID DPN probability • It can also contain DPN’s for some non-resident VPN PID pages (not common) • If a translation cannot be resolved in this table then the software consults a data structure that has an entry for every existing page Primary Memory
February 25, 2010 CS152, Spring 2010 34 Acknowledgements
• These slides contain material developed and copyright by: – Arvind (MIT) – Krste Asanovic (MIT/UCB) – Joel Emer (Intel/MIT) – James Hoe (CMU) – John Kubiatowicz (UCB) – David Patterson (UCB)
• MIT material derived from course 6.823 • UCB material derived from course CS252
February 25, 2010 CS152, Spring 2010 35