Next Generation of Stem Stem of Generation Next

EDN

MARCH 1, 2012 MARCH

Series resonance in MARCH1 power systems Pg 18 Issue 5/2012 www.edn.com EDN.comment Pg 10 Smart wireless for your world Pg 20 Design Ideas Pg 43 Printer parking brake VOICE OF THE ENGINEER Pg 50 NEXT GENERATION OF STEM STEM OF GENERATION NEXT

IIII IIII ENGINEERING THE CRITICAL-AREA ANALYSIS AND MEMORY REDUNDANCY REDUNDANCY MEMORY AND ANALYSIS CRITICAL-AREA NEXT GENERATION OF IIII AUDIO-CONVERTER-SUBSYSTEM DESIGN CHALLENGES DESIGN AUDIO-CONVERTER-SUBSYSTEM STEMPage 26

Addressing critical-area analysis and memory redundancy Page 21

Audio-converter-subsystem design challenges in the 21st century Page 33

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Mouser and Mouser Electronics are registered trademarks of Mouser Electronics, Inc. contents 3.1.12

Addressing critical- area analysis and memory redundancy How susceptible is 21your design to random defects, and which areas of the layout could benefit from modi- fications that would provide the greatest positive effect on overall yield? by Simon Favre, Mentor Graphics

Audio-converter- engineering the next subsystem design generation of STem challenges in the Industry participants, reacting to the 21st century so-called engineering crisis, are doing 26what they can to foster science, Some key strategies technology, engineering, and math talent and 33enable you to achieve encourage more students to pursue engineering optimum audio-converter careers. performance. 5V by Suzanne Deffree, by Ian Dennis, Managing Editor, Online Prism Sound Group

+ 100 μF R3 S Cover imAge: SHUTTerSToCK/giULiA FiNi-gULoTTA 1 START 1M C1

R R6 4 100 R2 1k 10k Q2 DesignBC549 iDeas CD4011 G 1 TIMER 43 CMOS gate makes long-duration timers using RC components

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Dilbert 14 Surface Mount pulse (and Plug In) Transformers and 12 Value-priced scopes extend 16 3-D computer simulations Inductors bandwidth to 1 GHz reveal diffusional behavior See Pico’s full Catalog immediately 14 Outdoor unit brings integration 16 Digital-audio processor inte- www.picoelectronics.com to the microwave backhaul grates power management Low Profile from 14 SOC enables measurement 17 Robust three-axis sensor for high-power monitoring in targets automotives ht. industrial applications .19" 17 Energy-measurement IC eases 14 High-current storage chokes utility meters’ transition to come in ERU 20 case size smart grid Audio Transformers Impedance Levels 10 ohms to 250k ohms, Power Levels to 3 Watts, Frequency Response ±3db 20Hz to 250Hz. All units manufactured and departments & Columns tested to MIL-PRF-27. QPL Units available. Power & EMI Inductors Ideal for Noise, Spike and Power Filtering 50 Applications in Power Supplies, DC-DC Converters and Switching Regulators Pulse Transformers 10 Nanoseconds to 100 Microseconds. ET Rating to 150 Volt Microsecond, Manufactured and tested to MIL-PRF-21038. Multiplex Data Bus Pulse Transformers Plug-In units meet the requirements 48 of QPL-MIL-PRF 21038/27. Surface units are electrical equivalents of QPL-MIL-PRF 21038/27.

9 EDN online: Join the conversation; Content; Engineering Community DC-DC Converter Transformers 10 EDN.comment: Do, make, design, build, and fix the future of STEM Input voltages of 5V, 12V, 24V And 48V. Standard Output Voltages to 300V (Special voltages can be supplied). Can be used as self 18 Signal Integrity: Series resonance in power systems saturating or linear switching applications. All units manufactured and tested to MIL-PRF-27. 20 Connecting Wireless: Smart wireless for your world 400Hz/800Hz 48 Product Roundup: Test and Measurement Power Transformers 0.4 Watts to 150 Watts. Secondary Voltages 5V to 300V. Units manufactured to MIL-PRF-27 50 Tales from the Cube: Printer parking brake Grade 5, Class S (Class V, 1550C available).

Delivery-Stock to one week EDN® (ISSN# 0012-7515) is published semimonthly by UBM Electronics, 600 Community Drive, Manhasset, NY 11030-3825. Periodicals for sample quantities postage paid at Manhasset, NY, and at additional mailing offices. SUBSCRIPTIONS—Free to qualified subscribers as defined on the subscrip- tion card. Rates for nonqualified subscriptions, including all issues: US, $150 one year; $250 two years; $300 three years. Except for special issues where price changes are indicated, single copies are available for $10 US and $15 foreign. For telephone inquiries regarding subscriptions, call 847-559-7597. E-mail: [email protected]. CHANGE OF ADDRESS—Notices should be sent promptly to EDN, PO Box 3609, for FREE PICO Catalog Northbrook, IL 60065-3257. Please provide old mailing label as well as new address. Allow two months for change. NOTICE—Every precaution is taken to ensure accuracy of content; however, the publishers cannot accept responsibility for the correctness of the information supplied or Call toll free 800-431-1064 advertised or for any opinion expressed herein. POSTMASTER—Send address changes to EDN, PO Box 3609, Northbrook, IL 60065-3257. CANADA POST: Publications Mail Agreement 40612608. Return undeliverable Canadian addresses to APC, PO Box 503, RPO West BVR CRE, in NY call 914-738-1400 Rich Hill. ON L4B 4R6. Copyright 2012 by UBM. All rights reserved. Reproduction in whole or part without written permission is prohibited. Fax 914-738-8225 Volume 57, Number 5 (Printed in USA). PICO Electronics, Inc. 143 Sparks Ave. Pelham, N.Y. 10803 E Mail: [email protected] [www.edn.com ] www.picoelectronics.com

online

Join thE convErsation contEnt Comments, thoughts, and opinions shared by EDN’s community Can’t-miss content on EDN.com

In response to “Adafruit, Sparkfun point to 5 EnginEErs: why DiD you the democratization of hardware,” a blog bEcomE an EnginEEr? post by EDN’s Margery Conner, http://bit.ly/ We asked, and you’re answering. xs0TeF, Chris G comments: More than 185 comments have been “The best thing about Sparkfun and Adafruit for a posted so far, ranging from “I wanted casual experimenter is that they offer components to make the world a better place” and subassemblies with most of the difficult work to “The devil made me do it.” Share already done. Sure, the nitty-gritty details need what it was that inspired you to to be understood before putting out a robust product, but, as my own pursue engineering as a career path efforts have shown, just trying to get a microprocessor to communicate in this blog post’s comment section. to another device over I2C can be daunting enough while also working out http://bit.ly/yD1hsg the communication handshaking, even after reading the device maker’s spec sheets. Having these things worked out in an experimenters’ kit is the ? reason that these companies are the ones to watch.”

In response to “Cow tipping,” a Tales from the Cube column by Arnold N Simonsen, http://bit.ly/ zaho6V, “bandit” comments: “A moooving story, ranging by degrees from fence post to fence samsung LED-Light- post. Our intrepid engineer bore- buLb tEarDown incLuDEs sighted right to the horns of the obJEctivE Dimming problem. The solution? Beefing up numbErs the trailer site, making hamburger of Samsung sent EDN’s Margery the problem, avoiding the cow patties Conner an LED-replacement bulb to in his path. Another government job

DANIEl VASCoNCElloS put through its paces and then tear properly steered away from danger.” down. How does the bulb do with the onerous TRIAC-dimming test? EDN invites all of its readers to constructively and creatively comment Pretty darned good, and Margery on our content. You’ll find the opportunity to do so at the bottom of each has posted a graph to prove it. article and blog post. To review current comment threads on EDN.com, visit http://bit.ly/EDN_Talkback. http://bit.ly/xEIkmE

EnginEEring community Opportunities to get involved and show your smarts

FrEE bEEr! Now that we have your attention, be sure to register for Design West, a new event this year that collocates seven summits for four days of training and education, hands-on knowledge exchanges, teardowns, giveaways, and more throughout the day … and, yes, free beer, snacks, and prizes during its expo networking event on Tuesday, March 27, 5:30 pm to 7 pm. Find out more at www.ubmdesign.com.

[www.edn.com ] MARCH 1, 2012 | EDn 9 edn.comment

BY Suzanne Deffree, Managing eDitor, online

Do, make, design, build, and fix the future of STEM y now, you’ve seen this issue’s cover. You may have even flipped through to the cover story. And you may be wonder- ing what such a story—sans schematics, technical jargon, and just plain design basics—is doing in EDN. We are about engineering, after all, so where’s the engineering in the cover If engineers—who story? In this issue’s cover story, instead of presenting a design are creative, intel- Btopic for you to build from, we’re presenting a challenge for all of us to overcome. That challenge is how to engineer a new generation of STEM ligent, productive (science/technology/engineering/math) talent. people—were run- We all know the problem. Too few engineers to help brighten the picture. ning things, we’d all new engineers, as well as other STEM It’s easy to point fingers; politicians be in a better posi- professionals, are graduating from US do it all the time. But, as engineers, you colleges. The underlying issue is that do, you make, you design, you build, and tion in the employ- kids these days aren’t taking an interest you fix. Those abilities—not the degree ment market. in science and math, without which you received—make you an engineer. they can’t develop critical-thinking Those same principles make the topic 9, at the College of New Jersey (Ewing, skills and that sense of curiosity that of next-generation STEM talent an NJ). Naomi and I will also attend the contributes to entrepreneurial attitudes engineering issue. We know there is a USA Science and Engineering Festival and life-long discovery. problem. Let’s do something to fix it; in Washington, DC, during the last Many people reading this editorial let’s engineer it. weekend in April to celebrate the bril- will say that we shouldn’t be encourag- As issues about STEM evolve, you’ll liance this next generation brings to ing kids to study STEM because of a see more content like this cover story the game. claimed lack of engineering jobs in the on how to engineer this crisis into a We hope to see you at these events United States. This situation isn’t just healthier state. This content will appear in March and April. You can find more about jobs, though. It’s about creating in print, on EDN.com, through our information about them in the online a climate of more creative and more social-media efforts, in our webcasts, version of this editorial. In the mean- intelligently thinking, and, ultimately, and through the events we attend. For time, we invite you to share your own more proactive people. We can be sure example, EDN is presenting a Design thoughts on what we can all be doing to of this: If engineers—who are creative, West panel on this topic on March 28 help encourage the next generation of intelligent, productive people—ran at the San Jose McEnery Convention STEM at http://bit.ly/zC6wYA. things in this country, we’d all be in Center. Look for it in the show-floor We’ll bring back the design focus a better position when it came to the theater at 1:30 pm. After the panel, in EDN’s March 15 cover story. But employment market, as well as many we’ll also host a networking session in don’t walk away thinking that this need other hot-button concerns. which we’ll invite experienced engi- for more STEM talent isn’t an engi- Engineering the next generation is neers and executives to connect with neering topic. It is vital to the future of about creating leaders who can help incoming and new STEM talent. engineering itself and something that us build a better tomorrow. Although Further, the IEEE has asked me we can together engineer—do, make, these leaders would preferably be and my colleague at UBM Electronics, design, build, and fix—toward a better new engineers, we also need more Naomi Price, online brand manager for future.EDN professionals in other fields, inside Innovation Generation, to speak at its

ImagE: thInkstock or outside STEM, who think like Integrated STEM Conference on March Contact me at [email protected].

10 EDN | march 1, 2012 [www.edn.com ] senior Vice president, Vice president/design director ubm electronics Gene Fedele David Blaza 1-415-947-6929; creatiVe director [email protected] David Nicastro

director of content, art director edn and designlines Giulia Fini-Gulotta Patrick Mannion 1-631-543-0445; production [email protected] Adeline Cannone, Production Manager Laura Alvino, Production Artist executiVe editor, Yoshihide Hohokabe, Production Artist edn and designlines Diane Malone, Production Artist Rich Pell Consumer edn europe 1-516-474-9568; Graham Prophet [email protected] Editor, Reed Publishing [email protected] managing editor Amy Norcross edn AsiA Contributed technical articles Huang Hua 1-781-869-7971; Operations General Manager [email protected] [email protected] Grace Wu managing editor, online Associate Publisher Suzanne Deffree [email protected] Electronic Business, Distribution Vivek Nanda, Executive Editor 1-631-266-3433; [email protected] [email protected] edn ChinA senior technical editor Huang Hua Steve Taranovich Operations General Manager Analog, Systems Design [email protected] 1-631-413-1834; Grace Wu [email protected] Associate Publisher OVER 800 STYLES AND [email protected] technical editor Jeff Lu, Executive Editor OPTIONS IN STOCK Margery Conner [email protected] Design Ideas, Power Sources, Components, Green Engineering edn JApAn 1-805-461-8242; Masaya Ishida, Publisher Suitable for applications subject [email protected] [email protected] to high amounts of vibration Makoto Nishisaka, Editor design ideas [email protected] and shock, Mill-Max pins contributing editor Glen Chenier and receptacles are available in ubm electronics [email protected] management team diameters from .008” (.20mm) to .250” Paul Miller, Chief Executive Officer, (6.35mm). Receptacles feature a 4 or 6 nger senior associate editor UBM Electronics, UBM Canon (Publishing), Frances T Granville, 1-781-869-7969; UBM Channel, and UBM Design Central beryllium copper or beryllium nickel contact to [email protected] Kathy Astromoff, ensure integrity of connection for use in the Chief Executive Officer, UBM Electronics associate editor Brent Pearson, harshest environments. Jessica MacNeil, 1-781-869-7983; Chief Information Officer [email protected] David Blaza, Don’t see what you need? Rapid Senior Vice President columnists Karen Field, prototyping and custom designs are Howard Johnson, PhD, Signal Consulting Senior Vice President, Content our specialty. Bonnie Baker, Texas Instruments Jean-Marie Enjuto, Pallab Chatterjee, SiliconMap Vice President, Finance Kevin C Craig, PhD, Marquette University Barbara Couchois, Vice President, Partner Services contributing technical editors and Operations Dan Strassberg, [email protected] Felicia Hamerman, Brian Bailey, [email protected] Vice President, Marketing Robert Cravotta, Amandeep Sandhu, [email protected] Director of Audience Engagement and Analytics

For a complete list of editorial contacts, www.mill-max.com/EDN621 see http://ubmelectronics.com/editorial-contacts Follow us Like us MillMaxMfg Mill-Max Mfg. Corp. [www.edn.com ] EDITED BY FrAN GrANVILLE

pINNOVatIONSu & INNOVatlseORS Value-priced scopes extend talkback “I became an

0 1 00 2 10 bandwidth to 1 GHz 3

engineer9 because

5 7 6 gilent is adding four models to its than do competitive devices. Prices for I like clarity and InfiniiVision 3000 X series of value- upgrades from lower analog bandwidths to specifics. I’ve A priced digital oscilloscopes, dou- 1 GHz begin at $2340. learned from expe- bling to 1 GHz the maximum bandwidth, The company has also announced the rience that, when- increasing the maximum acquisition rate $1000, 1-GHz N2795A active probe. The ever a company from 4G to 5G samples/sec/active chan- probe has one-quarter the input capacitance nel, and adding such optional features as a of passive probes that provide similar band- avoids giving spec- ±3-digit digital voltmeter/five-digit frequency width. Although Agilent specs this device’s ifications, espe- counter that uses the same signal leads as bandwidth at 1 GHz, a company spokesman cially those involv- the scope. This option simplifies simultane- says that, when you use the 1-GHz probe ing price, be wary ous numeric measurements and waveform with the 1-GHz scope, the combined −3-dB of fraud. Too many display. The company has also expanded bandwidth remains higher than 1 GHz. The companies substi- its Waveform Builder software line, which probe also sports a pair of LED “headlights” supports the built-in function/waveform- that make it easier to find probe points on tute [disreputable] generator option. Memory depth is, option- dense PCBs. You can use one or two of marketing strate- ally, 4M points/channel, and the maximum these probes with a 1-GHz-bandwidth 3000 gies for engineer- waveform-update rate remains 1 million X scope. For applications that require both ing transparency.” waveforms/sec, a spec that only one com- probing and 1-GHz bandwidth on more than —EDN reader Neil baker, in EDN’s petitor can equal without the use of special two channels, the company recommends its talkback section, at http://bit.ly/ operating modes. 1157A probes, which draw less power from wlqanx. add your comments. The wider bandwidth and increased acqui- the scope’s internal power supply. sition rate position the new units, which —by Dan Strassberg include two- and four-channel analog scopes ▷Agilent Technologies, and mixed-signal oscilloscopes, to invade www.agilent.com. portions of the turf of higher-priced scopes. US list prices The four-channel MSO-X for 1-GHz-bandwidth 3054A provides 1-GHz units start at $9950 maximum bandwidth, for a unit with two 2M-sample/channel analog channels. acquisition memory (4M According to Agi- samples optional), and lent, the 3000 X 16 digital timing-analysis series’ designed- channels. A digital in upgrade capa- multimeter/frequency counter bilities more effec- with on-screen readout, a tively extend the built-in function/waveform generator, and a 1-GHz active instruments’ life- probe are extra-cost options. time and preserve users’ investment

12 EDN | MARCH 1, 2012 [www.edn.com ] Name Peter Simonsen Job Title Design Engineer, Embedded Software Area of Expertise Renewable Energy LabVIEW Helped Me Perform real-world simulations with total control of the application Latest Project Develop a test architecture for veriﬁ cation of wind turbine control systems

NI LabVIEW

LabVIEW makes me better because I can SIMUL ATE real-world systems

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©2010 National Instruments. All rights reserved. LabVIEW, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. 2811 pulse Outdoor unit brings integration HigH-current to the microwave backhaul stOrage cHOkes cOme in roadcom’s new BCM85810 microwave point microwave-frequency bands and channel outdoor-unit IC combines the functions bandwidths, the BCM85810 simplifies system eru 20 case size Bof as many as 10 off- manufacturing, deploy- TDK-EPC has extended the-shelf application-specific ment, and inventory man- the standard EUR 13 and standard products, including IF agement, according to the ERU 25 series of Epcos

and RF synthesizers, low-noise company. power inductors with the 03.01.12 amplifiers, automatic-gain con- The device offers an new ERU 20 series. The trollers, bandpass-filter banks, automatic-gain-control devices have inductance lowpass-filter banks, IR mix- dynamic range of more values of 1 to 35 μH and ers, variable-gain and variable- than 70 dB, internal power a current rating of 93 to voltage attenuators with auto- controls, and on-chip- 50A. Their dc-resistance matic-gain control of more than selectable baseband fil- values range from 0.62 70 dB, and power-amplifier ters. It maintains receiver to 7 mΩ. The ERU case drivers and power detectors. output power over the full sizes suit use in high- The BCM85810 addresses the Bcm85810 fulfills the need for input-power range and current, low-voltage dc/ the need for higher bandwidth higher bandwidth in outdoor units. complies with European dc converters, point- and faster time to market in Telecommunications Stan- of-load converters, and microwave split-mount and full- and all-outdoor dards Institute and Federal Communications multiphase modules. The units. With support for high modulation and with Commission standards.—by Fran Granville design employs ferrite only two variants to cover all standard point-to- ▷Broadcom, www.broadcom.com. cores and flat-wire winding technology. Low core losses and efficient design with self-supporting sOc enables measurement winding permit ultra- compact dimensions and for high-power monitoring good storage density. in industrial applications The inductors have a 21×21.5-mm2 footprint axim’s new Teridian- metrology engine includes a Preloaded firmware supports and an insertion height based, three-phase range of embedded energy both Delta and Wye three- of 9.8 to 14.2 mm, de- M78M6631 power- diagnostics, including power phase applications, reducing pending on type. The measurement system on chip factor, harmonic distortion, volt- both development costs and ROHS-compatible de- embeds power monitoring age sag, and voltage dip. The time to market. The 78M6631 vices are also available into high-load applications. 78M6631 also provides better SOC is available in a lead-free in customer-specific The self-contained and cus- than 0.5% system accuracy QFN package and sells for versions. Applications in- tomizable system suits use in across a 2000-to-1 dynamic $5.78 (1000). clude power supplies in industrial panels and motors, range, enabling the use of the —by Fran Granville telecommunications and solar-panel inverters, storage lowest-value shunt for the cur- ▷Maxim Integrated IT systems and inverters power supplies, and data cen- rent sensor, thus reducing heat Products, for photovoltaic systems. ters. The device’s embedded and parasitic-power loss. www.maxim-ic.com. —by Fran Granville ▶TDK-EPC, DILBERT By Scott Adams www.epcos.com.

the eru 20 series has inductance values of 1 to 35 μH and a current rating of 93 to 50a.

14 EDN | MARCH 1, 2012 [www.edn.com ] More Flexibility

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into a specified direction. When 3-D computer simulations reveal they need to change the par- diffusional behavior ticle’s direction, they could trigger scatterers to rearrange into team of researchers at Hernandez and his for- gated shape of the scatterers. a different direction. The trig- the Georgia Institute of mer doctoral student, Ashley Surprisingly, however, the par- ger could even be the absence A Technology is exploring Tucker, assembled the rod- ticles sometimes diffuse faster of sufficient nanoparticles how nanoparticles move and like scatterers in one of two in the nematic environment than in a given part of the device. diffuse on a surface or in a fluid states during his simulations: in the disordered environment. The ensuing reordering of the under nonideal to extreme con- disordered, or isotropic, and That is, the channels left open nanorods would then drive a ditions. Rigoberto Hernandez, ordered, or nematic. When dis- between the ordered nanorods repopulation of nanoparticles a professor at the university’s ordered, the nanorods point in don’t just steer nanoparticles that would then be available to school of chemistry and bio- various directions and typically along a direction; they also perform a desired action, such chemistry, investigates these diffuse normally in all directions. enable them to speed right as to stimulate light flow. relationships by studying 3-D When every rod points in the through. As the density of the The National Science Foun- particle-dynamics simulations same direction, the particle, on scatterers increases, the chan- dation-funded work targets a on high-performance com- average, diffuses more in the nels become more crowded. better understanding of the puters. His findings focus on same direction as the rods than The particle diffusing through motion of particles within com- the movements of a spherical against the grain of the rods. In these assemblies slows dra- plex arrays at the nanoscale. probe among static needles this nematic state, the probe’s matically in the simulation. Nev- The work has significant long- (Reference 1). movement mimics the elon- ertheless, the nematic scatter- term implications on device ers continue to accommodate fabrication and performance at faster diffusion than do disor- such scales. dered scatterers, according to —by Fran Granville the researchers. ▷Georgia Institute of “These simulations bring Technology, us a step closer to creating www.gatech.edu. a nanorod device that allows scientists to control the flow of RefeR ence nanoparticles,” says Hernan- 1 Tucker, Ashley K, and dez. “Blue-sky applications of Rigoberto Hernandez, “Dif- such devices include the cre- fusion of a Spherical Probe ation of new light patterns, infor- through Static Nematogens: mation flow, and other micro- Effect of Increasing Geo- scopic triggers.” For example, metric Anisotropy and Long- Georgia Tech Professor Rigoberto Hernandez and his former if scientists need a probe to dif- Range Structure,” The Jour- doctoral student, Ashley Tucker, assembled the rodlike scatter- fuse in a specific direction at nal of Physical Chemistry B, ers in one of two states during simulations: disordered, or isotro- a particular speed, they could Dec 8, 2011, pg 1328, pic, and ordered, or nematic. trigger the nanorods to move http://bit.ly/zFH6Yd. Digital-audio processor integrates power management

onexant’s new dual-core, 32-bit PCM interface; an I2C master and slave; analyzer and JTAG, a UART, and dedicated CX20805 digital-audio processor and an SPI master and slave. peripheral and memory-to-memory DMA Cintegrates high-speed USB 2.0, an Other features include support for a channels. Integrated dc/dc conversion, 800-MIPS DSP, and support for as many quad digital microphone with pulse-density power gating, power retention, dynamic as eight endpoints. The chip comes with modulation, SPDIF receiving and transmit- voltage scaling, and frequency scaling a C compiler, software tools, and a suite ting, tricolor PWM-LED drivers, and 24 reduce power consumption. of DSP algorithms. It uses the vendor’s programmable I/Os. A custom audio bus Housed in a 9×9-in., 116-pin, dual- CAPE (Conexant audio-processing-engine) connects to multichannel audio row QFN package, the device sells architecture. Each dual-core DSP includes devices, and the product for $5.50 (10,000). Evaluation kits dual media-access controllers operating has an AES 128 decryp- are available to qualified custom- at 200 MHz. The CX20805 also includes tion engine, an on-chip logic ers and partners. 520 kbytes of embedded SRAM and 352 —by Fran Granville kbytes of embedded ROM; a full-duplex, The CX20805 processor sup- ▷Conexant Systems Inc, I2S-multiplexed stereo with a four-channel ports eight endpoints. www.conexant.com.

16 EDN | MARCH 1, 2012 [www.edn.com ] Robust three-axis sensor targets automotives TMicroelectronics’ new ings also improve The three-axis A3G4250D angular- map-matching, the A3G4250D auto- Srate gyroscope aims process of aligning a motive gyroscope to add position accuracy and sequence of observed provides motion stability to a range of automo- user positions with the measurement along all three orthogonal tive applications, including in- road network on a digi- axes. dash navigation, telematics, tal map, such as those and vehicle-tolling systems. for traffic-flow analysis and sleep modes and The AEC-Q1000-qualified and driving directions. an embedded first-in/ gyroscopes provide accurate The device employs first-out memory block meas urements of angular- one sensing struc- for power manage- motion detection, significantly ture for motion meas- ment. The A3G4250D enhancing dead-reckoning and urement along the embeds an 8-bit tem- map-matching capabilities in orthogonal yaw, roll, perature sensor and car-navigation and telematics and pitch axes, eliminating digital bit stream that transmits operates at an extended applications. interference between the axes, to a dedicated microcontroller temperature range of −40 to By monitoring motion, dis- increasing measurement pre- chip through a standard SPI or +85°C. The device is robust tance traveled, and altitude, cision, and providing output I2C protocol. The device pro- against EMI and withstands dead-reckoning systems com- stability over time and tempera- vides interrupt and data-ready shocks as large as 10,000g. It pensate for the loss of satellite ture. The A3G4250D measures output lines and four user- sells for $6 (1000). signals indoors and in urban angular rates to ±250°/sec. An selectable output-data rates. —by Fran Granville canyons between tall build- on-chip IC interface converts The 3V-single-supply sen- ▷STMicroelectronics, ings. Precise gyroscope read- the angular motion into a 16-bit sor integrates power-down www.st.com.

Energy-measurement IC eases For transducer I/O—critical to utility meters’ transition to smart grid this application—the ICs support shunt resistor, current transformer, Look out, you spinning-disk utility unneeded hardware blocks, ac- and Rogowski-coil pickups, with meters out there. Your days of rul- cording to the vendor, and using configurable digital outputs for ing the power line are coming to a optocouplers, thus requiring fewer energy pulses, zero crossing, or close—at least you’ll get that im- signal lines to isolate. Applications energy direction. The chip’s self-

pression as smart meters that em- for these IC-based energy meters calibration time is less than 2 sec, 03.01.12 ploy electronic sensing to provide go beyond residential lines and which Cirrus claims is one-tenth advanced connectivity continue their metering. Vendors are looking the time of other available de- to replace the venerable glass-en- to incorporate them into applianc- vices. Calibration time is important cased meters that have served the es, smart power strips, power sup- because these meters and their utility industry for more than 100 plies, and power-hungry servers in sensors require calibration at the years. The latest entry in the enterprise applications. factory’s production line. At the metering-IC arena is the The devices offer measurement other side of the I/O situation, the CS548x/9x family from Cirrus accuracy for both active and reac- family offers SPI and UART inter- Logic. The family supports single- tive power (power factor) of 0.1% faces, depending on IC model. The and multiple-phase ac-line meas- over a 4000-to-1 dynamic range, devices operate from a single 3.3V urement of voltage and current surpassing industry requirements, supply, and power consumption is through per-channel ADCs and whereas current rms measurement less than 13 mW. then calculates the power usage accuracy is 0.1% over a 1000-to-1 The CS548x/9x family includes using an internal digital core. range with readings using simul- two-, three-, and four-channel Other ICs for this application taneous-sampling converters and front ends, which are available in use SOC front ends and separate 24-bit, fourth-order delta-sigma 16-lead SOIC, 24-lead QFN, and communications processors, but modulators. On-chip measure- 28-lead QFN packages. Prices be- the topology of the Cirrus devices ments include active, reactive, and gin at 75 cents (100,000) for the puts the converters and calculat- apparent power; rms voltage and smallest member of the family. ing core at the front end, lowering current; power factor; and line —by Bill Schweber cost through the elimination of frequency. ▶Cirrus Logic, www.cirrus.com.

[www.edn.com ] MARCH 1, 2012 | EDN 17 SIGNAL INTEGRITY

BY howard johnson, phd

circuit is useful only with continuous stimulation. It is powerless to prevent noise from random data events. You must place the series-resonant circuit within a small fraction of one wavelength of any device that it is protecting. Within that limited radius, the spreading inductance of the power and ground planes modifies the effective series inductance of the resonant Series resonance in power circuit. Consequently, the exact posi- tioning of a resonant circuit matters systems tremendously, so you cannot alter the layout without implementing a com- any digital systems suffer excessive power-supply noise at plete redesign. Even worse, a resonant frequencies relating to the system clock. Could a series- element that provides substantial atten- resonant circuit, such as the one in Figure 1, connected uation for clock noise emanating from between the power and the ground planes attenuate that one location may provide no benefit noise? The answer can be yes, but only if your circuit satis- or may even exacerbate the noise from fies the following improbable conditions. another source. MFirst, the frequency of the system quencies can possibly work under these In a sinusoid-based clock must remain fixed. In systems conditions. system, such as an without a crystal-controlled clock, the The allure of a series-resonant circuit clock frequency may wander ±30% or is that it permits the use of a smaller AM or an FM radio, more. Low-power systems often slow value of capacitor than otherwise might resonating power- the clock to conserve power when idle. be necessary if you match that capacitor High-performance systems sometimes with appropriate values of inductance supply components come in speed variants, for which cus- and resistance, creating the series-reso- can provide aston- tomers pay extra to gain performance. nant effect. Unfortunately, the smaller As a diagnostic test, a designer may the capacitor, the more precise the cir- ishing benefits. slow the system clock to reveal certain cuit must become. Last, remember that a resonant cir- timing-related failures. No power-sup- For example, a capacitor of one-fifth cuit attenuates noise at only one fre- ply-noise-mitigation strategy employ- the ordinary value requires capacitor quency. It provides little or no benefit at ing careful tuning of exact noise fre- and inductor components with ±10% other harmonics of the clock rate. In a tolerance. A capacitor of one-tenth sinusoid-based system, such as an FM or

V the normal value requires ±5% toler- an AM radio, resonating power-supply CC ance, and so on. It is difficult to imple- components can provide truly astonish- ment high-frequency inductors with ing benefits. such tight tolerances. If you think of In a digital system that starts and L the layout inductance as fixed and plan stops at various clock speeds and in 1 a smaller value of capacitance to place which the layout constantly changes F = RES 2π LC the series-resonant point at a favorable from one version to the next, the use of R location, you will face the same difficul- resonating power-supply-filter elements ty: You cannot easily control the exact does not pass the KISS (keep it simple, values of capacitance and inductance. stupid) test. A digital-power system is C The clock must play continuously, better served by lots of large, simple, repeating forever without stops or gaps. If nonresonant bypass capacitors.EDN the clock stops, your resonant circuit will spin on, plunging out of control, creating Howard Johnson, PhD, of Signal Consult- disturbances just as bad as the problem ing, frequently conducts technical work- Figure 1 The impedance of this network you were trying to mitigate. When the shops for digital engineers at Oxford Uni- attains its smallest value at the resonant clock restarts, the resonant circuit takes versity and other sites worldwide. Visit his frequency. many cycles to catch up—providing zero Web site at www.sigcon.com, or e-mail him benefit during that period. A resonant at [email protected].

18 EDN | MARch 1, 2012 [www.edn.com ]

EDN120301HJ Fig 1.eps DIANE Look What’s Happening at IMS2012!

Plenary Session Speaker: Steve Mollenkopf Monday, 18 June 2012 President and Chief Operating O cer, Qualcomm 1730-1900 3G/4G Chipsets and the Mobile Data Explosion

The rapid growth of wireless data and complexity of 3G and 4G chipsets drives new design and deployment challenges for radio and device manufacturers along with carriers. This talk will provide a perspective on the problem from the point of view of a large, worldwide manufacturer of semiconductors and technology for cellular and connected consumer electronics devices. The increase in device and network complexity will result in signi cant business opportunities for the industry.

Closing Ceremony Speaker: Thomas H. Lee Thursday, 21 June 2012 Professor, Stanford University 1700-1830 The Fourth Age of Wireless and the Internet of Everything “Making predictions is hard, particularly about the future.” The patterns of history are rarely discernible until they’re obvious and perhaps irrelevant. Wireless may be an exception, at least in broad outline, for the evolution of wireless has been following a clear pattern that tempts us to extrapolate. Marconi’s station-to-station spark telegraphy gave way to a second age dominated by station-to-people broadcasting, and then to today’s ubiquitous people-to-people cellular communications. Each new age was marked by vast increases in value as it enlarged the circle of interlocutors. Now, these three ages have covered all combinations of “stations” and “people,” so any Fourth Age will have to invite “things” into the mix to provide another stepwise jump in the number of interlocutors. This talk will describe how the inclusion of multiple billions of objects, coupled with a seemingly insatiable demand for ever-higher data rates, will stress an infrastructure built for the Third Age. Overcoming the challenges of the coming Fourth Age of Wireless to create the Internet of Everything represents a huge opportunity for RF engineers. History is not done.

The IMS2012 Housing Bureau and Registration are now open! Don’t miss your chance to see the latest RF/Microwave technology advancements while accessing over 500 companies technologies and services. Visit http://ims2012.mtt.org for complete details and to download your Program Book. Review technical sessions, workshop descriptions and exhibiting companies so you can make the most of your time at Microwave Week!

http://ims2012.mtt.org ConneC ting wireless

BY PallaB Chatterjee

802.16 standard covers and which supports PHY-layer devices from the 2- to 11-GHz and the 10- to 66-GHz spectra; and the mainstream wireless-data networks of Wi-Fi, under the IEEE 802.11 standards, which use multiple simul- taneous data streams on the 2.4- and Smart wireless for your world 5-GHz bands. Manufacturers are integrating these ireless for data transmission has been around for a device domains into peer-to-peer net- long time and has slowly been creeping into com- works, mesh networks, LANs, and puting devices in networks. Although RF interfaces WANs. These networks supplement were previously on IT and industrial-control systems, the multiple bands and protocols for cellular communication. Cell networks which had full-time management, the prevalence of currently employ the 850-, 900-, 1800-, high-performance embedded computing has created and 1900-MHz bands. All of these net- Wa need for distributed networks without full-time administration. This need works have made the digital shift to exists independently of the platform you use—whether a microcontroller, requiring little user intervention for a DSP, or a processor. communication, including automated handshaking, network connection, and The digital-function and control applications and across spectra. This device identification. The challenge for side of the network has advanced to trend shifts the interoperability issue to the end device is to determine which the point that it can address the self- the RF from the digital as reconstructed network to use. RF must appear in the handshaking and protocol negotiation data becomes reconstructed data in the end devices as a selection of one of mul- necessary for these devices to both con- digital domain. tiple blocks. nect and identify themselves with mini- The common domains for the device A typical tablet PC with cellular mal user intervention. A key portion of networks are Z-Wave in the 900-MHz connection may have more than seven this task is the ability for the software spectrum; Zigbee in the 2.4-GHz spec- RF-amplifier-transceiver blocks—four and controller to manage the nonse- trum, which the IEEE 802.15.4 stan- quad bands for the 3G cellular system, quential turn-on and turn-off cycles of dard covers; Bluetooth, also in the 2.4- at least two blocks for 2.4 and 5G Wi-Fi devices in the network as people move GHz band; WiMax, which the IEEE bands, and one block for Zigbee or the devices to multiple locations Z-Wave home- and industrial- and run multiple tasks without INTERNET OF THINGS automation network control and administration. CONNECTED DEVICES AND NETWORKS interface. The Wi-Fi blocks may This control function is now support as many as four antennas, influencing the RF side to move which the 801.11ac spec allows, from individual power amplifiers, TRANSPORT and the RF must run in parallel. SAW (surface-acoustic-wave) fil- The size, power, and module ters, multiplexers, and low-noise EDUCATION integration of the required bias, amplifiers to full modules ranging ENERGY amps, filters, multiplexers, and from single-frequency transceiv- multiple signal paths are driving ers to multiple-frequency cellular BUSINESS the analog and RF community to blocks. The resulting challenges move to its equivalent of an RF in the RF area are spectrum HOME SOC. Manufacturers are releas- crowding and the existence of OTHER ing these devices with full sig- multiple standards. nal conditioning, and they will The RF spectra neatly divide EARTH soon include data-conversion into discrete data bands that and postsignal-recovery capa- all serve different system goals. bilities that are driving both the These discrete functions, how- growth and the consolidation of ever, are all blending into the Figure 1 The RF spectra neatly divide into discrete data the industry.EDN Internet of Things, which is bands that all serve different system goals. These dis- growing daily (Figure 1). Most crete functions, however, are all blending into the Internet Pallab Chatterjee has been an in- embedded computing devices are of Things, which is growing daily. dependent design consultant since now transferring data to other 1985.

20 EDN | MarCh 1, 2012 [www.edn.com ] imagE: SHUTTERSTOCK D mE analysis critical-area A r [ b effect onoverall yield? tHat would provide tH layout couldbenefitfrommodifications random defects How susceptible is your design to avoid manufacturing-ramp-up issues. facturing) problems when the design is still in progress, you can costly redesign. By promptly addressing DFM (design-for-manu - www.edn.com y s imon f ED DDrE avre • ] mory you can address a manufacturing problem without downstream a design goes, the less likely it is that further The issues. design’s manufacturing to a sensitivity reducing of goal the handle should processes— (integrated-device-manufacturer) esign teams—whether using fabless, fablite, or IDM u mentor g NDAN , and wH rapH ssi ics e greatest positive icH & areas of tHe Ng cy MARCH 1, 2012 |EDN21 One aspect of DFM is determining at a glance ures. Analysis often shows that via and how sensitive a physical design, or lay- contact failures are the dominant failure The probability of a random par- out, is to random particle defects. The ↘ mechanisms. You can incorporate other ticle defect is a function of the probability of a random particle defect spacing of layout features. Because failure mechanisms into the analysis, is a function of the spacing of layout memories are relatively dense struc- depending on the defect data the fab features, so tighter spacing increases tures, they are inherently more sen- provides. random defects. Because memories are sitive to random defects, so they Critical area increases with increas- relatively dense structures, they are can affect the overall yield of the ing defect, or particle, size. At the limit, inherently more sensitive to random device. the entire area of the chip is critical defects, so embedded memories in an for a large-enough defect size. In prac- ↘ For a critical-area-analysis tool SOC design can affect the overall yield to accurately analyze memory tice, however, most fabs limit the range of the device. redundancy, it must know the repair of defect sizes that they can simulate, Understanding how to employ criti- resources available in each memory based on the range of defect sizes that cal-area analysis becomes more impor- block, a breakdown of the failure they can detect and measure with test tant at each successive node. Memories modes by layer and defect type, chips or metrology equipment. keep getting bigger, and smaller dimen- and which repair resource these sions introduce new defect types. The modes are associated with. Defect Densities trade-offs that have worked well on Semiconductor fabs have various meth- ↘ If you do not apply redundancy, previous nodes may give suboptimal then you may need to use alterna- ods for collecting defect-density data. results at the 28-nm node. For example, tive methods to improve die yield. For use with critical-area analysis, the although manufacturers have avoided These methods may include making fab must convert the defect-density data the use of row redundancy because they the design smaller or reducing into a form compatible with the analy- considered it too costly in access time, defect rates. If you apply redundan- sis tool. The most common format is the technique becomes necessary at cy in designs in which it has no the following simple power equation: the 28-nm node so that vendors can benefit, then you waste die area D(X)=K/XQ, where K is a constant you achieve acceptable yields. All of these and test time, increasing manufac- derive from the density data, X is the turing cost. factors make careful analysis more valu- defect size, and Q is the fall power. The able as a design tool. fabs curve-fit the open and short cir- ues for the expected average number of cuits’ defect data for each layer to an critical-area analysis faults and yield based on the dimensions equation of this form to support criti- Critical area is the area of a layout in and spacing of layout features and the cal-area analysis. In principle, a defect which a particle of a given size will particle size and density distribution density must be available for every layer cause a functional failure. Critical area that the fab measures. In addition to and defect type to which you will apply depends only on the layout and the classic short- and open-circuit calcula- critical-area analysis. In practice, how- range of particle sizes you are simulat- tions, current practice in critical-area ever, layers that have the same process ing. Critical-area analysis calculates val- analysis includes via and contact fail- steps, layer thickness, and design rules typically use the same defect-density values. Manufacturers may also provide defect-density data in a table form that lists each defect’s size and density value. A simplifying assumption is that, beyond the range of defect sizes for which the fab has data, the defect density is zero.

calculating anf, yielD To determine the average number of faults for a design, manufacturers use a tool that supports critical-area analysis, such as Mentor Graphics’ Calibre, to extract the critical area for each layer over the range of defect sizes. To achieve this goal, manufacturers measure the layout and determine all of the areas in which a particle of a given size could result in a failure. Figure 1 A critical-area analysis using Calibre shows the effects of memory redundan- The tool then uses numerical inte- cy on the average number of faults for different configurations. gration, along with the defect’s size and density data, to calculate the

22 EDN | March 1, 2012 [www.edn.com ] EQUATION 1 expected average number of faults, vias, than for other layers. Most foundries multiplexing of bit lines and I/O ports— according to the following equation: define a probabilistic failure rate for all not the address decoding. D single vias in the design and assume that To analyze failures with critical-area MAX via arrays do not fail. This simplifying analysis, it is important to define which ANF=∫ D CA(X)×D(X)DX, MIN assumption ignores the fact that a large layers and defect types are associated where ANF is the average number of enough particle can cause multiple fail- with which memory-failure modes. By faults; DMIN and DMAX are the minimum ures, but it greatly simplifies the calcula- examining the layout of a typical six- and the maximum defect sizes, respec- tion of the average number of faults and or eight-transistor SRAM bit cell, you tively, according to the defect data reduces the amount of data the fab must can make some simple associations. For available for that layer; and CA(X) and provide. The designer needs only a sum of example, by looking at the connections D(X) are the critical area and the all the single cuts on a layer and can cal- of the word lines and the bit lines to the defect-density data, respectively. culate the average number of faults as the bit cell, you can associate diffusion and Once the manufacturer has calculated product of the count and the failure rate. contact to diffusion on column lines with EDN120301DF Equations.eps DIANE the average number of faults, it is usually column failures. Because contacts to dif- desirable to apply one or more yield mod- MeMory redundancy fusion and contacts to poly both connect els to make a prediction of the defect-lim- Embedded memories can account for to Metal 1, row and column layers must ited yield of a design. The defect-limited significantly large yield loss in SOCs share the Metal 1 layer. Most of the lay- yield cannot account for parametric-yield due to random defects. Although SOCs ers in the memory design find use in mul- issues, so be careful when attempting to can use other types of memories, assume tiple places, so not all defects on these correlate this figure to actual die yields. that the design uses embedded SRAM. layers will cause failures that are associ- One of the simplest and most com- Typically, SRAM-IP (intellectual-prop- ated with repair resources. Irreparable, mon yield models is the Poisson model: erty) providers make redundancy an or fatal, defects, such as short circuits Y=E−ANF, where Y is the yield, E is a con- option that designers can choose. The between power and ground, also occur. stant, and ANF is the average number most common form of redundancy is of faults. It is generally simpler to calcu- the use of redundant rows and columns. repair resources late the average number of faults and the Redundant columns are typically easier Embedded-SRAM designs typically yield for cut layers, such as contacts and to apply because they address only the use either built-in self-repair or fuse

[www.edn.com ] MARCH 1, 2012 | EDN 23 structures that allow multiplexing out cost. The goal of analyzing memory layer and defect type, and which repair the failed structures and replacing redundancy with critical-area analysis resource these failure modes are asso- them with the redundant structures. is to maximize defect-limited yield and ciated with. Calibre can specify these Regardless of the method of applying minimize the effect on die area and variables as a series of critical-area- the repair, the use of redundant struc- test time. analysis rules. Each memory block also tures in the design adds area, which A critical-area-analysis tool can requires a count of total and redundant directly increases the cost of manufac- accurately analyze memory redundancy rows and columns. To identify the areas turing the design. Additional test time only if it knows the repair resources of the memory that can be repaired, also increases cost, and designers may available in each memory block, the you can either specify the bit-cell name have a poor basis for calculating that breakdown of the failure modes by that each memory block uses or use a marker layer in the layout database to allow the tool to identify the core areas of the memory. Listing 1 provides the sramConfig memory-redundancy specification. The first two lines list the critical-area-analysis rules—that is, the type of defects that can occur—that have redundant resources for a family of memory blocks. The first two lines also contain the column rules and the row rules. These rules depend on the type and the structure of the memory block but are independent of the number of rows and columns and the redundancy resources. The last two lines describe an SRAM block design and specify, in order, the block name, the rule-configuration name, the total columns, the redundant columns, the total rows, the redundant rows, the dummy columns, the dummy rows, and the name of the bit cell. In Figure 2 A critical-area analysis shows the memory-repair ratio for many parameters. this example, both block specifications refer to the same rule configuration, sramConfig. Given these parameters, Calibre calculates the unrepaired yield using the defect-density data that the fab provides.

yield with redundancy Once the critical-area-analysis tool has performed the initial analysis, providing the average number of faults without redundancy,EQUATION 2you can calculate the yield with redundancy. Calibre uses a calculation method employing the principle of the Bernoulli Trials, according to the following equation:

K=NR (N −K) K YR=∑ K=0 C(NF,(NF−K))×P F ×Q ,

where NF is the number of functional, nonredundant memory units; NR is the number of redundant memory units; P is the probability of success, or yield, you derive from the average number of Figure 3 A memory plot shows the average number of faults for various memory- faults; Q is the probability of a failure redundancy configurations. The combination of one redundant row and one redundant (1−P);EDN120301DF and C(N Equations.epsF, (NF−K)) is DIANEthe bino- column causes a large decrease in the average number of faults. mial coefficient, which is a standard mathematical function. If the critical-

24 EDN | March 1, 2012 [www.edn.com ] area-analysis tool can postprocess the Using Calibre to determine an opti- by design total, by total of all analysis calculations with different memory- mum redundancy configuration, you layers, by memory, by block, and by redundancy specifications, it can present must first set up a configuration file layers or groups. Figure 3 shows a tool- numeric and graphical output that for the tool (Listing 2). The bit-cell created plot depicting the average num- makes it easy to visually determine the name, ram6t, tells the tool the name ber of faults for each redundancy con- optimal amount of redundancy. The goal of the hierarchical-layout element that figuration and for each type of defect. is to ensure the required number of good describes a memory unit that can be The combination of one redundant row units out of a total number of units. repaired and that you should consider and one redundant column causes a To see how effective memory redun- in this analysis. This name enables the large decrease in the average number dancy can be, consider a hypothetical tool to calculate the critical area of of faults, and adding resources has little example. The memory of interest is a the entire memory core, including all further effect. From these results, you 4-Mbit, 32-kbit×128-bit SRAM. The instantiations of ram6t. can deduce that the expected average goal is to realize at least 128 good units With this configuration informa- number of faults is based on the layout from a total of 130 units. In this case, tion, Calibre calculates the average of the memory under consideration and there are two units needing repair and number of faults for memory with the defect density of the fab and the no defective units. Analysis determines no redundancy, as well as for various process. The designer can now deter- that the unit yield considering one defect redundancy configurations. Figure 1 mine the effect of various redundancy type is 0.999. The unrepaired yield of shows the results as a table with values configurations on the expected yield of the entire core is then 0.999 raised to of the average number of faults for dif- an embedded memory. the 128th power, or 0.8798. If you per- ferent redundancy configurations. The Memory redundancy is intended to form the analysis for all defect types, the table rows show the results for the entire reduce manufacturing cost by improving expected yield is approximately 0.35. design, for just the memory, and for spe- die yield. If no redundancy is applied, If you add redundancy to repair any cific types of defects. In the highlighted alternative methods to improve die unit defects, the repaired overall yield is row, the average number of faults for yield may include making the design 0.999. Memory designers use the repair- the 1024×32-bit memory core improves smaller or reducing defect rates. If you ratio metric to express the efficacy of substantially; the failure rate in Column apply redundancy to parts of the design memory redundancy. It stipulates that 6 is half that in Column 5. To achieve in which it has no benefit, then you the repaired yield minus the unrepaired this improvement, Column 6 includes waste die area and test time, increasing yield divided by one minus the unre- one redundant row, but adding a second manufacturing cost. Between these two paired yield equals the repair ratio. A redundant row shows almost no further extremes, you apply redundancy or not, value in the high 90s is good. In this improvement (Column 7). depending on broad guidelines. Designs case, the repair ratio is (0.99−0.35)/ Figure 2 lists the effects of redun- with high defect rates may require more (1−0.35), or 0.985. dancy schemes in terms of repair ratio redundancy; those with low defect rates may require no redundancy. The analysis LISTING 1 MEMORy-REdUNdANCy-SpECIFICATION EXAMpLE of memory redundancy using critical- area analysis and accurate foundry-defect sramConfig = statistics is necessary for quantifying the { {DIFF.OPEN} {DIFF.SHORT} {single.ODCO} {M1 {0.4}} yield improvement and determining the {single.VIA1} {M2} } optimal configuration.EDN { {PO.OPEN} {single.POCO} {M1 {0.4}} {single.VIA1} {M2} {single.VIA2} {M3} } Acknowledgment A version of this article originally appeared R128x32 sramConfig 34 2 128 0 0 0 ram6t on EDN’s sister site, EDA Designline, R2048x32 sramConfig 34 2 2048 0 0 0 ram6t http://bit.ly/ygj3Fq.

LISTING 2 CONFIGURATION ENTRIES FOR 4-MBIT SRAM Author’s biogrA phy Simon Favre is a technical- sramConfig = marketing engineer in the { {DIFF.OPEN} {DIFF.SHORT} {single.ODCO} {M1.SHORT} Mentor Graphics Calibre di- {M1.OPEN} {single.VIA1} {M2.SHORT 0.6} vision, where he supports {M2.OPEN 0.6} } and directs improvements to the Calibre Yield Analyzer { {PO.SHORT} {PO.OPEN} {single.POCO} {M1.SHORT} product. Before joining Mentor Graphics, {M1.OPEN} {single.VIA1} {M2.SHORT 0.4} Favre worked for Ponte Solutions, which {M2.OPEN 0.4} {single.VIA2} {M3.SHORT} Mentor acquired in 2008. He previously {M3.OPEN} } worked at other EDA companies, as well as at several semiconductor companies. Favre spram_2048x32_core sramConfig 34 2 2050 2 0 0 ram6t has bachelor’s and master’s degrees in elec- spram_128x32_core sramConfig 34 2 130 2 0 0 ram6t trical engineering and computer science from the University of California—Berkeley.

[www.edn.com ] MARCH 1, 2012 | EDN 25

ENGINEERING THE NEXT GENERATION

SINDUSTRY PARTICIPANTS,TE REACTINGM TO THE SO-CALLED ENGINEERING CRISIS, ARE DOING WHAT THEY CAN TO FOSTER SCIENCE, TECHNOLOGY, ENGINEERING, AND MATH TALENT AND ENCOURAGE MORE STUDENTS TO PURSUE ENGINEERING CAREERS.

BY SUZANNE DEFFREE • MANAGING EDITOR, ONLINE

he engineering industry is concerned about the lack of interest in STEM (science/technology/engineering/math) studies and careers from the youth of the United States. Some in the electronics industry refer to this concern as the “engineering crisis.” The fear is that, as baby boomers exit the work force, there will be too few engineers to replace them. The problem has reached all levels of publicT acknowledgment—from President Obama’s commenting on the need for STEM graduates in his January 24 State of the Union address to Sesame Street, which is incorporating more science and technology into its programming and which made “engineer” a word of the day in a September 2011 episode. Despite these concerns, more undergraduate students graduated in 2011 than in 2010 with engineering degrees in all of the eight top engineering disciplines—aerospace, biomedical, chemical, civil, computer, electrical and electronic, mechanical, and nuclear (Reference 1). Yet, at a year-over-year increase of only 5071 new US bachelor’s degrees in engineering for a total of 84,599 new degrees in 2011, the numbers are low, especially when you compare them with estimates from the President’s Council of Advisors in Science and Technology describing a need for 1 million more STEM graduates over the next decade (Reference 2). Moreover, new degrees for electrical and electronic engineering declined from 2005’s high of 14,742 through 2010’s 11,968, only to inch up last year with an additional 37 degrees for 12,005 new degrees total in 2011.

[www.edn.com ] MARCH 1, 2012 | EDN 27 Steve Lyle, director of education, at a gL anCe having more fun—me or the kids!” work-force development, and diver- Kinzer requires his teams to apply sity at Texas Instruments, admits that ↘ Competition for STEM (science/ a full discipline to their projects. “The the number of engineering graduates technology/engineering/math) talent robotics portion isn’t just robotics. It’s remains high. is a concern. “The competition today mechanics, it’s physics, it’s programming, for STEM talent is very, very tight in ↘ The industry is using several [and] it’s engineering documentation,” the United States,” he says, noting tactics, including robotics competi- he says. “It’s the difference between a that, although the unemployment rate tions, to spark students’ interest bunch of kids molding things together remains generally high in the United in STEM. until it works and [kids] really think- States, the rate is below 4% for elec- ing out the process and identifying how trical engineers. “From an education ↘ Mutual respect between mentors things are going to work. Those are the and mentees can lead to a reward- standpoint, we [and our competitors] types of abilities that [make you not only ing experience for both parties. recognize that other countries—namely, a] successful engineer but also successful India and China—are outpacing us in ↘ “Do engineering”—allowing next- in life.” As a mentor, Kinzer recognizes the number of engineers that are com- generation talent the experiences of that he is there to guide the students, not ing out of their universities.” actual engineering, as opposed to direct them. “I really don’t like giving TI, like many other electronics theory-focused education—is a students ideas,” he explains. “I only want companies, isn’t ignoring the prob- strong way to encourage interest [them] to expand on theirs. That [factor lem. Instead, it’s working toward a fix. in STEM. is] a key element of [being] a mentor.” The company has invested more than Ed Smith, president of Avnet $150 million in STEM programs in the also a member of the FIRST board of Electronics Marketing Americas, has last five years and, like many others directors, notes that the competition previously mentored younger employees in the space, focuses its STEM efforts had to turn away teams because of venue and interns at the company and has also on student-achievement and teacher- size. Next year, organizers may add a sec- tried to develop next-generation talent effectiveness programs. ond competition or utilize a larger venue as a former president of the National Like TI, Microchip Technology has to accommodate more teams. Electronics Distributors Association engaged in STEM efforts through simi- Carol Popovich, senior community Education Foundation. Smith advises lar programs. “In the US political cir- relations representative for FIRST and mentors to listen more than they talk cuit, we often talk about the end prod- Vex Robotics and a 16-year Microchip when working with their students. He uct, which is jobs, but that [product] is veteran whose full-time job is to work also reminds mentors to be cautious of the output of the rest of it,” says Steve within the community on STEM, time commitments when entering a Sanghi, Microchip’s president and chief expects further expansion in the future. mentoring relationship. Recognition executive officer. “We have to work She notes a dramatic 30% growth in that the student’s time is as valuable as on it well ahead of time and get kids 9- to 14-year-old participants in the the mentor’s time is significant. “Don’t excited about science, math, engineer- local FIRST Lego League in 2011 and do it unless you have the right amount ing, and technology. Corporations need anticipates that these young partici- of time,” says Smith. “If you don’t have to help nurture the resources and the pants will continue to explore robotics the right amount of time, it really frus- community in which they operate. That as they enter high school. Popovich trates [the mentees]. They don’t feel [goal is] what we are trying to [achieve]: is one of approximately 40 Microchip important.” Prepare our future engineers; prepare employees involved in the competition. Respecting the importance of the our future employees; and educate the She describes the programs as having “a mentees, not only about their available youth in math, science, engineering, high fun quotient” that keeps not just time but also about the value of their and technologies.” the kids but also the sponsors and men- ideas, goes a long way and is key to a Both Microchip and TI are pro- tors returning each year. rewarding experience for both parties. ponents of FIRST (For Inspiration “A lot of these students tend to take us and Recognition of Science and Mentoring and hiring under their wing, as well,” says Stewart Technology), an international program Daniel Kinzer, a technical-support engi- Christie, product-marketing engineer in for children that combines hands-on, neer who has worked at Raytheon for the intelligent-systems group at Intel. interactive robotics with a sportslike 28 years, started volunteering six years Christie works with interns at Intel; is atmosphere and that provides more ago with his local high school’s robotics engaged in student robotics and STEM than $14 million in college scholar- club. The club’s 40 students are spread activities at local schools; and often ships. FIRST started in 1989 with over three FIRST Tech Challenge acts as a judge and a mentor in student approximately 20 teams. It has grown to teams, which Raytheon sponsors. On competitions, including this spring’s more than 26,800 teams and currently a strictly volunteer basis, he spends four Cornell Cup, a college-level embedded- reaches nearly 300,000 students. That to five hours a week at Palm Harbor design competition. Intel and Tektronix growth is clear evidence that STEM can University High School (Palm Harbor, sponsor this competition, which gives attract new young talent. FL) during the building cycle and double teams the opportunity to win as much Microchip is the organizing spon- that time, plus weekends, during compe- as $10,000 (references 3 and 4). “It’s sor of the FIRST Robotics Competition titions. “If I could retire, I’d do this full great to have the fresh perspective and Arizona Regional, and Sanghi, who is time,” Kinzer says. “I’m not sure who’s a much younger outlook than some of

28 EDN | MARCH 1, 2012 [www.edn.com ] us here have [at the office]. It’s a mutual that [mentoring] is an important part respect,” Christie says. of leadership.” Modularity meets “We who have been in the work force for a long [time] don’t appreciate GettinG on the SteM path diversity – that what took us awhile to learn these Chris Gammell, a 28-year-old analog young kids seem to have in their genes,” engineer, didn’t wander into STEM ¸VTE, the new says Pranav Mehta, senior principal until a high-school physics class sparked engineer and chief technology officer an interest. “My high-school physics universal test plat- for the intelligent-systems group at teacher was really engaging,” he says. Intel. “It is amazing how advanced they “That set it off. I was always a science form for MHL inter- are. If you just point them in the right geek, but I had never done electronics direction, the kind of results that they before that. That’s a big problem. face measurements can produce is mind-boggling. Many “My first digging into circuits was a of my years-old assumptions shatter in co-op, and I just kind of hacked along,” As unique as your application as seconds. Knowledge of society and the Gammell explains. “I’m a big proponent compact, scalable and automated is collective conscience has advanced to of co-ops. That’s where I really learned our ¸VTE – the new Video Tester a point where these kids just see things how to solder. Someone finally sat me from Rohde & Schwarz. It is ideal for that some of us cannot.” down and said, ‘You’re doing this wrong; measuring interface conformity of That excellence has encouraged let’s show you how to do this.’ There protocol and media content – both Intel, as well as Avnet and TI, to hire are a lot of engineers like that. As long in R&D and quality assurance. many of its mentored interns. The as you actually want to listen and learn companies often bring in young tal- and you aren’t egotistical about it, men- Take your AV testing to the very ent through internships or cooperative tors are around and are gold.” next level: arrangements and then place them into Mentoring college students, interns, ❙ Source, sink and dongle testing rotational programs, allowing them to and entry-level employees helps cement of the MHL 1.2 interface test-drive several design and business STEM interest and give rise to young ❙ Difference picture analysis in units. “As you increase the number careers—a necessary effort because realtime for testing transmission of students coming in from college 45% of students who receive engineer- of video over LTE campuses, it’s more important to have ing degrees are not practicing engineers ❙ Future-ready modular concept very robust development programs,” 10 years later, according to the ASEE accommodating up to three says TI’s Lyle, who notes that even TI’s (American Society of Engineering measurement modules current chief executive officer, Rich Education). But tapping interest at ❙ Localizable touchscreen user Templeton, started at TI on a rotational a younger age is important, as well. interface basis. “We want to expose them to as “[Kindergarten to Grade 12] is where it ❙ Integrated test automation with many aspects of TI as possible so that all starts,” says Susan Donohue, general protocol generation they feel like they are getting a good co-chairwoman of the IEEE Integrated start at the company.” STEM Education Conference, program A measurable edge in analyzing AV The companies rarely work a con- chairwoman elect of the ASEE K-12 signals. Test and measurement tinued mentoring responsibility into program, and lecturer at the University solutions from Rohde & Schwarz. job descriptions, but, as Lyle says, “Part of Virginia School of Engineering and of being a leader is leading people. Part Applied Science. “If you [shortchange] For more information: of leading a group is either directly them at the K-12 level, it’s going to be providing that mentorship or ensuring so hard for them to catch up, and we that individuals in the organization, can’t afford to lose anybody.” especially your high-potential talent, Donohue has for several years been have the proper mentorship. It’s not presenting engineering-teaching-kit necessarily written down in everyone’s workshops through the ASEE and www.the-av-experts.com job description, but it is understood Frontiers in Education. These kits include such tools as lesson plans, objec- Join The tives, worksheets, bills of materials, and project materials, when possible. The conversaTion self-contained kits enable teachers to EDN recently asked its online open them and immediately bring more readers what they could do STEM into the classroom. each day to help inspire more National Instruments has also taken interest in STEM. Share your steps to bring more STEM directly into answer and review other the K-12 classroom. “We’ve had data responses from your peers at come in that suggests that, if we don’t http://bit.ly/zC6wYA. have [children] interested before sev- enth and eighth grade, the likelihood

[www.edn.com ] Challenge, the sponsored kit had a value of approximately $150 and included LEDs and a microcontroller. Students blog about their progress as their projects move along. In January, iGen named the “Spectacular Seven” team from Oak Canyon Junior High (Lindon, UT) as the winner of the fall challenge. The seven girls on the team, along with their teacher and their mentor, built a small Christmas tree made from PVC (polyvinyl-chloride) piping and loaded with flashing LEDs on the branches and a star on the top that flashes a count- down sign. “We’re seeing a lot of energy from these kids,” Price says, commenting on all of the teams who entered the The “Spectacular Seven” team from Oak Canyon Junior High in Lindon, UT, was the challenge. “They are actually building winner of the iGen fall 2011 LED Challenge. something, and that [step] is important.” As part of its STEM efforts, Math- [that they will go] into an engineering universities to train its employees before Works emphasizes hands-on, project- career is less,” says Amanda Webster, they entered classrooms and began men- based learning. “I see more and more community-relations manager at NI. toring. Currently, the company hosts its professors looking to integrate projects For that reason, NI partners with Lego own technical training for mentors and into their classrooms to get students Group for educational robots and relies on teachers to help set expecta- excited and get a better understanding includes work with the FLL (FIRST tions for the mentor’s role in the class- of what they are actually going to be Lego League) among its STEM and room. “The training helps, but there is doing when they graduate,” says Tom mentoring activities. FLL is an alliance certainly a little trial by fire,” Webster Gaudette, principal education evan- between FIRST and the Lego Group says. “By session two or three, the kids gelist at the company. MathWorks has that uses robotics to ramp up excite- know them, and they become superhe- had close links to academia since its ment about STEM at an earlier age than roes in the classroom. So it’s just getting inception; its first customer was the the FIRST Robotics Competition or past that barrier and fear of going in.” Massachusetts Institute of Technology. FIRST Tech Challenge. That fear can be a major barrier Part of the company’s support for “I don’t think that Dr T, our founder, when a STEM professional considers project-based learning comes from its thought that, years down the road, this entering a classroom or working one work on an integrated curriculum that high-tech company would be partnering on one with next-generation talent as a includes its tools, as well as its work with this toy company. But, with Lego mentor. “After all, we are talking about to provide support materials for those being a top brand … , it has been a huge science and engineering, and these sys- tools, such as free video tutorials. opportunity for us to get into the K-12 tems can be very complex,” says Dave The company works with universities space,” says Webster. “[Lego] lends cred- Wilson, academic-relations director at to incorporate these tools, starting in ibility when you are standing in front NI. “But we have to take small steps and basic classes and throughout the educa- of a 7-year-old trying to get him or her be willing to have something not work. tion process, so that students spend less interested in math and science con- While these things can be daunting, the class time on tool review and more on cepts that, unfortunately, even young technology is really reaching a point theory and lab work. “Having those base children are showing a disinterest in.” where it helps out a lot. Just try it.” learning classes where students come in When looking at root causes of the and are able to touch and feel and try to lack of interest, NI finds that a lot of “Do engineering” program a robot or try to control some- teachers are either not interested in One of the best ways to encourage thing gives the student a better idea of this area or feel that this area is not interest in STEM is to let children what it is to be an engineer versus fresh- their strong suit. “We don’t have a lot actually engineer or, as Naomi Price, man classes [such as] calculus, where of EEs graduating and then going back online brand manager for Innovation they may not get the insight into what to teach elementary school,” Webster Generation, says, “let them get their it is to be an engineer,” Gaudette says. explains. “Our society has built up this hands dirty.” Innovation Generation, or MathWorks also supports hands- dynamic [of not encouraging STEM to iGen, is a Web site that aims to develop on engineering through EcoCar 2, a younger children. So] more than 150 excitement about STEM for the K-12 three-year competition during which [NI] employees go in, week after week, segment. UBM Electronics, the parent engineering students design and build to the same classroom with the same company of EDN, owns iGen, which environmentally friendly vehicles. teacher and students. As they go in hosts LED challenges that see student MathWorks equips all 16 participat- every week, [they become] role models.” teams design and build based on a pro- ing university teams with its tools for In the past, NI teamed with local vided kit. For the fall 2011 iGen LED model-based design, including Matlab

30 EDN | March 1, 2012 [www.edn.com ] and Simulink. “EcoCar is teaching that of approximately $2000; myDAQ, a process where you … do the design work student-owned measurement-and-con- Mark your and go through all the way to the last trol tool that is slightly bigger than an calENDar year of the competition, where you iPhone, has student pricing as low as for these upcoming STEM events: actually have a car driving around with $175. “[The myDAQ tool] gives exten- • IEEE Integrated STEM the algorithms that the students created sibility of the lab time to the students Education Conference, March running on systems,” Gaudette says. so they can experience the instrumenta- 9, 2012, at The College of New “That [achievement is] pretty impres- tion as well as create their own instru- Jersey in Ewing, NJ sive for undergraduate students. [When mentation anyplace in or outside the http://bit.ly/wZH08o they graduate], they can say, ‘I built a lab,” Wilson says. “We’re seeing little car, and I was part of a team that worked back rooms and small areas with a table • “Engineering the next gen- and did it all.’” suddenly becoming labs because stu- eration of STEM” panel ses- NI’s Wilson reiterates this need for dents can walk in with their laptop, sion and networking event at actually engineering to attract new engi- myDAQ, and a little accessory board; Design West, San Jose, March neers: “Theory is important. Simulation plug in; and do their labs right there.” 28, 2012 has its place, but, at some point, we With lab time often scarce, such www.ubmdesign.com honestly believe that a big answer to the nooks of engineering practice are • Second USA Science and question of how to attract, inspire, and becoming more commonplace on col- Engineering Festival, April 28 ultimately mint new scientists and engi- lege campuses, as well as elsewhere. to 29, 2012, Washington, DC neers is to give them the experiences As the “maker movement” continues http://bit.ly/xZtX1N and do engineering—not only theorize rising with, as Gammell describes, “a about it, not only conceptualize it, and resurgence of electronics and kits,” so not only simulate it. Those are parts of do hacker spaces. “I never realized that neering crisis. Still, much more effort is a process that have to culminate in the the students who come to these [hacker- necessary. “We all need to participate ‘do-engineering’ experience. If we can space] meetings aren’t allowed to sol- in this [effort],” says NI’s Wilson. “We give relevant, exciting, real, experien- der in the dorms,” says Intel’s Christie. need not to be so focused on the fact tial elements to students, the response “They have to have a place to go where that there is a problem. We’ve figured can be very good.” it is safe for them to use power tools and that out. Now, let’s challenge ourselves Supporting that view, NI offers those sorts of equipment. Often, those to bring our best ideas to the table. And reasonably priced versions of its uni- tools are not available at the university.” let’s set the bar—for pricing, accessibil- versity- and student-targeted tools— ity, functionality, and ease of use for ELVIS (Educational Laboratory Virtual Signal received educators. If we do that, everyone will Instrumentation Suite) and myDAQ The need for more next-generation respond. But a fully defined problem (data-acquisition). ELVIS, a LabView- skilled STEM professionals is on the is a half-solved problem. We need to based design and prototype platform radar of companies and individuals, and, start with the challenges. Once the con- for universities, has midpoint prices as such, they just may beat the engi- straints are clear, people will be really creative on how to solve them.”EDN

r eferenceS 1 “Bachelor’s degrees in engineering, by discipline, 2002–2011,” Engineering Workforce Commission. 2 Deffree, Suzanne, “President Obama: We need 1 million STEM graduates,” EDN, Feb 7, 2012, http://bit.ly/x8isBb. 3 Deffree, Suzanne, “The next generation: amazing student innovation and the Cornell Cup,” EDN Tech Clips, http://bit.ly/zuu1Jy. 4 “Cornell Cup USA,” Cornell Universi- ty, http://bit.ly/wtc7GJ.

You can reach Managing Editor, Online, Suzanne Deffree at 1-631-266-3433 and suzanne. Members of The Ohio State University team pose with their EcoCar vehicle. [email protected].

[www.edn.com ] March 1, 2012 | EDN 31

By Ian DennIs • PrIsm sounD GrouP

Audio-converter-subsystem design challenges in the 21st century

Some key StrAtegieS enAble you to Achieve optimum Audio-converter performAnce.

he habitat of audio converters is ever-changing. 130 dB and total harmonic distortion plus noise of 110 dB rms, Designers built early converters into stand- unweighted, in the audio band. The weak link in a conversion alone digital-audio equipment. Later, they system is most often elsewhere. No case exists for applying built them as stand-alone conversion devices design effort or budget to the data converter itself, except in with dedicated digital-audio connectivity. the most exacting of applications, and where it has already been Nowadays, converters are increasingly avail- applied in great measure to the rest of the converter subsystem. ableT as peripherals for PCs or computer networks. Meanwhile, To get the best from your chosen data converter, you must apply performance targets have been rising. In some ways, these painstaking design and relentless assessment. changes have affected audio-converter design; in other ways, it’s business as usual. Typical aDc anD Dac subsysTems It seems that the plan of campaign for most engineers set- Figures 1 and 2 show typical ADC and DAC subsystems. You ting out to design an audio-converter subsystem—that is, a must take special care of the analog bits; several parts of the stand-alone converter or that part of the equipment that deals subsystem will try to make that task difficult. A dashed line with audio conversion—is as follows: First, choose a data- indicates where you might consider isolating the analog and converter device—an ADC, a DAC, or a codec chip—which will meet the project’s requirements for per- PSU formance, channel count, cost, and SYNCHRONOUS DIGITAL PARTS features. Then, implement a design VREF PLL around the device using the manufacturer’s application note plus whatever DIGITAL- ANALOG INPUT SIGMA-DELTA DECIMATION DSP DIGITAL INTERFACE additional features and interfaces the INPUT CONDITIONING MODULATOR FILTER FUNCTIONS OUTPUT TRANSMITTER design requires. Most converter subsystems, however, either always or sometimes perform somewhat below figure 1 in a typical Adc, you must take special care of the analog bits (blue shading); the potential of their chosen data several parts of the subsystem will try to make that task difficult. converter—usually because of several issues: clocking, unruly switch-mode power supplies, low-quality analog- signal paths, lack of attention to the PSU voltage reference, and digital parts DIGITAL PARTS V that go awry. PLL REF When digital audio was new, the data converter itself was almost the DIGITAL- INTERPOLATOR DAC AND ANALOG only consideration because it was DIGITAL INTERFACE DSP AND SIGMA- LOWPASS OUTPUT OUTPUT INPUT RECEIVER FUNCTIONS DELTA FILTER CONDITIONING impossible to build one with as much MODULATOR dynamic range and linearity as the professional or high-end consumer user required in analog equipment. figure 2 in a typical dAc system, the dashed line indicates where you might consider Designers asked only, “What chip is in isolating the analog parts (blue shading) and the digital parts, but many ways are avail- it?” Nowadays, workmanlike data con- able for doing so, or you can opt not EDNto isolate MS4434 theFig 1.eps parts. DIANE verters can exceed a dynamic range of

[www.edn.com ] March 1, 2012 | EDN 33

EDN MS4434 Fig 2.eps DIANE REFERENCE LOOP FILTER REFERENCE PHASE CONVERTER VCO COMPARATOR CLOCK

/2N

HIGH CORNER LOW CORNER FREQUENCY FREQUENCY JITTER REJECTION OUTPUT-PHASE-NOISE (INTRINSIC-JITTER) SPECTRUM

Figure 3 You might use a conventional analog PLL to lock a converter to a reference clock.

the digital parts, but many ways are available for doing so, or Unfortunately, a low loop-filter corner frequency makes you can opt not to isolate the parts. the PLL slow to lock up. Worse, though, it prevents suppres- sion of the phase noise of the VCO around the loop. To avoid ClOCk reCOvery unacceptable intrinsic jitter, you must keep the loop filter’s The conversion clock of a data converter is critical to its corner frequency high, or choose a VCO with low phase noise linearity because any variation in the regularity of the clock in the first place. results in sampling jitter, which causes phase modulation of A good low-noise oscillator is a quartz VCXO. Because the converted signal (Reference 1). You can most easily assess of their high-Q factor, however, you can’t pull them far from this parameter by passing a high-amplitude, high-frequency their natural frequency, so they may have a pull range of only signal through the converter and looking for phase-modula- ±100 ppm, which may be insufficient for your requirements. tion sidebands or skirts in the spectrum of the output. On the other hand, a humble RC multivibrator VCO can Converter clocks are usually derived from phase-locked have all the pull range you need but is essentially untuned, so loops rather than local oscillators; it is unusual for a device it has large phase noise and is prey to all manner of interfer- to be able to always be the system-clock master. It must be ence. A few other VCO options exist between these extremes. able to lock to an external reference or to its digital-audioEDN MS4434 or FigTo 3.eps solve DIANE the pull-range problem with quartz, you could com- computer interface. To lock to all references, the lock range mission some VCXOs made of a special material with a lower may need to be as wide as ±1000 ppm and must usually accom- Q, such as LGS (langasite) or lithium tantalate, which are modate different sample rates (Reference 2). expensive. The need to lock converter clocks to various wide-ranging You could use a tuned-circuit LC VCO, which has a lower- references and to maintain low jitter tends to be among the Q factor than that of crystals, but at least it has a Q factor, so it most difficult challenges in converter design because it embod- can be designed with lower phase noise than a multivibrator. ies some tough trade-offs. Although other applications, such These circuits’ wide range can cover both 44.1- and 48-kHz as telecommunications, had somewhat solved this problem rates and can easily accommodate ±1000-ppm reference before digital audio emerged, audio engineers had to start inaccuracy. Overall, this circuit is not a bad choice; if you’re from scratch, and it’s taken a couple of decades to reinvent a good approach. The situation has become more challenging PLL now that you must lock to software-generated syncs and time HIGH F C RC REFERENCE stamps arriving over computer interfaces because they can VCO embody large amounts of jitter with uncontrolled spectrum (a) and may not come around as often as you’d like (Reference 3). PLL Figure 3 shows a conventional analog PLL that you might LOW FC QUARTZ REFERENCE use to lock a converter to a reference clock. A phase com- QUARTZ parator continually compares the external reference with the (b) PLL PLL regenerated version, and decides whether you should speed 1 2 LOW F HIGH F C LGS C LC up or slow down the voltage-controlled oscillator to make REFERENCE /N VCO VCO them match in frequency and phase. You need to respond (c) in a leisurely fashion; otherwise, you’ll track any incoming jitter. Smooth out the up/down requests with a lowpass loop filter before passing them to the control input of the VCO. Figure 4 Three analog PLL examples are shown. A basic PLL The tough trade-offs, however, are mostly about choosing chip operates in a digital-audio-interface receiver (a). A purpose- the right loop-filter characteristics and the right VCO. The designed PLL provides converter-clock recovery, with a higher-Q design must reject incoming jitter down to low frequencies so VCO and a low loop-filter corner frequency (b). Two cascaded that it does not become prey to audible sampling jitter. That PLLs—the first, with an LGS VCXO for wide lock range and a requirement also potentially allows you to accommodate a low-corner-frequency filter, which rejects jitter, and the second, low comparison frequency, such as a reference comprising with a tuned-circuit VCO and a high loop-filter corner frequency infrequent software time stamps or a video sync that lines up to cover all sample-rate multiples—provide good intrinsic jitter (c). with an audio sample only every few seconds.

34 EDN | March 1, 2012 [www.edn.com ]

EDN MS4434 Fig 4.eps DIANE picky, though, the intrinsic jitter won’t be top-class if the digital domain, thus eliminating the trade-off of phase noise corner frequency of the loop is dropped to where you’d like it. versus low corner frequency because the loop filter and the In considering these trade-offs, it is helpful to look at some VCO are both entirely digital. The VCO—now an “NCO”— real-world examples of applying analog PLL technology to is jittery because it is a varying integer division of a fixed converter subsystems (Figure 4). The circuit in Figure 4a uses master clock, but inclusion of a sigma-delta modulator in the a basic PLL chip or, for an AES3 (Audio Engineering Society loop means that you can confine its jitter to high frequencies. 3) or SPDIF (Sony/Philips-digital-interface) DAC, uses the It is therefore straightforward to cascade the NCO’s out- PLL in the digital-audio-interface receiver. The VCO, how- put into an analog PLL with a high corner frequency, which ever, has a low-Q factor and high phase noise, usually in the can then use an inexpensive VCO without intrinsic jitter. form of an RC multivibrator, which is vulnerable to all sorts Furthermore, you can change the corner frequency in soft- of interference, especially power-rail and ground noise, and ware to achieve fast lock and then extreme jitter rejection. the corner frequency of the loop filter is high. These prob- The hybrid PLL is inexpensive because it requires no reso- lems result in high intrinsic jitter and poor jitter rejection at nator-based VCO. Similar approaches are now available for audible frequencies. audio use from a number of vendors, including Cirrus Logic The circuit in Figure 4b uses a purpose-designed PLL for (Reference 4 and Figure 5). Some manufacturers even built converter-clock recovery, with a higher-Q VCO and a low them into data converters. loop-filter corner frequency. This setup results in good intrin- Another way to approach this problem is to use mod- sic jitter and jitter rejection, but the pull range may be insuf- ern, low-cost SRC (sample-rate-converter) chips, which ficient, and you must carry the cost of two or more VCXOs. are achieving performance that can exceed that of the data The circuit in Figure 4c uses two cascaded PLLs—the first, converter itself. You might elect to operate the conversion with an LGS VCXO for wide lock range and a low corner- element at a fixed rate provided by a local crystal, thus elimi- frequency filter, which rejects jitter, and the second, with a nating sampling jitter, and to convert the converter’s input tuned-circuit VCO and a high loop-filter corner frequency or output data rate. This approach can lead to other issues to cover all sample-rate multiples. This circuit has no jitter and places the responsibility on the SRC to achieve jitter so it requires no jitter rejection. If you make the LGS VCXO rejection that matches the same standard as in the PLL model frequency 44.1 and 48 kHz, you can provide a sample-rate while also protecting the quality of your audio components. reference for the second PLL with a simple programmable divider. This approach has good intrinsic jitter and jitter Power suPPlies rejection, works for all sample-rate multiples of 44.1 and High-quality line-powered audio equipment has traditionally 48 kHz, and has a wide lock range. Even with one VCXO, employed linear PSUs, but these devices have disadvan- though, it’s still expensive, and it still may have questionable tages of size, weight, heat, and cost and may need a manual performance at low comparison rates. line-voltage selector. Properly designed PSUs do have the An even better approach is to adapt the dual-loop archi- advantage of not providing a source of high-frequency inter- tecture as a hybrid PLL by implementing the first PLL in the ference into the analog circuits. An SMPS eliminates these

DELTA-SIGMA FRACTIONAL-N FREQUENCY SYNTHESIZER

PHASE INTERNAL PLL OUTPUT LCO COMPARATOR LOOP FILTER VCO

FRACTIONAL-N DIVIDER

DELTA-SIGMA MODULATOR

N DIGITAL PLL AND FRACTIONAL-N LOGIC

DIGITAL FILTER

FREQUENCY FREQUENCY REFERENCE COMPARATOR FOR CLOCK FRACTIONAL-N GENERATION

Figure 5 Cirrus Logic’s C2000 hybrid PLL is inexpensive because it requires no resonator-based VCO.

[www.edn.com ] March 1, 2012 | EDN 35

EDN ms4434 Fig 5.eps DIANE disadvantages, but it must be carefully designed if it is not is a consequence of the stray capacitance and the primary to become a major source of hostile switching noise. High- inductance, LP. The switch interrupts the oscillation at a end-audio designers have traditionally shied away from using random voltage, causing potential interference from the large SMPSs. switching voltage and current. You must design an SMPS in any type of equipment to The main problem, then, with the basic flyback topol- meet the appropriate electromagnetic-compatibility stan- ogy—and with most other basic topologies—is that the dards for conducted and radiated emissions. Nowadays, this transistor switches hard and randomly, causing high levels task is not difficult, with SMPS controller vendors providing of radiated and conducted interference to invade the analog application circuits that comply with these standards—usu- audio parts. You are now on a slippery slope, and can’t do ally, just meeting compliance requirements to save the costs of much to reduce the source of the problem. You can keep filter components. Unfortunately, the same sorts of misbehav- the switching loops as small as possible to reduce radiation, iors that might cause an SMPS to be noncompliant can wreak you can optimize the ground topology and make critical havoc with audio performance, even at much lower levels. tracks wider to reduce ground noise, and you can tame the Thus, SMPS design for audio applications can be elaborate. edge times with snubbers, but only at the cost of reduced efficiency and increased heat. So you end up having to take Drawbacks of low-cost sMPss disproportionate steps in the vulnerable parts to make sure Converter systems often need a large number of power rails that the audio remains clean. These steps can include the use and may benefit from isolation between the digital and the of screening cans, split grounds, or galvanic isolation. analog parts, so a flyback architecture is a popular choice Another problem is the random frequency of the SMPS because it conveniently offers these benefits, which may also controller, which can produce interference at the beat fre- be useful in dc-powered situations. A variety of other simple quency between itself and, for example, the audio sample SMPS architectures can be used instead; the problem for the rate, thus making it impossible to confine it to some incon- uninitiated is generally how to choose among them. spicuous part of the spectrum. A possible approach is to In a flyback converter, dc—either directly input or rec- lock the switching frequency to some multiple of the sample tified from the ac-line voltage—is switched through the rate to remove the beat frequency, but this approach can be primary of the flyback transformer by a transistor under the problematic. The regulatory variation of the duty cycle can control of a device that regulates the duty cycle of a train of cause its own beat, and some types of SMPS controllers vary switching pulses to regulate the various secondary outputs. the switching frequency to effect regulation. You could even Rectified and filtered secondaries provide the power rails. introduce a situation in which a software bug or a wayward Figure 6 shows a flyback converter and its switching sample rate could collapse the power rails. It’s easy to see why waveform. Stray capacitance, CD, across the switch and the designers are reluctant to use SMPSs in high-performance leakage inductance of inductor LLK causes the high-frequency audio equipment, but they often have no choice in dc-pow- oscillation at the point at which the switch turns off. This ered situations, and SMPSs are small and inexpensive. oscillation is a largely unavoidable source of hostile RF. You can control its amplitude with snubbers to protect the switch, resonant anD quasiresonant sMPss but this approach can make the interference even worse. Ideally, to combine the benefits of a linear supply and an The low-frequency oscillation before the switch turns on SMPS, you would like to find a way of passing a high-frequen-

LLK AND CD L AND C t=0 P D VF VDS

LM LS VOUT VDSS LP

VR LLK

VIN V CIN IN

RP VR

VDSMIN

CD VDS

TON TFW t

TOFF T (a) (b)

Figure 6 In a flyback converter (a) and its switching waveform (b), stray capacitance, CD, across the switch and the leakage inductance of inductor LLK causes the high-frequency oscillation at the point at which the switch turns off.

36 EDN | MARCH 1, 2012 [www.edn.com ]

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ubmdesign.com cy sine wave through the transformer. An approximation to can improve interference and which increases EMC margins such an approach is a resonant SMPS. To losslessly achieve (Figure 8 and Reference 6). this architecture, it is usual to generate the sine wave by placing a resonant LC-tank circuit in the primary; a neat trick is SMPS Selection to use the primary inductance as the inductor. The stimulus It is often difficult for the uninitiated to make the correct for the waveform is still a hard-switching transistor under choice of SMPS architecture for audio because most SMPS- clever control, but the resonant circuit tunes the primary controller vendors organize their selection tables by power waveform to an approximation of a simple sine wave, with capability. They assume that audio designers, like other the switching happening at 0V or 0A moments, all of which designers, will want to choose the cheapest approach for their leads to less hostile switching noise. power requirement. The recommended SMPS for low-power On the other hand, resonant designs tend to be somewhat applications such as this one—say, less than 20W—is usually more costly and larger than flyback designs. A major draw- a basic, hard-switching type because the power is low enough back with many resonant architectures is that you must tailor for its emissions to remain below statutory EMC limits with the LC-tank circuit to the switching frequency and dc input minimal filtering and for the losses resulting from its indis- voltage to maintain resonant and zero-switching operation, criminate switching to be insufficient to set it on fire. which makes offline universal input design problematic unless Higher-power applications in which you must control you incorporate power-factor correction. switching noises and losses require the use of resonant and A good compromise is a quasiresonant converter. The quasiresonant topologies. For audio, however, it’s often a good idea here is that, because the problems in a simple flyback idea to make a low-power implementation of a high-power converter happen only at the moments of switching, it is topology in the interest of achieving minimum emissions; necessary to find a way of creating a resonant waveform only you can usually make up for the extra cost by not having to at the switching points. You can achieve this goal by simply armor-plate the audio parts. introducing primary resonance into an ordinary flyback topology and making the controller clever about deciding when to other conSiderationS switch. Figure 7 shows a zero-voltage-switching, or valley- Cross-regulation—varying load conditions on individual switching, quasiresonant converter, which is a low-cost way rails—can cause the voltages of other rails to vary and is often to cut SMPS emissions at their source (Reference 5). a problem with multirail-SMPS designs because the regulatory In this case, you create the tank circuit by simply adding a mechanism of the controller can generally operate on only one large capacitor across the switch. The tank circuit slows the rail. In performance-critical applications, it may be necessary switch-off rise time, and the controller arranges the switch- to provide linear postregulation on analog-power rails from the on instant to coincide with a valley in the low-frequency SMPS. If so, take care to provide adequate cooling for the lin- oscillation; this approach inherently makes the cycle period ear regulators. Linear regulators can usually regulate over only variable with an attendant spread-spectrum effect, which a limited frequency range, and the switching products from the SMPS can easily exceed this range, causing them to pass straight through the regulator. It is V therefore a good idea to use ferrite beads ahead GATE of linear postregulators. Line-powered linear and SMPS equipment usually draws current from the mains only during voltage peaks, which can cause distortion to the power line, with possible detriment to the per- N×VOUT formance of other sensitive audio equipment. It V D may be beneficial to incorporate PFC into your SMPS design to cause the least possible distortion to the power waveform. You can be sure, VALLEY VIN however, that all the other equipment around the SMPS will probably be causing distortion anyway. Some PFC schemes allow tight control 0 of the rectified voltage ahead of the SMPS, MAGNETIZATION DEMAGNETIZATION which can allow you to further reduce switching noise in resonant and quasiresonant designs IL by ensuring no switching for any input voltage. 1234 As well as applicable safety, EMC, and dis- 0 posal legislation, line-powered equipment is sub- t t t t t 0 1 2 3 00 ject to or will become subject to various territo- TIME rial legislation for standby-power consumption, when applicable, and operating efficiency—for Figure 7 A zero-voltage-switching, or valley-switching, quasiresonant converter example, under the European Union’s Ecodesign is a low-cost way to cut SMPS emissions at their source. Directive and the voluntary US EnergyStar program. Although territorial legislations vary,

38 EDN | MARCH 1, 2012 [www.edn.com ]

EDN MS4434 Fig 7.eps DIANE A11_EDN_1-3V_2-25x10_A11.qxd 11/2/11 11:15 A

maximum standby-power consumption must filter, cancel, or both filter and of 0.5W and minimum operating effi- cancel this noise in the first instance. ciency of approximately 80% are typical Therefore, to maintain in-band linear- for a 20W device. ity, the IVC must behave linearly at frequencies well above the audio band. If AnAlog-signAl pAth you are tempted to stray from the manu- Analog performance is the limit- facturer’s recommended IVC design, HIGH VOLTAGEOver ing factor in many converter designs. bear in mind the bandwidth require- 2500 Std. Models Somewhere along the line, perhaps you ment and note that the data converter’s Surface Mount and Thru-Hole forgot some of this wisdom. All of the output loading will probably have to be buffer amplifiers, gain stages, and other similar to that of the application circuit components between the outside world for optimum performance. DC-DC Converters and the ADC and between the DAC As for the rest of the analog-signal 2V to 10,000 VDC Outputs and the outside world are obvious areas path, it is important to choose the right in which good design practice will pay components and circuit topologies. The Low Profile / Isolated dividends. It is no mean feat to main- most straightforward way is to use op Up to 10,000 Volts Standard Regulated Models Available tain the performance of a flagship data amps. This approach is currently a good converter through the analog circuits, policy except in a few situations, such particularly if you must incorporate sig- as microphone/phonograph preamps nificantly high performance. and high-current outputs. It will pay to In general, use a ground plane for familiarize yourself with the noise models analog circuits and take advantage of for op-amp circuits, such as those that the small surface-mount-technology Reference 8 describes, and to implement packages that are now available. Lay a spreadsheet to calculate noise levels for things down instead of standing them your circuit. A simpler but less versatile up. These measures are free and will approach is to use op-amp manufacturers’ reduce susceptibility to interference and noise-reckoning tools (Reference 9). crosstalk. The best approach is to use a full-blown Of particular importance are the buf- Spice simulator (Reference 10). fer circuits, which drive by the input of You will find that your choice of op the ADC or are driven by the output of amps in each stage is generally restricted the DAC. In general, the safest policy to relatively few that have the requi- is to stick with the exact circuit topol- site voltage-noise, current-noise, or ogy and components that the converter both voltage- and current-noise per- See PICO’s full catalog immediately manufacturer recommends. The vendor formance. The world is full of op amps, www.picoelectronics.com will have spent a long time coaxing the most of which are not good for audio. best out of the device by tweaking its On the other hand, beware the best- buffer. However, this scenario is not audio-op-amp syndrome. High always true. With experience and care, No op amp will behave best in every it is sometimes possible to exceed the audio stage. In each case, you must select Power application-note performance. On the the right one for the job. Usually, you other hand, if cost is important, you can make this selection from looking at Up to 350 VDC Outputs can often scrimp a bit on op-amp types. available data or by trading off require- (Units up to 150 Watts) Sigma-delta ADC inputs often have ments against cost, power, and other Regulated / Wide Input Range a nonlinear-input characteristic and factors. But don’t be afraid to use trial Isolated Outputs produce aliasing components if subject and error in the end, although doing so to high frequency, so an ideal ADC buf- requires some determination and good fer must achieve a lot of high-frequency eyesight in this age of SMT. With some roll-off—but without compromising in- dexterity, you can persuade dual-inline band flatness—and a low output imped- sockets onto the SOIC sites in your pro- ance. It’s better to avoid the passive pole totype. In general, it’s a good idea to use between the output of the buffer and the dual-op-amp sites because doing so is a input of the converter and to instead good trade-off of cost and choice and use, for example, an analog-input buffer allows tight layout in balanced circuits. (Reference 7). Designers generally prefer inverting- INDUSTRIAL • COTS • MILITARY Many high-quality DACs have cur- op-amp topologies over noninverting Delivery Stock to One Week for sample quantities rent outputs, requiring an outboard models because the inverting devices’ current-to-voltage-converter circuit. input terminals operate at virtual earth. Sigma-delta DACs often produce sig- The dynamic input-common-mode PICO ELECTRONICS, Inc. 143 Sparks Ave., Pelham, New York 10803 nificant out-of-band noise, and the IVC voltage of noninverting configurations See EEM or send direct for Free PICO Catalog Call Toll Free 800-431-1064 • FAX 914-738-8225 E Mail: [email protected] [www.edn.com ] (a) (b)

Figure 8 The tank circuit slows the switch-off rise time (a), and the controller arranges the switch-on instant to coincide with a valley in the low-frequency oscillation (b). may add distortion, particularly at high frequencies with some when possible and strive to keep the area between flat; you op amps. Consider adopting a fully balanced topology end to will notice the difference. end—perhaps using a “symmetrizer” in the ADC’s case to achieve balance through the channel even with unbalanced RefeRence voltage inputs. Avoid mode-conversion types, however. Using a fully Nearly all data converters have at least one accessible refer- balanced topology not only reduces interference and crosstalk ence-voltage pin, reference-current pin, or both. The refer- but also can achieve higher performance because distortion ence multiplies the input to the converter to produce the mechanisms often tend to cancel. Most high-end data con- output, so how you handle the reference is just as important verters operate in a balanced mode anyway. as the analog-signal path. Any noise or interference on the It is important to select a gain structure that maximizes reference modulates the converter’s output. You must filter the dynamic range, or SNR, and thus minimizes the need for internally generated voltage references by placing suitable excessively low-noise design, with its attendant cost. Even so, capacitors close to the pins. This approach usually requires resistor values must be low enough for their thermal noise to an assortment of low-value, high-frequency, large electrolytic be out of the picture but not low enough to bring problems or tantalum capacitors. of overdissipation or circuit loading. In some cases, you may want to drive a voltage reference The linearity of resistors and capacitors is also important. externally from a well-regulated and filtered source. Some Resistors must be metal-film or thin-film types, not the usual converter devices require both high and low reference volt- chip resistors, which change resistance according to voltage ages to define their operating range, and some require sepa- and the seasons. Capacitors must be low-k ceramic types, such rate references per channel. Although users can sometimes as C0G and NP0 types, or low-loss plastic, such as polysty- to some degree modify the reference voltages, manufactur- rene. Failure to observe these rules leads to nonlinearity and ers often optimize converter performance at a particular distortion in most circuit topologies. Keep electrolytics out voltage, and it’s best to stick with that voltage. When your of the signal path; there are other ways to ensure extended design has distortion or noise problems, remember to look low-frequency response. at the reference. If modulation issues, such as sidebands PCB layout of the channel circuits is critical for minimiz- or noise skirts around the signal frequency, get worse with ing both interference and interchannel crosstalk. Make sure increasing signal frequency, it’s jitter. If those issues don’t that the op amp’s output and the ground nodes of the stages get worse, then the problem is most likely the reference are outermost and that the op amp’s input nodes are inner- voltage (Reference 11). most in your channel-strip layout. Pay attention to the bandwidth of your stages. It’s not Digital PaRts always better to go for a dc-to-light approach. Limiting the Any low-quality digital processing in the signal path can undo bandwidth at the top end reduces susceptibility to interfer- all of your good work in the analog domain. Make sure that ence, and the presence of excessive high frequency, even if your design has enough precision everywhere and that algo- inaudible, does no good to the in-band signal. Limiting the rithms are beyond reproach. Culprits often include dithering, bandwidth at the bottom end removes wandering dc, which noise-shaping, and dynamics processing. Remember, too, those can cause problems with mixing and switching, as well as parts of the digital-signal path that designers often overlook. the risk of unexpected overload. On the other hand, keep For computer interfaces, the driver or parts of the operating a healthy disrespect for the −3-dB, 20- to 20-kHz approach. system that you thought you had bypassed sometimes let you Extend the top and the bottom end beyond the bare essentials down. You must be able to test your entire signal path, so make

40 EDN | MARCH 1, 2012 [www.edn.com ] sure that your dual-domain audio-test equipment can work in RefeR ences the computer domain, directly interfacing with your driver 1 Dunn, Julian, and Ian Dennis, “The diagnosis and solution layers. of jitter-related problems in digital audio systems,” Preprint In the old days, it was almost possible to keep all of the 3868, Audio Engineering Society, February 1994, http://bit. digital parts of a converter system ticking at some multiple ly/w6uBUo. of the sample rate. Consider the simple case of an AES3- 2 “AES11-2009: AES recommended practice for digital interfaced converter with no DSP and no microcontroller. audio engineering - Synchronization of digital audio equip- Nowadays, though, you must have a boxload of computers, ment in studio operations (Revision of AES11-2003),” Audio including DSPs, RISC processors, and FPGAs, all running Engineering Society, 2009, http://bit.ly/w1S33y. asynchronously, and probably a computer interface buzzing 3 Dunn, Julian, “Sample clock jitter and real-time audio over away across the entire spectrum. Although lower operating the IEEE1394 high performance serial bus,” Preprint 4920, power, lower core voltages, and smaller dice and packages Audio Engineering Society, 1999, http://bit.ly/wKIQpU. contribute to reducing the hostile intent of digital electron- 4 CS2000-CP, “Fractional-N Clock Synthesizer & Clock ics, a designer can do little to fix it beyond observing good Multiplier,” Cirrus Logic, http://bit.ly/yJlmqU. EMC design at ports and good power decoupling and filtering. 5 Kleuskens, J, and R Kennis, “75W SMPS with TEA1507 You must make some fundamental decisions at the outset QuasiResonant Flyback controller,” Philips Semiconductors, of your design. These decisions include the choice between June 30, 2000, http://bit.ly/AurkSB. line power and dc power, as well as choices regarding 6 “L6565 quasi-resonant SMPS controller,” STMicroelec- whether you can put your design into its own metal box, tronics, http://bit.ly/xoMAVu. whether it must cohabit with digital parts, or whether 7 “AK5394A Super High Performance 192kHz 24-bit ΔΣ it must reside in a host computer. You also must decide ADC,” Asahi Kasei, 2005, http://bit.ly/wNJAzw. whether you need and whether you can afford screening 8 Karki, James, “Calculating noise figure in op amps,” Texas cans. Another decision comes up when you consider con- Instruments, http://bit.ly/A27aF3. struction: Can you use a multilayer PCB with groundplanes, 9 “Noise Calculator, Generator and Examples,” Texas a small SMT device, or another configuration? What about Instruments, http://bit.ly/x2xDGU. isolation? Can you galvanically isolate the analog and digi- 10 “TI TINA-TI SPICE-based Analog Simulation Program,” tal domains using optical or magnetic isolators? This isola- Texas Instruments, http://bit.ly/wniJs3. tion can be beneficial in computer or computer-interface 11 Dennis, Ian; Julian Dunn; and Doug Carson, “The Numeri- cases, in which the digital ground can be toxic. You also cally-Identical CD Mystery: A Study in Perception versus need to weigh EMC compliance and efficiency. Project Measurement,” 1997, http://bit.ly/zU0BZs. requirements and component budget probably dictate the 12 “IEC 61606-3: Audio and audiovisual equipment - answers to these questions. Digital audio parts - Basic measurement methods of audio The objective assessment of converter systems, both characteristics - Part 3: Professional use,” International during design and in general, is a complex subject and the Electrotechnical Commission, October 2008, http://bit.ly/ subject of many international standards, such as IEC 61606-3 AckWHL. and AES17-1998 (references 12, 13, and 14). It is useful, 13 “AES17-1998 (r2009): AES standard method for digital however, in many situations to make a simpler assessment. audio engineering - Measurement of digital audio equipment For many engineers, this assessment involves instead using (Revision of AES17-1991),” Audio Engineering Society, listening tests to determine audibility. The debate about 1998, http://bit.ly/xgOPWH. whether measuring or listening is better will rage forever. 14 “AES-12id-2006 (r2011): AES Information Document for However, developing high-performance audio requires both digital audio measurements - Jitter performance specifica- methods. Some engineers believe that it is better to use tions,” Audio Engineering Society, Oct 5, 2011, http://bit.ly/ measurement to debug the design and to worry about listen- zKCKfq. ing tests after that. For debugging, first equip yourself with an audio ana- AuthoR ’s biogRAphy lyzer, which can stimulate and measure in the analog, Ian Dennis is technical director of the Prism Sound digital, and computer domains. Analyzers should be able Group, a manufacturer of audio converters, test- to display a continuous high-resolution FFT, and they and-measurement equipment, audio workstations, should be user-programmable so that you can automat- and media servers. He has been designing audio ically hop among key measurements. You must be able equipment since the early 1980s. At Prism Sound, to define all of the key measurement parameters when he focuses on R&D and production activities but you set up the debugger. Make a lead to connect a pair also works on a few design projects now and then. Current inter- of small probes to the analog analyzer’s input so that you ests include audio conversion, audio-test equipment and methods, can meas ure between all the stages. SMPS and computer- media-streaming devices, and audio networking. Dennis is vice based devices also need a means of seeing the wideband chairman of the Audio Engineering Society SC-02-01 Standards spectrum, which EMC precompliance also requires. Table Committee for audio test and measurement and also works on 1, available with the Web version of this article at http:// standards development within the BSi and International Electro- bit.ly/w29NCL, provides a guide to the most important technical Commission, most recently contributing to IEC 61606- audio-performance parameters that apply to conversion 3 test methods for professional digital-audio equipment and ITU systems.EDN BS.1770 loudness metering.

[www.edn.com ] March 1, 2012 | EDN 41 Isolated LED Current Control with Active PFC

90V to 265V AC

VIN DCM

VIN_SENSE FB

Regulated LT3799 LED Current VREF 20W (Typically ±5%) CTRL3 GATE LED Power CTRL2 SENSE CTRL1 VINTVCC

GND Fault FAULT CT COMP + COMP –

Complete TRIAC Dimmable Schematic

TRIAC Dimmable LED Driver Needs No Opto-coupler Our LT®3799 isolated LED controller with active power factor correction (PFC) is specifically designed for driving LEDs over a wide input range of 24V to 480V+. It is ideal for LED applications requiring 4W to over 100W of LED power and is compatible with standard TRIAC in-wall dimmers. The LT3799’s unique current sensing scheme delivers a well regulated current to the secondary side with no opto-coupler, enabling it to provide ±5% LED current accuracy. It also offers low harmonic distortion while delivering efficiencies as high as 90%. Open and short LED protection ensures long term reliability and a simple, compact solution footprint addresses a wide range of applications.

LED Current vs TRIAC Angle LT3799 Demo Board (25W) Info & Free Samples

1.2 www.linear.com/product/LT3799 1.0 1-800-4-LINEAR

0.8

0.6

0.4 LED Current (A) 120V app 0.2 220V app

0 0 30 60 90 120 150 180 TRIAC Angle (Degrees) , LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

LT3799 Ad EDN.indd 1 4/14/11 10:53 AM designreaderSideas SOLVe deSIGN PrOBLeMS

CMOS gate makes long-duration DIs Inside timers using RC components 44 Microcontroller drives piezoelectric buzzer at high voltage Raju Baddi, Tata Institute of Fundamental Research, Pune, India 44 Circuit simultaneously The CD4011 CMOS NAND sufficiently below its switching thresh- delivers square and square root gate has a typical input current of old to maintain its high output state. of two input voltages ↘10 pA at room temperature. You can Momentarily closing and then releasing 47 Conversion circuit handles charge a capacitor connected to the S1 starts the timed period by discharging binary or BCD gate input with currents on the order of C1. This action drives the gate output hundreds of picoamperes and neglect low and ensures that Q is biased off, 3 ▶To see and comment on all the influence of the gate-input current which allows Q and Q to slowly charge 1 2 of EDN’s Design Ideas, visit on the charging time of the capacitor. C through the constant-current action. 1 www.edn.com/designideas. You normally need large-value resistors The power-supply current draw of the to limit currents to this low level. These gate increases somewhat as its input resistors are not commonly available. voltage pulls away from the 5V rail. Linearity with changes in R1 is You can instead use a transistor as a When the C1 charge reaches the gate- impossible due to variations in the current attenuator, despite its more switching threshold of approximately transistor’s current gain. The built and usual amplifying nature. 2.5V, the gate output begins to rise, turn- tested circuit does exhibit linearity with

The circuit in Figure 1 uses one ing on Q3. This action increases the cur- the value of timing capacitor C1, which CD4011 package containing four rent through Q1 and Q2, resulting in satu- you can choose experimentally for the NAND gates, which you can use to ration of Q2 and a faster charging of C1. required time. Once you determine a build four independent long-duration This positive feedback provides the neces- time for a short interval, such as that for timers. Note, however, that temperature sary hysteresis to complete the charging a 10- or a 100-nF capacitor, you can use variations and component parameters of C1 and return the gate output high. this knowledge to scale to longer tim- affect the timing, a situation ing. In the tested circuit, with 5V that may be acceptable if you are R1 set to 1 MΩ, a C1 value of 10 not concerned about accurate nF results in a time of 10 sec; a timing and need only a simple + C1 value of 100 nF increases the 100 μF circuit without large-value elec- R3 S time to 100 sec. C 1 START trolytic capacitors and resistors. 1M 1 Editor’s notes: Constructing

The series-connected diode R R6 a low-current circuit is chal- R2 4 100 voltage drops of D and D bias 10k TO 1k lenging. Some types of PCB- 1 2 Q 47k 2 current source Q1. The resulting soldering flux can become con- voltage across R is a Q base- BC549 ductive, wreaking havoc with 1 1 CD4011 G1 to-emitter-voltage junction drop TIMER what should be a tiny current. less and sets the Q collector cur- Consider “open-air” connec- 1 Q rent, which is also the Q emitter 1 tion of the Q -emitter collector 2 D BC549 R 1 1 5 C2 current. The resulting Q2 base 1N4148 1M and the Q2-emitter base leads to C 100 nF current is its emitter current 3 remove them from the board. 100 nF D 2 R1 Q3 divided by its current gain and 1N4148 Transistor-leakage currents 10M BC549 charges timing capacitor C1. and current gains vary widely Before the start of the timed from device to device and with NOTE: SEE TEXT REGARDING VALUE OF C . period, the gate output is high, 1 temperature. This variation can biasing on Q and Q , allowing drastically affect the expected 3 1 Figure 1 A constant-current source and current divider C to charge through the base- low-level current and capaci- 1 reduce the timing capacitor current to a low level to in- emitter junction of Q . This tor charge time. Although the 2 crease the charging time. action holds the gate input CD4011’s typical input current

[www.edn.com ] March 1, 2012 | EDN 43

EDN120301DI5223 Fig 1.eps DIANE designideas

is 10 pA at room temperature, it could might be necessary to hand-select tran- must remain in their linear region as set

be as high as 100 nA and increase to sistors and CD4011 inputs or devices to by the value of the Q2 collector resistor. 1 μA at high temperature. Likewise, overcome this problem. Also, remember Timing capacitor C1 should have the transistor collector-to-base leakage to tie any other unused CD4011-gate a high-quality, low-leakage dielectric, could be a maximum of 15 nA at room inputs to ground or 5V to avoid float- such as polyester; check the leakage temperature and 125 μA at high tem- ing-input problems. specifications of the size and type you

perature, and it approximately doubles Do not set R1 so low that Q1 or Q2 intend to use for suitability with the for every 10°C rise in temperature. It saturates during the timed period; they low-level current.EDN

Microcontroller drives piezoelectric buzzer at high voltage Mehmet Efe Ozbek, PhD, Atilim University, Ankara, Turkey

Piezoelectric buzzers find wide use switching the P-channel transistors, ration. The operation is as follows: The

in embedded systems for audible- however. microcontroller turns Q2 on and Q4 off ↘signal generation. You can drive a piezo- The circuit in Figure 1 solves the by applying high- and low-logic-level electric element directly from a micro- problem using a cross-coupled configu- voltages to I/O Pin 1 and I/O Pin 2, controller’s I/O pins, but the respectively. The voltage on VDD VDD maximum voltage rating and 15V 15V Node A goes low, turning on loudness of a piezoelectric Q3. Node B is now 15V, which buzzer are typically several is sufficient to keep Q1 off. The times larger than the voltage voltage on the piezoelectric Q Q an I/O pin supplies. Using four 1 3 buzzer is 15V. The microcon- enhancement-mode MOSFETs troller then toggles I/O Pin 1 AB that connect in an H-bridge and I/O Pin 2, resulting in a configuration, the microcon- piezoelectric voltage of −15V troller can drive the buzzer at a PIEZOELECTRIC for an effective 30V p-p. These high alternating voltage. The BUZZER cycles are repeated to gener- Q2 Q4 gate terminals of the N-channel I/O PIN 1 I/O PIN 2 ate an alternating voltage with transistors in the lower arms of the desired frequency. By using the bridge can connect directly MOSFETs with proper voltage to the microcontroller’s I/O ratings, you can use higher sup- pins. The voltage level on the Figure 1 This cross-coupled configuration enables you to ply voltages that the piezoelec- drive a piezoelectric buzzer from a microcontroller’s I/O pins. I/O pins is insufficient for tric element can tolerate.EDN

Circuit simultaneously delivers square tors CS1 and CS2; these voltages appear at VOUTX and VOUTY through unity-gain and square root of two input voltages amplifiers IC and IC . 2A 2B Marián Štofka, Slovak University of Technology, Bratislava, Slovakia Signals VOUTL and VOUTQ from the linear and quadratic pulse generator are

This Design Idea requires inputs edge trigger, Q is high and, through IC8, at 0V during idle, holding comparator from the circuit in a previous holds switches S and S of IC in the outputs IC and IC low. A rising trig- ↘ 2 3 1 4 5 Design Idea (Reference 1). IC1 and IC3 open position. ger edge at the clock signal begins the are ADG5213 quad switches with indi- Q is low, and, through IC7’s Reset ramp generation of VOUTL and VOUTQ. vidual logic-level control inputs (Figure high closes IC1’s S1 and S4, discharg- The Q and IC8 outputs fall low, closing EDN120301DI5270 Fig 1.eps DIANE 1 and Reference 2). With a high input, ing CT2 and CT4 and zeroing the input IC1’s S2 and S3 and ensuring that Track switches S2 and S3 are open, and switch- voltage to unity-gain amplifiers IC2D 2 remains low. Q rises and forces Reset es S1 and S4 are closed. The switches and IC2C. Q low also sets Track 2 low low through IC7, opening S1 and S4 of toggle to opposite states with their con- through IC6 and holds IC3’s S1 and S4 in IC1 and allowing CT2 to follow the ris- trol inputs low. The circuit is in the idle the open position. The circuit retains ing VOUTQ and CT4 to follow the rising pretriggered condition. During the ini- any sampled voltages from a previous VOUTL. tial idle condition before a clock rising- operation in sample-and-hold capaci- When linear ramp VOUTL rises to

44 EDN | March 1, 2012 [www.edn.com ] Navigate to the Future Maxim speeds you past integration challenges on the road ahead

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© 2012 Maxim Integrated Products, Inc. All rights reserved. Innovation Delivered, Maxim, and the Maxim logo are trademarks or registered trademarks of Maxim Integrated Products, Inc., in the United States and other jurisdictions throughout the world. All other company names may be trade names or trademarks of their respective owners. designideas

analog input VX, IC4’s output rises and, ing the sampled voltages on CT2 and CT4 for the next trigger. VOUTX is the squared through IC8, Track 1L opens S2 of IC1 to transfer to CS1 and CS2 through unity- voltage of input VX, and VOUTY is the and allows CT2 to hold the present level gain amplifiers IC2D and IC2C. Unity-gain square root of the voltage of input VY. of VOUTQ. In a similar manner, when qua- amplifiers IC2A and IC2B present the CS1 You can view the equations at www.edn. EDN dratic ramp VOUTQ rises to analog input and CS2 voltages at VOUTX and VOUTY. com/120301dia. VY, IC5’s output rises and, through IC8, When Track 2 returns low, IC3’s S1 and Track 1Q opens IC1’s S3 and allows CT4 S4 open, and the sampled voltages on CS1 RefeR ences 1 to hold VOUTL’s present level. The pulse and CS2 are retained. Štofka, Marián, “Positive edges trig- generator terminates when the ramps The fall of Q triggers IC7 to produce ger parabolic timebase generator,” reach 5V. The ramps then fall back to a 50-μsec delayed rise on Reset, which EDN, July 28, 2011, pg 51, http://bit.ly/

0V, Q returns high, and Q returns low. RD2 and CD2 time to occur after Track 2 yYvu3F. 2 The rise of Q immediately triggers IC6 has returned low and the sampled volt- “ADG5212/ADG5213 High Voltage to generate a high pulse of approximately ages are safely captured on CS1 and CS2. Latch-up Proof, Quad SPST Switch- 20 μsec on Track 2 based on RD1 and CD1. Reset’s high state closes IC1’s S1 and S4, es,” Analog Devices, 2011, http://bit.ly/ This action closes IC3’s S1 and S4, allow- discharging CT2 and CT4 in preparation w6XTO3.

5V 15V IN2 IN3

S2 S3

LINEAR AND 15V VOUTL IN2 IN3 QUADRATIC D2 D3 CLOCK PARABOLIC IC VOUTQ S2 S3 3 PULSE S ADG5213 S GENERATOR 1 4 330 330 Q Q

D2 D3 CS1 D1 D4 C C IC1 R 1 nF S2 T2 C T1 1 nF 1 nF ADG5213 T4 1k IN IN S1 S4 1 nF 1 4 GND –15V

D1 D4

IN IN RT2 1 4 1k GND –15V − 15V − IC2D IC2C + + 5V TRACK 1L ADA4062-4 330 TRACK 1Q + + V 4 6 X − 5 IC2A IC2B 1 IC4 3 − –15V − + 2 ADCMP608 RESET 5V

330 V 4 6 IC8 Y − 5 1 SN74AHC32 V IC5 OUTX 3 + ADCMP608 2 OUTPUTS GROUND UNUSED INPUTS VOUTY

R 5V D1 TRACK 2 20k

IC6

CD1 SN74AHC1G08 15V 1 nF –15V 5V 100 nF RD2 20k 5V 100 nF IC7 100 nF SN74AHC1G02 CD2 2.4 nF

Figure 1 With this circuit, you can find the square at Channel X and the square root at Channel Y for any positive dc or slowly varying voltages of 0 to 5V.

46 EDN | March 1, 2012 [www.edn.com ]

EDN120301DI5205 Fig 1.eps DIANE designideas CLASSICS Originally published in the April 5, 1979, issue of EDN Want to see more Conversion circuit handles of the binary or BCD classics? Revisit 50 of the R Srinivasan, R Ramesh, and DK Murthi, best Design Ideas National Aeronautical Lab, Bangalore, India from the Golden Age of electrical Systems requiring arithmetic oper- For applications not requiring fast con- engineering. ations on data usually perform version, a single circuit that can perform ↘those operations in binary form. As a both conversions proves adequate. One http://bit.ly/DesignIdeasClassics result, they must convert the data to BCD such circuit (Figure 1) utilizes up/down form for display purposes. Address- counters to obtain the desired results. To counts up, and when the binary coun- selection information from digit switches, perform binary-to-BCD conversion, preset ter reaches zero, the BCD counter holds. on the other hand, must be converted to the binary value in the binary counter and For BCD-to-binary operation, the BCD binary form for use in memory-addressing clear the BCD counter. The binary count- counter counts down from the BCD value operations. er counts down while the BCD counter while the binary counter counts up.EDN

Figure 1 Separate binary and BCD up/down counters permit both binary-to-BCD and BCD-to-binary conversion in one circuit.

[www.edn.com ] March 1, 2012 | EDN 47 productroundup

TesT and measuremenT

more than 10 Mbytes/sec, and an integrated lithium-polymer battery with 8000 or 16,000 mAhr provides as much as three or six hours of runtime, respectively. The analyzer features modular con- struction for fast extension and custom- ization of the front end and also includes a directional-tracking and EMC antenna, an aluminum carrying case, a battery charger, a power supply, and an international adapter set. The included MCS real-time spectrum-analyzer software runs with any operating system, including Mac OS, Linux, and Windows, and provides real-time remote control with any of the vendor’s Spectran spectrum analyzers. Agilent E5515E wireless-communication Pricing starts at €2998 (approximately test set accelerates design $3950) for the 10-MHz to 2.5-GHz The E5515E 8960 series 10 wireless-communication test set supports GSM, Spectran HF-8025 V5. GPRS, EGPRS, E-EDGE, WCDMA, CDMA2000, 1×EVDO, EHRPD, Aaronia AG, www.aaronia.com TDSCDMA,↘ TDHSDPA, TDHSUPA, IS-95, TIA/EIA-136, and AMPS wireless- device testing. The device has a 292- to 2700-MHz frequency range, including all commercial 3GPP and 3GPP2 frequency bands. Other features include a −110 to Pico 4262 scope −13-dBm output-level range with modulation, a VSWR of less than 1.2-to-1 at includes arbitrary- 400 to 2000 MHz, and less than ±1-dB channel-power measurement accuracy. The Agilent E5515E mainframe is priced at $59,200, including all hardware options; waveform generator software options are available at additional cost. The two-channel, 16-bit Pico- Agilent Technologies, www.agilent.com Scope 4262 has a built-in low- ↘distortion signal generator. With a 5-MHz bandwidth, it can analyze audio, ultra- Planar Caban R54 vec- Aaronia spectrum sonic, and vibration signals; characterize tor reflectometer meas- analyzer offers real-time noise in switched-mode power supplies; measure distor- ures S11 parameters data streaming tion; and perform pre- The Caban R54 vector reflec- Aaronia’s Spectran V5 series of cision-measurement

tometer measures S11 parameters spectrum analyzers, scheduled to tasks. The scope over↘ an 85-MHz to 4.2-GHz frequency ↘start shipping in 2012, offers extremely includes a function range. The device measures magnitude low-noise signal processing—up to 170 generator and an and phase of reflection coefficient, dBm/Hz—as well as a 200-MHz real-time arbitrary-waveform genera- cable loss, and distance to fault. Per- bandwidth. Each spectrum analyzer pro- tor that has a sweep function to enable point measurement time is 200 μsec, vides real-time streaming and a real-time frequency-response analysis. It also offers and frequency-setting resolution is as remote control for GSM, WLAN, and mask-limit testing, math and reference high as 10 Hz. The USB-powered USB and has a TFT display with channels, advanced triggering, serial device measures 117×39×19 mm, 800×480-pixel resolution. The analyzer decoding, automatic measurements, and weighs 0.25 kg, and sells for $2995. utilizes an integrated 3-D motion sensor a color-persistance display. In spectrum- Planar LLC, www.planar.chel.ru and a 3-D magnetic-field sensor. It uses analyzer mode, the scope provides a menu 480-kbps USB 2.0 and has a USB slave of 11 automatic frequency-domain meas- interface to connect devices such as urements, such as IMD, THD, SFDR, and GSM, WLAN, printer, and memory. A SNR. The PicoScope 4262 connects to micro-SD slot supports SDHC cards with any Windows XP, Vista, or Windows 7

48 EDN | March 1, 2012 [www.edn.com ] computer with a USB 2.0 port. The unit tion, the units cost $1999 to $4699. sells for £750 (approximately $1200). Rigol Technologies Inc, Pico Technology, www.picotech.com www.rigolna.com

Tektronix TPI4000 A DVERTISER I NDEx analyzer lets users test Rigol’s DS4000 oscil- multiple serial protocols loscopes have 100- to Company Page Agilent Technologies C-3 The TPI4000 protocol-analyzer 500-MHz bandwidth Centellax 8 series allows users to perform Coilcraft 3 multiple↘ test functions and to look at a The general-purpose DS4000 Digi-Key Corp C-1, C-2 variety of protocols, such as Ethernet, series of digital oscilloscopes fea- Emulation Technology 23 Fibre Channel, and common public- ↘tures bandwidths of 100, 200, 350, or IMS 2012 19 radio interface. A user-edit- 500 MHz; two or four analog channels; International Rectifier C-4 able database allows users to a real-time sampling rate of 4G samples/ Linear Technology 34A–34B, 42 define custom protocols using sec; a memory depth of 140 million Maxim Integrated Products 45 the optional protocol-editor points; and a waveform-acquisition rate Mill-Max Manufacturing 11 tool. The series includes the of 110,000 waveforms/sec. The vendor’s Mouser Electronics 4, 6 portable TPI4202, which UltraVision technology and a 9-in. National Instruments 13 has a built-in monitor WVGA display offer an intensity-grad- Pico Electronics Inc 7, 39 and keyboard and sup- ing, real-time waveform recording. Rohde & Schwarz GmbH ports as many as eight ports, and the Waveform visualization and replay and & Co KG 29 4U-rack-mount TPI4208, which sup- customizable real-time hardware filters UBM EDN 37, 49 ports as many as 32 ports. Pricing for a are available. Targeting applications in Vicor Corp 15 complete system starts at $40,000. communications, defense, aerospace, EDN provides this index as an additional service. The 82389_EDN_halfhoriz:Layout 1 10/26/11 12:13 PM Page 1 publisher assumes no liability for errors or omissions. Tektronix, www.tektronix.com industrial electronics, R&D, and educa- Customize Your Reprints!

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[www.edn.com ] March 1, 2012 | EDN 49 Tales from The Cube Dan Dull • noVo engineering

code. Everything seemed to be going Printer parking brake well. All of the major functional blocks appeared to be working correctly. The firmware team started working on the project, and, once the team had written enough firmware to make the printer function, it was apparent that this microprocessor appeared significantly slower than the old one. It should have been at least 10 times faster based on clock rate alone, but it also had caches and a DMA controller to further speed things up. The board had copi- ous amounts of high-speed memory, and the FPGA had logic to offload some of the data-processing tasks from the main microprocessor. Something was horribly wrong, and, because I had designed the system, I was the only one who could fix it. The user’s manual for the microprocessor comprised two books with more than 1000 pages each. I grabbed both books and started reading. This incident occurred before PDF files were common, so searching was a manual process. While reading through the debugging bout 15 years ago, I was working for a wide-format- section, I came across an interesting ink-jet-printer company in the San Diego area. The feature. This feature set the level of printers we designed could print on rolls of paper detail about the microprocessor’s core that were 5 feet wide and several hundred feet long. and instruction pipeline that is reported to an external debugger. Needless to say, we needed to send an enormous As I read more about this debug- amount of data to these printers to keep the print ging feature, I discovered that it headsA moving and the paper advancing. One of the key product affects the microprocessor’s perform- requirements was throughput, specified in square feet per hour. ance. If you want more detail about Ideally, the print head’s firing rate governed the throughput. The what is happening internally, the core rest of the system had to ensure that the print heads were always slows down. I checked to see what the default setting was and was pleased to squirting ink onto the paper. If the print heads were not squirting, discover that maximum detail, slowest we were wasting time. Our customers tended to get upset when core was the reset value. I modified the their expensive printer paused and hesitated while printing post- firmware to turn this feature completely ers because they charge their customers by the square foot. The off, and the microprocessor started run- longer it takes to print the poster, the less money they make. ning at full speed. The printer ran at full speed with no hesitation. My co- My primary jobs were to design the was occasionally making the printer workers and I then decided to call this controller board for these printers, hesitate after each pass of the print feature the parking brake.EDN design the FPGA that was on the con- heads and would definitely not be suf- troller board, and write the low-level ficient for the next-generation product. Dan Dull currently works as an electrical firmware that interfaced with the hard- After doing some research and anal- engineer for Novo Engineering, a product- ware. Each new product we developed ysis, I found a microprocessor that I felt development company in Vista, CA. was roughly twice as fast as the previous could handle our processing needs for product, so I constantly had to find new at least several more future products. I This Tale is a runner-up in EDN’s Tales from the Cube: Tell Us Your Tale contest, sponsored by ways to process the image data faster. I designed a controller board using this Tektronix. Read the other finalists’ entries at http:// started evaluating new microprocessors part, designed the FPGA logic, and bit.ly/Talesfinal_EDN. because the one we were currently using wrote the device drivers and some test Daniel Vasconcellos

50 EDN | MARCH 1, 2012 [www.edn.com ] “I need a function generator that generates conﬁ dence, too.”

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Compact, Powerful CCM PFC from 75W to 4kW+

PFC Control ICs The µPFC family of controller ICs radically alters traditional thinking about PFC solutions. The Part Number Description IR115x uses a “One-Cycle Control integrator with Fixed 66KHz switching frequency with brownout protection IR1152 reset” technique to deliver the high performance and dual OVP protection of Continuous Conduction Mode (CCM) PFC Fixed 22KHz switching frequency with brownout protection IR1153 with the simplicity and low component count of and programmable OVP protection Discontinuous Current Mode (DCM).

IR1155 Programmable switching frequency and programmable OVP protection Features • Small, easy, powerful solution 600 V PFC IGBTs for High Power Systems • Fast time to market • Enables compliance with energy I @ 100C V (max) Part Number Circuit c CE(on) Package standards (1W, Blue Angel, Energy Star) (A) (V) • No AC line voltage sense required IRGB20B60PD1 22 2.35 TO-220AB • 0.999 power factor IRGP20B60PD 22 2.35 TO-247AC Co-Pack • Switching frequency of 22kHz, 66kHz or IRGP35B60PD 35 2.15 TO-247AC programmable value available IRGP50B60PD1 45 2.35 TO-247AC • Average current mode control

IRG4(B/IB)C20W 6.5 2.6 TO-220AB; TO-220 FullPak • Cycle by cycle peak current limit system protection IRG4(B/IB/P)C30W 12 2.7 TO-220AB; TO-220 FullPak; TO-247AC

IRG4(B/P)C40W 20 2.5 TO-262; TO-220AB; TO-247AC

IRG4PC50W Discrete 27 2.3 TO-247AC

IRGP4069 35 1.85 TO-247AC

IRGP4063 48 2.14 TO-247AC

IRGP4066 90 2.1 TO-247AC

for more information call 1.800.981.8699 or visit us at www.irf.com THE POWER MANAGEMENT LEADER

11251AD_uPFC_EDN_r1.indd 1 8/12/11 1:31 PM