UNITED STATES INTERNATIONAL TRADE COMMISSION Washington, D.C

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UNITED STATES INTERNATIONAL TRADE COMMISSION Washington, D.C.

Before the Honorable E. James Gildea Administrative Law Judge

In the Matter of

CERTAIN CONSUMER ELECTRONICS WITH Inv. No. 337-TA-884 DISPLAY AND PROCESSING CAPABILITIES

COMPLAINANT GRAPHICS PROPERTIES HOLDINGS, INC. ID OF EXPERTS

Pursuant to the Procedural Schedule (Order No. 13) and the Administrative Law Judge’s

Ground Rule 5, Complainant Graphics Properties Holdings, Inc. (“GPH”) respectfully submits

its identification of expert witnesses, their curriculum vitae and descriptions of their respective

expertise. GPH reserves the right to supplement or amend this identification of expert witnesses

as appropriate the parties.

A. Dr. Glenn Reinman

Dr. Glenn Reinman is an expert in software, computer architecture, microprocessors, and

graphics processors. Dr. Reinman’s CV is attached hereto as Exhibit A.

B. Dr. William Mangione-Smith

Dr. Bill Mangione-Smith is an expert in software, computer architecture, microprocessors,

and graphics processors. Dr. Mangione-Smith’s CV is attached hereto as Exhibit B.

C. Dr. John Hart

Dr. John Hart is in expert in hardware and software related to computer graphics, animation,

and graphics processors. Dr. Hart’s CV is attached hereto as Exhibit C.

D. Dr. Manish Bhardwaj

Dr. Manish Bhardwaj is an expert in electrical engineering, including semiconductors, integrated circuit layout and design. Dr. Bhardwaj’s CV is attached hereto as Exhibit D.

E. Tamer Rizk

Mr. Rizk is an expert in software development, computer architecture, electrical engineering, and computer engineering. Mr. Rizk’s CV is attached hereto as Exhibit E.

F. Dr. Tom Yeh

Dr. Yeh is an expert in software, computer architecture, and microprocessors. Dr. Yeh’s CV is attached hereto as Exhibit F.

G. Dr. Milos Prulovic

Dr. Prulovic is an expert in software, computer architecture, system design, electrical engineering, and microprocessors. Dr. Prulovic’s CV is attached hereto as Exhibit G.

H. Dr. Jonathan Babb

Dr. Babb is an expert in electrical engineering, computer science, computer architecture, semiconductors, and microprocessors. Dr. Babb’s CV is attached hereto as Exhibit H.

In addition to the expert witnesses identified above, GPH reserves the right to offer opinion testimony from lay witnesses that it calls at the hearing in this Investigation as to matters within the perception of the lay witness. GPH further reserves the right to elicit testimony that may be deemed expert testimony from lay witnesses who have the requisite scientific, technical, or other specialized knowledge to provide that testimony and hereby designates those lay witnesses with regard to such testimony.

2 Dated: September 3, 2013 Respectfully submitted,

/s/ Michael T. Renaud Michael T. Renaud James M. Wodarski Michael J. McNamara Jack C. Schecter Andrew H. DeVoogd Michael C. Newman Daniel B. Weinger MINTZ, LEVIN, COHN, FERRIS, GLOVSKY AND POPEO, P.C. One Financial Center Boston, MA 02110 Phone: (617) 542-6000 Fax: (617) 542-2241

Counsel for Complainant Graphics Properties Holdings, Inc.

21271835v.1

3 Exhibit A Glenn D Reinman UCLA Computer Science Department [email protected] Research Interests Computer architecture, augmented reality, parallel programming, compiler optimizations, graphics processing, and systems. Education ● University of California - San Diego (San Diego, CA) ○ Doctor of Philosophy degree in Computer Science, June 2001 Advisor: Professor Brad Calder. ○ Master of Science degree in Computer Science, March 1999. ● Massachusetts Institute of Technology (Cambridge, MA) ○ Bachelor of Science degree in Computer Science and Engineering, June 1996. Recent Research Highlights ● Accelerator-Rich Chip Multiprocessors (CMPs) – energy-efficient high-performance SoC platforms that features both application-specific accelerators and heterogeneous cores. ● RF Interconnect – a promising alternative interconnect for both on-chip and off-chip communication for future CMPs. It can be adaptively tuned to the communication needs of an individual application. We have also explored wireless RF interconnect and RF-integrated memory technology. ● Mobile Augmented Reality – sensing and guidance framework for real-time critical situations. We are leveraging our work on automated planning engines and our work to accelerate computer vision as the basis for this line of research. ● Real-Time Physics – we have proposed a novel physics processor and explored dynamically trading accuracy for improved performance while maintaining believability. ● Dynamically Leveraging Statically Partitioned Resources – CMPs statically partition resources for scalability and performance/energy efficiency. We look at dynamically composing these static resources into more powerful components. Work Experience ● University of California – Los Angeles (Los Angeles, CA) ○ Assistant Professor (2001-2007) ○ Associate Professor (2007-Present) ● Expert Witness Experience ○ Served as an expert witness in fourteen separate instances. Have been deposed, written detailed expert reports, constructed patent claim charts, deciphered decades-old designs from schematics and microcode, uncovered prior work to anticipate claims, profiled a variety of software and hardware systems, architecturally simulated patented designs to demonstrate claim validity, analyzed and traced a variety of source code (both hardware and software), and worked closely with lawyers to educate them on technical details. ● University of California - San Diego, Research Assistant (San Diego, CA) ○ Implemented a profile-based approach to classifying loads for memory renaming, value prediction, and dependence prediction using SimpleScalar and ATOM. Created an aggressive fetch unit using a two-level branch prediction structure called an FTB. Worked with SimpleScalar to implement a hybrid load prediction mechanism, combining renaming, value prediction, address prediction, and dependence prediction. Explored importance of confidence in value prediction. Used C and C++. (Fall 1997-Spring 2001) ○ Implemented a contention resolution scheme for embarassingly parallel applications (such as the DOT project at the San Diego Supercomputing Center). Worked in MPICH and C. (Spring 1997-Fall 1997) ● COMPAQ (now HP) - Western Research Lab, Summer Internship 1999 (Palo Alto, CA) Expanded the CACTI cache compiler (CACTI 2.0). Enhancements include fully associative cache model, power modeling, multiple port models, transistor tuning, and tag path balancing. ● Intel Corporation - Microprocessor Research Lab, Summer Intern 1998 (Hillsboro, OR) Studied the viability of caching state from the branch predictor, TLB, and BTB in the second level data cache. Modified SimpleScalar to use ITR traces for Win95 applications for initial predictability experiments. Used out- of-order simulation with SimpleScalar to determine the effectiveness of this technique. Teaching Experience ● University of California – Los Angeles, Assistant Professor (Los Angeles, CA) ○ Computer Systems Architecture (CSM151B - Upper Division Undergraduate class) - I have taught this class since Winter 2003, covering instruction set architecture design, ALU design, processor datapath and control design, pipelining, caches, virtual memory, IO devices, multithreading, multiprocessors, and multicore architectures. ○ Advanced Topics in Microprocessor Design (CS259 - Graduate class) - I introduced this class in Spring 2002, covering cutting edge research in general purpose microarchitecture. The processor pipeline is explored in detail, with attention to performance, complexity, cycle time, power, and area. Recent real world architectures are used for illustration, along with on-going research efforts in topics that includes multicore processors, NoC design, cache coherence mechanisms, GPU design and programming, branch prediction, load speculation, simultaneous multithreading, cache design/prefetching, register file design, and various techniques to combat processor scaling trends. Introduction to cycle-accurate microprocessor simulation. Lab intensive class designed to give students practical experience with simulation techniques and tricks. On- going work in architecture and compilers is discussed during class and then integrated into lab assignments using the simulation infrastructure. ○ Microprocessor Simulation (CS259 - Graduate class) - I introduced this class in Winter 2003, providing a practical application of my Advanced Topics class students make use of execution-driven cycle-accurate processor simulators. ○ Parallel and Distributed Systems (CS133 - Upper Division Undergraduate class) - I have completely reorganized this class in Winter 2007 to focus on programming in OpenMP, POSIX threads, MPI, and CUDA for both shared and distributed memory multiprocessors. The class also has a component on next generation chip multiprocessors, including design tradeoffs and un-core optimizations. ○ Computer Organization (CS33 - Lower Division Undergraduate class) - I completely reorganized this class in Fall 2009 to make it a gateway systems class using low-level C programming and x86 assembly. It is a practical class, with several labs including an introduction to parallel programming with CUDA as the demonstration vehicle. ○ Computer Science Seminar Series (CS201 - Graduate class) ● University of California - San Diego, Teaching Assistant (San Diego, CA) ○ Teaching Assistant - taught discussion sections for classes on data structures, artificial intelligence, and compilers. Recipient of 1996/97 TA Excellence Award. Publications Refereed Conference and Workshop Publications: 1. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Hui Huang, and Glenn Reinman, "Composable Accelerator-rich Microprocessor Enhanced for Adaptivity and Longevity", International Symposium on Low Power Electronics and Design (ISLPED), Sep 2013 2. Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewpu Jou, Glenn Reinman, Jason Cong, and Mau-Chung Frank Chang. A 60GHz On-Chip RF-Interconnect with λ/4 Coupler for 5Gbps Bi- Directional Communication and Multi-Drop Arbitration. IEEE Custom Integrated Circuits Conference (CICC), Sep 2012 3. Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar and Glenn Reinman. Static and Dynamic Co-Optimizations for Blocks Mapping in Hybrid Caches. International Symposium on Low Power Electronics and Design (ISLPED), Jul/Aug 2012. 4. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian and Glenn Reinman. CHARM: A Composable Heterogeneous Accelerator-Rich Microprocessor. International Symposium on Low Power Electronics and Design (ISLPED), Jul/Aug 2012. 5. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu and Glenn Reinman. BiN: A Buffer- in-NUCA Scheme for Accelerator-Rich CMPs. International Symposium on Low Power Electronics and Design (ISLPED), Jul/Aug 2012. 6. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, and Glenn Reinman. Accelerator-Rich Architecture for Power-Constrained CMPs. Dark Silicon Workshop (DaSi - held in conjunction with ISCA), Jun 2012 7. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, and Glenn Reinman. Architecture Support for Accelerator-Rich CMPs. Design Automation Conference (DAC), Jun 2012 8. Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak and Glenn Reinman. Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design. Conference on Design, Automation, and Test in Europe (DATE), Mar 2012. 9. Yangkyo Kim, Gyungsu Byun, Adrian Tang, Jason Cong, Glenn Reinman, and M. F. Chang. An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simulataneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression. International Solid-State Circuits Conference (ISSCC), Feb 2012. 10. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, and Marco Vitanza. Compilation and Architecture Support for Customized Vector Instruction Extension. Asia and South Pacific Design Automation Conference (ASP-DAC), Jan/Feb 2012. 11. Mubbasir Kapadia, Matthew Wang, Glenn Reinman, and Petros Faloutsos. Improved Benchmarking for Crowd Simulations. Motion In Games (MIG), Nov 2011 12. Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, and Frank Chang. The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System. IEEE International Conference on Computer Design (ICCD), Oct 2011. 13. Yu-Ting Chen, Jason Cong and Glenn Reinman. HC-Sim: A Fast and Exact L1 Cache Simulator with Scratchpad Memory Co-simulation Support. International Conference on Hardware/Software Co-Design and System Synthesis (CODES+ISSS), Oct 2011. 14. Beayna Grigorian, Marco Vitanza, Jason Cong, and Glenn Reinman. Accelerating Vision and Navigation Applications on a Customizable Platform. International Conference on Application-specific Systems, Architectures and Processors (ASAP), Sep 2011. 15. Mubbasir Kapadia, Matthew Wang, Shawn Singh, Glenn Reinman, and Petros Faloutsos. Scenario Space: Characterizing Coverage, Quality, and Failure of Steering Algorithms. Symposium on Computer Animation (SCA), Aug 2011. 16. Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman and Yi Zou. An Energy- Efficient Adaptive Hybrid Cache. International Symposium on Low Power Electronics and Design (ISLPED), Aug 2011. 17. Mubbasir Kapadia, Shawn Singh, Glenn Reinman, and Petros Faloutsos. Multi-Actor Planning for Directable Simulations. Workshop on Digital Media and Digital Content Management, May 2011. 18. Gyungsu Byun, Yangkyo Kim, Jongsun Kim, Sai-Wang Tam, Jason Cong, Glenn Reinman, and M. F. Chang. An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling. International Solid-State Circuits Conference (ISSCC), Feb 2011. 19. Jason Cong, Mohammadali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman and Yi Zou. AXR- CMP: Architecture Support in Accelerator-Rich CMPs. Workshop on SoC Architecture, Accelerators and Workloads (SAW-2), Feb 2011. 20. Shawn Singh, Mubbasir Kapadia, Billy Hewlett, Glenn Reinman and Petros Faloutsos. A Modular Framework for Adaptive Agent-Based Steering. Symposium on Interactive 3D Graphics and Games (I3D), Feb 2011. 21. Zoran Budimlic, Alex Bui, Jason Cong, Glenn Reinman, Vivek Sarkar. Modeling and Mapping for Customizable Domain-Specific Computing. Workshop on Concurrency for the Application Programmer (CAP), co-located with SPLASH 2010, Oct 2010. 22. Jason Cong, Chunyue Liu, and Glenn Reinman. ACES: Application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. Design Automation Conference (DAC), Jun 2010. 23. Shawn Singh, Mubbasir Kapadia, Petros Faloutsos, and Glenn Reinman. On the Interface Between Steering and Animation for Autonomous Characters. Workshop on Crowd Simulation held in conjunction with the 23rd Annual Conference on Computer Animation and Social Agents, May 2010. 24. Shawn Singh, Mubbasir Kapadia, Glenn Reinman and Petros Faloutsos. An Open Framework for Developing, Evaluating, and Sharing Steering Algorithms. Motion In Games (MIG), Nov 2009. 25. Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang, and Jason Cong. A Scalable Micro Wireless Interconnect Structure for CMPs. International Conference on Mobile Computing and Networking, Sept 2009. 26. Mubbasir Kapadia, Shawn Singh, Brian Allen, Glenn Reinman, and Petros Faloutsos. An Interactive Framework for Specifying and Detecting Steering Behaviors. Symposium on Computer Animation (SCA), Aug 2009. 27. Jason Cong, M. Frank Chang, Glenn Reinman, and Sai-Wang Tam, Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communications, System Level Interconnect Prediction (SLIP 2009), July 2009. 28. M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, and Sai-Wang Tam. Power Reduction of CMP Communication Networks via RF-Interconnects. International Symposium on Microarchitecture (MICRO), Nov 2008. 29. Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, and Glenn Reinman. MC-Sim: An Efficient Simulation Tool for MPSoC Designs. International Conference on Computer-Aided Design (ICCAD), Nov 2008. 30. Shawn Singh, Mubbasir Kapadia, Mishali Naik, Petros Faloutsos, and Glenn Reinman. Watch Out! A Framework for Evaluating Steering Behaviors. Proceedings of Motion In Games (MIG), June 2008. 31. M. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, and Glenn Reinman. RF Interconnects for Communications On-Chip. International Symposium on Physical Design (ISPD), Apr 2008. 32. M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, and Sai-Wang Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. International Symposium on High-Performance Computer Architecture (HPCA), Feb 2008. BEST PAPER AWARD 33. Tom Yeh, Petros Faloutsos, Sanjay Patel, Milos Ercegovac, and Glenn Reinman. The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. International Symposium on Microarchitecture (MICRO), Dec 2007. 34. Yongxiang Liu, Yuchun Ma, Eren Kursun, Jason Cong, and Glenn Reinman. Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration. IEEE International Conference on Computer Design (ICCD), Oct 2007. 35. Yongxiang Liu, Yuchun Ma, Eren Kursun, Jason Cong, and Glenn Reinman. 3D Architecture Modeling and Exploration. VLSI/ULSI Multilevel Interconnection Conference, Sept 2007. 36. Tom Yeh, Petros Faloutsos, Sanjay Patel, and Glenn Reinman. ParallAX: An Architecture for Real-Time Physics. In 34th Annual International Symposium on Computer Architecture (ISCA), June 2007 37. Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, and Qian Zhou. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. 12th Asia and South Pacific Design Automation Conference (ASPDAC), Jan 2007. 38. Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, and Miodrag Potkonjak. Reducing Energy of DRAM/Flash Memory System by OS-Controlled Data Refresh. In International Symposium on Circuits and Systems (ISCAS), May 2007. 39. Anahita Shayesteh, Glenn Reinman, Norm Jouppi, Suleyman Sair, and Tim Sherwood. Improving the Performance and Power Efficiency of Shared Helpers in CMPs. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Oct 2006. 40. Vasily Moshnyaga, Hoa Vo, Glenn Reinman, and Miodrag Potkonjak. Handheld System Energy Reduction by OS-Driven Refresh. Power and Timing Modeling, Optimization, and Simulation (PATMOS), September 2006. 41. Tom Yeh, Petros Faloutsos, and Glenn Reinman. Enabling Real-Time Physics Simulation in Future Interactive Entertainment. ACM SIGGRAPH Video Game Symposium, Aug 2006. 42. Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, and Yan Zhang. An Automated Design Flow for 3D Microarchitecture Evaluation. 11th Asia and South Pacific Design Automation Conference (ASPDAC), Jan 2006. 43. Anahita Shayesteh, Eren Kursun, Tim Sherwood, Suleyman Sair, and Glenn Reinman. Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines. IEEE International Conference on Computer Design (ICCD), Oct 2005. 44. Yongxiang Liu, Gokhan Memik, and Glenn Reinman. Reducing the Energy of Speculative Instruction Schedulers. IEEE International Conference on Computer Design (ICCD), Oct 2005. 45. Tom Yeh and Glenn Reinman. Fast and Fair: Data-stream Quality of Service. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Sep 2005. 46. Jason Cong, Ashok Jagannathan, Glenn Reinman, and Yuval Tamir. Understanding The Energy Efficiency of SMT and CMP with Multi-clustering. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Aug 2005. 47. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, and Glenn Reinman. Tornado Warning: the Perils of Selective Replay in Multithreaded Processors. International Conference on Supercomputing (ICS), June 2005. 48. Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, and Zhiru Zhang. Instruction Set Extension with Shadow Registers for Configurable Processors. 13th ACM International Symposium on Field-Programmable Gate Arrays, Feb 2005. 49. Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, and Jason Cong. Microarchitecture Evaluation with Floorplanning and Interconnect Pipelining. Asia South Pacific Design Automation Conference (ASPDAC), Jan 2005. 50. Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, and Tim Sherwood. Low-Overhead Core Swapping for Thermal Management. Workshop on Power-Aware Computer Systems (PACS'04) held in conjunction with the 37th Annual International Symposium on Microarchitecture, December 2004. 51. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, and Glenn Reinman. The Calm Before the Storm: Reducing Replays in the Cyclone Scheduler. IBM T.J. Watson Conference on Interaction between Architecture, Circuits, and Compilers, Oct 2004. 52. Jason Cong, Ashok Jagannathan, Glenn Reinman, and Yuval Tamir. A Communication-Centric Approach to Instruction Steering for Future Clustered Processors. IBM T.J. Watson Conference on Interaction between Architecture, Circuits, and Compilers, Oct 2004. 53. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, and Glenn Reinman. Scaling the Issue Window with Look-Ahead Latency Prediction. International Conference on Supercomputing (ICS), June 2004. 54. Fang-Chung Chen, Foad Dabiri, Roozbeh Jafari, Eren Kursun, Vijay Raghunathan, Thomas Schoellhammer, Doug Sievers, Deborah Estrin, Glenn Reinman, Majid Sarrafzadeh, Mani Srivastava, Ben Wu, Yang Yang. Reconfigurable Fabric: An enabling technology for pervasive medical monitoring. Communication Networks and Distributed Systems Modeling and Simulation Conference, Jan 2004. 55. Jason Cong, Ashok Jagannathan, Glenn Reinman, and Michail Romesis. Microarchitecture Evaluation with Physical Planning. Design Automation Conference (DAC), 2003. 56. Gokhan Memik, Glenn Reinman, and William H. Mangione-Smith. Reducing Energy and Delay Using Efficient Victim Caches. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2003. 57. Gokhan Memik, Glenn Reinman, and William H. Mangione-Smith. Just Say No: Benefits of Early Cache Miss Determination. In the proceedings of the 9th IEEE/ACM International Symposium on High Performance Computer Architecture (HPCA), Feb. 2003. 58. Glenn Reinman, Brad Calder and Todd Austin. High Performance and Energy Efficient Serial Prefetch Architecture. In the proceedings of the 4th International Symposium on High Performance Computing, May 2002, (c) Springer-Verlag. 59. Glenn Reinman, Brad Calder, and Todd Austin. Fetch Directed Instruction Prefetching. In 32nd International Symposium on Microarchitecture (MICRO), November 1999. 60. Glenn Reinman, Brad Calder, Dean Tullsen, Gary Tyson, and Todd Austin. Classifying Load and Store Instructions for Memory Renaming. In ACM International Conference on Supercomputing (ICS), June 1999. 61. Glenn Reinman, Todd Austin, and Brad Calder. A Scalable Front-End Architecture for Fast Instruction Delivery. In 26th Annual International Symposium on Computer Architecture (ISCA), May 1999. 62. Brad Calder, Glenn Reinman, and Dean Tullsen. Selective Value Prediction. In 26th Annual International Symposium on Computer Architecture (ISCA), May 1999. 63. Glenn Reinman and Brad Calder. Predictive Techniques for Aggressive Load Speculation. In 31st Annual International Symposium on Microarchitecture (MICRO), December 1998. Refereed Journal Publications: 64. Chunhua Xiao, Frank Chang, Jason Cong, Michael Gill, Zhangqin Huang, Chunyue Liu, Glenn Reinman, Hao Wu. Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects. ACM Transactions on Architecture and Code Optimization (TACO), Jan 2013 65. Kanit Therdsteerasukdi, Gyung-Su Byun, Jeremy Ir, Glenn Reinman, Jason Cong, and M.F. Chang. Utilizing Radio Frequency Interconnect for a Many-DIMM DRAM System. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2012. 66. Mubbasir Kapadia, Shawn Singh, Wiliam Hewlett, Glenn Reinman, and Petros Faloutsos. Parallelized Egocentric Fields for Autonomous Navigation. The Visual Computer, 2012. 67. Yanghyo Kim, Sai-Wang Tam, Gyung-Su Byun, Hao Wu, Lan Nan, Glenn Reinman, Jason Cong, and Mau-Chung Frank Chang. Analysis of Non-Coherent ASK Modulation Based RF-Interconnect for Memory Interface. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Jun 2012. 68. Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, Frank Chang, and Glenn Reinman. Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System. ACM Transactions on Architecture and Code Optimization (TACO), Jan 2012. 69. Mubbasir Kapadia, Shawn Singh, Glenn Reinman, and Petros Faloutsos. A Behavior Authoring Framework for Multi-Actor Simulations. IEEE Computer Graphics and Applications: Special Issue on Digital Content Authoring, December 2011 70. Shawn Singh, Mubbasir Kapadia, Glenn Reinman and Petros Faloutsos. Footstep Navigation for Dynamic Crowds. Computer Animation and Virtual Worlds, April 2011. 71. Jason Cong, Vivek Sarkar, Glenn Reinman, and Alex Bui. Customizable Domain-Specific Computing. IEEE Design & Test, March/April 2011. 72. Tom Yeh, Glenn Reinman, Sanjay Patel, and Petros Faloutsos. Fool me twice: Exploring and exploiting error tolerance in physics-based animation. ACM Transactions on Graphics (TOG), December 2009. 73. Shawn Singh, Mubbasir Kapadia, Petros Faloutsos, and Glenn Reinman. SteerBench: A Benchmark Suite for Evaluating Steering Behaviors. Journal of Computer Animation and Virtual Worlds, Feb 2009. 74. Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, and Jason Cong. Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design. ACM Journal on Emerging Technologies in Computing Systems (JETC), Oct 2008. 75. Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, and Krzysztof Rutkowski. Accelerating Sequential Applications on CMPs Using Core Spilling. In IEEE Transactions on Parallel and Distributed Systems (TPDS), August 2007. 76. Glenn Reinman and Gruia Pitigoi-Aron. Trace Cache Miss Tolerance for Deeply Pipelined Superscalar Processors. In IEE Proceedings on Computers and Digital Techniques, September 2006. 77. Eren Kursun, Anahita Shayesteh, Suleyman Sair, Tim Sherwood, and Glenn Reinman. An Evaluation of Deeply Decoupled Cores. In the Journal of Instruction Level Parallelism (JILP), February 2006. 78. Anahita Shayesteh, Glenn Reinman, Norm Jouppi, Suleyman Sair, and Tim Sherwood. Dynamically Configurable Shared CMP Helper Engines for Improved Performance. In SIGARCH Computer Architecture News, November 2005. 79. Gokhan Memik, Glenn Reinman, and Bill Mangione-Smith. Precise Instruction Scheduling. In the Journal of Instruction Level Parallelism (JILP), January 2005. 80. Glenn Reinman. Using an Operand File to Save Energy and to Decouple Commit Resources. In the IEE Proceedings on Computers and Digital Techniques, Vol 152, Issue 5, September 2005. 81. Glenn Reinman and Brad Calder. Using a Serial Cache for Energy Efficient Instruction Fetching. In the Journal of Systems Architecture (JSA), 2004. 82. Brad Calder and Glenn Reinman. A Comparative Survey of Load Speculation Architectures. In the Journal of Instruction Level Parallelism (JILP), May 2000. 83. Glenn Reinman, Brad Calder, and Todd Austin. Optimizations Enabled by a Decoupled Front-End Architecture. IEEE Transactions on Computing (TOC), Vol 50, No 4, February 2000. Patents: 84. M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, and Sai-Wang Tam. On-Chip Radio Frequency (RF) Interconnects for Network-On-Chip Designs. US 8,270,316. Filing date: Jan. 30, 2009. Publication date: Sep. 18, 2012. Textbook Chapters: 85. Glenn Reinman. Chapter 2: Instruction Cache Prefetching. Speculative Execution in High Performance Computer Architectures. Edited by David Kaeli and Pen Yew. CRC Press, 2005. Technical Reports: 86. Glenn Reinman and Norm Jouppi. CACTI version 2.0: An Integrated Cache Timing and Power Model. WRL Research Report, 2000/7. Expert Witness Experience Patent Infringement Cases: 1. GPH vs Toshiba, ASUS, Vizio, and Acer, 2013 (Active) Mintz Levin LLP: Analysis of patents and technical specifications. 2. LSI vs Barnes and Noble, 2013 (Active) Fenwick & West LLP: Analysis of patents and technical specifications. Software profiling. Drafted claim charts. 3. GPH vs Sony, Samsung, RIM, HTC, and LG, 2012 (ITC Matter - Settled) Mintz Levin LLP: Analysis of patents, RTL (VHDL and verilog), C driver code, technical documents, and prior art. Hardware testing on various devices (phones and tablets). Wrote two expert reports supporting infringement (for three patents at issue), and was deposed for two and a half days. 4. Realtime Data vs FactSet, IDCO, Penson/Nexa, C.A. No. 6:10-cv-425, 2012 (Settled) Irell and Manella, LLP: Analysis of patents and software. Wrote expert reports supporting invalidity and non- infringement, and was deposed for a day. 5. Undisclosed, 2011-Present (Stayed) Sidley Austin LLP: Has not started. Retained, but no work performed as of yet. 6. LSI vs Funai, 2012-Present (ITC Matter - Active) Irell and Manella LLP (first) --- Kilpatrick Townsend & Stockton LLP (later): Analysis of patents, RTL and driver source code, and technical specifications. Construction of claim charts. Software profiling. Wrote report on infringement and was deposed for one day. Testified at trial in the ITC. 7. Softview LLC v. Apple Inc., et al., C.A. No. 10-389-LPS, 2011-Present (Active) Irell and Manella LLP: Analysis of patents, technical specifications, and Java/C++/C source code. Conducted device testing. Construction of claim charts, drafted a declaration. 8. Microlinc vs Intel, 2011-Present (Active) Wilmer Hale LLP: Analysis of patents and prior art. Drafted a declaration. 9. WARF vs Intel, 2009-2010 (Settled) Irell and Manella LLP: Analysis of patents and technical specifications. Implemented designs on simulation framework to analyze performance impact of various patents. 10. Undisclosed, 2009 (Advisory Role Only) Irell and Manella LLP: Analysis of patents and technical specifications. 11. Broadcom vs SiRF, 2008-2011 (Settled) Simpson Thatcher & Bartlett LLP: Analysis of patents and detailed technical specifications including a large repository of verilog source code. Wrote four detailed expert reports, and supporting statements for a number of motions. Was deposed for over a day and a half to testify about both infringement and invalidity of two asserted patents. 12. Undisclosed, 2008 (Advisory Role Only) Fish and Richardson LLP: Analysis of patents and technical specifications. 13. Intergraph Hardware Technologies Company vs Toshiba, 2007 (Settled) Foley and Lardner LLP: Analysis of patents and technical specifications involving cache coherency and chip multiprocessors. Prepared an expert witness report after analyzing a significant amount of design drawings and microcode. 14. Amberwave, 2006 (Advisory Role Only) Irell and Manella LLP: Analysis of patents and technical specifications.

Other Litigation: 15. Alki David et al vs CBS Interactive et al, 2013 (Case Dismissed) Kendall Brill & Klieger LLP: Authored report on file sharing technology that lead to a denial of a preliminary injunction and dismissal of the case. Awards and Grants

● Center for Future Architectures Research (C-FAR). Part of the Semiconductor Technology Advanced Research network (STARnet) sponsored by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA), 2013 ● NSF Expedition Grant (CO-PI) to establish the Center for Domain Specific Computing (CDSC), 8/2009-7/2014 ○ Architecture Thrust Leader (one of four members of the Executive Committee for the Center) ● Semiconductor Research Corp 2008-HJ-1796 (PI) - Network-On-Chip Design with RF-Interconnects for Future Chip Multiprocessors – 4/2008-5/2011 ● Best Paper Award, International Symposium on High-Performance Computer Architecture, Feb 2008. ● Voted Professor of the Year by the Engineering Society of the University of California, 2006 ● UCLA Faculty Career Development Award 2004 ● Northrop Grumman Excellence in Teaching Award 2004 ● DARPA SA5430-79952 (CO-PI) - GSRC-MARCO, 9/2006-8/2007 ● Semiconductor Research Corp 2005-TJ-1317 (CO-PI) - Design and Evaluation of Power-Efficient High-Performance Heterogeneous Multi-Core Processors w/Programmable Fabric, 6/2005-5/2008 ● UC MICRO Program (CO-PI) – MEVA: Microarchitectural Evaluation with Physical Planning, 7/2003-12/2004 ● NSF ITR (CO-PI) – Reconfigurable Fabric, 9/01/2002-8/31/2005 ● NSF CAREER Award (PI) – The Evaluation and Design of an Scalable, High-Performance, and Energy-Efficient Microprocessor Architecture, 9/01/2001-8/31/2006 References Available upon request.

Exhibit B William Henry Mangione-Smith

4146 118th Ave NE Kirkland WA, 98033 (425) 654-1424 [email protected]

Highlights

Reviewed and valued thousands of patents. Priced over $500M worth in patent portfolios. Key technical support for licensing that has raised more than $1B. Significant experience developing claim charts and evidence of use. Former tenured professor at the University of California. Deposition and trial testifying experience.

Education

BSE, MSE, & Ph.D. University of Michigan Doctoral Thesis 1992: Performance Bounds and Buffer Space Requirements for Concurrent Processors

Employment

2009-Present Sole Proprietor of Phase Two LLC – Consulting and intellectual property services

2012 May-June CTO Computers and Consumer Electronics at IP Navigation Group

2005-2008 Intellectual Ventures, Bellevue Washington 2005 Patent valuation, licensing support, focus on computer patents 2006 Head of all IV valuation efforts – managed a team of 12 2007 Director of technology, outbound licensing in consumer electronics 2008 Director of investment strategy, inventor relations

2001-2005 Associate Professor, EE UCLA 1995-2001 Assistant Professor, EE UCLA Focus low power embedded multimedia communications systems

1993-1995 Motorola Wireless Data Group Systems architect for General Magic wireless PDA

1991-1992 Motorola Corporate Research Parallel computer performance monitoring Low power processor architecture

1986-1987 Chrysler Corporation Software Architect

Patents 8,473,818 - Reliable communications in on-chip networks 8,473,388 - Facilitating compensation arrangements providing for data tracking … 8,473,387 - Facilitating compensation arrangements between data providers and data … 8,468,073 - Facilitating compensation arrangements providing for data tracking … 8,452,182 - Data center with free-space optical communications 8,442,440 - Hierarchical spectrum sensing for cognitive radios 8,434,674 - Fiducial markers for augmented reality 8,429,040 - Facilitating compensation arrangements for data brokering 8,423,824 - Power sparing synchronous apparatus 8,402,257 - Alteration of execution of a program in response to an execution- … 8,401,393 - Data center with free-space optical communications 8,392,342 - Method and apparatus for predicting movement of a tool in each of four … 8,385,831 - Secure cognitive radio transmissions 8,384,043 - Plasmon filter 8,375,247 - Handling processor computational errors 8,369,708 - Data center with free-space optical communications 8,346,872 - Context parameters and identifiers for communication 8,327,358 - Hypervisor driver management in virtual machine environments 8,327,155 - Screening for masquerading content 8,301,028 - Data center with free-space optical communications 8,281,036 - Using network access port linkages for data structure update decisions 8,255,745 - Hardware-error tolerant computing 8,243,045 - Touch-sensitive display device and method 8,224,930 - Signaling partial service configuration changes in appnets 8,224,907 - System and method for transmitting illusory identification characteristics 8,214,191 - Cross-architecture execution optimization 8,209,755 - Signaling a security breach of a protected set of files 8,209,524 - Cross-architecture optimization 8,203,609 - Anonymization pursuant to a broadcasted policy 8,191,140 - Indicating a security breach of a protected set of files 8,161,232 - Periodically and empirically determined memory refresh intervals 8,126,938 - Group content substitution in media works 8,126,190 - Targeted obstrufication of an image 8,117,654 - Implementation of malware countermeasures in a network device 8,082,225 - Using destination-dependent criteria to guide data transmission decisions 8,065,404 - Layering destination-dependent content handling guidance 8,055,797 - Transmitting aggregated information arising from appnet information 8,055,732 - Signaling partial service configuration changes in appnets 8,055,648 - Managing information related to communication 7,972,557 - Plasmon filter 7,930,389 - Adaptive filtering of annotated messages or the like 7,877,584 - Predictive processor resource management 7,860,887 - Cross-media storage coordination 7,752,255 - Configuring software agent security remotely 7,739,524 - Power consumption management 7,653,834 - Power sparing synchronous apparatus 7,607,042 - Adjusting a processor operating parameter based on a performance criterion 7,519,995 - Programmable hardware for deep packet filtering 7,512,842 - Multi-voltage synchronous systems 7,493,516 - Hardware-error tolerant computing 5,793,991 - Method of equalizing loads on a computer bus

Expert Consultant in IP Matters

2013

Microlinc, LLC v Sony Computer Entertainment America LLC U.S. District Court for the Eastern District of Texas Case No.: 2:13-CV-520-MHS Retained by The Law offices of Eugene M. Cummings, P.C., on behalf of Microlinc, L.L.C. Technology related to computer systems communications.

dunnhumby USA, LLC, et al. v. emnos USA Corp. U.S. District Court for the Northern District of Illinois Case No.: 1:13-cv-00399 Retained by Baker Hostetler who represents dunnhumby Technology relates to database technology.

FlashPoint Technology, Inc. v. HTC Corporation, HTC America, Inc., Pantech Co., Ltd., Pantech Wireless, Inc., Huawei Technologies Co., Ltd., FutureWei Technologies, Inc. d/b/a Huawei Technologies (USA), ZTE Corporation, ZTE (USA) Inc., USA International Trade Commission Certain Electronic Imaging Devices, Inv. No. 337-TA-850 Expert for FlashPoint, who is represented by Pepper Hamilton, LLP.

St. Clair Intellectual Property Consultants, Inc. v. Acer, Inc., Acer America Corporation, Dell Inc., Gateway Companies, Inc., Gateway, Inc., Lenovo Group, Limited and Lenovo (United States) Inc. United States District Court for the District of Delaware - 1:2009cv00354 Consultant for St. Clair Intellectual Property Consultants St. Clair is represented by R. Terrance Rader, Charles W. Bradley, Glenn E. Forbis, and Justin S. Cohen of Rader Fishman & Grauer PLLC Filed reports regarding validity and infringement and provided deposition testimony. Subject matter relates to power management and graphics hardware.

2012

Graphics Properties Holdings v. HTC et. al. Graphics Properties Holdings v. LG Electronics et. al. Graphics Properties Holdings v. Sony et. al. Graphics Properties Holdings v. Samsung Electronics et. al. Graphics Properties Holdings v. Apple Graphics Properties Holdings v. Research In Motion et. al. United States District Court for the District of Deleware Testifying expert witness for GPH on matters related to invalidity. Pepper Hamilton LLP and Mintz, Levin, Cohn, Ferris, Glovsky and Popeo LLP represent plaintiffs. Subject matter relates to graphics systems and CPU microarchitecture.

IPValue Non-litigation related patent evaluation services.

TV Interactive Data Corporation v. Sony Corporation, Sony Computer Entertainment Inc, Sony Computer Entertainment America Inc, Sony Corporation of America, Sony Electronics Inc, Samsung Electronics Co Ltd, Samsung Electronics America Inc, Royal Philips Electronics NV, Philips Electronics North America Corporation, Toshiba Corporation, Toshiba America Inc., Toshiba America Consumer Products LLC, Panasonic Corporation, Panasonic Corporation of North America, Victor Company of Japan, LTD, JVC Americas Corp, LG Electronics Inc, LG Electronics USA Inc., Zenith Electronics LLC, Pioneer Corporation, Pioneer Electronics (USA) Inc., Sharp Corporation, Sharp Electronics Corporation, Funai Electric Co., Ltd., Funai Corporation, Inc., D&M Holdings Inc., D&M Holdings US Inc. and Denon Electronics (USA), LLC United States District Court for the Northern District of California Case 5:2010cv00475 Consultant for defendant Funai Defendants Funai Electric Co. Ltd. and Funai Corporation, Inc. are represented by Kevin W. Kirsch, David A. Mancino, John F. Bennett, Matthew P. Hayden, and Hayes F. Michel of Baker Hostetler Subject matter relates to DVDs and computer Operating Systems.

Interval Licensing LLC, v. AOL, Inc.,; Apple, Inc.; eBay, Inc.; Facebook, Inc.; Netflix, Inc.; Office depot, Inc.; Officemax, Inc.; Staples, Inc.; Yahoo! Inc.; and Youtube, LLC. United States District Court for the Western District of Washington Case 2:10-cv-01385 Consultant for Interval Licensing LLC Interval Licensing LLC is represented by Michael F. Heim, Eric J. Enger, and Nathan J. Davis of Heim, Payne & Chorush, L.L.P. Subject matter relates to online search, advertising and data presentation.

ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC., v. APPLE, INC. HIGH TECH COMPUTER CORP., a/k/a HTC CORP., HTC (B.V.I.), HTC AMERICA, INC., EXEDEA, INC., RESEARCH IN MOTION LTD., and RESEARCH IN MOTION CORPORATION United States District Court for the District of Delaware - 1:10-cv-00982-LPS Consultant for St. Clair Intellectual Property Consultants St. Clair is represented by R. Terrance Rader, Charles W. Bradley, Glenn E. Forbis, and Justin S. Cohen of Rader Fishman & Grauer PLLC Filed a declaration. Subject matter relates to cameras and messaging.

Red Chalk Group Subject matter relates to patent analysis.

Siemens Subject matter relates to patent analysis.

Phoenix Technologies Subject matter relates to patent analysis.

2011

Negotiated Data Solutions Consultant for Negotiated Data Solutions Negotiated Data Solutions is represented by Susman, Godfrey LLP. Subject matter relates to IO devices.

Acqis LLC Declarations filed with USPTO in response to a series of reexamination requests. Deposed in a related case (Texas Eastern District Court 6:2009cv00148) as a consequence of declarations. Acqis LLC is represented by Cooley, Godward, Kronish LLP Subject matter relates to computer systems.

FlashPoint Technology, Inc. v. Nokia Corp. of Finland, Nokia, Inc. of Irving, Texas, Research In Motion Ltd. of Canada, Research In Motion Corp. of Irving, Texas, HTC Corp. of Taiwan, HTC America, Inc. of Bellevue, Washington, LG Electronics of South Korea, LG Electronics U.S.A., Inc. of Englewood Cliffs, New Jersey, and LG Electronics MobileComm U.S.A., Inc. of San Diego, California US ITC Inv. No. 337-TA-726 Consultant for FlashPoint Technology, Inc. FlashPoint Technology Inc. is represented by William D. Belanger, Gregory D. Len, and Frank Liu of Pepper Hamilton LLP. Filed reports regarding validity and infringement and provided testimony both via deposition and in court. Subject matter relates to camera systems.

MicroUnity, Inc.v. Texas Instruments Inc., Qualcomm, Inc., Samsung Electronics Co LTD, Motorola, Inc., Nokia Corporation, Palm, Inc., Samsung TeleCommunications America, LLC, Acer, Inc., HTC Corporation, Google Inc., LG Electronics Inc, Apple, Inc., Cellco Partnership d/b/a Verizon Wireless, Sprint Nextel Corporation and AT&T 2:2010cv00091 Consultant for MicroUnity, Inc. Eastern District of Texas MicroUnity, Inc., is represented by Heim, Payne, and Chorush LLP. Subject matter relates to graphics hardware and microarchitecture.

2010

St. Clair Intellectual Property Consultants, Inc. v. Acer, Inc., Acer America Corporation, Dell Inc., Gateway Companies, Inc., Gateway, Inc., Lenovo Group, Limited and Lenovo (United States) Inc. United States District Court for the District of Delaware - 1:2009cv00354 Consultant for St. Clair Intellectual Property Consultants St. Clair is represented by R. Terrance Rader, Charles W. Bradley, Glenn E. Forbis, and Justin S. Cohen of Rader Fishman & Grauer PLLC Subject matter relates to power management and graphics hardware.

Negotiated Data Solutions Consultant for Negotiated Data Solutions Negotiated Data Solutions is represented by Susman, Godfrey LLP. Subject matter relates to IO devices.

Saxon Innovations, LLC v. Apple, Inc., Gateway, Inc., Gateway Companies, Inc., Acer America Corp., Acer, Inc., Hewlett-Packard Co. and Dell, Inc Eastern District of Texas 6:2008cv00265 Consultant for Saxon Innovations, LLC Representing Saxon Innovations, LLC, who was represented by Heim, Payne, and Chorush LLP. Subject matter relates to multiprocessors systems and computer systems.

Joel M. Geddis and Shaun Legacy v. Microsoft Corporation, Toshiba Corporation, Freescale Semiconductor, Inc., Wolfson Microelectronics, Inc., Wolfson Microelectronics PLC Superior Court of Washington in and for King County 08-2-40731-4 SEA Consultant for Toshiba Corporation Toshiba Corporation is represented by Forsberg & Umlauf, P.S. Subject matter relates to portable audio devices.

2009 Saxon Innovations, LLC v. LG Electronics Inc., LG Electronics USA Inc., LG Electronics Mobilecomm U.S.A., Inc., Samsung Electronics Co. Ltd, Samsung Electronics America Inc., Samsung Telecommunications America LLC, Palm Incorporated, Research in Motion Ltd, Research In Motion Corporation, Nintendo Co. Ltd, and Nintendo of America Eastern District of Texas 6:07-CV-490 Prepared expert report regarding invalidity on behalf of Saxon Innovations, LLC. Saxon Innovations, LLC, was represented by Pepper Hamilton LLP. Subject matter relates to multiprocessors systems and computer systems.

Saxon Innovations, LLC, v. Nokia Corp., Research In Motion Ltd., High Tech Computer Corp., Palm, Inc., Panasonic Corporation, US ITC 337-TA-667 Expert witness for Saxon Innovations, LLC. Submitted reports, was deposed, and testified at trial regarding claim construction and invalidity. Saxon Innovations, LLC was represented by William D. Belanger, Aaron J. Levangie, Gregory D. Len, and Charles H. Carpenter of Pepper Hamilton LLP. Subject matter relates to multiprocessors systems and computer systems.

Advanced Micro Devices, Inc. v. Samsung Electronics Co, Ltd. U.S. District Court for the Northern District of California 3:08-cv-00986-SI Consultant for Advanced Micro Devices, Inc. Reverse engineering efforts to support infringement contentions. Advanced Micro Devices, Inc is represented by Robins, Kaplan, Miller and Ciresi LLP. Subject matter relates to memory devices.

Intellectual Ventures Subject matter relates to patent analysis.

2005 Speedera Networks,Inc., v. Akamai Technologies,Inc. U.S. District Court for the Northern District of California 5:02-cv-03050-JW Consultant for Speedera Networks, Inc. Reviewed depositions and provided review of computer security. Speedera Networks, Inc. was represented by Jim Bowman of O’Melveny & Myers LLP.

Research in Motion Limited et al. v. Inpro II Licensing SARL U.S. District Court for the Northern District of Texas 3:03-cv-02669-B Consultant for InPro II Licensing SARL . Provided patent analysis. InPro II Licensing SARL was represented by Dechert.

Digi International, Inc. v. Lantronix, Inc., 0:04-cv-01560-DWF-SRN U.S. District Court for the District of Minnesota Consultant for Lantronix, Inc. Prepared expert reports. Lantronix, Inc. was represented by Stradling Yocca Carlson & Rauth.

2004 Intergraph Hardware Technologies Company, Inc v. Hewlett-Packard U.S. District Court for the Eastern District of Texas Company6:04-cv-00214-LED Expert for Intergraph Hardware Technologies Company, Inc. Prepared expert reports and claim charts. Intergraph represented by McDermott, Will and Emery LLP.

Mentor Graphics Provided licensing support and IP valuation.

Veterinary Imaging Centers, Inc. v. Sound Technologies, Inc., et al., 1:02-cv-00282- DCN U.S. District Court for the Northern District of Ohio Consultant for Sound Technologies, Inc. Prepared expert reports.

Interealty Corp. v. Superaltive, Inc., et al., 8:01-cv-00969-AHS-AN U.S. District Court for the Central District of California Consultant for Superlative,Inc. Matter involved software copyright. Prepared expert reports and was deposed. Superlative, Inc. was represented by Edward F. O'Connor with the law firm of Levin & O'Connor.

All Computers, Inc. v. Intel Corporation, 1:04-cv-00586-GBL-LO U.S. District Court for the Eastern District of Virginia Consultant for All Computers, Inc. Filed numerous expert reports. Deposed by Ruffin Cordell of Fish & Richardson. Plaintiff was represented by Edward F. O'Connor with the law firm of Levin & O'Connor.

2001 Ikos Systems, Inc. v. Axis Systems, Inc., 5:01-cv-21079-JW U.S. District Court for the Northern District of California Filed numerous expert reports. Deposed by Ikos Counsel. Presented tutorial to Judge Ware. Deposed. Axis Sytems, Inc. was represented by George Riley of O’Melveny and Myers

Professional Activities

Member of ACM and IEEE Program Chair 26’th International Symposium on Microarchitecture General Chair 36’th International Symposium on Microarchitecture Associate Editor of IEEE Transactions on Computers Associate Editor of ACM Transactions on Embedded Computing Systems Associate Editor of IEEE Computer Program Committees: ISCA, MICRO, ISLPED, Network Processors Workshop, FPL, Complexity-Effective Design, RAW, Workshop on Mediaprocessors and DSP, FPT, INTERACT

Publications

Journal

1. W. H. Mangione-Smith, T.-P. Shih, S. G. Abraham, and E. S. Davidson, "Approaching a Machine-Application Bound in Delivered Performance on Scientific Codes," Proceedings of the IEEE, vol. 81, pp. 1166-1178, 1993. 2. C. Chien, S. Nazareth, P. Lettieri, S. Molloy, B. Schoner, W. A. I. Boring, J. Chen, C. Deng, W. H. Mangione-Smith, and R. Jain, "An Integrated Testbed for Wireless Multimedia Computing," Journal of VLSI Signal Processing, vol. 13, pp. 105-24, 1996. 3. K.-G. Chia, H. J. Kim, S. Lansing, W. H. Mangione-Smith, and J. Villasenor, "High Performance Automatic Target Recognition through Data-Specific VLSI," IEEE Transactions on VLSI, vol. 6, pp. 364-372, 1998. 4. N. R. Shnidman, W. H. Mangione-Smith, and M. Potkonjak, "On-line Fault Detection for Bus-Based Field Programmable Gate Arrays," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, pp. 656-66, 1998. 5. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Low Overhead Fault-Tolerant FPGA Systems," IEEE Transactions on Very Large Scale Integration, pp. 212-21, 1998. 6. D. Kirovski, C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Application-Driven Synthesis of Memory-Intensive Systems-on-Chip," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 18, pp. 1316-1326, 1999. 7. W. H. Mangione-Smith, "Technical Challenges for Designing Personal Digital Assistants," Design Automation for Embedded Systems, vol. 4, pp. 23-39, 1999. 8. D. Kirovski, J. Kin, and W. H. Mangione-Smith, "Procedure Based Program Compression," International Journal of Parallel Programming, vol. 27, pp. 457-475, 1999. 9. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Enhanced FPGA Reliability through Efficient Run-Time Fault Reconfiguration," IEEE Transactions on Reliability, vol. 49, pp. 296-304, 2000. 10. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Constraint-based Watermarking Techniques for Design IP Protection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 1236-52, 2001. 11. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Fingerprinting Techniques for Field- Programmable Gate Array Intellectual Property Protection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 1253-61, 2001. 12. C. Lee, J. Kin, M. Potkonjak, and W. H. Mangione-Smith, "Exploring Hypermedia Processor Design Space," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 27, pp. 171-186, 2001. 13. J. Kin, C. Lee, W. H. Mangione-Smith, and M. Potkonjak, "Exploring the Diversity of Multimedia Systems," IEEE Transactions on VLSI Systems, vol. 9, pp. 474-485, 2001. 14. J. Kin, M. Gupta, and W. H. Mangione-Smith, "Filtering Memory References to Increase Energy Efficiency," IEEE Transactions on Computers, vol. 49, pp. 1-15, 2002. 15. G. Memik and W. H. Mangione-Smith, “Precise Instruction Scheduling”, To Appear in the Journal of Instruction-Level Parallelism, 2005.

Conference

1. T. Conte and W. Mangione-Smith, "Determining Cost-Effective Multiple Issue Processor Designs," presented at International Conference on Computer Design, 1993. 2. W. H. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "The Effects of Memory Latency and Fine-Grain Parallelism on Astronautics ZS-1 Performance," presented at Twenty-Third Hawaii International Conference on System Sciences, 1990. 3. W. H. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "Architectural vs. Delivered Performance of the IBM RS/6000 and the Astronautics ZS-1," presented at Twenty-Fourth Hawaii International Conference on System Sciences, 1991. 4. W. H. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "Vector Register Design for Polycyclic Vector Scheduling," presented at Fourth Conference on Architectural Support for Programming Languages and Operating Systems, 1991. 5. W. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "Register Requirements of Pipelined Processors," presented at International Conference on Supercomputing, 1992. 6. W. H. Mangione-Smith and B. Hutchings, "Configurable Computing: The Road Ahead," presented at Reconfigurable Architectures Workshop, Geneva, 1997. 7. J. Kin, C. Lee, W. H. Mangione-Smith, and M. Potkonjak, "Hypermedia Processors: Design Space Exploration," presented at Multi-Media Signal Processing Conference, 1998. 8. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Fingerprinting Digital Circuits on Programmable Hardware," presented at Second International Workshop on Information Hiding, 1998. 9. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Signature Hiding Techniques for FPGA Intellectual Property Protection," presented at IEEE/ACM International Conference on Computer-Aided Design, 1998. 10. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "FPGA Fingerprinting Techniques for Protecting Intellectual Property," presented at Custom Integrated Circuits Conference, 1998. 11. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Efficiently Supporting Fault- Tolerance in FPGAs," presented at International Symposium on Field Programmable Gate Arrays, 1998. 12. W. Mangione-Smith, "Configurable Computing: Concepts and Issues," presented at Thirtieth Hawaii International Conference on System Sciences, 1997. 13. J. Villasenor, B. Schoner, C. Kang-Ngee, C. Zapata, K. Hea Joung, C. Jones, S. Lansing, and B. Mangione-Smith, "Configurable Computing Solutions for Automatic Target Recognition," presented at FPGAs for Custom Computing Machines, 1996. 14. B. Mangione-Smith, "Low Power Communications Protocols: Paging and Beyond," presented at IEEE Symposium on Low Power Electronics, 1995. 15. H. J. Kim, W. H. Mangione-Smith, and M. Potkonjak, "Protecting Ownership Rights of a Lossless Image Coder through Hierarchical Watermarking," presented at IEEE Workshop on Signal Processing Systems, 1998. 16. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Watermarking Techniques for Intellectual Property Protection," presented at Design and Automation Conference, 1998. 17. Rashid, J. Leonard, and W. H. Mangione-Smith, "Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability," presented at FPGAs for Custom Computing Machines, 1998. 18. D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith, "Synthesis of Power Efficient Systems-on-Silicon," presented at Asia and South Pacific Design Automation Conference, 1998. 19. J. Leonard and W. H. Mangione-Smith, "A Case Study of Partially Evaluated Hardware Circuits: Key-Specific DES," presented at Field-Programmable Logic and Applications, 1997. 20. N. R. Shnidman, W. H. Mangione-Smith, and M. Potkonjak, "Fault Scanner for Reconfigurable Logic," presented at Advanced Research in VLSI, 1997. 21. J. Kin, M. Gupta, and W. H. Mangione-Smith, "The Filter Cache: an Energy Efficient Memory Structure," presented at International Symposium on Microarchitecture, 1997. 22. D. Kirovski, J. Kin, and W. H. Mangione-Smith, "Procedure Based Program Compression," presented at International Symposium on Microarchitecture, 1997. 23. D. Kirovski, C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Application-Driven Synthesis of Core-Based Systems," presented at International Conference on Computer Aided Design, 1997. 24. Mangione-Smith, P. S. Ghang, S. Nazareth, P. Lettieri, W. Boring, and R. Jain, "A Low Power Architecture for Wireless Multimedia Systems: Lessons Learned from Building a Power Hog," presented at International Symposium on Low Power Electronics and Design, 1996. 25. Lee, J. Kin, M. Potkonjak, and W. H. Mangione-Smith, "Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor," presented at Design Automation Conference, 1998. 26. Lee, M. Potkonjak, and W. H. Mangione-Smith, "MediaBench: a Tool for Evaluating and Synthesizing Multimedia and Communications Systems," presented at International Symposium on Microarchitecture, 1997. 27. Rashid, J. Asher, W. H. Mangione-Smith, and M. Potkonjak, "Hierarchical Watermarking for Protection of DSP Filter Cores," presented at IEEE 1999 Custom Integrated Circuits Conference, San Diego, CA USA, 1999. 28. H. Zou, H. J. Kim, S. Kim, B. Daneshrad, R. Wesel, and W. H. Mangione-Smith, "Equalized GMSK, Equalized QPSK, and COFDM, a Comparative Study for High Speed Wireless Indoor Data Communications," presented at International Vehicular Technology Conference, Houston, TX USA, 1999. 29. J. Kin, C. Lee, W. H. Mangione-Smith, and M. Potkonjak, "Power Efficient Mediaprocessors: Design Space Exploration," presented at Design Automation Conference, New Orleans, LA USA, 1999. 30. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Robust FPGA Intellectual Property Protection through Multiple Small Watermarks," presented at Design Automation Conference, 1999. 31. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Efficient Error Detection, Localization and Correction for FPGA-based Debugging," presented at Design Automation Conference, 2000. 32. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures," presented at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1999. 33. Lee, J. Kin, M. Potkonjak, and W. Mangione-Smith, "Designing Power Efficient Hypermedia Processors," presented at International Symposium on Low Power Electronics and Design, 1999. 34. J. Lach, W. H. Mangione-Smith, and W. Potkonjak, "Enhanced Intellectual Property Protection for Digital Circuits on Programmable Hardware," presented at International Workshop on Information Hiding, 1999. 35. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Runtime Logic and Interconnect Fault Recovery on Diverse FPGA Architectures," presented at Military and Aerospace Applications of Programmable Devices and Technologies, 1999. 36. Benyamin and W. Mangione-Smith, "Functional Unit Specialization through Code Analysis," presented at International Conference on Computer Aided Design, 1999. 37. J. Kin, C. Lee, W. H. Mangione-Smith, and M. Potkonjak, "A Technique for QoS- Based System Partitioning," presented at ASP-DAC, 2000. 38. S. Brown, C. Lee, and W. H. Mangione-Smith, "Offline Program Re-Mapping to Improve Branch Prediction Efficiency in Embedded Systems," presented at ASP-DAC, 2000. 39. H. Kim and W. Mangione-Smith, "Factoring Large Numbers with Programmable Hardware," presented at International Symposium on Field Programmable Gate Arrays, 2000. 40. G. Memik, W. Hu, and W. Mangione-Smith, "NetBench: A Benchmarking Suite for Network Processor," presented at Computer Aided Design, 2001. 41. G. Memik, S. Memik, and W. Mangione-Smith, "Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic," presented at IEEE Symposium on FPGAs for Custom Computing Machines, 2002. 42. G. Memik and W. Mangione-Smith, "A Flexible Accelerator for Layer 7 Networking Applications," presented at Design Automation Conference, 2002. 43. Y. Cho, S. Navab, and W. Mangione-Smith, "Specialized Hardware for Deep Network Packet Filtering," presented at International Conference on Field Programmable Logic and Application, 2002. 44. G. Memik and W. Mangione-Smith, "Improving Power Efficiency of Multi-Core Network Processors Through Data Filtering," presented at International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2002. 45. G. Memik, G. Reinman, and W. Mangione-Smith, "Just Say No: Benefits of Early Cache Miss Determination," presented at International Symposium on High Performance Computer Architecture, 2002. 46. G. Memik and W. Mangione-Smith, "NEPAL: A Framework for Efficiently Structuring Applications for Network Processors," presented at NP-2: The Second Workshop on Network Processors, Anaheim, CA, 2003. 47. G. Memik, G. Reinman, and W. H. Mangione-Smith, "Reducing Energy and Delay Using Efficient Victim Caches," presented at International Symposium on Low Power Electronics and Design, Seoul, Korea, 2003. 48. Young Cho and William H. Mangione-Smith, “Programmable Hardware for Deep Packet Filtering on a Large Signature Set.” First Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac 2 ), Yorktown, NY, Oct. 6-8, 2004 49. Young Cho and William H. Mangione-Smith, “Deep Packet Filter with Dedicated Logic and Read-Only-Memories.” IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley / CA, April 2004.

Book Chapters

1. W. H. Mangione-Smith, "Register Requirements for High Performance Code Scheduling," in The Interaction of Compiler Technology and Computer Architecture, D. Lilja and P. Bird, Eds.: Kluwer Academic Press, 1994, pp. 51-84. 2. W. H. Mangione-Smith, "Performance Bounds for Rapid Computer System Evaluation," in Fast Simulation of Computer Architectures, T. Conte and C. Gimarc, Eds.: Kluwer Academic Press, 1995. 3. G. Memik and W. H. Mangione-Smith, "NEPAL: A Framework for Efficiently Structuring Applications for Network Processors," in Network Processor Design: Issues and Practices, vol. 2, P. Crowley, M. A. Franklin, H. Hadimioglu, and P. Z. Onufryk, Eds.: Morgan Kaufman, 2003.

Magazine Articles

1. W. H. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1," in IEEE Computer, vol. 24, 1991. 2. W. H. Mangione-Smith, B. Hutchings, D. Andrews, A. DeHon, C. Ebeling, R. Hartenstein, O. Mencer, J. Morris, K. Palem, V. K. Prasanna, and H. A. E. Spaanenburg, "Seeking Solutions in Configurable Computing," in IEEE Computer, vol. 30, 1997, pp. 38-43. 3. W. H. Mangione-Smith, "Application Design for Configurable Computing," in IEEE Computer, vol. 30, 1997, pp. 115-17. 4. J. Villasenor and W. H. Mangione-Smith, "Configurable Computing," in Scientific American, vol. 276, 1997, pp. 54-9. 5. W. H. Mangione-Smith, "Mobile Computing and Smart Spaces," in IEEE Concurrency, vol. 6, 1998, pp. 5-7. 6. W. H. Mangione-Smith, "'Beauty Depends on Size'-Aristotle," in IEEE Concurrency, vol. 6, 1998, pp. 8-10.

Exhibit CC Curriculum Vitæ

John C. Hart

Siebel Center for Computer Science Professor (217) 649-1695 201 N. Goodwin Ave. Dept. of Computer Science [email protected] Urbana, IL 61801 University of Illinois http://graphics.cs.uiuc.edu/~jch  Experience 

Academia

• Full Professor. Dept. of Computer Science, University of Illinois, 2006-. • Associate Professor (with tenure). Dept. of Computer Science, University of Illinois, 2003-2006. • Associate Professor (“Q” appointment). Dept. of Computer Science, University of Illinois, 2000-2003. • Associate Professor (with tenure). School of Electrical Engineering and Computer Science, Washington State University, 1998-2000. • Assistant Professor. School of Electrical Engineering and Computer Science, Washington State University, 1992-1998. • Postdoctoral Research Associate. Electronic Visualization Laboratory, University of Illinois at Chicago, and National Center for Supercomputing Applications, University of Illinois at Urbana-Champaign, 1991- 1992. • Research Assistant. Electronic Visualization Laboratory, Electrical Engineering and Computer Science Dept., University of Illinois at Chicago, 1988-1991. • Teaching Assistant. Analog & digital circuit design courses, EECS Dept. University of Illinois at Chicago, 1987-1988. Industry

• Intrinsic Medical Imaging LLC, Bloomfield Hills, MI. Consultant, 2012-13. Mesh construction and simulation of coronary arterial blood flow. • Pratt & Whitney, Hartford, CT. Consultant, 2011. Flux estimation in a lensed system. • Science Applications International Corp. (SAIC), Champaign, IL. Consultant, 2008. Ray-NURBS intersection. • Adobe Systems, Inc., Seattle, WA. Visiting Researcher, 2007. Project: Rendering meshed objects as stylized vector art. • The Teaching Company, Chantilly, VA. Consultant, 2003. Produced custom educational video elements on the platonic solids. • Evans & Sutherland Computer Corp., Salt Lake City, Utah. Consultant, 1999-2000. Project: Design of the Evans & Sutherland Multi-Texturing Language.

John C. Hart Page 1 7/1/2013 • Blue Sky | VIFX, Inc., Culver City, California. Consultant, 1998. Project: development of a custom software plug-in for the Houdini procedural animation package to polygonize a feature film villain modeled as a complex implicit surface. • Evans & Sutherland Computer Corp., (group formerly known as Silicon Reality, Inc.) Federal Way, Washington. Consultant, 1997-8. Project: design of graphics hardware to support antialiased procedural solid texturing. • Kleiser-Walczak Construction Company (a visual effects production company). Lennox, Massachussetts. Consultant, 1992-1993. Project: development of a new fractal-based video transition effect for an attraction at the Luxor Hotel, Las Vegas. • AT&T Pixel Machines. AT&T Bell Laboratories, Holmdel, New Jersey. Summer Intern, 1990. • IBM T.J. Watson Research Center. Hawthorne, New York. Summer Intern, 1989. Expert Services

• Microsoft XBox. Graphics Hardware Expert on deinterlacing, through Sidley Austin LLP, 2010. • NVIDIA & AMD (ATI), Graphics Hardware Expert on graphics card features, through Cooley Godward Kronish LLP, San Francisco. 2008. • Broadcom. Graphics Hardware Expert on graphics accelerators, through McAndrews, Held & Malloy, Ltd, 2006. Education

• Ph.D. Electrical Engineering and Computer Science Dept., University of Illinois at Chicago, 1991. Thesis title: ``Computer Display of Linear Fractal Surfaces.'' Advisor: Thomas A. DeFanti. • M.S. EECS Dept., University of Illinois at Chicago, 1989. Thesis title: ``Image Space Algorithms for Visualizing Quaternion Julia Sets.'' Advisor: Thomas A. DeFanti. • B.S. College of Liberal Arts and Science, Aurora University, 1987. Major: Computer Science. Minors: Mathematics, Physics, Sociology Awards and Honors

• Winner. 2004 Fantasy Graphics League. • Listed. International Who's Who of Professionals, 1997. • Champion. SIGGRAPH Bowl II, SIGGRAPH 94. Captain of the EVL Alumni Team. • NSF Research Initiation Award. “Modeling, Rendering and Animation of Implicit Surfaces,” to support the generalization of methods developed for the visualization of fractal models to the more common implicit surfaces used in CAGD and entertainment, 1993. • First Runner-Up. Truevision Videographics Competition, SIGGRAPH 90. • Graduate Fellowship. Graduate College, University of Illinois at Chicago, 1990-1991.

John C. Hart Page 2 7/1/2013  Research Funding  From Industry

• Intel. Intel Illinois Parallelism Center. $2,500,000, Co-PI, 2011-2012. • Intel. Leveraging Larrabee’s Programmable Rasterization. $130,000, 2009-2011. • Intel/Microsoft. Universal Parallel Computing Research Center. $18,000,000, Co-PI, 2008-2012. • NAVTEQ. “Surface Classification and Reconstruction from LIDAR and images.” $60,000, 2008. • Thomas M. Siebel. “MethMorph: Visual Simulation of Methamphetamine Addiction.” $35,000, Spring 2006. • NVidia Corp. $15,000 annually though the UIUC CS Affiliates Program, 2004–, and $125,000 total to date in Ph.D. student fellowships ($25K directly to the student to support one year of Ph.D. research): Nate Carr: 2002 & 2003, Jesse Hall: 2003 & 2004, Jared Hoberock: 2005 & 2008. • Microsoft Research. “Precomputed Radiance Transfer Compression.” $15,000, Sep. 2002. • Evans & Sutherland Computer Corp. “Real Time Procedural Solid Texturing.” $83,246, June 1999 – May 2000. • Evans & Sutherland Computer Corp. and Washington Technology Center. “APST: Computer Graphics Hardware for Antialiased Procedural Solid Texturing.” $77,089. Aug. 16, 1998 - Aug. 15, 1999. • Intel Natural Data Types Group. “Procedural Modeling.” $43,000. Aug. 16, 1997 - Aug. 15, 1998. • Intel Natural Data Types Group. “Recurrent Modeling -- Beyond Fractal Block Coding.” (Co-PI with P. Flynn.) $93,000. Apr. 1, 1995 - Mar. 31, 1997. From Government Agencies

• NSF. #OCI-1216788 “Collaborative Research: Conceptualizing an Institute for Using Inter-Domain Abstractions to Support Inter-Disciplinary Applications” (Co-PI with David Padua and Philippe Geubelle, and other collaborators at Purdue and UT-Austin), $135,000, Oct. 2012 – indefinite. • NSF. #EF-1115112 “Collaborative Research: Digitization TCN: InvertNet--An Integrative Platform for Research on Environmental Change, Species Discovery and Identification” (co-PI with Christopher Dietrich, Christopher Taylor, Nahil Sobh and Umberto Ravaioli), $2,809,463, July 2011-June 2015. • NSF. #OCI-1047764 “SI2-SSE: Collaborative Research: Lagrangian Coherent Structures for Accurate Flow Structure Analysis” (co-PI with Shawn Shadden) $251,643, Sep. 2010 – Aug. 2013. • NSF. #IIS-0534485 “Analysis and Visualization of Complex Graphs” (co-PI with Michael Garland) $300,000, Sep. 2006 – Aug. 2009. • UIUC Critical Research Initiative. “A New Approach to Bone Replacement.” (Co-PI with Russ Jamison, Michael Goldwasser, Ben Grosser, Matei Stroila and Amy Wagoner Johnson.) $100,000, Sep. 2005 – Aug. 2006. • NSF Small Grant for Exploratory Research. “Application Directed Surface Parameterization.” $97,868, Jan. 2005 – Dec. 2005. • NSF/DARPA CARGO (Computational and Algorithmic Representations of Geometric Objects) Award. “Robust Lagrangian Surface Propagation with Topological Control.” (Lead PI, with Michael Heath, Jim Jiao and John Sullivan), $400,000, May 2003 – May 2006.

John C. Hart Page 3 7/1/2013 • NSF Information Technology Research. #NSG-0219594 “Making 3D Visibility Practical.” (Co-PI with Steve LaValle, Jeff Erickson, Fredo Durand) $499,923. Aug. 2002 – Aug. 2005. • CNRS (Centre National de la Recherche Scientifique). Supplement to “Making 3D Visibility Practical” to support UIUC – INRIA collaboration, $7,000, 2003-5. • NSF Information Technology Research. #ACI-0113968 “Multipass Programming for Personal High- Performance Computing.” $489,671, Aug. 2001 – July 2006. • NSF Information Technology Research. #ACI-0121288 “Procedural Representation and Visualization Enabling Personalized Computational Fluid Dynamics.” (Co-PI with David Ebert, David Marcum, Kelly Gaither and Penny Rheingans) $3,989,773. Aug. 2001 – July 2006. • NSF. #NSG-9732379 “Applications of Morse Theory and Catastrophe Theory to Computer Graphics.” (Co-PI with R. Lewis.) $220,541. Aug. 16, 1997 – Aug. 15 2000. • NSF. #CCR-9529809 “Recurrent Modeling.” (Co-PI with P. Flynn.) $206,435. June 15, 1996 - May 31, 1999. Research Experience for Undergraduates Supplement: $5,000. Jan. 1, 1998 - May. 31, 1999. • NSF Research Initiation Award. #CCR-9309210 “Modeling, Rendering and Animation of Implicit Surfaces.” $97,925. July 1, 1993 - June 30, 1996. Research Experience for Undergraduates Supplement: $4,885. Jan. 1, 1995 - Dec. 31, 1995. Education Projects

• Nokia University Cooperation Funding. “Teaching Mobile Augmented Reality on the Windows Phone Platform.” $11,377.64. 2013. • UIUC College of Engineering Strategic Instructional Initiatives Program. Improvement of key ME courses (Statics, Dynamics and Solid Mechanics), $450,000, with MechSE Profs. Tortorelli, Dullerud Keane and West, 2012-2014. • NSF Special Project. #EIA-9911033 “The Story of Computer Graphics Documentary Project.” $48,000. Sept. 15, 1999 – Aug. 31, 2000. Equipment Grants and Donations

• Intel. Dell XPS 12, $1,000, 2012. • Intel. Two Knights Ferry development workstations, $4,940, 2009. • NVidia. Various graphics cards, 2002-. • ATI. One graphics card, 2002. • Tektronix Phaser 340 Color Printer. Tektronix. $5,000. Oct. 1995. • High-Performance Networking and Computing Infrastructure for Imaging Research. (Co-PI with T. Fischer, P. Flynn and R. Bamberger.) NSF Research Instrumentation and Infrastructure. CISE Instrumentation Program, Office of Cross-Disciplinary Activites. $100,000. March 1, 1994 - April 30, 1996. Awarded: Jan. 1995. • Silicon Graphics Inc. Workstation Upgrade. $9,000. Apr. 1993. • XAOS Tools. Software Donation. Pandemonium and n-title. $6,500. Feb. 1993. • Karen Guzak. Art Donation. 12 Prints. $4,800. May 1995.

John C. Hart Page 4 7/1/2013  Publications 

Most of the following publications are available online via http://graphics.cs.uiuc.edu/~jch/papers. Reviewed Publications

1. D. Mayerich, J.C. Hart, “Volume Visualization of Serial Electron Microscopy Images Using Local Variance.” Proc. BioVis (IEEE Symposium on Biological Data Visualization), pp. 9-16, Oct. 2012 2. C. Dietrich, J. Hart, D. Raila, U. Ravaioli, N. Sobh, O. Sobh, C. Taylor. InvertNet: a new paradigm for digital access to invertebrate collections. ZooKeys 209, July 2012, pp. 165-181. 3. Jia, Y., Garland, M. and Hart, J. C. Social Network Clustering and Visualization using Hierarchical Edge Bundles. Computer Graphics Forum 30(8), Dec. 2011, pp. 2314–2327. 4. Y. Jia, V. Lu, J. Hoberock, M.J. Garland, J.C. Hart. Edge v. Node Parallelism for Graph Centrality Metrics. GPU Computing Gems – Jade Edition, Oct. 2011, pp 15-28. 5. M. Kamali, F.N. Iandola, H. Fang, J.C. Hart. MethMorph: Simulating Facial Deformation due to Methamphetamine Usage. Proc. International Symposium on Visual Computing. Sep. 2011. 6. M. Kamali, J. Cho, M. Stroila, E. Shaffer, J.C. Hart. Robust Classification of Curvilinear and Surface-like Structures in 3D Point Cloud Data. Proc. International Symposium on Visual Computing. Sep. 2011. 7. M. Kamali, E. Ofek, F. Iandola, I. Omer, J.C. Hart Linear Clutter Removal from Urban Panoramas. Proc. International Symposium on Visual Computing. Sep. 2011. 8. K. Karsch, J.C. Hart. Snaxels on a Plane. Proc. Non-Photorealistic and Artistic Rendering, Aug. 2011. 9. J. Hoberock, J.C. Hart. Arbitrary Importance Functions for Metropolis Light Transport. Computer Graphics Forum 29(6), 2010, pp. 1993-2003. 10. S. Shi, M. Kamali, K. Nahrstedt, J.C. Hart, R. Campbell. High-Quality Zero-Delay Remote Rendering System for 3D Video. Proc. Multimedia, Oct. 2010. 11. B. Choi, R. Komuravelli, V. Lu, H. Sung, R.L. Bochino, S.V. Adve, J.C. Hart. Parallel SAH k-D Tree Construction. Proc. High Performance Graphics, June. 2010. 12. Y. Jia, X. Ni, E. Lorimer, M. Mullan, R. Whitaker, J.C. Hart. RBF Dipole Surface Evolution . Proc. Shape Modeling International, June 2010. 13. W.-W. Feng, B.-U. Kim, Y. Yu, L. Peng, J.C. Hart, Feature-Preserving Triangular Geometry Images for Level- of-Detail Representation of Static and Skinned Meshes, ACM Transactions on Graphics 29(2), March 2010, Article 11. 14. J. Hoberock, V. Lu, Y. Jia, J.C. Hart. Stream Compaction for Deferred Shading. Proc. High Performance Graphics, Aug. 2009. 15. J.C Hart. Assistive Technology for the Aesthetically Impaired. Proc. CHI Workshop on Computational Creativity Support, Apr. 2009. 16. J. Hoberock, S. Hornus, J.C. Hart. On Constructing and Visualizing the Topological Structure of the Visibility and Radiance of Architectural Models. Proc. TopoInVis: Topological Methods in Data Analysis and Visualization, Feb. 2009. 17. Y. Jia, J. Hoberock, M. Garland, J.C. Hart. On the Visualization of Social and other Scale-Free Networks. (Proc. Infovis), IEEE Transactions on Visualization and Computer Graphics 14(6), Nov. 2008, pp. 1285-1292.

John C. Hart Page 5 7/1/2013 18. A. Godiyal, J. Hoberock, M. Garland, J.C. Hart. Rapid Multipole Graph Drawing on the GPU. Proc. Graph Drawing, Sep. 2008. 19. E. Eisemann, H. Winnemoller, J.C. Hart, D. Salesin. Stylized Vector Art from 3D Models with Region Support. (Proc. Eurographics Rendering Symposium), Computer Graphics Forum 27(4), June 2008, pp. 1199-1207. 20. M. Stroila, E. Eisemann, J.C. Hart. Clip Art Rendering of Smooth Isosurfaces. IEEE Transactions on Visualization and Computer Graphics 14(1), Jan. 2008, pp. 71-81. 21. H. Fang, J.C. Hart. Detail Perserving Shape Deformation in Image Editing. Proc. SIGGRAPH, ACM Transactions on Graphics 26(3), Aug. 2007, #12. 22. T. Bergstrom, K. Karahalios, J.C. Hart. Isochords: Visualizing Structure in Music. Proc. Graphics Interface, May 2007. 23. H. Fang, J.C. Hart. RotoTexture: Automated Tools for Texturing Raw Video. IEEE Transactions on Visualization and Computer Graphics 12(6), Nov. 2006, pp. 1580-1589. 24. X. Jiao, A. Colombi, X. Ni, J.C. Hart. Anisotropic Mesh Adaptation for Evolving Triangulated Surfaces. Proc. Meshing Rountable, Sept. 2006, pp. 173-190. 25. S. Dong, P.-T. Bremer, M. Garland, V. Pascucci, J.C. Hart. Spectral Surface Quadrangulation. Proc. SIGGRAPH, ACM Transactions on Graphics 25(3), July 2006, pp. 1057-1066. 26. N.A. Carr, J. Hoberock, K. Crane, J.C. Hart. Rectangular Multi-Chart Geometry Images. Proc. Sym. on Geom. Proc., July 2006, pp. 181-190. 27. N.A. Carr, J. Hoberock, K. Crane, J.C. Hart. Fast GPU Ray Tracing of Dynamic Meshes using Geometry Images. Prof. Graphics Interface, May 2006, pp. 203-209. 28. P.-T. Bremer, J.C. Hart. A Sampling Theorem for MLS Surfaces. Proc. Point Based Graphics, June 2005. 29. J.O. Talton, N.A. Carr, J.C. Hart. Voronoi Rasterization of Sparse Point Sets. Proc. Point Based Graphics, June 2005. 30. W. Su, J.C. Hart, A Programmable Particle System Framework for Shape Modeling, Proc. Shape Modeling International, June 2005. 31. S. Zelinka, H. Fang, M. Garland, J.C. Hart. Interactive Material Replacement in Photographs. Proc. Graphics Interface, May 2005. 32. S. Hornus, J. Hoberock, S. Lefebvre and J.C. Hart. ZP+: Correct Z-pass Stencil Shadows. Proc. ACM Symposium on Interactive 3-D Graphics and Games, Apr. 2005. (Highest ranked paper according to review score.) 33. H. Fang, J.C. Hart, "Textureshop: Texture Synthesis as a Photograph Editing Tool," ACM Transactions on Graphics 23(3) (also in Proc. SIGGRAPH 2004), Aug. 2004, pp. 354-359. 34. X. Li, M. Garland, J.C. Hart, "Fair Morse Functions for Extracting the Topological Structure of a Surface Mesh," ACM Transactions on Graphics 23(3) (also in Proc. SIGGRAPH 2004), Aug. 2004, pp. 613-622. (Second highest ranked paper according to tertiary review score.) 35. N. Carr, J.C. Hart, "Painting Detail," ACM Transactions on Graphics 23(3) (also in Proc. SIGGRAPH 2004), Aug. 2004, pp. 845-852. 36. N. Carr, J.C. Hart, "Dynamic Clustering of Meshed Surfaces," Proc. Symposium on Geometry Processing, July 2004. 37. O.S. Lawlor, J.C. Hart, "Bounding Recursive Procedural Models using Convex Optimization," Proceedings of Pacific Graphics 2003, October 2003, pp. 283-292. 38. P-P. Sloan, J. Hall, J. Hart, J. Snyder. Clustered Principle Components for Precomputed Radiance Transfer. (Proc. SIGGRAPH 2003) ACM Transactions on Graphics 22(3), July 2003. 39. N.A. Carr, J.D. Hall and J.C. Hart, GPU Algorithms for Radiosity and Subsurface Scattering, Proc. Graphics Hardware, July 2003.

John C. Hart Page 6 7/1/2013 40. John C. Hart, Jeyprakash Michaelraj, Brent Baker. Structural Simulation of Tree Growth. The Visual Computer 19(2-3), May 2003, pp. 151-163. 41. P. Sherman, J.C. Hart. Direct Manipulation of Recurrent Models. Computers & Graphics 27(1), Feb. 2003, pp. 143-151. 42. A. Sheffer, J.C. Hart. Seamster: Inconspicuous Low-Distortion Texture Seam Layout. Proc. Visualization 2002, Oct. 2002. 43. N.A. Carr, J.D. Hall and J.C. Hart. The Ray Engine. Proc. Graphics Hardware 2002, Sep. 2002. 44. H. Fang, J. Hart. Randomly Accessible Procedural Animation of Physically Approximate Turbulent Motion. Proc. Computer Animation 2002, June 2002. 45. J. Hart, E. Bachta, W. Jarosz, T. Fleury. Using Particles to Sample and Control More Complex Implicit Surfaces. Proc. Shape Modeling International 2002, May 2002, pp. 129-136. 46. N. Carr, J. Hart. Meshed Atlases for Real-Time Procedural Solid Texturing. ACM Transactions on Graphics 21(2), Apr. 2002. 47. J.C. Hart. Perlin Noise Pixel Shaders. Proc. Graphics Hardware 2001, Aug. 2001. 48. W. Cochran, R. Lewis, J. Hart. The Normal of a Fractal Surface. The Visual Computer 17(4), 2001, pp. 209- 218. 49. J.C. Hart. Using the CW-Complex to Represent the Topological Structure of Implicit Surfaces and Solids. Proc. Implicit Surfaces '99, Sept. 1999, pp. 107-112. 50. J.C. Hart, N. Carr, M. Kameya, S.A. Tibbitts, T.J. Coleman. Antialiased Parameterized Solid Texturing Simplified for Consumer-Level Hardware Implementation. Proc. Graphics Hardware 99, Aug. 1999, pp. 45-53. 51. J.C. Hart, A. Durr and D. Harsch. Critical points of polynomial metaballs. Proc. Implicit Surfaces '98, June 1998, pp. 69-76. 52. J.C. Hart. Morse Theory for Implicit Surface Modeling. In Mathematical Visualization, H-C Hege and K. Polthier, Eds., Springer-Verlag, Berlin, Oct. 1998, pp. 257-268. (Reviewed paper presented at VisMath '97, Berlin, 1997.) 53. W.O. Cochran, J.C. Hart, P.J. Flynn. On Approximating Rough Curves with Fractal Functions. Proc. Graphics Interface '98, June 1998, pp. 65-72. 54. A.K. Dunker, E. Garner, S. Guilliot, P. Romero, K. Albrecht, J. Hart, Z. Obradovic, C. Kissinger and J.E. Villafranca. Protein Disorder and the Evolution of Molecular Recognition: Theory, Predictions and Observations. Pacific Symposium on Biocomputing 3: 435-446, Jan. 1998. 55. B. Stander, J.C. Hart. Guaranteeing the Topology of an Implicit Surface Polygonization. Computer Graphics Annual Conference Series (Proc. SIGGRAPH 97) Aug., 1997, pp. 279-286. 56. J.C. Hart. Implicit formulations of rough surfaces. Computer Graphics Forum 16(2), June 1997, pp. 91-99. 57. B. Burch, J.C. Hart. Linear Fractal Shape Interpolation. Proc. Graphics Interface '97. May, 1997, pp. 155-162. 58. J.C. Hart, P.J. Flynn, W.O. Cochran. Similarity Hashing: A model-based vision solution to the inverse problem of recurrent iterated function systems. Fractals 5, Apr. 1997, pp. 39-50. 59. W.O. Cochran, J.C. Hart, P.J. Flynn. Fractal volume compression. IEEE Transactions on Visualization and Computer Graphics 2(4) Dec. 1996, pp. 313-322. 60. J.C. Hart. Sphere tracing: A geometric method for the antialiased ray tracing of implicit surfaces. The Visual Computer 12(10), Dec. 1996, pp. 527-545. 61. S. Worley, J.C. Hart. Hyper-rendering of hyper-textured surfaces. Proc. of Implicit Surfaces '96, Oct. 1996, pp. 99-104. 62. J.C. Hart, B. Baker. Implicit Modeling of Tree Surfaces. Proc. of Implicit Surfaces '96, Oct. 1996. pp. 143-152.

John C. Hart Page 7 7/1/2013 63. J.C. Hart. Fractal image compression and the inverse problem of recurrent iterated function systems. IEEE Computer Graphics and Applications 16(4) July 1996, pp. 25-33. 64. K. Albrecht, J. Hart, A. Shaw, and A.K. Dunker. Quaternion contact ribbons: A new tool for visualizing intra- and intermolecular interactions in proteins. Pacific Symposium on Biocomputing 1: 41-52, Jan. 1996. 65. D. Hepting, J.C. Hart. The escape buffer: Efficient computation of escape time for linear fractals. Proc. of Graphics Interface '95, May 1995. pp. 204-214. 66. J.C. Hart. Implicit formulations of rough surfaces. Proc. Implicit Surfaces '95, Apr. 1995, pp. 33-44. 67. B.T. Stander, J.C. Hart. A Lipschitz method for accelerated volume rendering. Proc. of the 1994 Symposium on Volume Visualization, Oct. 1994. pp. 107-114. 68. J.C. Hart. Distance to an Ellipsoid. Chapter in: Graphics Gems IV, P. Heckbert, Ed., Academic Press, 1994, pp. 113-119. 69. J.C. Hart, G.K. Francis, L.H. Kauffman. Visualizing quaternion rotation. ACM Transactions on Graphics 13(3) July 1994, pp. 256-276. 70. J.C. Hart. On recording virtual environments. Proc. of IEEE Visualization '93 Symposium on Research Frontiers in Virtual Reality, Nov. 1993, pp. 80-83. 71. J.C. Hart, G.W. Lescinsky, D.J. Sandin, T.A. DeFanti, L.H. Kauffman. Scientific and artistic investigation of multidimensional fractals on the AT&T Pixel Machine. Visual Computer 7(9) July 1993, pp. 346-355. 72. C. Cruz-Niera, D.J. Sandin, T.A. DeFanti, R.V. Kenyon, J.C. Hart. The CAVE audio visual experience automatic virtual environment. Communications of the ACM 35(6) June 1992, pp. 64-72. 73. J.C. Hart. The object instancing paradigm for linear fractal modeling. Proc. of Graphics Interface '92, Morgan Kauffman, May 1992, pp. 224-231. 74. J.C. Hart, T.A. DeFanti. Efficient antialiased rendering of 3-D linear fractals. Computer Graphics 25(3) (Proc. SIGGRAPH 91) Aug. 1991, pp. 91-100. 75. J.C. Hart, L.H. Kauffman, D.J. Sandin. Interactive visualization of quaternion Julia sets. Proc. of Visualization '90. IEEE Computer Society Press. Oct. 1990, pp. 209-218. 76. J.C. Hart, A. Norton. Use of curves in rendering fractures. Proc. of SPIE/SPSE Symposium on Curves and Surfaces in Computer Vision and Graphics. Feb. 1990. 77. J.C. Hart, D.J. Sandin, L.H. Kauffman. Ray tracing deterministic 3-D fractals. Computer Graphics 23(3) (Proc. SIGGRAPH 89) Aug. 1989, pp. 289-296. Books, Invited Book Chapters and Edited Course Notes

78. M. Olano, W. Heidrich, J. Hart and M. McCool, Real Time Shading, AK Peters, July 2002. 79. J.C. Hart, "Procedural Geometry," Chapter in Modeling and Texturing, a Procedural Approach, 3rd Edition, D. Ebert, Editor, Morgan Kauffman, November 2002. 80. J.C. Hart, "Real-Time Procedural Solid Texturing," Chapter in Modeling and Texturing, a Procedural Approach, 3rd Edition, D. Ebert, Editor, Morgan Kauffman, November 2002. 81. D. Ebert and J. Hart, Editors, “Procedural Implicit Techniques for Modeling and Texturing," ACM SIGGRAPH 1998 Course Notes, July 1998. 82. D. Ebert and J. Hart, Editors, “New Frontiers in Modeling and Texturing,” ACM SIGGRAPH 1997 Course Notes, August 1997. 83. J. Hart and D. Saupe, Editors, “Fractal Models for Image Synthesis, Compression and Analysis,” ACM SIGGRAPH 1996 Course Notes, August 1996.

John C. Hart Page 8 7/1/2013 84. J. Hart, Editor, “New Directions for Fractal Modeling in Computer Graphics,” ACM SIGGRAPH 1994 Course Notes, July, 1994. 85. J. Hart and K. Musgrave, Editors, “Fractal Modeling in 3-D Computer Graphics and Imaging,” ACM SIGGRAPH 1991 Course Notes, July 1991. Patents

86. H. Fang and J.C. Hart, Methods and Systems for Image Modification. #7,365,744. Filed: 26 July 2004, Granted: 29 April 2008. 87. S. Tibbitts, T. Coleman and J.C. Hart. Antialiased Procedural Solid Texturing Hardware. Provisional Patent #60,088,879. Evans & Sutherland, 1998. Invited Papers, Articles, Tech Reports and Other Publications

88. S.V. Adve, V.S. Adve, G. Agha, M.I. Frank, M.J. Garzaran, J.C. Hart, W.W. Hwu, R.E. Johnson, L.V. Kale, R. Kumar, D. Marinov, K. Nahrstedt, D. Padua, M. Parthasarathy, S.J. Patel, G. Rosu, D. Roth, M. Snir, J. Torrellas, C. Zilles. Parallel Computing Research at Illinois: The UPCRC Agenda. Whitepaper, Nov. 2008. 89. S. Dong, P.-T. Bremer, M. Garland, V. Pascucci and J.C. Hart. Quadrangulating a Mesh using Laplacian Eigenvectors. Tech Rep. UIUCDCS-R-2005-2583, June 2005. 90. P. Lacz and J.C. Hart. Procedrual Geometric Synthesis on the GPU. Poster (with accompanying manuscript) for SIGGRAPH 2004 and GP2: The ACM Workshop on General Purpose Computing on Graphics Processors, Aug. 2004. 91. J.D. Hall and J.C. Hart. GPU Acceleration of Iterative Clustering. Poster (with accompanying manuscript) for SIGGRAPH 2004 and GP2: The ACM Workshop on General Purpose Computing on Graphics Processors, Aug. 2004. 92. M. Mullan, R. Whitaker and J.C. Hart. Procedural Level Sets. Manuscript presented at NSF/DARPA CARGO Annual Meeting, May 2004. 93. J.D. Hall, N.A. Carr and J.C. Hart. Cache and Bandwidth Aware Matrix Multiplication on the GPU. Tech. Report UIUCDCS-R-2003-2328, May 2003. 94. M. Kameya, and J.C. Hart. Bresenham noise. SIGGRAPH 2000 Conference Abstracts and Applications, July 2000. 95. J.J. Kim and J.C. Hart. Contour-Based Polygonization of Regular Grid Terrain Data. Proc. Western Computer Graphics Symposium. Mar. 1999. 96. A. Aceves, K. Hammil and J.C. Hart. Proposal and Partially Implemented: The Studio: A Large High Resolution Immersive Projection System for Research and Education. Proc. Western Computer Graphics Symposium. Mar. 1999. 97. M. Kameya and J.C. Hart. Bit Width Necessary for Solid Texturing Hardware. Proc. Western Computer Graphics Symposium. Mar. 1999. 98. N. Carr and J.C. Hart. APST Antialiased Procedural Texturing Interface for OpenGL. Proc. Western Computer Graphics Symposium. Mar. 1999. 99. C. Kulratanayan and J.C. Hart. Restructuring the Scene Graph for Efficient Visibility of Natural Scenes. Proc. Western Computer Graphics Symposium. Mar. 1999. 100. J.C. Hart. Computational Topology for Shape Modeling. Invited Talk and Paper. Proc. Shape Modeling International '99, Univ. Aizu, Japan, Mar. 1999, pp. 36-45. 101. J.C. Hart. Morse Theory for Computer Graphics. WSU Technical Report EECS-97-002. Chapter in ``New Frontiers in Modeling and Texturing,'' SIGGRAPH '97 course notes, J. Hart, D. Ebert eds., Aug. 1997.

John C. Hart Page 9 7/1/2013 102. I.M. Danciu, J.C. Hart. Fractal Color Image Compression in the L*a*b* Uniform Color Space. Poster. Abstract in: Proc. of Data Compression Conference '97. IEEE Computer Society Press, Apr. 1997, p. 434. 103. B.T. Stander, J.C. Hart. Topologically Guaranteed Blobby Surface Polygonization. Proceedings of Western Computer Graphics Symposium. Mar. 1996. pp. 1-9. 104. J.C. Hart. On the Hyperbolic Plane and Chinese Checkers. Proceedings of Western Computer Graphics Symposium. Mar. 1996. pp. 69-75 105. W.O. Cochan, J.C. Hart, P.J. Flynn. Similarity and Affinity Hashing. Proceedings of Western Computer Graphics Symposium. Mar. 1996. pp. 89-98. 106. B.T. Stander, J.C. Hart. Interactive re-polygonization of blobby implicit curves. Proceedings of Western Computer Graphics Symposium. Mar. 1995. 107. W.O. Cochran, J.C. Hart, P.J. Flynn. Principal component classification for fractal volume compression. Proceedings of Western Computer Graphics Symposium. Mar. 1995. 108. J.C. Hart. Sphere tracing: simple robust antialiased rendering of distance-based implicit surfaces. WSU Technical Report EECS-93-015. Chapter in ``Design, Visualization and Animation of Implicit Surfaces,'' SIGGRAPH '93 course notes, J. Bloomenthal, B. Wyvill, eds., Aug. 1993. 109. J.C. Hart. Ray Tracing Implicit Surfaces. WSU Technical Report EECS-93-014. Chapter in ``Design, Visualization, and Animation of Implicit Surfaces,'' SIGGRAPH '93 intermediate course notes, J. Bloomenthal and B. Wyvill, eds., Aug. 1993. 110. T.A. DeFanti, J.C. Hart, D.J. Sandin, L.H. Kauffman. Visualization of multidimensional fractals. Proceedings of the Argonne National Lab. Seventh International Conference on Advanced Science and Technology. Mar. 1991, pp. 289-298. 111. T.A. DeFanti, D.J. Sandin, G.W. Lescinsky, J.C. Hart, M.D. Brown, L.H. Kauffman. Simulacra/Stimulacra::Fractal. Art Futura, Jan. 1991. 112. J.C. Hart. Parallel algorithms for visualization of multidimensional fractal objects (extended abstract.) Electronic Imaging East '90. Nov. 1990, pp. 459-462. 113. D.J. Sandin, J.C. Hart, L.H. Kauffman. Interactive visualization of complex, stacked and quaternion Julia sets. Proceedings of Ausgraph '90, Sep. 1990. (Invited paper.) 114. T.A. DeFanti, D.J. Sandin, J.C. Hart, G.W. Lescinsky. One picture's worth a thousand gigaflops (One animation's worth a thousand teraflops). Pixel 1(3) July 1990, pp. 40-41. 115. J.C. Hart, A. Norton. Use of curves in rendering fractures. IBM Technical Report. Aug. 1989. Film and Animation Credits

116. Executive Producer (with C. Machover). “The Story of Computer Graphics.” A SIGGRAPH Production of a feature-length documentary on the human struggle to bring computer graphics from the inspired revelation that computers can be used to draw pictures to the present, where low-cost graphics and the Internet combine to provide virtual environments for people to communicate. Premiered at a special event in the Shrine Auditorium, LA, as part of the SIGGRAPH 99 Computer Animation Festival. 117. Contributor. “Air on the Dirac Strings.” Produced by L.H. Kauffman, G.K. Francis, D.J. Sandin. SIGGRAPH '93 Electronic Theater. SIGGRAPH Video Review 93, Aug. 1993. 118. Producer. “SIGGRAPH 93 Technical Session Sampler.” SIGGRAPH '93 Electronic Theater. Video compilation, narrated by J. Blinn. SIGGRAPH Video Review 91, Aug. 1993 119. Producer. “Highlights from the SIGGRAPH '92 Technical Session.” SIGGRAPH '92 Electronic Theater. Video compilation, narrated by J. Blinn.

John C. Hart Page 10 7/1/2013 120. Producer/Director/Animator. “Fun with Octrees: Graph Topologies on the Recurrent Cube.” SIGGRAPH '92 Animation Screening Room. SIGGRAPH Video Review 87, Aug. 1992. Appears in: ``The Fractal Universe: Animation,'' Media Magic, 1993. 121. Producer/Director/Animator. “unNatural Phenomena.” SIGGRAPH '91 Electronic Theater. SIGGRAPH Video Review 71, Aug. 1991. Appears in: ``The Fractal Universe: Animation,'' Media Magic, 1993. Excerpts appear in: ``Beyond The Minds Eye,'' Mirimar, and ``Prime Time Live,'' ABC. 122. Producer/Director/Animator (with S. Das.). “Sierpinski Blows His Gasket.” SIGGRAPH '90 Animation Screening Room. SIGGRAPH Video Review 61, 1990. First Runner-Up, Truevision Videographics Competition, 1990. Appears in: ``The Fractal Universe: Animation,'' Media Magic, 1993. 123. Producer/Director/Animator. “Dynamics in the Quaternions.” SIGGRAPH Video Review 42, 1989. Appears in: ``The Fractal Universe: Animation,'' Media Magic, 1993.  Educational Activities  Postdoctoral Associates

• Matei Stroila, 2005-6. Research Scientist, NAVTEQ. • Peer-Timo Bremer, 2004-6. Research Scientist, Lawrence Livermore National Labs. • Nate Carr, 2004-5. Senior Research Scientist, Adobe. Ph.D. Students

• Mingcheng Chen. • Victor Lu. Nokia. • Mahsa Kameya. Now at Microsoft. MSR Internship 2010. • Yuntao Jia (2010). Now at Facebook. • Jared Hoberock (2008). Research Scientist, Nvidia. NVidia Fellowship 2005,2007. NVidia Internship 2005. • Xinli Ni (2007). Now at Google, Microsoft Internship 2005. • Hui Fang (2006). Now at Google. Adobe Internship 2005. • Nate Carr (2004). Senior Research Scientist, Adobe. NVidia Fellowship 2002 and 2003. Intel Internship 1999. NVidia Internship 2002. • Wayne Cochran (1998). Assistant Professor, School of Engineering and Computer Science, Washington State University, Vancouver. • Bart Stander (1997), Full Professor, Computer and Information Technology, Dixie State College of Utah. M.S. Students

• 2013: JohnMark Lau. • 2011: Rajesh Bhasin. • 2009: Apeksha Godiyal. Microsoft Visio. • 2005: Jerry Talton (Ph.D. Stanford, 2012), Tony Kaap (Alias), Matei Stroila (NAVTEQ).

John C. Hart Page 11 7/1/2013 • 2004: Jesse Hall (NVidia, Microsoft Research Internship 2002. NVidia Fellowship 2003 and 2004), Patrick Lacz (RadTIME), Wen Su (NVidia). • 2002: Hui Fang (continued), Ed Bachta (visualization programmer at IUPUI) • 2000: Nate Carr (continued), Jay Kim. • 1999: Chanikarn Kulratanayan. • 1998: Jeyprakash Michaelraj (Alias). • 1997: Paul Sherman (Periphery Consulting). • 1996: Ioana Danciu. (Adobe), Brandon Burch (WSU Instructor), Yingjun Yu (Nokia), Wenbiao Jiang (CFD Research), Kurt Albrecht. • 1994: Anand Ramagapalrao (Microsoft), Wayne Cochran (continued). • 1992: Yongqi Yang (Adobe). Courses Taught

UIUC Courses

• ENG 198 Grand Challenges (Fall 2012) • CS 418 Interactive Graphics (since 2007) • CS 419 Production Graphics (since 2000) • CS 519 Scientific Visualization (since 2001) • CS 497 JCH Advanced Shape Modeling (Fall 2000) • CS 498 Procedural Modeling and Shading in Computer Graphics (Fall 2002) • CS 498 Particle System Programming (Spring 2004, voluntary addition to course load) • CS 498 Shape Modeling (Fall 2004) • CS 598 JCH Surface Reconstruction (2008) • CS 491 EH Computational Topology Seminar (co-organized with J. Erickson) • CS 491 GHY Graphics Seminar (co-organized with M. Garland, Y. Yu)

WSU Courses

• CptS 330 Numerical Computing • CptS 442 Computer Graphics • CptS 443 Computer-Human Interaction • CptS 548 Advanced Computer Graphics

SIGGRAPH Reviewed One-Day Courses

• 2005: “Modern Techniques for Implicit Modeling” (Terry Yoo, James O’Brien), and “GPU Shading and Rendering” (Marc Olano) • 2004: “Real Time Shading” (Marc Olano)

John C. Hart Page 12 7/1/2013 • 2003: “Beyond Blobs: Recent Advances in Implicit Surfaces” (Terry Yoo, Greg Turk) and “Real Time Shading” (Marc Olano) • 2002: “Beyond Blobs: Recent Advances in Implicit Surfaces” (Terry Yoo and Greg Turk, org.) and “Real Time Shading” (Marc Olano). • 2001: “Real Time Shading” (Marc Olano) • 2000: “Approaches for Procedural Shading on Graphics Hardware” (Marc Olano) • 1998: “Procedural Implicit Techniques for Modeling and Texturing” (Co-organizer with D. Ebert) • 1997: “New Frontiers in Modeling and Texturing” (Co-organizer with D. Ebert.) • 1996: “Fractal Models for Image Synthesis, Compression and Analysis” (Co-organizer with D. Saupe), “Procedural Modeling, Texturing, and Animation Techniques” (D. Ebert) and “Implicit Surfaces for Geometric Modelling and Computer Graphics (Jai Menon and Brian Wyvill) • 1995: “Procedural Modeling, Texturing, and Animation Techniques” (D. Ebert). • 1994: “New Directions for Fractal Modeling in Computer Graphics” (Course organizer). • 1993: “Design, Visualization and Animation of Implicit Surfaces” (J. Bloomenthal, B. Wyvill). • 1992: “Fractals: from Folk Art to Hyperreality” (P. Prusinkiewicz). • 1991: “Fractal Modeling in 3-D Computer Graphics and Imaging” (Co-organizer with K. Musgrave).

Other

• Adler Planerarium, Scientific Visualization by Supercomputer. Chicago, Sept.-Nov. 1988. Invited Colloquia and Presentations

Note: colloquia presented for the purpose of interviewing have been omitted.

• University of Notre Dame, Center for Research Computing, “High Performance Computer Vision, An Oxymoron?,” May 2012. • Graphics Interface Conference, Keynote: Assistive Technology for the Aesthetically Impaired,” May 2011. • University of Iowa Computing Conference, organized and invited by U. Iowa students, “Assistive Technology for the Aesthetically Impaired,” Feb. 2010. • AMS MathViz09, U. Illinois, “It’s Nice to See This Stuff Actually Used for Something,” Mar. 2009. Host: George Francis. • INRIA, Grenoble, France, “Assistive Technology for the Aesthetically Impaired,” Sep. 2009. Host: Elmar Eisemann. • Texas A&M University. Distinguished Lecture: “Assistive Technology for the Aesthetically Impaired,” Feb. 2008. Host: Scott Schaeffer. • NAVTEQ. “Industry Collaborations,” Nov. 2007, Chicago, IL. Host: Matei Stroila. • Adobe-MIT Research Retreat. “Textureshop Redux,” Oct. 2007, Cambridge, MA. Host: David Salesin and Fredo Durand. • University of Konstanz Summerschool. “Computational Topology of Implicit Surfaces” and “Computational Topology of Meshes,” Sep. 2006, Gaschurn, Austria. Host: Dietmar Saupe.

John C. Hart Page 13 7/1/2013 • Wolfram Research. “Mathematical Visualization,” May 2006, Champaign, IL. Host: Roger Germundsson. • Carnegie-Mellon University. “Surface Constrained Particle Systems” and “Global Illumination on the GPU,” Feb. 2005. Host: Doug James. • Imagina. “Global Illumination on the GPU,” Monaco, Feb. 2005. • 3D Festival. “Global Illumination on the GPU,” Copenhagen, Denmark, May 2004. • INRIA, Grenoble, France, “Global Illumination on the GPU,” Mar. 2004, Host: Samuel Hornus. • University of Utah. “Global Illumination on the GPU,” Oct. 2003, Host: Chuck Hansen. • NVidia U. Keynote speaker. July 2003, Host: Herbert Hu. • Army High Performance Computing Research Center (AHPCRC) Workshop on Graphics Modeling, Simulation and Visualization. “Harnessing the Supercomputer in your PC’s Graphics Card,” June 2003. Host: Boquan Chen. • University of Illinois at Chicago (Math Dept.). “Computational Topology for Computer Graphics.” Apr. 2002. Host: Anatoly Libgober. • Colorado Springs SIGGRAPH Chapter. “The Quest for Real-Time Procedural Solid Texturing.” Mar. 2001. Host: Dino Schweitzer. • Northwestern University. “The Quest for Real-Time Procedural Solid Texturing.” Oct. 2000. Host: Benjamin Watson. • Shape Modeling International. Invited Speaker, Aizu, Japan, March 1999. • Universität Freiburg. “Recurrent Modeling.” Sep. 1997. Host: Dietmar Saupe. • University of Utah. “The Topology of Implicit Surfaces.” Feb. 1997. Host: Chuck Hansen. • University of Illinois at Chicago (EECS Dept.). “The Topology of Implicit Surfaces.” Feb. 1997. Host: Tom DeFanti. • Interval Research. “Recurrent Modeling.” July 1996. Host: Sally Rosenthal. • University of Washington. “Recurrent Modeling.” Dept. of Computer Science and Engineering. Jan. 1996. Host: Linda Shapiro. • Boeing Information & Support Services. “Why Fractal Image Compression Isn't Fractal.” Computer Graphics & Multimedia Group. Jan. 1996. Host: David Kerlick. • University of Idaho. “Why Fractal Image Compression Isn't Fractal.” Computer Science Dept. Nov. 1995. Host: Deborah Frincke. • NATO Advanced Study Institute on Fractal Image Compression and Image Analysis. “Similarity Hashing: A model-based vision solution to the inverse problem of recurrent iterated function systems.” July 1995. • Simon Fraser University. “Recurrent Modeling.” School of Computing Science. July 1995. Host: F. David Fracchia. • University of Calgary. “Procedural Geometric Instancing.” Dept. of Computer Science. Jan. 1994. Host: Przemyslaw Prusinkiewicz. • Purdue University. “Linear Fractals in Computer Graphics.” Computer Science Dept. June 1992. Host: Chandrajit Bajaj.

John C. Hart Page 14 7/1/2013  Professional Activities  Editorships and Paper Chairs

• Papers Co-Chair (with Scott Schaefer), Shape Modeling International, 2012. • Editor-in-Chief, ACM Transactions on Graphics, 2002-8. Past Editor-in-Chief, 2009-. • Associate Editor, ACM Transactions on Graphics, 2000-2. • Guest Editor, Communications of the ACM 35(6) June 1992. • Guest Editor, SIGGRAPH Video Review 96, ``Video Supplement to the Conference Proceedings,'' Aug. 1993. • Guest Editor (with E.E. Catmull), SIGGRAPH Video Review 86, ``Video Supplement to the Conference Proceedings,'' July 1992. Organizational Leadership

• ACM SIGGRAPH Advisory Board, 2005. • SIGGRAPH Small Conferences Committee, 2010- • Chair, SIGGRAPH Service Award, 2005-8. • Director for Communications, SIGGRAPH Executive Committee, 1996-9. • Director at Large, SIGGRAPH Executive Committee, 1994-6. External Review Panels

• King Abdullah University of Science and Technology, Mar. 2012. • Science Foundation Ireland, Oct. 2006. • INRIA Systemes Cognitifs D, May 2006. Conferences Chaired

• Co-Chair (with Marie-Paule Cani), Shape Modeling International, MIT, June 2005. • Co-Chair (with K. van Overveld), Implicit Surfaces, Eindhoven, Netherlands, 1996. • Chair. Western Computer Graphics Symposium, Panorama, BC, 1996. Program Committees

• SIGGRAPH Papers Committee: 2001, 2006, 2007, 2010 • SIGGRAPH Asia Papers Committee, 2008. • SIGGRAPH Sketches Jury: 1998, 1999.

John C. Hart Page 15 7/1/2013 • Symposium on Geometry Processing, all since 2006. • Interactive 3D Graphics and Games, all since 2005. • Pacific Graphics, all since 2002. • Shape Modeling International, all since 1997. • Implicit Surfaces (all). • Eurographics 2004. • Graphics Hardware, all since 2004. • Web3D 2003. • IEEE Virtual Reality 2000, 2001, 2002. • Virtual Reality Annual International Symposium 1998. • Visualization and Mathematics 1997. • Supercomputing 1991-3, 1995. Memberships

• Association for Computing Machinery • ACM Special Interest Group on Computer Graphics and Interactive Techniques (SIGGRAPH) • IEEE Computer Society University Committees

Illinois

• Chair, Technology, Facilities and Services Committee (CS), 2013-. • Chair, Senate Subcommittee on IT (Campus), 2013-. • University Senate Executive Committee (Campus) 2013-. • University Technology Management Team (University of Illinois System), 2012-. • IT Governance Executive Committee (Campus), 2012-. • Chair, IT Governance Research Subcommittee (Campus), 2012-. • Executive Committee (College of Engineering), 2011-. • Chair, Engineering IT Steering Committee (College of Engineering), 2010-11. • Chair, IT@Illinois Stewarding Excellence Project Team (Campus), 2010. • Area Chair, Graphics and Human-Computer Interaction (CS), 2004-2011. • Senate (peer elected) (Campus), 2007-, • Senate IT Subcommittee (Campus), 2008-2010. • Human Factors Transition Committee (Campus), 2008-9. • Chair Search Committee (CS), 2007-9.

John C. Hart Page 16 7/1/2013 • Advisory Committee (peer elected) (CS), 2005-6. • Industry Relations Committee (CS), 2005-. • Technology, Facilities and Services Committee (CS), 2005-. • Engineering Open House CS Representative (CS), 2001-06. • Recruiting Committee, (CS), 2004, 2005. • Curriculum Committee (CS), 2002-3. • Distinguished Lecture Series (CS), 2000-2 (chair, 2001-2). • Computer Systems (CS), 2000-1. • Fellowships, Assistantships and Admissions (CS), 2000-1.

WSU

• School of EECS Computer Science Area Chair, 1998-2000. • School of EECS Computer Science Accreditation Coordinator, 1999-2000. • School of EECS Curriculum Committee 1998- (Chair, 1999-2000). • School of EECS Graduate Studies Committee 1993-8. • School of EECS Laboratory Committee 1994-6. • WSU Center for Visualization, Analysis and Design in the Molecular Sciences (VADMS) Advisory Board 1994-2000.

John C. Hart Page 17 7/1/2013 EXHIBIT D Manish Bhardwaj 118 Riverway, Apt #7 • Boston, MA 02215 • 617.510.0589 [email protected]

EDUCATION Massachusetts Institute of Technology Cambridge, MA 2005 - 2009 Ph.D., Electrical Engineering and Computer Science

Thesis: “Communications Design in the Observation Limited Regime”. Developed new modem techniques with potential to enhance battery lifetime of wireless clients by 10x.

1999 - 2001 S.M, Electrical Engineering and Computer Science

Thesis: “Power Aware Systems”. Advanced theory and practice of energy scalable circuits and wireless networks.

 Cited more than 400 times in peer-reviewed conferences and journals.  Named IBM Ph.D. Fellow (20 graduate students out of 350 nominees nationwide).  Published over 30 papers in circuits, design automation, computer architecture, VLSI, wireless, and networking.  Recipient of the MIT Graduate Award for “Excellence in Teaching”.

1993 - 1997 Nanyang Technological University Singapore Bachelor of Applied Science (Honors) in Computer Engineering

 Awarded Compaq Gold Medal, given to the top graduating student (class of 300 students).

 Received Sony Gold Medal for Honors thesis.

EXPERIENCE 2009 -Present Innovators In Health, Inc. Cambridge, MA Non-profit started by MIT alumni to enable data-driven healthcare delivery in the developing world.

Co-founder & CEO. Recruited the IIH team, raised money, delivered award-winning solutions, built capacity in communities with extremely limited access. Currently serves a population of close to 200,000 rural residents.

2011 - Present IPX Consulting, LLC. Cambridge, MA Startup providing intellectual property (IP) consulting services. Clients include Flashpoint Technology, Inc.; Saxon Innovations, LLC; Nazomi, Inc.; Graphics Properties Holding, Inc.; Tela, Inc., and Apple, Inc.

Founder and CEO.

2001 - 2005 Engim, Inc. Acton, MA Wireless semiconductor start-up focused on creating multi-channel, enterprise WLAN access points. The company raised $32M from Benchmark, Bessemer, and Matrix. Technology and patent portfolio acquired by Edgewater, Inc. of Ottawa, Canada.

Co-founder & VP, Chief Architect. Hands-on architect of industry’s first multi-channel, 162Mb/s, 802.11a/b/g WLAN chipset.

1997 - 1999 Siemens Semiconductors Singapore and Austria Member of Technical Staff Digital ASIC Designer; Inventor and Lead Architect  ALCA - An advanced VLIW digital signal processor (DSP); 2-3x faster than available DSP cores.  Renaissance - A highly parallel, vector co-processor; 2x faster for embedded DSP applications.

2005 - 2010 Consultant Cambridge, MA Communications Technology Specialist

 ABB, Oslo, Norway: Feasibility analysis of new technologies.  Schlumberger, Houston: Feasibility analysis of communications product.

EXHIBIT E Tamer Rizk

955 Massachusetts Avenue #310 - Cambridge, MA 02139 - 888.580.6895 x704 - [email protected]

SYNOPSIS A driven, hands-on technology leader inspiring innovation and delivering measurable results.

PROFESSIONAL Inficron Inc. Cambridge, MA CTO 07/2006 – Present . Lead architect on successful Silicon Valley based ventures in mobile, e-commerce and security. Contributor to open source JavaScript server side projects and frameworks. National media recognition for technical activities related to preserving Internet freedom. . Management of technology operations including KPI analysis, business process automation, budgeting, scheduling, agile feature driven development, unit testing, and production. . Technical mentorship of engineers including code and design reviews, promoting standards and best practices for security, performance, scalability and usability. . Business development including lead generation, solution proposals and plans, precise specifications, understandable reports, and compelling presentations. Negotiation of contracts with customers such as government and commercial entities. . Product development, branding, marketing and strategy on company software and solutions. . Lead technical member filing new intellectual property, litigation of breached contracts and assisting prosecution of IP infringement. . Spearhead data mining, analysis and visualization initiatives for clients, helping them to identify and pre-process data, perform dependency modeling as well as clustering and classification.

Inficron Inc. North Andover, MA Technical Manager 06/2004 - 07/2006 . Streamline roll out of software products across Microsoft and Linux platforms including development in C, C++, Java, Perl, Python and PHP. . Implementation of paradigms such as object-oriented design, functional programming, design patterns, refactoring; incremental and iterative processes such as agile development. . Oracle, PostgreSQL, MySQL, and MS SQL data architecture and modeling using OLAP and UML tools such as SQL Power Architect and StarUML. . Negotiation and execution of contracts with carriers such as Level 3, Qwest and XO Communications to facilitate datacenter network operations. Oversee network design, deployment and security. . Development of asynchronous routing infrastructure to enable traffic engineering and ISP cost control. Responsible for turning up Inficron peering with Level3 and Qwest. . Significant business development activities including spearheading meetings both nationally and internationally, marketing presentations and pitches, customer and capital solicitation.

955 Massachusetts Avenue #310 - Cambridge, MA 02139 - 603.247.3300 - [email protected]

Inficron Inc. Woodbridge, NJ Lead Software Architect 02/2002 - 06/2004 . Implementation of complete software development life cycle. Draft specifications, software development and evolution, and process quality management over multiple projects. . Lead developer on a number of web and mobile applications receiving national press. Provision of technical mentorship to engineering team including code and design reviews as well as enforcing coding standards and best practices. . Design, development and implementation of spatial analysis system utilizing C hooks, spatial indexes and geometry conversion to handle primitive spatial query implementation.

TDI Power Inc. Cedar Knolls, NJ Electrical Engineer 08/1998 - 01/2002 . Management of electronic and software projects including high frequency electronic circuit design, layout, high level and assembly programming, testing, failure mode analysis, certification, multi-sourced parts procurement, and budgeting. . Design, test, analysis, and simulation of switch mode power supplies. Choice of parts for optimum system performance, topology implementation, power magnetics, housekeeping functions, as well as feedback loop optimization for converters utilizing high frequency pulse width modulated switching with current mode control. . Client/Server TCP and UDP socket programming in C for system/PC remote communication and management. Embedded programming of PIC processors for test automation. Implementation using serial protocols such as GPIB, I2C and RS232. . Development of database driven intranet applications for management, purchasing and engineering, such as distributed schedules, parts search and dynamic requisitions. Fine-tuning of database queries using SQL. Performance enhancement of database queries via strategic index implementation.

TECHNICAL . Internet Freedom activities developing technology to combat protectionist measures in proposed legislation such as SOPA/PIPA, resulting in recognition by media such as Forbes, International Business Times, and ReadWriteWeb. . Participation in TeaJS and qteajs.org open source, high performance server side JavaScript platform development, running on V8 as an Apache 2.4 module in event multiprocessing mode. . Development of cloud base SSH VPN product, HushTunnel. Development of Win/Mac Java client and slave nodes running an OpenSSH mod in C. . Build and launch of The DSE, a B2B equipment marketplace, including product categorization and Lucene search, business process automation, and AI enabled content generation leading to #1 Google ranking for important keywords. Transfer of technology to new CTO and remain as board technical advisor. . Build and launch of end-to-end system, Presence.co, enabling businesses to offer location based virtual services to mobile clients, including intellectual property development and patent application. Development of HTML5 mobile application using Sencha Touch and custom libraries. Scala based Android port with reduced footprint using ProGuard treeshake. . Development of web and mobile multimedia aggregation and sharing service winning Nokia judge’s choice award. Development of mobile applications using Symbian C++ and utilizing FFmpeg to deliver an MMS to email gateway for mobile video content to web accounts. . Led development of Objective C based iPhone applications such as LiveDiamond for Stuller, the world’s largest diamond distributor.

955 Massachusetts Avenue #310 - Cambridge, MA 02139 - 603.247.3300 - [email protected]

. Design and programming of a mobile J2ME to web application on top of Movable Type, in order to extend mobile micro-blogging, featured in CNN Money. . Enable W3C support for non-blocking background worker threads in Internet Explorer using C#. . Creation of Microsoft calendar gadget software, with wide adoption on the Windows gadgets gallery. Server side API in Python using modules such as urllib2, xml.dom, and geopy. . Implementation and launch of community and collaboration projects such as an Elgg collaboration network, Open Atrium Intranet and workforce development tool. . Build and maintenance of IEEE Smart Grid Interoperability P2030 collaboration suite on top of Linux, Apache and mod_perl. . Creation and configuration of websites and databases for clients such as the Commonwealth of Massachusetts using frameworks such as Drupal on a replicated MySQL back-end. XHTML/CSS Standards compliant accessibility for patrons with disabilities. . Integration of payment processing using PayPal Website Payments Pro API and Authorize.net to create and power multiple bespoke ecommerce and billing systems. . Development of web crawling and data mining software using Perl LWP Crypt::SSLeay and XML::Parser with signature masking and proxy IP rotation. . Development of asynchronous routing software and infrastructure to enable traffic engineering and ISP cost control between Level3 and Qwest. Programming of multithreaded network and communications applications using C++ STL and Boost. . Application of Linux expertise to system installation/configuration, SSH administration, bash shell scripting, IPTables firewall customization, and system security. MTA management and spam filter design.

CERTIFICATES Advanced Entrepreneurship Developing Innovative Ideas for New Companies . Professor Clint Korver . Dr. James V. Green University of Stanford Venture Labs University of Maryland Organizational Analysis Computing for Big Data . Dr. Daniel McFarland . Dr. Roger Peng Stanford University Johns Hopkins University Operations Management (distinction) Business Strategy . Dr. Christian Terwiesch . Dr. Michael J. Lenox University of Pennsylvania, Wharton University of Virginia

DEGREE Bachelor of Science, Electrical and Computer Engineering May, 2001 . The New York Institute of Technology (NYIT)

ABOUT Characteristics: Proactive and inspirational leader, capable of optimizing productivity under pressure. -- Passion for directing product builds for companies, and launching projects from the ground up. -- As comfortable doing as delegating, working in large groups and independently. Computing: OS: Linux, Mac, Windows. -- Programming: C, C++, C#, Java, R, Perl, Python, PHP, JavaScript, SQL. – Databases/stores: Oracle, PostgreSQL, MySQL, MariaDB, BDB, MS SQL, SQLite, Redis, Memcached. -- Office: Project, Visio, Excel, PowerPoint, Word.

955 Massachusetts Avenue #310 - Cambridge, MA 02139 - 603.247.3300 - [email protected]

Exhibit F Curriculum Vitae THOMAS Y. YEH C: (310) 849-7411 [email protected]

Objective:

To explore an expert consulting role for the law firm of Mintz Levin.

Research Interests:

Real-Time Physics Simulation, Interactive Entertainment, Processor Microarchitecture, Chip- Multiprocessor, Stream Processing, Perceptual Error Tolerance, Computer Arithmetic.

Education:

University of California – Los Angeles Doctor of Philosophy degree in Computer Science, June 2007 Advisors: Professor Glenn Reinman and Professor Petros Faloutsos

University of California – Los Angeles Masters of Science degree in Computer Science, June 1999 Advisor: Professor Milos Ercegovac

University of California – Berkeley Bachelor of Science degree in Electrical Engineering and Computer Science, June 1997 General and Computer Science Focuses

Thesis:

Architectural and Algorithmic Acceleration of Real-Time Physics Simulation in Interactive Entertainment

Research:

Architecture for Real-Time Physics Simulation: Future interactive entertainment applications will feature the physical simulation of thousands of interacting objects using explosions, breakable objects, cloth effects, and fluid simulation. While these applications require a tremendous amount of performance to satisfy the minimum frame rate of 30 FPS, there is an embarrassing amount of parallelism in physical simulation. We propose and characterize a set of forward-looking benchmarks, PhysicsBench, to represent future physics load [2]. In response to the workload’s demand, we propose the ParallAX architecture [2] which consists of two sets of cores: a set of larger cores handles the serial and coarse-grain parallel components, and a flexible set of smaller cores exploits fine-grain parallelism. ParallAX combines intelligent, application-aware L2 management, dynamic allocation of smaller cores to larger cores, and tight coupling of the two sets of cores.

Perceptual Error Tolerance: The error tolerance of human perception offers opportunities to trade numerical accuracy for performance in physics-based simulation. However, most previous approaches either focus exclusively on understanding the tolerance of the human visual system or burden the application developer with case-specific implementations. In [3], based on a detailed set of perceptual metrics, we propose a methodology to identify the error tolerance of physics simulation for interactive entertainment. In [4], we leverage error tolerance at the algorithmic level with Fast Estimation with Error Control (FEEC). FEEC allows dependent components to use intermediate results while the full simulation executes in parallel. Error propagation is eliminated by correcting at frame boundaries. In [1], we leverage perceptual error tolerance at the arithmetic operation level. We propose a hierarchical floating-point unit (FPU) that leverages dynamic precision reduction to enable efficient FPU sharing among multiple cores.

Scalable Cache Design for Chip-Multiprocessors: Both per-core and overall throughput of chip- multiprocessors (CMPs) are significantly impacted by the organization of the lowest level on-chip cache due to increased demand and contention. To complicate the problem, cache demand changes dynamically with phase changes, context switches, power saving features, and thread assignment to asymmetric cores. We propose PDAS [5], a physically distributed NUCA L2 cache design with an adaptive sharing mechanism. Each core independently measures its dynamic need. Then, all cache resources are managed to improve utilization, reduce migration, and lower interference. Per-core performance degradation is bounded while overall throughput is optimized.

Refereed Publications:

[1] Thomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, and Glenn Reinman. The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. In 40th International Symposium on Microarchitecture (MICRO).

[2] Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, and Glenn Reinman. ParallAX: An Architecture for Real-Time Physics, In 34th International Symposium on Computer Architecture (ISCA), Jun 2007.

[3] Thomas Y. Yeh, Glenn Reinman, Sanjay J. Patel, and Petros Faloutsos. Fool me Twice: Exploring and Exploiting Error Tolerance in Physics-Based Animation, ACM Transactions on Graphics (TOG ) – accepted with major revisions, 2007

[4] Thomas Y. Yeh, Petros Faloutsos, and Glenn Reinman. Enabling Real-Time Physics Simulation in Future Interactive Entertainment, In ACM SIGGRAPH Video Game Symposium (Sandbox), Jul 2006.

[5] Thomas Y. Yeh and Glenn Reinman. Fast and Fair: Data-stream Quality of Service, In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Sep 2005.

[6] Thomas Y. Yeh and Hong Wang. Redundant Arithmetic Optimizations, In 6th Annual European Conference on Parallel Computing (Euro-Par), Aug 2000.

Patents:

Optimization of Time-Critical Software Components for Real-Time Interactive Applications, United States Patent 7583262 [Awarded]

Optimal Redundant Arithmetic for Microprocessor Design, United States Patent 6848043 [awarded]

Method and Apparatus for Preventing Undesirable Packet Download With Pending Read/Write Operations in Data Packet, United States Patent 7058065 [awarded]

Method and Apparatus for Improving Dispersal Performance in a Processor Through the Use of No-op Ports, United States Patent 6721873 [awarded]

Awards:

Nominated to compete for UCLA’s 2007 Edward K. Rice Outstanding Doctoral Student Award

Selected by UCLA CS department to compete for 2006 IBM fellowship

Employment:

IEnteractive, Irvine, CA Sept 07 – Present Founder / CEO  Founded company with Air Force SBIR funding  Principal investigator of SBIR grant to develop software tools to facilitate application parallelization for many-core execution  Secured business and developed physics benchmarks for gaming console company  Main developer for OpenGL simulator project with UIUC  Main author of multiple SBIR grant proposals in GPU computing

Employment Continued:

UCLA, Los Angeles, CA Sept 03 – June 07  Research Assistant in Microprocessor Architecture Researchers Lab  Teaching Assistant for Logic Design, Parallel and Distributed Computing, Computer Systems Architecture, and Digital Design Laboratory  Proposed and guided Masters student thesis on defining gaming AI workload  Supervised four undergraduate research projects (two honor student projects)

Independent Consultant, New York, NY Nov 02 – Aug 03  Prior work search for patent litigations

Sun Microsystems, Sunnyvale, CA Mar 02 – Oct 02 Microarchitect [Ultrasparc 5] Memory Scheduling Window  Improved critical sub-block TRB timing by ~40%  Found major memory architectural bug and drove resolution  Owner of Design For Testing  Designed ASI logic  Contributed to sub-block to sub-block timing

Clearwater Networks / Xstream Logic, Los Gatos, CA Jan 01 – Feb 02 Design Engineer [Network Processor]  Owner of 50+% of the entire chip area: data cache, packet memory, and vector-load datapath  All designs have 0 functional bugs and meet timing  Identified memory bottleneck and architected solution to improve product performance by ~23%  Drove resolution of tools, directed testing, and monitor coverage issues  Worked on floorplan, pin placement, memory placement/orientation with physical team.

Intel Corporation, Santa Clara, CA Sep 99 – Jan 01 IA64 Microarchitect/Logic Designer [Montecito]  Investigated IA64 ISA arithmetic extension with circuit, logic, and architecture teams  Investigated multi-threading technologies  Designed Instruction Prefetcher for multi-threading processor  Modified existing uArch interface/validation tool to support uArch changes  Rotation Engineer Program buddy coordinator and interviewer

IA64 Mircoprocessor Researcher  Ranked and rated 1st in peer group with outstanding performance and faster trending  Presented redundant arithmetic research to design team  Analyzed hot-spots and pointer-chasing on Olden Benchmarks

Mobile Platform Marketing  Developed marketing plan for notebook product marketing and strategic planning  Awarded for meeting deadlines on short notice  Competitive analysis on Transmeta at the Embedded Processor Conference  Recognized for demonstrating technologies at Intel Developer Forum

Intel Corporation, Hillsboro, OR Jan 98 - Aug 98 Itanium Chipset Verification [Merced]  Developed tests that generate random traffic patterns  Found 7 design bugs  Awarded for outstanding effort during period of heavy team absence

SBE Inc., San Ramon, CA Jan 96 - May 96 Hardware Engineer  Project leader in redesign of PCI bus based E1/T1 network card

Training:

Situational Leadership, Platform Marketing, Break-through System, Presentation Skills, Behavioral Interviewing.

Activities:

Habitat for Humanity, Sports Car Club of America, Chinese American Baseball and Softball Association, martial arts, rollerblading, tennis, basketball, biking, reading.

Tools:

Open Dynamics Engine, Povray, Simics, Gems, Ptlsim, SimpleScalar, Synopsys Design Compiler, Virage, Signalscan, Clearcase, CVS, RCS, Visio, X-windows, C, C++, Verilog, System-C, VHDL, Java, OpenGL, Perl, SQL, LISP, Unix, Linux, Windows, SunOS, AIX, Excel, Word, PowerPoint, Access, Visual Interdev, Front Page, Star Office.

Personal:

US citizen. Fluent in Chinese. Basic German and Japanese. Extensive international travel.

References:

Professor Glenn Reinman Computer Science Department University of California – Los Angeles 310-794-9755 E-mail: [email protected]

Dr. Sanjay J. Patel Professor at University of Illinois at Urbana-Champaign Founder and CEO of Nuvixa E-mail: [email protected]

Dr. Enric Musoll Xpliant E-mail: [email protected]

Exhibit GG Milos Prvulovic

Associate Professor School of Computer Science Georgia Institute of Technology Klaus Building, 266 Ferst Drive Atlanta, GA 30332-0280, USA Phone: (404) 385-6364 E-mail: [email protected]

Table of Contents

Educational Background 2

Employment History 2

Current Fields of Interest 2

I. Teaching 3 A. Courses Taught ...... 3 B. Curriculum and Course Development ...... 4 C. Individual Student Guidance ...... 5 D. Teaching Honors and Awards ...... 7

II. Research and Creative Scholarship 8 A. Thesis ...... 8 B. Published Journal Papers (refereed) ...... 8 C. Published Books and Parts of Books (Refereed) ...... 9 C.1. Chapters in Books ...... 9 D. Conference Presentations ...... 9 D.1. Conference Presentations with Proceedings (refereed and archival) ...... 9 D.2. Conference Presentations with Proceedings (refereed) ...... 11 D.3. Conference Presentations with Proceedings (abstract refereed) ...... 11 D.4. Conference Presentations without Proceedings (abstract refereed) ...... 11 E. Other ...... 12 E.1. Technical Reports ...... 12 E.2. Software ...... 12 F. Research Proposals and Grants (Principal Investigator) ...... 12 G. Research Honors and Awards ...... 13

III.Service 14 A. Professional Activities ...... 14 A.1. Memberships and Activities in Professional Societies ...... 14 A.2. Conference Committee Activities ...... 14 B. On-Campus Georgia Tech Committees and Service ...... 15 C. Member of Ph.D. Committees ...... 15

IV.National and International Professional Recognition 18 A. Invited Conference Session Chair ...... 18 B. Editorial and Reviewer Work ...... 18 C. Patents ...... 19

Printed: April 26, 2013 Modiﬁed: April 26, 2013 Page 1 of 19 Educational Background

Degree Year University Field

Ph.D. 2003 University of Illinois, Computer Science Urbana, IL, USA. M.S. 2001 University of Illinois, Computer Science Urbana, IL, USA. B.Eng. 1998 University of Belgrade, Electrical Engineering Belgrade, Yugoslavia.

Employment History

Title Organization Years

Associate Professor School of Computer Science 2009-present Georgia Institute of Technology, Atlanta, GA Assistant Professor School of Computer Science 2003-2009 Georgia Institute of Technology, Atlanta, GA Research Assistant Department of Computer Science 2000-2003 University of Illinois, Urbana, IL Teaching Assistant Department of Computer Science 1998-2000 University of Illinois, Urbana, IL Research Intern HP Labs Summer 2000 Hewlett-Packard, Palo Alto, CA

Current Fields of Interest

Computer Architecture, with emphasis on architectural support for software engineering, many-core performance, security, and reliability.

Goals: The goal of my research is to design computer architectures that are fundamentally more secure, more reliable, easier to program, and have better performance/complexity/power tradeoffs. While the pri- mary focus of this research is to make fundamental contributions to computer architecture, its interdisciplinary nature also involves signiﬁcant contributions in the areas of security, software engineering, and reliability and fault tolerance. My recent work involves hardware mechanisms to 1) protect against physical (hardware) attacks, untrusted system software, and untrusted system components, 2) perform runtime checks to improve software reliability, and 3) identify performance limiters in many-core execution. Each of these projects will enable important advances that change the target property of the system not only quantitatively (more can be done), but also qualitatively (new things become possible). In general, reducing runtime overheads of hardware security and software monitoring is beneﬁcial for systems and users that have to use them. However, when overheads are negligible, security, reliability, and monitoring tools and mechanisms can be adopted in all systems and remain active always, instead of relying on users to decide when they should be activated. This can help build new self-repairing and self-tuning systems that deal with security, reliability, correctness, and performance problems automatically and transparently.

Milos Prvulovic Complete C.V. Page 2 of 19 I. Teaching

A. Courses Taught The “Effectiveness as Teacher” data is taken from course-instructor surveys conducted by Georgia Tech. The question on the survey form ﬁlled by students is “Considering everything, the instructor was an effective teacher” with possible selections from 1 (strongly disagree) to 5 (strongly agree). The median rating of instructors of classes taught between 2001 and 2010 in the College of Computing is 4.5 for small classes (fewer than 16 students), 4.13 for medium-sized classes (16-35 students), and 4.11 for large classes (36-99 students).

Semester Course # of Effectiveness Comments Students as Teacher Spring 2013 CS 2200 115 Spring 2012 CS 7290 20 4.3 New Course Fall 2011 CS 3220 24 4.7 Spring 2011 CS 3220 18 4.4 Revised Fall 2010 CS 8804RSA 10 4.9 New Course Spring 2010 CS 3220 26 4.7 Redesigned Fall 2009 CS 6290 41 4.9 CS 4290 11 4.5 Cross-listed with CS 6290 Spring 2009 CS 6290 94 4.6 Revised CS 4290 7 4.5 Cross-listed with CS 6290 Fall 2008 CS 2200 78 4.1 Enhanced Fall 2007 CS 6290 71 4.8 Revised Fall 2007 CS 2200 60 4.6 Spring 2007 CS 8803AIC 9 4.8 Revised Spring 2007 CS 2200 88 4.2 Spring 2006 CS 8803AIC 12 4.4 New Course Fall 2005 CS 2200 71 4.1 Spring 2005 CS 2110 39 4.2 Fall 2004 CS 2200 56 3.8 Enhanced Spring 2004 CS 6290 37 4.4 Revised CS 4290 4 5.0 Cross-listed with CS6290 Seminars Fall 2008 CS 8001CPU 17 Seminar Fall 2008 CS 8001CAS 20 Seminar Fall 2007 CS 8001CAS 23 Seminar Spring 2007 CS 8001CAS 14 Seminar Spring 2006 CS 8001CAS 17 Seminar Fall 2005 CS 8001CAS 11 Seminar Spring 2005 CS 8001CAS 19 Seminar Fall 2004 CS 8001CAS 12 Seminar Spring 2004 CS 8001CAS 1 Seminar

Milos Prvulovic Complete C.V. Page 3 of 19 Course titles: CS 8804RSA Reliability and Security in Computer Architecture (now CS 7292) CS 8803AIC Advanced Issues in Computer Architecture CS 7290 Advanced Microarchitecture CS 6290 High-Performance Computer Architecture CS 4290 Advanced Computer Architecture CS 3220 Processor Design CS 2200 Introduction to Computer Systems & Networks CS 2110 Computer Organization & Programing CS 8001CAS Computer Architecture Seminar CS 8001CPU Computer Architecture Colloquium

B. Curriculum and Course Development CS 7290 Advanced Microarchitecture (Spring 2012): This is an advanced computer architecture class, taken primarily by PHD students in this area and by MS students in the Computer Architecture specialization. It covers the details of how a modern microprocessor works, including superscalar fetch and multi-branch prediction, decoding of multiple variable-length instructions, instruction wakeup and select, superscalar execution and bypass, load/store handling, and a detailed overview of several real-world microprocessors.

CS 7292 (was CS 8804RSA) Reliability and Security in Computer Architecture (Taught in Fall 2010): This is an entirely new course that is intended to be part of our regular computer architecture curriculum, and covers the entire spectrum of reliability and security concerns and solutions in modern computer architectures, such as device degradation over the lifetime of modern nanoscale silicon devices, extreme low-power operation, support for process isolation and protection, isolation of virtual machines running on the sam physical machine to improve fairness and reduce the possiblity of cross-VM snooping attacks, and physical snooping concerns.

CS 6290 High-Performance Computer Architecture (Spring 2009): This course was co-taught with four sections, one for undergraduates in Atlanta (9 students), one for graduates in Atlanta (56 students), one for graduates in GT-Lorraine via distance learning (9 students), and one for graduate students at Korea University via a live video link (29 students). The fact that the course spanned three contintinents and had both undergraduate and graduate students posed unique challenges and required major changes in the way lectures were delivered, the way assignments and exams were coordinated and graded, the way students were kept engaged, and the course material that had to be reviewed and taught. Course material was also revised due to new developments in the area of computer architecture (e.g. the rise of multi-core machines) and new (heavily revised) edition of the texbook.

CS 8001 CPU - Computer Architecture Colloquium (2008): This is a seminar in which we invited external speakers to give talks on topics and trends in computer architecture. At the time, our regular computer architecture seminar (CS 8001 CAS) used to be the venue for the occasional talk by external visitors. With the growth of our computer architecture group and with our increased research presence in top computer architecture conferences, our regular seminar schedule was completely ﬁlled with student’s research presentations and practice talks. At the same time, we hosted external visitors much more often. As a result, we started a new colloquium for external visitors’ talks. Unfortunately, recent departures of computer architecture faculty have eliminated the need for a separate colloquium.

Milos Prvulovic Complete C.V. Page 4 of 19 CS 2200 Introduction to Computer Systems & Networks(2008): This is my fourth offering of this key undergraduate course, and I have added several new issues related to many-core computing, as well as a many-core programming assignment to expose students to some of the many-core programmability issues they will face when they graduate.

CS 6290 High-Performance Computer Architecture (2007): Updated course content with recent developments in computer architecture. In particular, the major emphasis of the course is now on multi- and many-core architectures.

CS 8803AIC Advanced Issues in Computer Architecture (2006): The CS graduate curriculum currently does not have a course that covers important programmability, reliability, and security as- pects of modern computer architecture, especially in relation to the current trend toward larger-scale chip-multiprocessors. Lack of advanced graduate courses in computer architecture has recently been identiﬁed as one of the main difﬁculties in recruiting top graduate students. This new course was designed to alleviate this problem. It has since been superceded by CS 8804RSA and eventually CS 6292.

CS 2200 Introduction to Computer Systems & Networks(2004): An intermediate undergraduate course in computer architecture and systems. Augmented course content with recent developments, while keeping the course at the intermediate level. These developments include the recent trend toward portable devices, the power/performance tradeoff, and reliability and security concerns. The course was already well-established and the projects/homework/exam structure matches my teaching philosophy well. However, we added optional in-class quizzes to encourage students to attend lectures and study the material throughout the semester.

CS 4290/6290 Advanced Computer Architecture (2004): A co-taught undergraduate and intro- ductory graduate course in computer architecture. Augmented course content with recent developments in the ﬁeld, which include new and improved architectural mechanisms, the trade-off between power efﬁciency and performance, etc. Changed the format of the project to include a substantial in- depth exploration of an advanced architectural mechanism via simulation. This helps the students understand and deal with the level of detail and the trade-offs that accompany the early stages of a real computer architecture project.

C. Individual Student Guidance Ph.D. Students Supervised Sunjae Park (CS) Fall 2011-Present. Hardware support for performance debugging of many-core programs. Chink-Kai Liang (CS) Fall 2011-Present. Security from hardware snooping and side-channel attacks, and more recently advanced on- and off-chip interconnects. Co-Advised with Dr. Alenka Zajic. Anshuman Goswami (CS) Fall 2010-Present. Security and architectural implications from off-chip leakage of ”secure” on-chip information. Co-Advised with Dr. Alenka Zajic.

Milos Prvulovic Complete C.V. Page 5 of 19 Jungju Oh (CS) Fall 2008-Present. Hardware support for performance debugging of many-core programs. Jungju is the second person ever, and the only person in the past 30 years, to be the ﬁrst author of papers in both ICSE (top SWEng conference) and ISCA (top CompArch conference) in the same year. Only seven people ever were authors on both an ISCA and an ICSE paper in the same year, and the only two in the past 12 years are Jungju and myself (for our papers in 2011).

Can Hantas (CS) Fall 2011-Spring 2012. On-chip interconnects using advanced interconect technologies. Co-Advised with Alenka Za- jic. Student changed advisors. Ioannis Doudalis (CS) Fall 2006-Summer 2011. Hardware support for security, on-the-ﬂy detection of software bugs, and for reverse execution debugging. Ioannis graduated in Summer 2011 and is now a researcher in Intel. Guruprasadh Venkataramani (CS) Fall 2004-Summer 2009. Graduated Hardware support for debugging of software performance, correctness, and security. Guru is now an Assistant Professor at the George Washington University. Chenyu Yan (CS) Summer 2004 - Fall 2008. Graduated. Memory encryption and cache performance optimization. Chenyu is now with Microsoft.

Daniel Englender (CoC) Fall 2005. Switched to another area. Memory encryption and checkpointing. This student has switched to another area. Jianli Shen (CoC) Fall 2004 - Summer 2006. Left PhD program. Microarchitectural support for memory tagging. This student has left the PhD program without graduating.

M.S. Students supervised Brian DiRito (CS) Fall 2007-Spring 2008. Graduated. Advanced simulation infrastructure for computer architecture research. Graduated. Minjang Kim (CS) Spring 2006-Fall 2008. Now a PhD student. Data race detection in multi-threaded software. Minjang transfered into our PhD program. Aniket Naik (ECE) Spring 2005 - Fall 2006. Left MS program. Architectural support for parallel programming (checkpointing, deterministic replay and data race detection). Aniket left the MS program after receiving and accepting an employment offer from NVIDIA. Jaidev Amrite (ECE) Spring 2006. Compiler and architecture support for intensive and continuous program monitoring.

Milos Prvulovic Complete C.V. Page 6 of 19 Undergraduate Research Students. Brandyn Roemer (CoC) Fall 2004 - Fall 2006. Graduated. Brian DiRito (CoC) Fall 2005 - Fall 2006. Graduated.

Daniel Walls (CoC) Fall 2004 - Spring 2005. Graduated. Eric McCorkle (CoC) Summer 2004 - Fall 2004. Graduated. Tyler Tarwater (CoC) Fall 2004.

D. Teaching Honors and Awards 1. Hesburgh Teaching Fellowship, 2010-2011. Each year, one faculty member from each college at GT is selected for this fellowship. 2. Distinguished Alumni Educator Award, 2012, from the Department of Computer Science at the University of Illinois at Urbana-Champaign.

Milos Prvulovic Complete C.V. Page 7 of 19 II. Research and Creative Scholarship

A. Thesis Ph.D. Thesis Title: “Architectural Support for Reliable Parallel Computing” Date Completed: October 2003, Advisor: Dr. Josep Torrellas, University: University of Illinois at Urbana-Champaign. M.S. Thesis Title: “Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization.” Date Completed: January 2001, Advisor: Dr. Josep Torrellas, University: University of Illinois at Urbana-Champaign. B.Eng. Thesis Title: “The Split Spatial/Non-Spatial Cache.” Date Completed: June 1998, Advisor: Dr. Veljko Milutinovic, University: University of Belgrade.

B. Published Journal Papers (refereed) B.0.1 I. Doudalis, J. Clause, G. Venkataramani, M. Prvulovic, A. Orso, “Effective and Efﬁcient Mem- ory Protection Using Dynamic Tainting”, IEEE Transactions on Computers, Vol. 61, Issue 1, January 2012. B.0.2 G. Venkataramani, C.J. Hughes, S. Kumar, M. Prvulovic, “DeFT: Design Space Exploration for On-the-Fly Detection of Coherence Misses”, ACM Transactions on Computer Architecture and Compiler Optimization (TACO), Vol. 8, Issue 2, July 2011.

B.0.3 J. Torrellas, L. Ceze, J. Tuck, C. Cascaval, P. Montesinos, W. Ahn, M. Prvulovic, “The Bulk Mul- ticore Architecture for Improved Programmability”, in Communications of the ACM (CACM), pp. 58 - 65, Vol. 52, Issue 12, December 2009. B.0.4 G. Venkataramani, Y. Solihin, M. Prvulovic, “MemTracker: An accelerator for memory debugging and monitoring”, in ACM Transactions on Architecture and Code Optimization (TACO), pp. 1 - 33, Vol. 6, Issue 2, June 2009. B.0.5 S. Chhabra, B. Rogers, Y. Solihin, M. Prvulovic, “Making secure processors OS- and performance- friendly”, in ACM Transactions on Architecture and Code Optimizations (TACO), pp. 1 -35, Vol. 5, Issue 4, March 2009.

B.0.6 R. Shetty, M. Kharbutli, Y. Solihin, and M. Prvulovic, “HeapMon: A helper-thread Approach to programmable, automatic, and low-overhead memory bug detection”, in IBM Journal of Research and Development, pp. 261-275, Vol 50, Number 2/3, February 2006. B.0.7 M.J. Garzaran, M. Prvulovic, J.M. Llaberia, V. Vinals, L. Rauchwerger, and Josep Torrellas, “Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in Multipro- cessors”, in ACM Transactions on Architecture and Code Optimization (TACO), pp. 247 - 279, Vol 2, Issue 3, September 2005. B.0.8 B. Rogers, Y. Solihin, M. Prvulovic, “Memory Predecryption: Hiding the Latency Overhead of Memory Encryption”, in ACM SIGARCH Computer Architecture News, Special issue on the

Milos Prvulovic Complete C.V. Page 8 of 19 Workshop on Architectural Support for Security and Anti-virus (WASSA) pp. 27-33, Vol 33, Issue 1, March 2005.

C. Published Books and Parts of Books (Refereed) C.1. Chapters in Books C.1.1 M.J. Garzaran, M. Prvulovic, J.M. Llaberia, V. Vinals, L. Rauchwerger, and J. Torrellas. “Soft- ware Logging under Speculative Parallelization.” Chapter in High Performance Memory Sys- tems, pp. 181–193, H. Hadimioglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas (Editors), ISBN 0-387-00310-X, Springer-Verlag, 2003.

D. Conference Presentations D.1. Conference Presentations with Proceedings (refereed and archival)

[Refereed publications in respected conferences, with extensive reviewing, and appearing in archival proceedings and in ACM Digital Library and/or IEEExplore.] [For the purposes of this CV, refereed means full paper (not just abstract) reviewed by four or more peers. Review by an editor is not considered refereed.]

D.1.1 I. Doudalis, M. Prvulovic, “Euripus: A Flexible Uniﬁed Hardware Memory Checkpointing Ac- celerator for Bidirectional Debugging and Reliability”, in Proceedings of the 39th ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2012.

D.1.2 S. Chhabra, B. Rogers, Y. Solihin, M. Prvulovic. “SecureME: A Hardware-Software Approach to Full System Security”, in Proceedings of the ACM International Conference on Supercom- puting (ICS), June 2011. D.1.3 J. Oh, M. Prvulovic, A. Zajic, “TLSync: Support for Multiple Fast Barriers Using On-Chip Transmission Lines”, in Proceedings of the 38th ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2011. D.1.4 J. Oh, C.J. Hughes, G. Venkataramani, M. Prvulovic, “LIME: A Framework for Debugging Load Imbalance in Multi-threaded Execution”, in Proceedings of the 33rd ACM International Conference on Software Engineering (ICSE), May 2011. D.1.5 I. Doudalis, M. Prvulovic, “HARE: Hardware Assisted Reverse Execution”, in Proceedings of the 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA), January 2010. D.1.6 G. Venkataramani, I. Doudalis, Y. Solihin, M. Prvulovic, “FlexiTaint: Programmable Architec- tural Support for Efﬁcient Dynamic Taint Propagation”, in Proceedings of the 14th IEEE In- ternational Symposium on High-Performance Computer Architecture (HPCA), February 2008.

D.1.7 B. Rogers, C.Yan, S. Chhabra, M. Prvulovic, Y. Solihin, “Single-Level Integrity and Conﬁden- tiality Protection for Distributed Shared Memory Multiprocessors”, in Proceedings of the 14th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Febru- ary 2008.

D.1.8 S. Subramaniam, M. Prvulovic, G. Loh, “PEEP: Exploiting Predictability of Memory Depen- dences in SMT Processors”, in Proceedings of the 14th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2008.

Milos Prvulovic Complete C.V. Page 9 of 19 D.1.9 B. Rogers, S. Chhabra, Y. Solihin, M. Prvulovic, “Using Address Independent Seed Encryp- tion and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly”, in Proceedings of the 40th Annual IEEE/ACM Symposium on Microarchitecture (MICRO), De- cember 2007. D.1.10 J. Clause, I. Doudalis, A. Orso, M. Prvulovic, “Effective Memory Protection Using Dynamic Tainting”, in Proceedings of the 22nd IEEE/ACM International Conference on Automated Soft- ware Engineering (ASE), November 2007. D.1.11 G. Venkataramani, B. Roemer, M. Prvulovic, Y. Solihin, “MemTracker: Efficient and Pro- grammable Support for Memory Access Monitoring and Debugging”, in Proceedings of the 13th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2007. D.1.12 M. Kharbutli, X. Jiang, Y. Solihin, G. Venkataramani, M. Prvulovic, “Comprehensively and Efficiently Protecting the Heap”, in Proceedings of the 12th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Octo- ber 2006. D.1.13 B. Rogers, M. Prvulovic, Y. Solihin, “Efficient Data Protection for Distributed Shared Mem- ory Multiprocessors”, in Proceedings of the Fifteenth IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2006. D.1.14 C. Yan, B. Rogers, M. Prvulovic, and Y. Solihin, “Improving Cost, Performance, and Security of Memory Encryption and Authentication”, in Proceedings of the 33rd Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2006. D.1.15 M. Prvulovic, “CORD: Cost-effective (and nearly overhead-free) Order Recording and Data race detection”, in Proceedings of the 12th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2006. D.1.16 C. S. Ballapuram, H. S. Lee, and M. Prvulovic, “Synonymous address compaction for energy reduction in data TLB”, in Proceedings of the 2005 IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 357–362, August 2005. D.1.17 M. Garzaran, M. Prvulovic, V. Vinals, J. Llaberia, L. Rauchwerger, and J. Torrellas, “Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation”, in Pro- ceedings of the IEEE/ACM International Conference on Parallel Architectures and Compila- tion Techniques (PACT), pp. 170–181, September 2003. D.1.18 M. Prvulovic and J. Torrellas, “ReEnact: Using Thread-Level Speculation Mechanisms to De- bug Data Races in Multithreaded Codes”, in Proceedings of the 30th Annual IEEE/ACM In- ternational Symposium on Computer Architecture (ISCA), pp. 110-121, June 2003. D.1.19 M. Garzaran, M. Prvulovic, J. Llaberia, V. Vinals, L. Rauchwerger, and J. Torrellas, “Trade- offs in Buffering Memory State for Thread-Level Speculation in Multiprocessors”, in Proceed- ings of the Ninth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 191-202, February 2003. D.1.20 J. Martinez, J. Renau, M. Huang, M. Prvulovic, and J. Torrellas, “Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors”, inProceedings of the 35th Annual IEEE/ACM Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 3–14, November 2002. D.1.21 M. Prvulovic, Z. Zhang, and J. Torrellas, “ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors”, in Proceedings of the 29th Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 111-122, May 2002.

Milos Prvulovic Complete C.V. Page 10 of 19 D.1.22 M. Garzaran, M. Prvulovic, A. Jula, H. Yu, Y. Zhang, L. Rauchwerger, and J. Torrellas, “Ar- chitectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors”, in Proceedings of the IEEE/ACM International Conference on Parallel Architectures and Compi- lation Techniques (PACT), pp. 243–254, September 2001. D.1.23 M. Prvulovic, M. Garzaran, L. Rauchwerger, and J. Torrellas, “Removing Architectural Bot- tlenecks to the Scalability of Speculative Parallelization”, in Proceedings of the 28th Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 204–215, July 2001.

D.2. Conference Presentations with Proceedings (refereed)

[Publication in peer refereed conference/workshop proceedings.]

D.2.1 I. Doudalis, M. Prvulovic, “HARE++: Hardware Assisted Reverse Execution Revisited”, in Workshop on Runtime Environments/Systems, Layering, and Virtualized Environments (RE- SoLVE 2011), March 2011. D.2.2 G. Venkataramani, C. J. Hughes, S. Kumar, M. Prvulovic, “Coherence Miss Classiﬁcation for Performance Debugging in Multi-Core Processors”, in Proceedings of Interact-13: Workshop on Interaction Between Compilers and Computer Architecture, February 2009. D.2.3 S. Roy, R. Kumar, M. Prvulovic, “Improving System Performance with Compressed Mem- ory”, in Proceedings of the 15th International Parallel and Distributed Processing Symposium (IPDPS), pp. 66-72, April 2001. D.2.4 F. Dang, M.J. Garzaran, M. Prvulovic, Y. Zhang, A. Jula, H. Yu, N. Amato, L. Rauchwerger, J. Torrellas, “SmartApps, an Application centric approach to high performance computing: compiler-assisted software and hardware support for reduction operations”, in Proceedings of the 2002 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp. 172–181 , April 2002. D.2.5 R. Shetty, M. Kharbutli, Y. Solihin, M. Prvulovic, “HeapMon: a Low Overhead, Automatic, and Programmable Memory Bug Detector”, in Proceedings of the 1st IBM Watson P = ac2 Conference, pp. 25–34, October 2004. D.2.6 J. Shen, G. Venkataramani, M. Prvulovic, “Tradeoffs in Fine-Grained Heap Memory Protec- tion”, in First Workshop on Architectural and Systems Support for Improving Software De- pendability (ASID), pp. 52–57, October 2006.

D.3. Conference Presentations with Proceedings (abstract refereed) D.3.1 J. Protic, M. Prvulovic, D. Ristanovic, “The Effect of User Behavior and Internet Provider Pol- icy on the Accessibility of SezamPro Online System”, in Proceedings of the 23rd EUROMICRO Conference ’97: New Frontiers of Information Technology - Short Contributions, pp. 126–131, Budapest, Hungary, September 1997.

D.4. Conference Presentations without Proceedings (abstract refereed) D.4.1 M. Prvulovic, D. Marinov, V. Milutinovic, “Performance Evaluation of Split Temporal/Spatial Caches: Paving the Way to New Solutions”, in Workshop on Performance Analysis and its Impact to Design (PAID), Barcelona, Spain, June 1998. D.4.2 M. Garzaran, M. Prvulovic, J. Llaberia, V. Vinals, L. Rauchwerger, and J. Torrellas, “Software Logging under Speculative Parallelization”, in 2nd Workshop on Memory Performance Issues in conjunction with ISCA-29, June 2001.

Milos Prvulovic Complete C.V. Page 11 of 19 D.4.3 F. Dang, M. Garzaran, M. Prvulovic, Y. Zhang, A. Jula, H. Yu, N. Amato, L. Rauchwerger, J. Torrellas, “Compiler-Assisted Software and Hardware Support for Reduction Operations”, in NSF Workshop on Next Generation Software Systems, April 2002.

E. Other E.1. Technical Reports E.1.1 M. Prvulovic, “Architectural Support for Reliable Parallel Computing”, University of Illinois at Urbana-Champaign, Department of Computer Science Technical Report # UIUCDCS-R-2003- 2365, July 2003.

E.2. Software E.2.1 “SESC”, a detailed cycle-by-cycle architectural simulator (2002-present), is among the most commonly used by computer architecture research groups in both academia and industry. I designed and implemented the main processor and system front-end emulation framework, as well as simulator functionality related to thread-level speculation, rollback recovery, recording and replay. I also participated in the development of the main back-end simulation system.

F. Research Proposals and Grants (Principal Investigator) a. Approved and Funded 1. SHF:Medium: MEDITA - Multi-layer Enterprise-wire Dynamic Information-ﬂow Track- ing & Assurance Sponsor: National Science Foundation. Software and Hardware Foundations Program Investigator(s): A. Orso (PI), M. Prvulovic (Co-PI), N. Feamster (Co-PI) Amount: $ 900,000 Funded: June 2010 - May 2013. 2. Support for the 43rd International Symposium on Microarchitecture Sponsor: National Science Foundation. Software and Hardware Foundations Program Investigator(s): M. Prvulovic (PI) Amount: $ 15,000 Funded: September 2010 - August 2011. 3. SHF:Small: Understanding and Mitigation of Electromagnetic Data Leakage from Modern Computer Processors and Systems Sponsor: National Science Foundation. Software and Hardware Foundations Program Investigator(s): M. Prvulovic (PI), A. Zajic (Co-PI) Amount: $ 106,659 Funded: September 2010 - August 2011.

4. Performance Debugging Support for Many-Core Processors Sponsor: National Science Foundation. NSF/SRC Multicore Chip Design and Architecture (MCDA) Program. Investigator(s): M. Prvulovic (PI) Amount: $ 137,278 Funded: August 2009 - July 2012.

5. Performance Debugging Support for Many-Core Processors Sponsor: Semiconductor Research Corporation (SRC). NSF/SRC Multicore Chip Design and Architecture (MCDA) Program.

Milos Prvulovic Complete C.V. Page 12 of 19 Investigator(s): M. Prvulovic (PI) Amount: $ 90,000 Funded: August 2009 - July 2012. 6. SHF:Small:Collaborative Research: Beyond Secure Processors - Securing Systems Against Hardware Attacks Sponsor: National Science Foundation. Software and Hardware Foundations Program. Investigator(s): Milos Prvulovic (PI), Yan Solihin (Collaborative Co-PI) Amount: $500,000, $ 259,071 for Georgia Tech (Prvulovic) Funded: September 2009 - August 2012. 7. CAREER: Architectural Support for Parallel Execution as a Continuum of Transac- tions (ASPECT) Sponsor: National Science Foundation. CAREER Program 2004 (CCF-CPA Division) Investigator(s): M. Prvulovic (PI) Amount: $ 400,000 Funded: July 2005 - June 2010. 8. Collaborative Research: Software and Hardware Support for Efﬁcient Monitoring of Program Behavior Sponsor: National Science Foundation. Computing Processes and Artifacts Program 2005 Investigator(s): A. Orso (PI), M. Prvulovic (Co-PI), Y. Solihin (Collaborative Co-PI), J. Cook (Collaborative Co-PI) Amount: $750,00 total, $ 350,000 for Georgia Tech (Orso and Prvulovic) Funded: August 2006 - July 2009 9. Research Experiences for Undergraduates (REU) Supplement to “Collaborative Re- search: General Purpose Memory Tagging for Reliable, Secure, and Fast Comput- ing”. Sponsor: National Science Foundation. Computing Processes and Artifacts Program. Investigator(s): M. Prvulovic (PI) Amount: $ 6,000 Funded: June 2005 - July 2007. 10. Collaborative Research: General Purpose Memory Tagging for Reliable, Secure, and Fast Computing. Sponsor: National Science Foundation. Computing Processes and Artifacts Program 2004 Investigator(s): M. Prvulovic (PI), Y. Solihin (Collaborative Co-PI) Amount: $100,000 total, $ 75,661 for Georgia Tech (Prvulovic) Funded: August 2004 - July 2007.

G. Research Honors and Awards • National Science Foundation, CAREER Award, 2005.

• Intel PhD Fellowship, 2002. • W.J. Poppelbaum Memorial Award, 2001. Awarded by the Computer Science Department at the University of Illinois at Urbana-Champaign to one outstanding PhD student in the area of computer architecture each year.

Milos Prvulovic Complete C.V. Page 13 of 19 III. Service

A. Professional Activities A.1. Memberships and Activities in Professional Societies • Member, Executive Committee for ACM SIGMICRO, 2011-present.

• Treasurer of ACM SIGMICRO, 2008-2011. • Senior Member, Institute of Electrical and Electronics Engineers (IEEE). – IEEE Computer Society. – IEEE Computer Society, Technical Committee on Computer Architecture.

• Senior Member, Association for Computer Machinery. – SIGARCH, Special Interest Group on Computer Architecture. – SIGMICRO, Special Interest Group on Microarchitecture.

A.2. Conference Committee Activities 1. Member, Steering Committee, IEEE/ACM International Symposium on Microarchitecture (MICRO), February 2012-present.

2. Member, Program Committee, 40th Annual IEEE/ACM International Symposium on Com- puter Architecture (ISCA), June 2013. 3. Member, Program Committee, 45th Annual IEEE/ACM International Symposium on Mi- croarchitecture (MICRO), December 2012.

4. Co-Chair, Program Committee, 44th Annual IEEE/ACM International Symposium on Mi- croarchitecture (MICRO), December 2011. 5. Finance Chair, 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2010.

6. Member, Program Committee, 43rd Annual IEEE/ACM International Symposium on Mi- croarchitecture (MICRO), December 2010. 7. Member, Program Committee, 27th IEEE International Conference on Computer Design (ICCD), October 2010. 8. Member, Program Committee, 16th IEEE International Conference on High-Performance Computer Architecture (HPCA), January 2010. 9. Member, Program Committee, 27th IEEE International Conference on Computer Design (ICCD), October 2009. 10. Member, Program Committee, 2009 ACM International Conference on Supercomputing (ICS), June 2009. 11. Member, Program Committee, 2009 IEEE International Parallel and Distributed Process- ing Symposium (IPDPS), May 2009. 12. Registration Chair, 15th IEEE International Conference on High-Performance Computer Architecture (HPCA), February 2009.

Milos Prvulovic Complete C.V. Page 14 of 19 13. Member, Program Committee, 26th IEEE International Conference on Computer Design (ICCD), October 2008.

14. Member, Program Committee, 2008 IEEE/ACM International conference on Parallel Ar- chitectures and Compilation Techniques (PACT), October 2008. 15. Member, Program Committee, 40th Annual IEEE/ACM International Symposium on Mi- croarchitecture (MICRO), December 2007.

16. Member, Program Committee, 13th IEEE International Conference on High-Performance Computer Architecture (HPCA), February 2007. 17. Member, Program Committee, First Workshop on Architectural and System Support for Improving Software Dependability (ASID), held with ASPLOS in October 2006.

18. Co-Organizer and Program Committee Co-chair, First Workshop on Introspective Archi- tectures (WISA), held with HPCA in February 2006. 19. Member, Program Committee, 12th IEEE International Conference on High-Performance Computer Architecture (HPCA), February 2006. 20. Publicity Co-chair, 14th IEEE/ACM International Conference on Parallel Architectures and Compiler Techniques (PACT), September 2005.

B. On-Campus Georgia Tech Committees and Service 1. Member, Georgia Tech Committee on Responsible Conduct of Research, 2012-present. 2. Member, Georgia Institute of Technology, Academic Senate (elected position) , 2010-present.

3. Member, Georgia Institute of Technology, Student Honor Committee, 2010-present. 4. Chair, School of Computer Science, Ph.D. Student Review Committee, 2010-2011. 5. Member, School of Computer Science, School Chair Search Committee, 2011-2012.

6. Member, College of Computing, MSCS Committee, 2009-2011. 7. Area Coordinator, College of Computing, Computer Architecture Area, 2005-2011. 8. Lead, School of Computer Science, Annual Ph.D. Student Review, 2009. 9. Member, College of Computing, Committee to Reinvent the CS Master’s Program, 2008-2009.

10. Member, School of Computer Science, School Chair’s Advisor Committee (elected position), 2007-2009. 11. Member, College of Computing, PhD Admissions Committee, 2004 - 2007.

C. Member of Ph.D. Committees 1. Sunpyo Hong, Department of ECE, College of Engineering, Georgia Tech., November 2012. Thesis Title: Modeling Performance and Power for Energy-Efﬁcient GPGPU Computing Principal Advisor: Dr. Hyesoon Kim 2. Paul David Bryan, School of CS, College of Computing, Georgia Tech., October 2012. Thesis Title: Accelerating Microarchitectural Simulation via Statistical Sampling Principles Principal Advisor: Dr. Thomas M. Conte

Milos Prvulovic Complete C.V. Page 15 of 19 3. Ioannis Doudalis, School of CS, College of Computing, Georgia Tech., June 2011. Thesis Title: “Hardware Assisted Memory Checkpointing and Applications in Debugging and Reliability.” Principal Advisor: Dr. Milos Prvulovic. 4. Yuejian Xie, School of CS, College of Computing, Georgia Tech., May 2011. Thesis Title: “Efficient Shared Cache Management in Multicore Processors.” Principal Advisor: Dr. Gabriel Loh. 5. James Alexander Clause, School of CS, College of Computing, Georgia Tech., January 2011. Thesis Title: “Enabling and Supporting the Debugging of Software Failures” Principal Advisor: Dr. Alessandro Orso 6. Dong Hyuk Woo, Department of ECE, College of Engineering, Georgia Tech., September 2010. Thesis Title: “Designing Heterogeneous Many-Core Processors to Provide High Performance under Limited Chip Power Budget.” Principal Advisor: Dr. Hien-Hsin Lee 7. Brian Valentine, Department of ECE, College of Engineering, Georgia Tech., March 2010. Thesis Title: “Embedded Early Vision Techniques for Efficient Background Modeling and Midground Detection.” Principal Advisor: Dr. Linda Wills. 8. Brian Rogers, Department of ECE, College of Engineering, North Carolina State University., October 2009. Thesis Title: “Low-Overhead Designs for Secure Uniprocessor and Multiprocessor Architec- tures.” Principal Advisor: Dr. Yan Solihin, NCSU. 9. Guruprasadh Venkataramani, School of CS, College of Computing, Georgia Tech., July 2009. Thesis Title: “Low cost and Efficient Architectural Support for Correctness and Performance Debugging.” Principal Advisor: Dr. Milos Prvulovic. 10. Samantika Subramaniam, School of CS, College of Computing, Georgia Tech., December 2008. Thesis Title: “Improving Processor Efficiency by Exploiting Common-case Behaviors of Mem- ory Instructions.” Principal Advisor: Dr. Gabriel Loh 11. Chenyu Yan, School of CS, College of Computing, Georgia Tech., August 2008. Thesis Title: “Architectural Support for Improving Security and Performance of Memory Sub- systems.” Principal Advisor: Dr. Milos Prvulovic. 12. Hasnain Mandviwala, School of CS, College of Computing, Georgia Tech., June 2008. Thesis Title: “Capsules: Expressing Composable Computations in a Parallel Programming Model.” Principal Advisor: Dr. Umakishore Ramachandran. 13. Kiran Puttaswamy, Department of ECE, College of Engineering, Georgia Tech., September 2007. Thesis Title: “Designing High-Performance Microprocessors in 3D-Integration Technology.” Principal Advisor: Dr. Gabriel Loh. 14. Nissim Harel, College of Computing, Georgia Tech., October 2006. Thesis Title: “Memory Optimizations for Distributed Stream-based Applications.” Principal Advisor: Dr. Umakishore Ramachandran.

Milos Prvulovic Complete C.V. Page 16 of 19 15. Mazen Mahmoud Kharbutli, Department of ECE, College of Engineering, North Carolina State University., October 2005. Thesis Title: “Improving the Security of the Heap through Inter-Process Protection and Intra- Process Temporal Protection.” Principal Advisor: Dr. Yan Solihin, NCSU. 16. Yudong Tan, Department of ECE, College of Engineering, Georgia Tech., April 2005. Thesis Title: “Cache-related Timing Analysis for Preemptive Multi-tasking Real-time Sys- tems.” Principal Advisor: Dr. Vincent Mooney. 17. Tyson Hall, Department of ECE, College of Engineering, Georgia Tech., September 2004. Thesis Title: “Field-Programmable Analog Arrays: A Floating-Gate Approach.” Principal Advisor: Dr. David V. Anderson.

18. Santithorn Bunchua, Department of ECE, College of Engineering, Georgia Tech., June 2004. Thesis Title: “Fully Distributed Register Files for Heterogeneous Clustered Microarchitec- tures.” Principal Advisor: Dr. Scott Wills

Milos Prvulovic Complete C.V. Page 17 of 19 IV. National and International Professional Recognition

A. Invited Conference Session Chair 1. 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2010, Session on Tools. 2. 16th IEEE International Conference on High Performance Computer Architecture (HPCA), January 2010, Session on System Architecture and Performance Evaluation. 3. 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2007, Session on Memory. 4. 13th IEEE International Conference on High Performance Computer Architecture (HPCA), February 2007, Session on Thermal Modeling and SIMD. 5. First Workshop on Architectural and System Support for Improving Software Dependability (ASID), October 2006 (with ASPLOS), Short Papers Session. 6. 12th IEEE International Conference on High Performance Computer Architecture (HPCA), February 2006, Session on Multi-threaded Systems.

B. Editorial and Reviewer Work 1. Program Committee Member, 40th Annual IEEE/ACM International Symposium on Com- puter Architecture (ISCA), June 2013. 2. Program Committee Member, 45th Annual IEEE/ACM International Symposium on Microar- chitecture (MICRO), December 2012. 3. Selection Committee Member, IEEE Micro Top Picks, June/July 2012 Issue. 4. Program Committee Co-Chair, 44th Annual IEEE/ACM International Symposium on Microar- chitecture (MICRO), December 2011. 5. Program Committee Member, 43rd Annual IEEE/ACM International Symposium on Microar- chitecture (MICRO), December 2010. 6. Program Committee Member, 28th IEEE International Conference on Computer Design (ICCD), October 2010. 7. Program Committee Member, 16th IEEE International Conference on High Performance Com- puter Architecture (HPCA), January 2010. 8. Program Committee Member, 27th IEEE International Conference on Computer Design (ICCD), October 2009. 9. Program Committee Member, 2009 ACM International Conference on Supercomputing (ICS), June 2009. 10. Program Committee Member, 2009 IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2009. 11. Program Committee Member, 26th IEEE International Conference on Computer Design (ICCD), October 2008. 12. Program Committee Member, 2008 IEEE/ACM International conference on Parallel Architec- tures and Compilation Techniques (PACT), October 2008.

Milos Prvulovic Complete C.V. Page 18 of 19 13. Program Committee Member, 40th Annual IEEE/ACM International Symposium on Microar- chitecture (MICRO), December 2007.

14. Program Committee Member, 13th IEEE International Conference on High Performance Com- puter Architecture (HPCA), February 2007. 15. Program Committee Member, 12th IEEE International Conference on High Performance Com- puter Architecture (HPCA), February 2006.

16. NSF Panel Member, CPA program. 17. NSF Panel Member, CAREER program. 18. Editorial Board Member, Journal of Instruction Level Parallelism (www.jilp.org). 19. Program Committee Member, First Workshop on Architectural and System Support for Im- proving Software Dependability (ASID), October 2006 (with ASPLOS). 20. Co-organizer and Program Committee Co-char, First Workshop on Introspective Architectures (WISA), February 2006 (with HPCA). 21. Reviewer for ACM Transactions on Architecture and Code Optimization (TACO), ACM Com- puter Architecture Letters, IEEE Transactions on Computer Systems (TOCS), IEEE Trans- actions on Parallel and Distributed Systems (TPDS), International Symposium on Computer Architecture (ISCA), International Symposium on Microarchitecture (MICRO), International Symposium on High Performance Computer Architecture (HPCA), International Conference on Parallel Architectures and Compilation Techniques (PACT), International Conference on Supercomputing (ICS), International Parallel and Distributed Processing Symposium (IPDPS), Supercomputing, Euro-Par, Journal of Instruction Level Parallelism (JILP), Journal of Paral- lel and Distributed Computing (JPDC), International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS).

C. Patents • S. Roy, R. Kumar, M. Prvulovic, K. M. Wilson, “Virtual memory system utilizing data compression implemented through a device”, U.S. Patent 6,516,397, issued on February 4, 2003.

Milos Prvulovic Complete C.V. Page 19 of 19 Exhibit H Jonathan William Babb

Citizenship: USA Address: 20 Watertown St. #205, Watertown, MA 02472 Email: [email protected], mobile: 508-878-9041

Education Massachusetts Institute of Technology ...... Cambridge, MA Ph.D. Electrical Engineering and Computer Science 2001 S.M. Electrical Engineering and Computer Science 1994 Minor: Business and Entrepreneurship GPA: 4.9 / 5.0 Selected coursework: Graduate Computer Architecture, Computer-Aided Design of Integrated Circuits, Parallel Processing: Systems, Architecture and Applications, Parallel Processing: VLSI and Microarchitecture, Digital Signal Processing. Georgia Institute of Technology ...... Atlanta, GA B.S. Electrical Engineering 1991 Minors: Computer Engineering and Economics GPA: Overall: 4.0 / 4.0 Major: 4.0 / 4.0 Rank: 1/432 PhD Dissertation High Level Compilation for Reconfigurable Architectures Committee: Anant Agarwal (chair), Srinivas Devadas, Martin Rinard Designed an end-to-end compilation toolchain from high-level languages into silicon and fine-grain architectures. Created the system by progressively raising the level of abstraction of the hardware model and low- ering the level of abstraction of the compiler target. Showed (1) how to take a collection of reconfigurable devices and treat them as a single, gigantic reconfigurable device, (2) how to combine this technology with logic-level synthesis to create application-specific, technology-independent computing hardware, (3) how to compile from high-level sequential languages, and (4) how to integrate these techniques with a parallelizing compiler. The resulting compiler generates hardware circuits from sequential programs. Experience IPX Consulting, LLC ...... Cambridge, MA 11/11 - present Consultant. Provide due diligence and technical expertise for patent valuation and litigation in the electronics industry. Cases: Nazomi Communications, Inc. v. Nokia Corp. et al., 5:10-cv-4686 (N.D. Cal.) - consulting expert for plaintiff Nazomi Communications, Inc. regarding Java hardware acceleration. U.S.I.T.C. Inv. No. 337-TA-836 (In the matter of Certain Consumer Electronics and Display Devices) – consulting expert for complainant Graphics Properties Holdings, Inc. regarding graphics processors and CPUs. U.S.I.T.C. Inv. No. 337-TA-850 (In the matter of Certain Electronic Imaging Devices) – consulting expert for complainant FlashPoint Technologies, Inc. regarding digital imaging devices. Enterasys Networks, Inc. v. Foundry Networks, LLC; and Brocade Communication Systems, Inc., 1:05-cv-11298 (E.D. Mass.) - consulting expert for plantiff Enterasys Networks, Inc. regarding network switch technology. U.S.I.T.C. Inv. No. 337-TA- 882 (regarding Certain Digital Media Devices, Including Televisions, Blu-Ray Disc Players, Home Theater Systems, Tablets and Mobile Phones, Components Thereof and Associated Software) – consulting expert for complainant Black Hills Media, LLC regarding sharing of media across various electronic devices. Massachusetts Institute of Technology ...... Cambridge, MA 9/09 - present Postdoctoral Associate (CSAIL & Synthetic Biology Center). Ported 16-core Raw microprocessor to 45nm and reduced energy cost in FPGA softcore systems in a collaboration with faculty at UCSD on the Green- droid Mobile Application Processor. Active member of the synthetic biology community and work regularly with many principal investigators to apply engineering concepts to biology. General Chair for the Inter- national Workshop on BioDesign Automation. Running MIT iGEM (international genetically-engineered machines) and Cornell Cup (embedded computing) teams. Project portfolio includes automatic compilation of high-level language to robotically-assembled DNA biocircuits, DNA computing to programmatically self- assemble large gene networks, invention of a BioFPGA for flexible and field-programmable genetic devices, fault tolerant biocircuit using cell-cell communication networks, and on-chip microfluidic gene assembly. Moderna Therapeutics, Inc...... Cambridge, MA 2/13 - present Consultant to design and apply bioinformatics algorithms for a messenger RNA therapeutics company. IKOS Systems, Inc...... San Jose, CA 2/02 - 2/02 Consultant in a patent infringement lawsuit (IKOS Systems Inc. et al v. Axis Systems Inc., 5:01-cv-21079-JW (N.D. Cal.)). Also helped MIT enforce the related technology license agreement. Jonathan Babb, 1 of 6 Operation Simulation Associates, Inc. (TVA spinoff) ...Cambridge Innovation Center, Cambridge, MA 6/91 - 9/09 Consultant, CTO, University Relations Manager. Scientific modeling for the power industry to reduce the environmental cost of producing reliable energy across continental-scale networks. Marketed proposals internationally. Led software teams modeling sustainable heat and power, wind integration, and energy security. Babb International ...... Ringgold, GA 1/00 - 1/03 Angel Investor and C-level Advisor. Manufactured a new cleantech product, autoclaved aerated concrete, based on a proprietary formulation from flyash, reclaimed from coal-fired power plants. I joined this $20M cleantech venture as an angel investor and advised the CEO on financial and operational issues. Princeton University ...... Princeton, NJ 9/99 - 9/00 Lecturer. Research and teaching position (predoctoral) in Electrical Engineering. Developed curriculum for new VLSI design lab and taught VLSI course to graduate and undergraduate students. Massachusetts Institute of Technology ...... Cambridge, MA 9/91 - 9/01 NSF Fellow. Extensive R&D under DARPA grants in CAD, compilers, and architecture. Led the Virtual Wires team that implemented a complete FPGA-based logic emulation system. Wrote the founding grant proposal for RAW. Developed compilers from high-level languages to novel computational substrates. Virtual Machine Works ...... Cambridge, MA 8/93 - 11/94 Founder, President and CEO. Founded VMW to commercialize logic emulation technology developed at MIT. Invented the technology, co-authored the business plan, negotiated a technology transfer license, raised $3M venture capital, administered DARPA grant, hired the initial employees. Acquired by IKOS Systems in 1996 (for $15M) and later Mentor Graphics in 2002 (for $110M) to become Mentor’s emulation offering. Georgia Institute Of Technology ...... Atlanta, GA 9/90 - 6/91 Developed a CAD tool to generate CIF (Caltech Intermediate Format) for automated design and fabrication of high-aspect ratio micromotors in silicon, an early application of MEMS. With Prof. Mark Allen. Honeywell Space and Strategic Avionics Division, Manned Space Program ...... Clearwater, FL 6/90 - 9/90 Designed a real-time software simulation testbed for the Space Station Attitude Determination and Control System using C, multi-tasking Ada (IBM AIX), and embedded multiprocessors under NASA contracts. Georgia Tech Research Institute, Defense Systems Division ...... Atlanta, GA 6/88-6/90 Digital design, SPICE analysis, and phase 1 testing of a testbed for the B-1 Bomber’s radar warning receiver. Research Massachusetts Institute of Technology ...... Cambridge, MA 6/09 – present Greendroid Mobile Application Processor – Inter-university collaboration with two principle investigators at UCSD to reduce power consumption in mobile multicore processors using silicon compilation [3]. Ported RAW microprocessor to 45nm technology node [5]. Reduced energy cost in FPGA softcore systems [2, 4]. 9/09 – present Synthetic Biology – Ongoing research in synthetic biology, including foundational technologies such as fault tolerant biocircuits and kill switches [40], programmable biomaterial formation [42], and automated DNA assembly protocols [39] using liquid handling robotics [41] and microfluidics. Invented reconfigurable chassis with BioPLA [38] and BioFPGA platform designs (see Patents). 1/98 – 9/01 DeepC Silicon Compiler – Developed the DeepC Silicon Compiler [8], as part of my dissertation, entitled: ”High Level Compilation for Reconfigurable Architectures”. DeepC is a end-to-end toolchain from high level languages directly into silicon and fine-grained architectures (such as FPGAs). 1/96 – 9/99 Raw Project – Originated the Raw Project from Virtual Wires [20] and FPGA computing research [13]. Co-authored the initial proposal (see Grants) and defined the key features of Raw Machines [10]. Developed first publicly released series of reconfigurable computing benchmarks [12]. Co-developed one of the first compilers to efficiently support multicore architectures [9]. 1/93 – 1/94 Virtual Wires Logic Emulation – Invented Virtual Wires [20], proved the concept with a prototype compilation system, and led a research group that implemented a complete FPGA-based logic emulation system [17]. Developed a scalable message-passing protocol based on static scheduling to overcome pin limitations [11]. 9/91 – 1/93 Alewife Multiprocessor – Built hardware and software for the Alewife Multiprocessor project [19]. De- signed and tested asynchronous logic for the Cache Controller and Memory Management Unit [15] and CalTech mesh router interface. Implemented a series of test vectors for functional verification.

Jonathan Babb, 2 of 6 Georgia Institute Of Technology ...... Atlanta, GA 9/90 - 6/91 Micromotor Fabrication – Developed a CAD tool for synthesizing tiny electromechanical motors (MEMS) in silicon [22]. Worked on a new electroplating technique for creating high-aspect ratio motors, fabricated novel devices in a micro-fabrication cleanroom, and built a three phase high-voltage power supply. Teaching Massachusetts Institute of Technology ...... Cambridge, MA 9/11 – 5/12 Advisor, Cornell Cup Team: Advised 5 member student team competing in Intel-sponsored embedded computing competition. One of 20 proposals accepted. Team won $2500 third place prize for development of a personal liquid handler with delta robot and embedded image processing software. 3/10 – present Advisor and Instructor, MIT iGEM Team: Three years teaching a seminar series and summer long, open- ended lab in synthetic biology to an interdisciplinary team of students competing in the iGEM competition. Oversaw 12 instructors, 13-18 students and all laboratory activities each year. We won gold medal, best manufacturing track award, and iGEMer’s award (voted best team) in 2010 and gold medal, best health and medicine track, and ranked in the final four of 160 teams in 2011. Initiated 2012 entrepreneurship team. 9/09 – present Supervisor, Undergraduate Research Opportunities Program (UROP): Advised 45 UROP students, working in teams and individually, including non-MIT undergraduates and high school students performing research in the field of synthetic biology. Students have received NSF funding, initiated startups based on their projects, gone to work for VC-funded startups, won the MIT $100K, and Thiel Fellowships. 2/98 – 5/98 Guest Lecturer for 6.891: Graduate Compiler Course. Compiler design for reconfigurable architectures. 9/95 – 12/95 Teaching and lab assistant for 6.002: Circuits and Electronics. 2/92 – 12/92 Grader and assistant for 6.823: Computer System Architecture. Graduate-level computer architecture. Princeton University ...... Princeton, NJ 9/99 - 9/00 Lecturer for EE462/562: Designed and taught Princeton’s VLSI course, including team-based student lab. Select Awards Two papers endorsed as top 5% in the first twenty years of the IEEE FCCM (leading FPGA conference) Third Place, Cornell Cup USA 2012 (MIT Team Advisor) Best Health and Medicine Track Award, 4th Finalist (MIT iGEM 2011 Team) Best Manufacturing Track Award (MIT iGEM 2010 Team) Sigma Xi Scientific Research Society Tau Beta Pi National Engineering Honor Society Phi Kappa Phi National Honor Society National Science Foundation Fellowship for Graduate Research Eta Kappa Nu Outstanding Electrical Engineer Award College of Engineering Outstanding Junior Award Eta Kappa Nu Outstanding Electrical Engineering Sophomore Award Phi Kappa Phi Sophomore Award Phi Eta Sigma Freshman Award

Service International Workshop on Bio-Design Automation (General Chair, Industry Liaison Chair) International Conference on Field-Programmable Technology (Program Committee, Best Paper chair) IEEE Symposium on Field-Programmable Custom Computing Machines (Program Committee) International Conference on Field Programmable Logic and Applications (Program Committee) International Genetically Engineered Machine Competition (Judge) Conrad Foundation’s Spirit of Innovation Challenge (Judge) IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems IEEE Transactions on Computers IEEE International Parallel & Distributed Processing Symposium IEEE Transactions on Signal Processing IEEE Transactions on VLSI IEEE Micro Also reviewer for ACM Transactions on Reconﬁgurable Technology and Systems, Architectural Support for Programming Languages and Operating Systems, International Conference on Supercomputing, Inter- national Conference on Parallel Processing, International Symposium on Computer Architecture, Nucleic Acids Research, ACS Synthetic Biology, Integrative Biology, Nature Communication, PNAS, and Systems and Synthetic Biology.

Jonathan Babb, 3 of 6 Silicon 1 J. Babb, “FCCM20 Endorsement of OneChip: An FPGA Processor with Reconﬁgurable Logic Ralph D. Publications Wittig, Paul Chow”, in the Highlights of the First Twenty Years of the IEEE International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, April 2013. 2 M. Arora, J. Sampson, N. Goulding-Hotta, G. Venkatesh, J. Babb, V. Bhatt, S. Swanson and M. Taylor, “An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coproces- sors”, 21st International Conference on Field Programmable Logic and Applications, September 2011.

3 N. Goulding, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, J. Babb, S. Swanson, M. Taylor, “The GreenDroid Mobile Application Processor: An Architecture for Silicon’s Dark Future”, IEEE Micro, March/April 2011. 4 Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Tay- lor and Steven Swanson, “Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems,” The IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2011. 5 N. Goulding, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, J. Babb, S. Swanson, M. Taylor, “The GreenDroid Mobile Application Processor: An Architecture for Silicon’s Dark Future” in HOTCHIPS, August 2010. 6 Jonathan Babb, “High Level Compilation for Gate Reconfigurable Architectures,” MIT PhD dissertation, September 2001. 7 Mark Stephenson, Jonathan Babb, Saman Amarasinghe, “Bitwidth Analysis with Applications to Silicon Compilation,” in Programming Language Design and Implementation, November 2000. 8 Jonathan Babb, Martin Rinard, Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe, “Parallelizing Applications into Silicon,” IEEE Symposium on Field-Programmable Gate Arrays for Custom Computing Machines, April 1999. 9 Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar and Saman Amarasinghe, “Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,” in Architectural Support for Programming Languages and Operating Systems, November 1998. 10 Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe and Anant Agar- wal, “Baring It All to Software: Raw Machines” in IEEE Computer, September 1997. 11 Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanano, David Hoki, and Anant Agarwal, “Logic Emulation with Virtual Wires,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1997. 12 Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold , Rajeev Barua, Michael Taylor, Jang Kim, Srikrishna Devabhaktuni, and Anant Agarwal, “The RAW Benchmark Suite: Computation Structures for General Purpose Computing” In IEEE Symposium on Field-Programmable Custom Computing Ma- chines, Napa Valley, CA, April 1997. 13 Jonathan Babb, Matthew Frank, Anant Agarwal, “ Solving Graph Problems with Dynamic Computation Structures,” In SPIE Photonics East: Reconfigurable Technology for Rapid Product Development & Computing, Boston, MA, November 1996. 14 Charley Selvidge, Jonathan Babb, Anant Agarwal, and Matthew Dahl, “TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation” in the Proceedings of the Third Interna- tional Workshop on Field Programmable Gate Arrays, Monterey, California, February 1995. 15 John Kubiatowicz, David Chaiken, Anant Agarwal, Arthur Altman, Jonathan Babb, David Kranz, Beng- Hong Lim, Ken MacKenzie, John Piscitello, Mike Parkin, and Donald Yeung, “The Alewife CMMU: Addressing the Multiprocessor Communications Gap,” in HOTCHIPS, August 1994. 16 Matthew Dahl, Jonathan Babb, Russell Tessier, Silvina Hanano, David Hoki, and Anant Agarwal, “Em- ulation of a SPARC Microprocessor with the MIT Virtual Wires Emulation System,” In the Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 1994. 17 Russell Tessier, Jonathan Babb, Matthew Dahl, Silvina Hanano, and Anant Agarwal, “The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment,” in the Proceedings of the 2nd International Workshop on Field Programmable Gate Arrays, Berkeley, California, February 1994.

Jonathan Babb, 4 of 6 18 Jonathan Babb, Russell Tessier, “Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Em- ulators,” in the Proceedings of the 1993 MIT Student Workshop on Supercomputing Technologies, Ply- mouth, MA, August 1993. 19 Anant Agarwal, Jonathan Babb, David Chaiken, Godfrey D’Souza, Kirk Johnson, David Kranz, John Ku- biatowicz, Beng-Hong Lim, Gino Maa and Ken Mackenzie, “Sparcle: A Multithreaded VLSI Processor for Parallel Computing“, in Lecture Notes in Computer Science, Vol 748, May 1993. 20 Jonathan Babb, Russell Tessier, and Anant Agarwal, “Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators,” in the Proceedings of the IEEE Workshop on FPGAs for Custom Com- puting Machines, Napa, California, April 1993. 21 Anant Agarwal, Jonathan Babb, David Chaiken, Godfrey D’Souza, Kirk Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Gino Maa, Ken MacKenzie, Dan Nussbaum, Mike Parkin, and Donald Yeung. “Sparcle: Today’s Micro for Tomorrow’s Multiprocessor,” in HOTCHIPS, August 1992. 22 A. Frazier, J. Babb, and M. Allen, “Design and Fabrication of Electroplated Micromotor Structures”, in The Winter Annual Meeting of the American Society of Mechanical Engineers, Atlanta, GA, Dec., 1991. Carbon 23 D. Kong, J. Babb and T. Thorsen, S. Wick, J. Gam, R. Weiss, and P. Carr, ”Microfluidic Genetic Circuit Publications Assembly”, International Workshop on BioDesign Automation, July 2013. and Talks 24 L. Ngo, D. Mishra, A. Yang, J. Babb, and R. Weiss, “Multicellular Pattern Detection and Formation’, poster at SynBERC Fall Retreat, September 2012. 25 J. Babb, D. Mishra, L. Ngo, A. Yang, L. Morinishi, and R. Weiss, “Pattern formation and detection for hybrid micro-bio-robot communication: Utilizing Synthetic Biology to Create Programmable Micro- Bio-Robots”, talk at ONR Naval Biosciences and Biocentric Technology: Synthetic Biology Program Review, June 2012. 26 Beal, J; Weiss, R; Densmore, D; Adler, A; Appleton, A; Babb, J; Bhatia, S. Davidsohn, N; Haddock, T; Loyall, J; Schantz, R; Vasilev, V; Yaman, F. “An End-to-End Workflow for Engineering of Biological Circuits from High-Level Specifications”, ACS Synth. Biol. 2012, 1(8), pp 317-331, July 2012. 27 J. Beal, R. Weiss, D. Densmore, A. Adler, E. Appleton, J. Babb, S. Bhatia, N. Davidsohn, T. Haddock, J. Loyall, R. Schantz, V. Vasilev, and F. Yaman, “Results from TASBE”, International Workshop on BioDesign Automation, June 2012. 28 MIT iGEM 2011 Team, “Programmed Mammalian Tissue Engineering: Local Interactions to Global Patterns”, talk at Geneious User’s Group Meeting, Nov 2011. 29 Jonathan Babb, Adam Rubin, Thomas Knight, and Ron Weiss, “Flexible cellular platforms for reconfigurable biocircuits”, poster at SynBERC Fall Retreat, September 2011. 30 Patrick Guye, Yinqing Li, Xavier Duportet, Jonathan Babb, Ron Weiss, “Rapid Assembly and Delivery of Large Scale Genetic Circuits into Mammalian Cells”, talk at SynBERC Fall Retreat, September 2011.

31 V. Vasilev, C. Liu, J. Fernandes, E. Orozco, T. Haddock, S. Bhatia1, A. Adler, F. Yaman, J. Beal, J. Babb, R. Weiss, and Douglas Densmore,“A Software Stack for Specification and Robotic Execution of Protocols for Synthetic Biological Engineering”, poster at SynBERC Fall Retreat, September 2011. 32 J. Babb, “APIs: The Future of Liquid Handler Programming”, talk at Tecan User’s Group meeting, Oct. 2011. 33 J Beal, R Weiss, D. Densmore, A. Adler, J. Babb, S. Bhatia, N. Davidsohn, T. Haddock, F. Yaman, R. Schantz, and J. Loyall, “TASBE: A Tool-Chain to Accelerate Synthetic Biological Engineering”, Syn- BioCCC: Workshop on the Design, Simulation, Construction and Testing of Synthetic Gene Regulatory Networks for Computation, Control, and Communications, August 2011. 34 Jonathan Babb, Adam Rubin, Thomas Knight, and Ron Weiss, “Flexible cellular platforms for reconfigurable biocircuits”, Synthetic Biology 5.0, June 2011. 35 Cristian Grecu, Jonathan Babb, Ron Weiss, “Robust Design of Genetic Circuits through Population-Wide Error Detection and Correction”, International Workshop on BioDesign Automation June 2011. 36 J. Beal, R. Weiss, D. Densmore, A. Adler, J. Babb, S. Bhatia, N. Davidsohn, T. Haddock, F. Yaman, R. Schantz, J. Loyall, “TASBE: A Tool-Chain to Accelerate Synthetic Biological Engineering”, Interna- tional Workshop on BioDesign Automation June 2011. 37 Viktor Vasilev, Chenkai Liu, Traci Haddock, Swapnil Bhatia1, Aaron Adler, Fusun Yaman, Jacob Beal, Jonathan Babb, Ron Weiss, and Douglas Densmore, “A Software Stack for Specification and Robotic Execution of Protocols for Synthetic Biological Engineering”, International Workshop on BioDesign Automation June 2011. 38 Jonathan Babb, Adam Rubin, Thomas Knight, and Ron Weiss, “Bio-Programmable Logic Array: A Reconfigurable Chassis”, poster at SynBERC Spring Retreat, March 2011. 39 Jonathan Babb, S. Cory Li, Thomas Knight, and Ron Weiss, “Multistep and multiway automated assembly of BioBricks using bead-based purification”, poster at SynBERC Spring Retreat, March 2011.

40 Cristian Grecu, Jonathan Babb, Lauren McGough, Ron Weiss, “Robust Circuit Design via a Voting- Based Error Correction Mechanism”, poster at SynBERC Spring Retreat, March 2011. 41 Aaron Adler, Jonathan Babb, Jacob Beal, Swapnil Bhatia, Douglas Densmore, Noah Davidsohn, Traci Haddock, Joe Loyall, Rick Schantz, Ron Weiss, Fusun Yaman,“Toward Automated Selection of Parts for Genetic Regulatory Networks”, Institute of Biological Engineering annual conference, March 2011. 42 MIT iGEM 2010 Team, “Programmable, Self-Constructing Biomaterials,” Institute of Biological Engi- neering annual conference, March 2011. 43 Jonathan Babb, S. Cory Li, Thomas Knight, Ron Weiss, “Rapid Multistep BioBrick Assembly using Programmable Magnetic Bead-based Solid Phase Probes”, poster at SynBERC Fall Retreat, Sep. 2010. 44 Cristian Grecu, Jonathan Babb, Cory Li, Jennifer Brophy, Ron Weiss, “Error Correction for Toggle Switches and 2D Cellular Arrays”, poster at SynBERC Fall Retreat, Sep. 2010. 45 MIT iGEM 2010 Team, “UV Inducible Pattern Formation and Phage Polymerization”, poster at Syn- BERC Fall Retreat, Sep. 2010. 46 Patrick Guye, Yinqing Li, Jonathan Babb, Ron Weiss, “Rapid Assembly and Delivery of Large Scale Genetic Circuits into Mammalian Cells”, talk presented at SynBERC Fall Retreat, Sep. 2010. 47 Jonathan Babb, Cristian Grecu, Ron Weiss, “Engineering Robust Systems in Synthetic Biology”, invited talk I presented at SynBERC Spring Retreat, Feb. 2010. Patents 47 Jonathan Babb, S.Cory Li, Thomas Knight, Ron Weiss, “Rapid Assembly of Multiple Arbitrary Length DNA Fragments.” Patent Cooperation Treaty applications PCT/US2011/053088, September 2011. 48 Jonathan Babb, Ron Weiss, Thomas Knight, Adam Rubin, “Bio-Field Programmable Gate Array and Bio-Programmable Logic Array: Reconfigurable Chassis Construction.” U.S. patent application 12/946,604, November 2010. 49 Michael Noakes, Charles Selvidge, Anant Agarwal, Jonathan Babb, and Matt Dahl, “Programmable Multiplexing Input/Output Port.” U.S. patent 5847578, December 1998. 50 Charles Selvidge, Anant Agarwal, Jonathan Babb, and Matt Dahl, “Pipelined Static Router and Sched- uler For Configurable Logic System Performing Simultaneous Communication and Computation.” U.S. patents 5850537 and 5659716, August 1997. 51 Anant Agarwal, Jonathan Babb, and Russell Tessier, “Virtual Interconnection for Reconfigurable Logic Systems.” U.S. patents 5761484 and 5596742, January 1997. Grants 52 “Genetic circuits for high-throughput, multi-sensory, live cell microRNA profiling”, Principle Investiga- tors: Ron Weiss, Peter Carr, Technical Authors: Jonathan Babb, David Kong, Todd Thorsen, National Cancer Institute (NIH R01), starts in 2013. 53 “MicroFluidic Gene Assembler ”, Principle Investigators: Ron Weiss, Todd Thorsen, Technical Authors: Jonathan Babb, Todd Thorsen, Lincoln Laboratory Campus Collaboration, Sep. 2010-2013. 54 “Technologies for Reconfigurable Architecture Workstations: The RAW Project.”, Principle Investigator: Anant Agarwal, Technical Authors: Anant Agarwal, Jonathan Babb, Russ Tessier, Advanced Research Projects Agency Proposal, March, 1996. 55 “A Technology for Low-Cost System Prototyping Based on Virtual Wires”, Principle Investigator: Anant Agarwal, Administrator: Jonathan Babb, Advanced Research Projects Agency Small Business Proposal, May, 1994.

Jonathan Babb, 6 of 6

List prior engagements potentially receiving confidential business information (CBI):

1. IPX Consulting, LLC, 11/11 – present, Consultant.  Due diligence and technical expert for patent valuation and litigation in the electronics industry.  Nazomi Communications, Inc. v. Nokia Corp. et al., 5:10-cv-4686 (N.D. Cal.) - consulting expert for plaintiff Nazomi Communications, Inc. regarding Java hardware acceleration, 11/11 – present.  U.S.I.T.C. Inv. No. 337-TA-836 (In the matter of Certain Consumer Electronics and Display Devices) - consulting expert for complainant Graphics Properties Holdings, Inc. regarding graphics processors and CPUs, 7/12 – 1/13.  U.S.I.T.C. Inv. No. 337-TA-850 (In the matter of Certain Electronic Imaging Devices), 9/12 – present.  Enterasys Networks, Inc. v. Foundry Networks, LLC; and Brocade Communication Systems, Inc., 1:05-cv-11298 (E.D. Mass.), 12/12 – 1/13.  U.S.I.T.C. Inv. No. 337-TA-882 (regarding Certain Digital Media Devices, Including Televisions, Blu-Ray Disc Players, Home Theater Systems, Tablets and Mobile Phones, Components Thereof and Associated Software), 7/13 – present.

2. Massachusetts Institute of Technology, 9/09 – present, Postdoctoral Associate. Research in computer architecture and synthetic biology.

3. Operation Simulation Associates, Inc.. 6/91 – 9/09 (no current contracts), Consultant (CTO and University Relations Manager). Software for power systems analysis. Computer accessibility software.

4. Moderna Therapeutics, Inc. 2/14 – present, Consultant. Bioinformatics software.

United States International Trade Commission Investigation No. 337-TA-884 Certain Consumer Electronics with Display Devices and Processing Capabilities

CERTIFICATE OF SERVICE

I, Megan A. De Renzis, hereby certify that on September 3, 2013, true and correct copies of the forgoing document was served on the parties listed below:

The Honorable Lisa R. Barton, Acting Secretary  Via EDIS U.S. International Trade Commission 500 E Street, S.W., Room 112  Via Federal Express (2 Copies) Washington, DC 20436

The Honorable E. James Gildea  Via Hand Delivery Administrative Law Judge U.S. International Trade Commission  Via Federal Express (2 Copies) 500 E Street, S.W., Room 317 Washington, DC 20436  Via Electronic Mail [email protected] [email protected] Matthew Bathon, Esq.  Via Hand Delivery Office of Unfair Import Investigations U.S. International Trade Commission  Via Federal Express 500 E Street SW, Suite 401 Washington, D.C. 20436  Via Electronic Mail [email protected]

On Behalf of Respondents Panasonic Corporation  Via Federal Express and Panasonic Corporation of North America:  Via Electronic Mail Steven J. Routh [email protected] Sten A. Jensen Diana M. Szego T. Vann Pearce, Jr. Christopher J. Higgins Jordan L. Coyle Orrick, Herrington &Sutcliffe, LLP 1152 15th St., NW Washington, D.C. 20005 Telephone: 202-339-8400

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United States International Trade Commission Investigation No. 337-TA-884 Certain Consumer Electronics with Display Devices and Processing Capabilities On Behalf of Respondents Toshiba Corporation,  Via Federal Express Toshiba America, Inc. and Toshiba America Information Systems, Inc.  Via Electronic Mail [email protected] Paul F. Brinkman [email protected] Marissa R. Ducca Patrick A. Fitch Quinn Emanuel Urquhart &Sullivan, LLP 1299 Pennsylvania Ave. NW, Suite 825 Washington, DC 20004 Tel.: (202) 538-8000 Fax: (202) 538-8100

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On Behalf of Respondents AmTran Logistics, Inc.  Via Federal Express and AmTran Technology Co., Ltd.  Via Electronic Mail Jamie D. Underwood [email protected]

United States International Trade Commission Investigation No. 337-TA-884 Certain Consumer Electronics with Display Devices and Processing Capabilities Thomas W. Davison Jennifer (Celine) Liu Christopher R. Byrnes Alston & Bird LLP 950 F Street NW Washington, DC 20004 Telephone: 202-239-3300

Megan A. De Renzis Legal Specialist Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C. One Financial Center Boston, MA 02111 Direct: (617) 348-4893 Fax: (617) 542-2241

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