SMARC Design Guide 2.0 March 23, 2017

Smart Mobility ARChitecture Design Guide

Note that some content of this SGeT document may be legally protected by patent rights not held by SGeT. SGeT is not obligated to identify the parts of this specification that require licensing or other legitimization. The contents of this SGeT document are advisory only. Users of SGeT documents are responsible for protecting themselves against liability for infringement of patents. All content and information within this document are subject to change without prior notice.

SGeT provides no warranty with regard to this SGeT document or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. SGeT assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and this SGeT document. In no event shall SGeT be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this SGeT document or any other information contained herein or the use thereof.

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REVISION HISTORY

Revision Comments Originator Date 1.0 Initial Release S. Milnor / Kontron July 1, 2013 1.1 Created sharper images for Fig 19, 60, 69 S. Milnor / Kontron July 5, 2013 Fixed small typos and grammar mistakes 2.0 Update to SMARC 2.0 Hardware B. Mayer / Technagon March 23, 2017 Specification

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CONTENTS

1 Introduction ...... 10 1.1 General Introduction ...... 10 1.2 Purpose of This Document ...... 10 1.3 Design Help ...... 10 1.4 Abbreviations and Acronyms Used ...... 11 1.5 Document References ...... 13 1.5.1 SGET Documents ...... 13 1.5.2 Industry Standards Documents ...... 13 1.6 Schematic Example Correctness ...... 15 1.7 Software Support ...... 15 1.8 Schematic Example Conventions ...... 16 2 Infrastructure: Connector, Power Delivery, System Management ...... 18 2.1 Module Connector ...... 18 2.2 Module Power ...... 21 2.2.1 Input Voltage Range ...... 21 2.2.2 Input Voltage Rise Time ...... 21 2.2.3 Module Maximum Input Power ...... 21 2.2.4 Power Path ...... 21 2.3 Module I/O Voltage ...... 23 2.4 VIN_PWR_BAD# ...... 24 2.5 CARRIER_PWR_ON ...... 24 2.6 Reset In to Module ...... 24 2.7 Power Button ...... 25 2.8 Force Recovery ...... 26 2.9 Power Up Sequence ...... 27 2.9.1 CARRIER_STBY# ...... 28 2.10 Boot Selection ...... 29 2.10.1 Boot Definitions ...... 29 2.10.2 SMARC BOOT_SEL Pins ...... 30 2.11 RTC Backup Power ...... 31 2.12 Reserved / Test Interfaces ...... 32 3 Display Interfaces ...... 33 3.1 Module LVDS ...... 33 3.1.1 NEC 1280 x 768 Single Channel LVDS Example ...... 33 3.1.2 LVDS Dual Channel example ...... 35 3.1.3 Display Parameters and EDID ...... 37 3.2 HDMI ...... 38 3.3 DisplayPort (DP++) ...... 39 3.3.1 HDMI over DP++ ...... 39 3.4 Embedded DisplayPort (eDP) ...... 40 3.5 MIPI DSI ...... 41 4 Low / Medium Speed Serial I/O Interfaces ...... 42 4.1 Asynchronous Serial Ports ...... 42 4.1.1 RS232 Ports ...... 42 4.1.2 RS485 Half-Duplex...... 43 4.2 I2C Interfaces ...... 45 4.2.1 General ...... 45 4.2.2 I2C Level Translation, Isolation and Buffering ...... 45 4.2.3 I2C_PM Bus EEPROMs ...... 47 4.2.4 General I2C Bus EEPROMs ...... 49 4.2.5 I2C Based I/O Expanders ...... 50 4.2.6 Other I2C Devices ...... 51 4.3 Touch Screen Controller Interfaces ...... 53 4.3.1 General ...... 53 4.3.2 Interface Types / Driver Considerations ...... 53

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4.3.3 Touch Controller Modules / ICs / Screens ...... 53 4.3.4 I2C Interface to Touch Controller ...... 55 4.4 I2S Interfaces ...... 56 4.4.1 General Information ...... 56 4.4.2 Cirrus Logic I2S Audio Example ...... 56 4.4.3 Texas Instruments TLV320AIC3105 I2S Audio Example ...... 57 4.4.4 lntel High Definition Audio over I2S2...... 58 4.4.6 Audio Switch ...... 59 4.5 SPI Interfaces ...... 59 4.5.1 General ...... 59 4.5.2 SMARC Implementation ...... 60 4.5.3 SPI Device Examples – 1.8V I/O ...... 61 4.6 CAN Bus ...... 62 4.6.1 General ...... 62 4.6.2 SMARC Implementation ...... 63 4.6.3 Isolation ...... 63 5 High Speed Serial I/O Interfaces...... 64 5.1 USB ...... 64 5.1.1 General ...... 64 5.1.2 USB0 Client / Host Direct From Module ...... 64 5.1.3 USB1 and USB2 Host Ports direct from Module ...... 66 5.1.4 USB 3.0 ...... 67 5.1.5 USB 3.0 OTG ...... 67 5.1.6 USB Hub On Carrier ...... 69 5.2 GBE ...... 72 5.2.1 GBE Carrier Connector Implementation Example ...... 72 5.2.2 GBE Mag-Jack Connector Recommendations ...... 74 5.2.3 GBE LEDs ...... 75 5.2.4 GBE software-defined Pins ...... 77 5.3 PCIe ...... 77 5.3.1 General ...... 77 5.3.2 PCIe x1 Device Down on Carrier ...... 78 5.3.3 Mini-PCIe ...... 79 5.3.4 PCIe Reference Clock buffer ...... 80 5.4 SATA ...... 81 5.4.1 General ...... 81 5.4.2 mSATA / MO-300 ...... 82 5.5 M.2 ...... 82 5.5.1 B keying ...... 83 5.5.2 M keying ...... 84 5.5.3 E keying ...... 84 6 Memory Card Interfaces ...... 86 6.1 SD Card ...... 86 7 Camera Interfaces ...... 87 7.1 General ...... 87 7.2 Camera Data Interface Formats...... 87 7.3 Camera Sensors and Camera Module Vendors ...... 87 7.4 Serial Camera Interface Example ...... 87 7.5 Other Camera Options ...... 88 8 GPIO ...... 89 8.1 SMARC Module Native GPIO ...... 89 8.2 GPIO Expansion ...... 89 9 Carrier Power Circuits ...... 90 9.1 Power Budgeting ...... 90 9.2 Input Power Sources ...... 91 9.3 Power Budgeting, Continued – Fixed 5V Power Source ...... 92 9.4 Fixed 5V DC Power Input Circuit Example ...... 93 9.5 Power Hot Swap Controller ...... 96 SMARC Design Guide 2.0 Page 5 of 119 Mar 23, 2017 ©SGeT e.V.

9.6 High Voltage LED Supply ...... 97 9.7 3.0V to 5.25V Power Input Example ...... 98 9.8 12V Input ...... 99 9.9 Wide Range Power Input ...... 100 9.10 Power Monitoring ...... 100 9.11 Power Over Ethernet ...... 102 9.12 Li-ION Battery Charger ...... 104 9.12.1 General ...... 104 9.12.2 Battery Charger Circuit Example ...... 105 10 Thermal Management ...... 109 10.1 General ...... 109 10.2 Heat Spreaders ...... 109 10.3 Heat Sinks ...... 111 10.4 Thermal Resistance Calculations...... 112 11 Carrier PCB Design Rule Summary ...... 113 11.1 General – PCB Construction Terms ...... 113 11.2 Differential Pair Cautions ...... 114 11.3 General Routing Rules and Cautions ...... 115 11.4 Trace Parameters for High-Speed Differential Interfaces ...... 116 11.5 Trace Parameters for Single Ended Interfaces ...... 117 11.6 PCB Construction Suggestions ...... 118

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FIGURES

Figure 1 Schematic Symbol Conventions ...... 16 Figure 2 Module Connector Pins P1-74 and S1-75 ...... 19 Figure 3 Module Connector Pins P75-156 and S76-158 ...... 20 Figure 4 Basic Module and Carrier Power Path ...... 22 Figure 5 Reset Switch ...... 24 Figure 6 Power Button Switch ...... 25 Figure 7 Force Recovery Switch ...... 26 Figure 8 SMARC Carrier Power up Sequence - No Power Button Case ...... 27 Figure 9 SMARC Carrier Power up Sequence - With Power Button Case ...... 28 Figure 10 Boot Selection Jumpers ...... 30 Figure 11 RTC Backup: Coin Battery / Super Cap ...... 31 Figure 12 Module LVDS: NEC Single Channel Display ...... 33 Figure 13 LVDS Dual Channel ...... 36 Figure 14 LVDS Dual Channel Power Supply ...... 36 Figure 15 Carrier EDID EEPROM ...... 37 Figure 16 HDMI Implementation ...... 38 Figure 17 DisplayPort ++ ...... 39 Figure 18 HDMI over DP++...... 40 Figure 19 Embedded DisplayPort (eDP) ...... 41 Figure 20 MIPI DSI ...... 41 Figure 21 Asynchronous Serial Port Transceiver – RS232 – TRS3253E ...... 42 Figure 22 Asynchronous Serial Port Transceiver – RS232 – MAX13235E ...... 43 Figure 23 Asynchronous Serial Port Transceiver - RS485 – Half Duplex ...... 44 Figure 24 I2C Power Domain Isolation – using FETs ...... 45 Figure 25 I2C Power Domain Isolation and Buffer – Fairchild FXMA2102 ...... 46 Figure 26 I2C_PM EEPROM: Carrier Power Domain ...... 47 Figure 27 I2C_PM EEPROM: Module Power Domain ...... 48 Figure 28 I2C_GP EEPROM...... 49 Figure 29 I2C Device: I/O Expander ...... 50 Figure 30 I2C Device: Accelerometer ...... 51 Figure 31 I2C Device: Accelerometer and Magnetometer ...... 51 Figure 32 I2C Device: Gyroscope ...... 52 Figure 33 Touch Screen Connector – I2C Interface ...... 55 Figure 34 I2S Audio Codec Cirrus Logic WM8904 ...... 56 Figure 35 I2S Audio CODEC: Texas Instruments ...... 57 Figure 36 Audio Amplifier: Texas Instruments ...... 57 Figure 37 HD Audio ...... 58 Figure 38 Audio switch ...... 59 Figure 39 SPI Flash Socket ...... 60 Figure 40 CAN Bus Implementation ...... 63 Figure 41 USB0 Client / Host Direct From Module ...... 65 Figure 42 USB1 and USB4 Host Ports Direct From Module ...... 66 Figure 43 USB 3.0 host dual ...... 67 Figure 44 USB 3.0 OTG ...... 68 Figure 45 USB Hub (1 of 2)...... 70 Figure 46 USB Hub (2 of 2)...... 71 Figure 47 GBE without POE ...... 72 Figure 48 GBE separate magnetic for current and voltage mode line driver ...... 73 Figure 49 GBE LED Current Sink ...... 75 Figure 50 GBE LED Current Sink / Source ...... 76 Figure 51 Interfacing a PCIe x1 Carrier Board Device ...... 78 Figure 52 Mini-PCIe Slot ...... 79 Figure 53 PCIe Clock buffer ...... 80 Figure 54 mSATA / MO-300...... 82

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Figure 55 M.2 Key B ...... 83 Figure 56 M.2 Key M ...... 84 Figure 57 M.2 Key E ...... 85 Figure 58 Micro SD Card Implementation ...... 86 Figure 59 Serial Camera Implementation ...... 88 Figure 60 5V Input Connector ...... 93 Figure 61 5V Carrier Power Switch ...... 93 Figure 62 3.3V 2A Buck Converter ...... 94 Figure 63 1.8V Buck Converter ...... 94 Figure 64 1.5V Buck Converter ...... 95 Figure 65 12V Boost Converter for Backlight Power ...... 95 Figure 66 Hot Swap Controller ...... 96 Figure 67 LP8545 LED Backlight Power ...... 97 Figure 68 5V, 2A Buck-Boost Converter ...... 98 Figure 69 3.3V 2A Buck-Boost Converter ...... 98 Figure 70 12V Step Down Switcher ...... 99 Figure 71 Wide Range Power Input Switcher ...... 100 Figure 72 Power Monitor - Incoming Power...... 101 Figure 73 GbE with PoE ...... 103 Figure 74 Li-ION Battery Charger - Block Diagram ...... 106 Figure 75 Li-ION Battery Charger - Schematic ...... 107 Figure 76 Battery Fuel Gauge ...... 108 Figure 77 Charger Present Detection ...... 108 Figure 78 Heat Spreader Example – 82mm x 50mm Module ...... 110 Figure 79 Heat Sink Add-On to Heat Spreader ...... 111 Figure 80 Stand-Alone Heat Sink ...... 111 Figure 81 PCB Cross Section – Striplines and Asymmetric Microstrips ...... 114

TABLES

Table 1 Schematic Power Net Naming ...... 17 Table 2 Boot Select Pins ...... 30 Table 3 I2C Device Examples - 1.8V I/O ...... 52 Table 4 Popular Touch Technologies ...... 53 Table 5 Touch Controller Module / IC / Screen Vendors ...... 53 Table 6 SPI Device Examples - 1.8V I/O ...... 61 Table 7 Recommended Gigabit Ethernet Connectors with Magnetics ...... 74 Table 8 PCIe Data Transfer Rates ...... 77 Table 9 SMARC PCIe Signal Summary ...... 77 Table 10 SATA SSD Form Factors ...... 81 Table 11 SATA SSD Vendors ...... 81 Table 12 Camera Sensors ...... 87 Table 13 Camera Module Vendors ...... 87 Table 14 Hypothetical Power Budget Example – Part 1 ...... 90 Table 15 Input Power Source Possibilities...... 91 Table 16 Hypothetical Power Budget Example – Part 2 ...... 92 Table 17 Lithium- Ion Battery Cell Voltages ...... 104 Table 18 Heat Spreader Hole Types ...... 110 Table 19 Hypothetical Thermal Parameters ...... 112 Table 20 PCB Terms and Symbols ...... 113 Table 21 High-Speed Differential Trace Parameters ...... 116 Table 22 Single Ended Trace Parameters ...... 117 Table 23 PCB Construction Example - 4 Layers ...... 118 Table 24 PCB Construction Example - 6 Layers ...... 118 Table 25 PCB Construction Example – 8 Layers ...... 119 SMARC Design Guide 2.0 Page 8 of 119 Mar 23, 2017 ©SGeT e.V.

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1 INTRODUCTION

1.1 General Introduction

SMARC (“Smart Mobility Architecture”) is a computer Module standard maintained by the SGeT (“Standardization Group for Embedded Technologies”). SMARC Modules are small form factor (82mm x 50mm and 82mm x 80mm), low power (typically <6W) computer Modules that are used on a Carrier board that utilizes a 314 pin 0.5mm pitch right-angle memory socket style connector to host the Module. SMARC Modules may utilize ARM, low power RISC or low power x86 CPUs / SOCs.

The SMARC Modules are specified in the SGeT Smart Mobility Architecture Hardware Specification 2.0. The specification document and an errata document are available free of charge from the SGET web site (www.sget.org), subject to their terms of use.

Similarly, this SMARC Design Guide is available free of charge from the SGET web site, subject to the SGET terms of use.

1.2 Purpose of This Document

The primary purpose of this document is to serve as a Design Guide for developers of SMARC Carrier Boards and for SMARC Module customers who wish to have a SMARC based system developed.

A secondary purpose of this document is to serve as a reference to SMARC Module developers, to help them understand the application of the Modules they are developing.

Finally, this document should be valuable to FAEs and Product managers to help them understand the SMARC infrastructure.

1.3 Design Help

There are a number of ways to have a SMARC Carrier board developed:

 Design internally, but have your SMARC Module vendor review your design. Make sure to also have the appropriate semiconductor companies review the portions of the design that utilize their components.

 Use a 3rd party firm that specializes in SMARC Carrier development. Such resources may be listed on the SGET web page (www.sget.org).

 Contact your SMARC Module vendor. The Module vendor will have an FAE available for advice. Many vendors will also undertake custom Carrier design projects, for significant opportunities.

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1.4 Abbreviations and Acronyms Used

 ADC Analog to Digital Converter  ARM Advanced RISC Machines www.arm.com  BCT Boot Configuration Table  BSP (software) Board Support Package  CAD Computer Aided Design  CAN Controller Area Network  CPLD Complex Programmable Logic Device  CODEC Coder – Decoder  CSI Camera Serial Interface www.mipi.org  DAC Digital to Analog Converter  DB-9 Connector, D shaped, B shell size, 9 pins  DDC Display Data Channel  DDI Digital Display Interface  DE Differential Ended (signal pair)  DNI Do Not Install (component is not loaded)  DP DisplayPort  DP++ Dual-mode DisplayPort  DSP Digital Signal Processor  DSI Display Serial Interface  EDID Extended Display Identification Data www.vesa.org  EEPROM Electrically Erasable Programmable Read Only Memory  eMMC Embedded Multi Media Card www.jedec.org  ESD Electro Static Discharge  FET Field Effect Transistor  FIFO First In First Out (buffer memory)  FS Full Speed (USB 2.0 12 Mbps)  GBE Gigabit Ethernet www.ieee.org  Gbps Gigabit per second  GPIO General Purpose Input / Output  GPS Global Positioning System  HDA High Definition Audio – Intel defined format www.intel.com  HDMI High Definition Multimedia Interface www.hdmi.org  HID Human Interface Device: USB device class  HS High Speed (USB 2.0 480 Mbps)  IC Integrated Circuit  I2C Inter-Integrated Circuit www.nxp.com  I2S Inter-Integrated Circuit – Sound www.nxp.com  IEEE Institute of Electrical and Electronics Engineers www.ieee.org  IO Input Output  ISO International Organization for Standardization (French) www.iso.org  JEDEC Joint Electron Device Engineering Council www.jedec.org  JPEG Joint Photographic Experts Group www.jpeg.org  LED Light Emitting Diode  Li-Ion Lithium Ion (rechargeable battery technology)  LVDS Low Voltage Differential Signaling  M2.5 Metric 2.5mm  M3 Metric 3.0mm  MAC Media Access Controller (e.g. logic circuits in GBE)  Mbps Megabit per second  MIPI Mobile Industry Processor Interface www.mipi.org  MLC Multi Level Cell (flash memory reference)  MOD Module (the SMARC Module) (schematic notation)

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 MO-297 Module Outline 297 (“Slim SATA” format) www.jedec.org  MO-300 Module Outline 300 (mini-PCIe Express card format) www.jedec.org  MPEG Motion Picture Experts Group www.mpeg.org  MXM Mobile pci eXpress Module www.mxm-sig.org  MXM3 MXM Revision 3  NAND A high density flash memory technology  ns Nano second (10 E -9)  NC Not Connected  NXP A semiconductor company www.nxp.com  OS Operating System  OTG On the Go (USB term – device can be host or client)  PCB Printed Circuit Board  PHY Physical (transceiver) – drives cable  PICMG PCI Industrial Computer Manufacturing Group www.picmg.org  PCI Peripheral Component Interface www.pcisig.org  PCIe PCI Express www.pcisig.org  PCI-SIG PCI Special Interest Group www.pcisig.org  PCM Pulse-Code Modulation  PLL Phase Locked Loop  POE Power Over Ethernet  ps Pico second (10 E -12)  PWM Pulse Width Modulation  RGB Video data in Red Green Blue pixel format  RISC Reduced Instruction Set Computing  ROM Read Only Memory  RS232 Recommend Standard 232 (asynchronous serial ports)  RS485 Asynchronous serial data, differential, multidrop  RTC Real Time Clock (battery backed clock and memory)  SAR Successive Approximation Register  SATA Serial ATA (serial mass storage interface) www.sata-io.org  SD Secure Digital (memory card)  SE Single Ended (signal, as opposed to differential)  SGeT Standardization Group for Embedded Technologies www.sget.org  SLC Single Level Cell (flash memory reference)  SMARC Smart Mobility Architecture www.sget.org  SMSC A semiconductor company, now MICROCHIP www.smsc.com  SOC System On Chip  S/PDIF Sony/Philips Digital Interconnect Format  SPI Serial Peripheral Interface  SSD Solid State Disk  TI Texas Instruments – semiconductor company www.ti.com  TIM Thermal Interface Material  UART Universal Asynchronous Receiver Transmitter  UL Underwriters Laboratories www.ul.com  USB Universal Serial Bus www.usb.org  VESA Video Electronics Standards Association www.vesa.org  WEC7 Windows Embedded Compact 7 (an OS)  YUV Video data format, more common in television  X5R Ceramic capacitor dielectric – good quality  X7R Ceramic capacitor dielectric – best quality  X86 Intel architecture (80x86) CPUs

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1.5 Document References

1.5.1 SGET Documents

 Smart Mobility Architecture Hardware Specification, V 2.0, June 2, 2016 © SGET (Standardization Group For Embedded Technologies) www.sget.org

1.5.2 Industry Standards Documents  BT.656 (“Recommendation ITU-R BT.656-5 Interface for digital component video signals in 525- line and 625-line television systems operating at the 4:2:2 level of Recommendation ITU-R BT.601”), International Telecommunications Union, December 2007 (www.itu.int)  CAN (“Controller Area Network”) Bus Standard – ISO 11898  CSI-2 (Camera Serial Interface version 2) The CSI-2 standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Interface Alliance”) (www.mipi.org).  CSI-3 (Camera Serial Interface version 3) The CSI-3 standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)  COM Express – the formal title for the COM Express specification is “PICMG® COM.0 COM Express Module Base Specification”, Revision 2.1, May 14, 2012. This standard is owned and maintained by the PICMG (“PCI Industrial Computer Manufacturer’s Group”) (www.picmg.org)  DisplayPort and Embedded DisplayPort These standards are owned and maintained by VESA (“Video Electronics Standards Association”) (www.vesa.org)  D-PHY CSI-2 physical layer standard – owned and maintained by the MIPI Alliance (www.mipi.org)  DSI (Display Serial Interface) The DSI standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)  eMMC (“Embedded Multi-Media Card”) the eMMC electrical standard is defined by JEDEC JESD84-B45 and the mechanical standard by JESD84-C44 (www.jedec.org).  eSPI (“Enhanced Serial Peripheral Interface”) The eSPI Interface Base Specification is defined by Intel (https://downloadcenter.intel.com/de/download/22112)  Fieldbus - this term refers to a number of network protocols used for real – time industrial control. Refer to the following web sites: www.profibus.com/downloads and www.canopen.org  GBE MDI (“Gigabit Ethernet Medium Dependent Interface”) defined by IEEE 802.3. The 1000Base-T operation over copper twisted pair cabling defined by IEEE 802.3ab (www.ieee.org).  HDA (HD Audio), High Definition Audio Specification, Intel, Revision 1.0a, June 17, 2010 (http://www.intel.com/content/dam/www/public/us/en/documents/product- specifications/high-definition-audio-specification.pdf)  HDMI Specification, Version 1.3a, November 10, 2006 © Hitachi and other companies (www.hdmi.org).  The I2C Specification, Version 2.1, January 2000, Philips Semiconductor (now NXP) (www.nxp.com).  I2S Bus Specification, Feb. 1986 and Revised June 5, 1996, Philips Semiconductor (now NXP) (www.nxp.com).  IEEE1588 - 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (http://standards.ieee.org/findstds/standard/1588- 2008.html)

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 .JTAG (“Joint Test Action Group”) This is defined by IEEE 1149.1-2001 - IEEE Standard Test Access Port and Boundary Scan Architecture (www.ieee.org )  JEDEC MO-300 (mSATA) defines the physical form factor of the mSATA format (www.jedec.org). The electrical connections are defined in the Serial ATA document.  MXM3 Graphics Module Mobile PCI Express Module Electromechanical Specification, Version 3.0, Revision 1.1, © 2009 NVidia Corporation (www.mxm-sig.org ).  PICMG® EEEP Embedded EEPROM Specification, Rev. 1.0, August 2010 (www.picmg.org).  PCI Express Specifications (www.pci-sig.org).  PCI Express Mini Card Electromechanical Specification Revision 2.0, April 21, 2012, © PCI- SIG (www.pci-sig.org).  RS-232 (EIA “Recommended Standard 232”) this standard for asynchronous serial port data exchange dates from 1962. The original standard is hard to find. Many good descriptions of the standard can be found on-line, e.g. at Wikipedia, and in text books.  Serial ATA Revision 3.1, July 18, 2011, Gold Revision, © Serial ATA International Organization (www.sata-io.org).  SD Specifications Part 1 Physical Layer Simplified Specification, Version 3.01, May 18, 2010, © 2010 SD Group and SD Card Association (“Secure Digital”) (www.sdcard.org).  SM Bus – “System Management Bus” Specification Version 3.0, 2© 2014 System Management Interface Forum, Inc. (http://www.smbus.org )  SPDIF (aka S/PDIF) (“Sony Philips Digital Interconnect Format) - IEC 60958-3.  SPI Bus – “Serial Peripheral Interface” – de-facto serial interface standard defined by Motorola. A good description may be found on Wikipedia (http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus).  UL 1642 Lithium Batteries – safety standard governing the use of lithium batteries (www.ul.com)  USB Specifications (www.usb.org).  VESA Enhanced Extended Display Identification Data Standard, Rev. 1, Feb 9, 2000, VESA (www.vesa.org) See also the “EDID” page on Wikipedia.

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1.6 Schematic Example Correctness

The schematic examples shown in this Design Guide are believed to be correct but correctness cannot be guaranteed. Most of the examples have been pulled from designs that have been built, tested, and are known to work. Most of them have been re-formatted to fit better in this design guide.

1.7 Software Support

Many hardware examples and suggestions are given in the following pages. SMARC Carrier hardware design is generally straightforward. However, before committing to a particular hardware selection, it is wise to check out the software driver support. A particular device may be supported in, say, for example, Linux but not in Windows. Your overall project may go smoother if you pick out hardware that already has software support in your target OS.

There are various possible sources for software drivers for a particular IC: the IC vendor, the OS vendor, the OS community, your Module vendor, your Carrier design partner, other independent sources and of course writing your own.

Most SMARC Module vendors offer a BSP (Board Support Package) for their Module. Your target Carrier device may be supported in the BSP – check this angle out as well.

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1.8 Schematic Example Conventions

Some of the conventions used in the schematic examples are described below. Note off-page connections that tie directly to the SMARC Module have the notation “MOD” in the off-page connect symbol.

Figure 1 Schematic Symbol Conventions

A b b re v ia tio n s

D N I D o N o t In s ta ll

O ff-S h e e t In te r-c o n n e c t: R e g u la r

In p u t

O u tp u t

B id ire c tio n a l

O ff-S h e e t In te r-c o n n e c t: T o /F ro m S M A R C M o d u le

M O D In p u t

M O D O u tp u t

M O D B id ire c tio n a l

O n -S h e e t In te r-c o n n e c t

G lo b a l P o w e r S y m b o ls

V _ 1 2 V0 V _ 5 V0 V _ 3 V3 V _ 1 V8 V _ 1 V5

V _M O D _ IN _ L E D V _ 3 V 0 _R T C V _M O D _ IN V _C A R R IE R _ IN

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Table 1 Schematic Power Net Naming

V_IN_RAW Power in to the overall system, before any filtering, fusing, polarity or rise time protection

V_IN Power in to the overall system, after (optional) filtering, fusing, polarity or rise time protection

V_MOD_IN Power into the SMARC Module. It must be within the 3.0V to 5.25V range defined by the SMARC specification

V_CARRIER_IN Power in to the Carrier Board. It may be the same as V_MOD_IN, depending on the design at hand.

On SMARC Evaluation Carrier boards, V_CARRIER_IN is sometimes kept separate from V_MOD_IN to allow easier measurements and tracking of where the power goes.

V_5V0 5V supply on the Carrier Board

V_3V3 3.3V supply on the Carrier Board

V_1V8 1.8V supply on the Carrier Board

V_1V5 1.5V supply on the Carrier Board

V_3V0_RTC Supply voltage from the Carrier Board to the SMARC VDD_RTC pin (pin S147) This is a low voltage, low current supply separate from V_MOD_IN, used to supply the Module RTC (Real Time Clock) in the absence of V_MOD_IN.

V_MOD_IN_LED Same as V_MOD_IN except isolated by a series jumper – used for power status LEDs – jumper can be removed to prevent status LEDs from consuming power

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2 INFRASTRUCTURE: CONNECTOR, POWER DELIVERY, SYSTEM MANAGEMENT

2.1 Module Connector

The SMARC Module connector is well described in the Smart Mobility ARChitecture Hardware Specification 2.0 and the complete description is not repeated here.

Briefly, the SMARC Module connector is a low profile, right angle 314 pin memory – socket style connector. The same connector is commonly used for MXM3 graphics cards. However, it is important to understand that the SMARC usage and pin-out of this connector is totally different from the usage as graphics card.

The SMARC Module connector is available from multiple sources, including at least one vendor that has qualified their offering for automotive use.

Various height profiles are available for the SMARC Module connector. The lowest profile available has a Carrier Board PCB top-side to Module PCB bottom-side separation of 1.5mm, and a connector body height of 4.3mm.

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Figure 2 Module Connector Pins P1-74 and S1-75

X1-1 P1 S1 MOD SMB_ALERT_1V8# CSI1_TX_P/I2C_CAM1_CK MOD P2 SMB_ALERT_1V8 CSI1_TX+/I2C_CAM1_CK S2 CSI1_TX_N/I2C_CAM1_DAT MOD P3 GND_01 CSI1_TX-/I2C_CAM1_DAT S3 MOD CSI1_CK_P P4 CSI1_CK+ GND_25 S4 MOD CSI1_CK_N RESERVED_05 MOD P5 CSI1_CK- RSVD_05 S5 MOD GBE1_SDP CSI0_TX_N/I2C_CAM0_CK MOD P6 GBE1_SDP CSI0_TX-/I2C_CAM0_CK S6 MOD GBE0_SDP CAM_MCK MOD P7 GBE0_SDP CAM_MCK S7 MOD CSI1_D0_P CSI0_TX_P/I2C_CAM0_DAT MOD P8 CSI1_RX0+ CSI0_TX+/I2C_CAM0_DAT S8 MOD CSI1_D0_N CSI0_CK_P MOD P9 CSI1_RX0- CSI0_CK+ S9 CSI0_CK_N MOD P10 GND_02 CSI0_CK- S10 MOD CSI1_D1_P P11 CSI1_RX1+ GND_26 S11 MOD CSI1_D1_N CSI0_RX0_P MOD P12 CSI1_RX1- CSI0_RX0+ S12 CSI0_RX0_N MOD P13 GND_03 CSI0_RX0- S13 MOD CSI1_D2_P P14 CSI1_RX2+ GND_27 S14 MOD CSI1_D2_N CIS0_RX1_P MOD P15 CSI1_RX2- CSI0_RX1+ S15 CIS0_RX1_N MOD P16 GND_04 CSI0_RX1- S16 MOD CSI1_D3_P P17 CSI1_RX3+ GND_28 S17 MOD CSI1_D3_N GBE1_MDI0_P MOD P18 CSI1_RX3- GBE1_MDI0+ S18 GBE1_MDI0_N MOD P19 GND_05 GBE1_MDI0- S19 MOD GBE0_MDI3_N GBE1_LINK100# MOD P20 GBE0_MDI3- GBE1_LINK100 S20 MOD GBE0_MDI3_P GBE1_MDI1_P MOD P21 GBE0_MDI3+ GBE1_MDI1+ S21 MOD GBE0_LINK100# GBE1_MDI1_N MOD P22 GBE0_LINK100 GBE1_MDI1- S22 MOD GBE0_LINK1000# GBE1_LINK1000# MOD P23 GBE0_LINK1000 GBE1_LINK1000 S23 MOD GBE0_MDI2_N GBE1_MDI2_P MOD P24 GBE0_MDI2- GBE1_MDI2+ S24 MOD GBE0_MDI2_P GBE1_MDI2_N MOD P25 GBE0_MDI2+ GBE1_MDI2- S25 MOD GBE0_LNK#_ACT# P26 GBE0_LINK_ACT GND_29 S26 MOD GBE0_MDI1_N GBE1_MDI3_P MOD P27 GBE0_MDI1- GBE1_MDI3+ S27 MOD GBE0_MDI1_P GBE1_MDI3_N MOD P28 GBE0_MDI1+ GBE1_MDI3- S28 MOD GBE0_CTREF GBE1_CTREF MOD P29 GBE0_CTREF GBE1_CTREF S29 MOD GBE0_MDI0_N PCIE_D_TX_P MOD P30 GBE0_MDI0- PCIE_D_TX+ S30 MOD GBE0_MDI0_P PCIE_D_TX_N MOD P31 GBE0_MDI0+ PCIE_D_TX- S31 MOD SPI0_CS1# GBE1_LINK_ACT# MOD P32 SPI0_CS1 GBE1_LINK_ACT S32 PCIE_D_RX_P MOD P33 GND_06 PCIE_D_RX+ S33 MOD SDIO_WP PCIE_D_RX_N MOD P34 SDIO_WP PCIE_D_RX- S34 MOD SDIO_CMD P35 SDIO_CMD GND_30 S35 MOD SDIO_CD# USB4_D_P MOD P36 SDIO_CD USB4+ S36 MOD SDIO_CLK USB4_D_N MOD P37 SDIO_CK USB4- S37 MOD SDIO_PWR_EN USB3_VBUS_DET MOD P38 SDIO_PWR_EN USB3_VBUS_DET S38 MOD SDIO_D[0..3] AUDIO_MCK MOD P39 GND_07 AUDIO_MCK S39 SDIO_D0 I2S0_LRCK MOD P40 SDIO_D0 I2S0_LRCK S40 SDIO_D1 I2S0_SDOUT MOD P41 SDIO_D1 I2S0_SDOUT S41 SDIO_D2 I2S0_SDIN MOD P42 SDIO_D2 I2S0_SDIN S42 SDIO_D3 I2S0_CK MOD P43 SDIO_D3 I2S0_CK S43 MOD SPI0_CS0# ESPI_ALERT0# MOD P44 SPI0_CS0 ESPI_ALERT0 S44 MOD SPI0_CK ESPI_ALERT1# MOD P45 SPI0_CK ESPI_ALERT1 S45 MOD SPIO_DIN RESERVED_06 MOD P46 SPI0_DIN RSVD_06 S46 MOD SPIO_DO RESERVED_07 MOD P47 SPI0_DO RSVD_07 S47 GND_08 GND_31 SATA_TX_P P48 S48 I2C_GP_CK MOD SATA_TX+ I2C_GP_CK MOD SATA_TX_N P49 S49 I2C_GP_DAT MOD SATA_TX- I2C_GP_DAT MOD P50 S50 HDA_SYNC/I2S2_LRCK GND_09 HDA_SYNC/I2S2_LRCK MOD SATA_RX_P P51 S51 HDA_SDO/I2S2_SDOUT MOD SATA_RX+ HDA_SDO/I2S2_SDOUT MOD SATA_RX_N P52 S52 HDA_SDI/I2S2_SDIN MOD SATA_RX- HDA_SDI/I2S2_SDIN MOD P53 S53 HDA_CK/I2S2_CK GND_10 HDA_CK/I2S2_CK MOD ESPI_CS0# P54 S54 SATA_ACT# MOD ESPI_CS0 SATA_ACT MOD ESPI_CS1# P55 S55 USB5_EN_OC# MOD ESPI_CS1 USB5_EN_OC MOD ESPI_CK P56 S56 ESPI_IO2 MOD ESPI_CK ESPI_IO_2 MOD ESPI_IO_0 P57 S57 ESPI_IO3 MOD ESPI_IO_0 ESPI_IO_3 MOD ESPI_IO_1 P58 S58 ESPI_RESET# MOD ESPI_IO_1 ESPI_RESET MOD P59 S59 USB5_D_P GND_11 USB5+ MOD USB0_D_P P60 S60 USB5_D_N MOD USB0+ USB5- MOD USB0_D_N P61 S61 MOD USB0- GND_32 USB0_EN_OC# P62 S62 USB3_SSTX_P MOD USB0_EN_OC USB3_SSTX+ MOD USB0_VBUS_DET P63 S63 USB3_SSTX_N MOD USB0_VBUS_DET USB3_SSTX- MOD USB0_OTG_ID P64 S64 MOD USB0_OTG_ID GND_33 USB1_D_P P65 S65 USB3_SSRX_P MOD USB1+ USB3_SSRX+ MOD USB1_D_N P66 S66 USB3_SSRX_N MOD USB1- USB3_SSRX- MOD USB1_EN_OC# P67 S67 MOD USB1_EN_OC GND_34 P68 S68 USB3_D_P GND_12 USB3+ MOD USB2_D_P P69 S69 USB3_D_N MOD USB2+ USB3- MOD USB2_D_N P70 S70 MOD USB2- GND_35 USB2_EN_OC# P71 S71 USB2_SSTX_P MOD USB2_EN_OC USB2_SSTX+ MOD RESERVED_01 P72 S72 USB2_SSTX_N MOD RSVD_01 USB2_SSTX- MOD RESERVED_02 P73 S73 MOD RSVD_02 GND_36 USB3_EN_OC# P74 S74 USB2_SSRX_P MOD USB3_EN_OC USB2_SSRX+ MOD S75 USB2_SSRX_N USB2_SSRX- MOD

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SMARC Design Guide 2.0 Page 19 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 3 Module Connector Pins P75-156 and S76-158

X1-2 P75 S76 PCIE_B_RST# MOD PCIE_A_RST# PCIE_A_RST PCIE_B_RST MOD MOD USB_4_EN_OC# P76 S77 PCIE_C_RST# MOD P77 USB4_EN_OC PCIE_C_RST S78 PCIE_C_RX_P MOD RESERVED_03 RSVD_03 PCIE_C_RX+ MOD MOD RESERVED_04 P78 S79 PCIE_C_RX_N MOD P79 RSVD_04 PCIE_C_RX- S80 P80 GND_13 GND_37 S81 PCIE_C_TX_P MOD PCIE_C_REFCK_P PCIE_C_REFCK+ PCIE_C_TX+ MOD MOD PCIE_C_REFCK_N P81 S82 PCIE_C_TX_N MOD P82 PCIE_C_REFCK- PCIE_C_TX- S83 P83 GND_14 GND_38 S84 PCIE_B_REFCK_P MOD PCIE_A_REFCK_P PCIE_A_REFCK+ PCIE_B_REFCK+ MOD MOD PCIE_A_REFCK_N P84 S85 PCIE_B_REFCK_N MOD P85 PCIE_A_REFCK- PCIE_B_REFCK- S86 P86 GND_15 GND_39 S87 PCIE_B_RX_P MOD PCIE_A_RX_P PCIE_A_RX+ PCIE_B_RX+ MOD MOD PCIE_A_RX_N P87 S88 PCIE_B_RX_N MOD P88 PCIE_A_RX- PCIE_B_RX- S89 P89 GND_16 GND_40 S90 PCIE_B_TX_P MOD PCIE_A_TX_P PCIE_A_TX+ PCIE_B_TX+ MOD MOD PCIE_A_TX_N P90 S91 PCIE_B_TX_N MOD P91 PCIE_A_TX- PCIE_B_TX- S92 P92 GND_17 GND_41 S93 DP0_LANE0_P MOD HDMI_D2_P/DP1_LANE0_P HDMI_D2+/DP1_LANE0+ DP0_LANE0+ MOD MOD HDMI_D2_N/DP1_LANE0_N P93 S94 DP0_LANE0_N MOD P94 HDMI_D2-/DP1_LANE0- DP0_LANE0- S95 DP0_AUX_SEL GND_18 DP0_AUX_SEL MOD MOD HDMI_D1_P/DP1_LANE1_P P95 S96 DP0_LANE1_P MOD P96 HDMI_D1+/DP1_LANE1+ DP0_LANE1+ S97 DP0_LANE1_N MOD HDMI_D1_N/DP1_LANE1_N HDMI_D1-/DP1_LANE1- DP0_LANE1- MOD P97 S98 DP0_HPD MOD P98 GND_19 DP0_HPD S99 DP0_LANE2_P MOD HDMI_D0_P/DP1_LANE2_P HDMI_D0+/DP1_LANE2+ DP0_LANE2+ MOD MOD HDMI_D0_N/DP1_LANE2_N P99 S100 DP0_LANE2_N MOD P100 HDMI_D0-/DP1_LANE2- DP0_LANE2- S101 GND_20 GND_42 MOD HDMI_CK_P/DP1_LANE3_P P101 S102 DP0_LANE3_P MOD P102 HDMI_CK+/DP1_LANE3+ DP0_LANE3+ S103 DP0_LANE3_N MOD HDMI_CK_N/DP1_LANE3_N HDMI_CK-/DP1_LANE3- DP0_LANE3- MOD P103 S104 UDB3_OTG_ID MOD P104 GND_21 USB3_OTG_ID S105 DP0_AUX_P MOD HDMI_HDP/DP1_HPD HDMI_HPD/DP1_HPD DP0_AUX+ MOD MOD HDMI_CTRL_CK/DP1_AUX_P P105 S106 DP0_AUX_N MOD P106 HDMI_CTRL_CK/DP1_AUX+ DP0_AUX- S107 LCD1_BKLT_EN MOD HDMI_CTRL_DAT/DP1_AUX_N HDMI_CTRL_DAT/DP1_AUX- LCD1_BKLT_EN MOD MOD DP1_AUX_SEL P107 S108 LVDS1_CK_P/eDP1_AUX_P/DSI1_CLK_P MOD P108 DP1_AUX_SEL LVDS1_CK+/eDP1_AUX+/DSI1_CLK+ S109 LVDS1_CK_N/eDP1_AUX_N/DSI1_CLK_N MOD GPIO0/CAM0_PWR GPIO0/CAM0_PWR LVDS1_CK-/eDP1_AUX-/DSI1_CLK- MOD MOD GPIO1/CAM1_PWR P109 S110 P110 GPIO1/CAM1_PWR GND_43 S111 LVDS1_D0_P/eDP1_TX0_P/DSI1_D0_P MOD GPIO2/CAM0_RST GPIO2/CAM0_RST LVDS1_0+/eDP1_TX0+/DSI1_D0+ MOD MOD GPIO3/CAM1_RST P111 S112 LVDS1_D0_N/eDP1_TX0_N/DSI1_D0_N MOD P112 GPIO3/CAM1_RST LVDS1_0-/eDP1_TX0-/DSI1_D0- S113 eDP1_HPD MOD GPIO4/HDA_RST GPIO4/HDA_RST eDP1_HPD MOD MOD GPIO5/PWM_OUT P113 S114 LVDS1_D1_P/eDP1_TX1_P/DSI1_D1_P MOD P114 GPIO5/PWM_OUT LVDS1_1+/eDP1_TX1+/DSI1_D1+ S115 LVDS1_D1_N/eDP1_TX1_N/DSI1_D1_N MOD GPIO6/TACHIN GPIO6/TACHIN LVDS1_1-/eDP1_TX1-/DSI1_D1- MOD MOD GPIO7 P115 S116 LCD1_VDD_EN MOD P116 GPIO7 LCD1_VDD_EN S117 LVDS1_D2_P/eDP1_TX2_P/DSI1_D2_P MOD GPIO8 GPIO8 LVDS1_2+/eDP1_TX2+/DSI1_D2+ MOD MOD GPIO9 P117 S118 LVDS1_D2_N/eDP1_TX2_N/DSI1_D2_N MOD P118 GPIO9 LVDS1_2-/eDP1_TX2-/DSI1_D2- S119 MOD GPIO10 GPIO10 GND_44 MOD GPIO11 P119 S120 LVDS1_D3_P/eDP1_TX3_P/DSI1_D3_P MOD P120 GPIO11 LVDS1_3+/eDP1_TX3+/DSI1_D3+ S121 LVDS1_D3_N/eDP1_TX3_N/DSI1_D3_N GND_22 LVDS1_3-/eDP1_TX3-/DSI1_D3- MOD MOD I2C_PM_CK P121 S122 LCD1_BKLT_PWM MOD P122 I2C_PM_CK LCD1_BKLT_PWM S123 RESERVED_08 MOD I2C_PM_DAT I2C_PM_DAT RSVD_08 MOD MOD BOOT_SEL0# P123 S124 P124 BOOT_SEL0 GND_45 S125 LVDS0_D0_P/eDP0_TX0_P/DSI0_D0_P MOD BOOT_SEL1# BOOT_SEL1 LVDS0_0+/eDP0_TX0+/DSI0_D0+ MOD MOD BOOT_SEL2# P125 S126 LVDS0_D0_N/eDP0_TX0_N/DSI0_D0_N MOD P126 BOOT_SEL2 LVDS0_0-/eDP0_TX0-/DSI0_D0- S127 LCD0_BKLT_EN MOD RESET_OUT# RESET_OUT LCD0_BKLT_EN MOD MOD RESET_IN# P127 S128 LVDS0_D1_P/eDP0_TX1_P/DSI0_D1_P MOD P128 RESET_IN LVDS0_1+/eDP0_TX1+/DSI0_D1+ S129 LVDS0_D1_N/eDP0_TX1_N/DSI0_D1_N MOD POWER_BTN# POWER_BTN LVDS0_1-/eDP0_TX1-/DSI0_D1- MOD MOD SER0_TX P129 S130 P130 SER0_TX GND_46 S131 LVDS0_D2_P/eDP0_TX2_P/DSI0_D2_P MOD SER0_RX SER0_RX LVDS0_2+/eDP0_TX2+/DSI0_D2+ MOD MOD SER0_RTS# P131 S132 LVDS0_D2_N/eDP0_TX2_N/DSI0_D2_N MOD P132 SER0_RTS LVDS0_2-/eDP0_TX2-/DSI0_D2- S133 LCD0_VDD_EN MOD SER0_CTS# SER0_CTS LCD0_VDD_EN MOD P133 S134 LVDS0_CK_P/eDP0_AUX_P/DSI0_CLK_P MOD P134 GND_23 LVDS0_CK+/eDP0_AUX+/DSI0_CLK+ S135 LVDS0_CK_N/eDP0_AUX_N/DSI0_CLK_N MOD SER1_TX SER1_TX LVDS0_CK-/eDP0_AUX-/DSI0_CLK- MOD MOD SER1_RX P135 S136 P136 SER1_RX GND_47 S137 LVDS0_D3_P/eDP0_TX3_P/DSI0_D3_P MOD SER2_TX SER2_TX LVDS0_3+/eDP0_TX3+/DSI0_D3+ MOD MOD SER2_RX P137 S138 LVDS0_D3_N/eDP0_TX3_N/DSI0_D3_N MOD P138 SER2_RX LVDS0_3-/eDP0_TX3-/DSI0_D3- S139 I2C_LCD_CLK MOD SER2_RTS# SER2_RTS I2C_LCD_CK MOD MOD SER2_CTS# P139 S140 I2C_LCD_DAT MOD P140 SER2_CTS I2C_LCD_DAT S141 LCD0_BKLT_PWM MOD SER3_TX SER3_TX LCD0_BKLT_PWM MOD MOD SER3_RX P141 S142 RESERVED_09 MOD P142 SER3_RX RSVD_09 S143 GND_24 GND_48 MOD CAN0_TX P143 S144 eDP0_HPD MOD P144 CAN0_TX eDP0_HPD S145 WDT_TIME_OUT# MOD CAN0_RX CAN0_RX WDT_TIME_OUT MOD MOD CAN1_TX P145 S146 PCIE_WAKE# MOD V_RTC P146 CAN1_TX PCIE_WAKE S147 VDD_RTC MOD CAN1_RX CAN1_RX VDD_RTC P147 S148 LID# VDD_IN_01 LID MOD P148 S149 SLEEP# MOD P149 VDD_IN_02 SLEEP S150 VIN_PWR_BAD# VDD_IN_03 VIN_PWR_BAD MOD V_MOD_IN P150 S151 CHARGING# MOD P151 VDD_IN_04 CHARGING S152 CHARGER_PRESENT# VDD_IN_05 CHARGER_PRSNT MOD P152 S153 CARRIER_STANDBY# MOD P153 VDD_IN_06 CARRIER_STBY S154 CARRIER_PWR_ON VDD_IN_07 CARRIER_PWR_ON MOD P154 S155 FORCE_RECOV# MOD P155 VDD_IN_08 FORCE_RECOV S156 BAT_LOW# VDD_IN_09 BATLOW MOD P156 S157 TEST# MOD VDD_IN_10 TEST S158 GND_49

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SMARC Design Guide 2.0 Page 20 of 119 Mar 23, 2017 ©SGeT e.V.

2.2 Module Power

2.2.1 Input Voltage Range

Per the SMARC Module Hardware Specification, the SMARC Modules may accept input power over the voltage range 3.0V to 5.25V. This range coincides with the range of a single-level lithium – ion cells and allows the use of common 5V or 3.3V fixed DC supplies.

2.2.2 Input Voltage Rise Time

There are currently no limits in the SMARC Module Hardware Specification on the Module power supply rise times. In general, it is not wise to expose the Module and Carrier electronics to extremely fast power supply rise times (as may be the case if a low impedance power source such as a battery pack or power brick is “hot-plugged”). Input power supply rise times faster than 50V / millisecond to the Module should be avoided. If a unit is to be “hot-plugged” to a low impedance power source, then the Carrier should implement measures to slow the power rise time as seen by the Module and Carrier circuits. The Carrier can do this by implementing a FET and hot-swap controller in the input power path. This is discussed in Section 9.5 Power Hot Swap Controller.

2.2.3 Module Maximum Input Power

The SMARC V2.0 specification document states that the allowable input voltage range is 3.0V to 5.25V. The rationale for this is that this range coincides with the voltage range of single level lithium-ion cells, and that it also allows the use of common 5V or 3.3V bench supplies. However, it is not mandatory in the V2.0 specification that Modules are required to work at the lower end (3.0V) of this range.

The SMARC Module physical connector is a MXM3 connector (although the pinout is completely different). The MXM3 specification document requires that the MXM3 connector pins be able to carry 0.5A current minimum. SMARC Modules allocate 10 pins for input power (and 49 GND pins for signal and power return). Thus, per the MXM3 connector requirement, the 10 pins should be capable of handling 5A. This allows a maximum power input range of 15W (for 3.0V power in) to 26W (for 5.25V power in).

For conservative design, let us operate the MXM3 connector pins at no more than 70% of their capacity. Then the following maximum power inputs are achieved:

10 pins * 0.5A * 70% * 3.0V = 10.5W (low end of Li-Ion battery)

10 pins * 0.5A * 70% * 4.75V = 16.6W (low end of 5V bench supply)

These numbers apply to the Module only, and not to the Carrier circuits. The 10.5W is adequate for low power Modules that are to be served by single level Lithium-Ion cells. The 16.6W should be adequate for higher power Modules (Including x86 designs) operating from a 5V supply.

2.2.4 Power Path

The power path for a basic, fixed input voltage arrangement SMARC Module and Carrier board system is shown in Figure 4 Basic Module and Carrier Power Path below. A number of features in the figure are optional and may be omitted (and bypassed) in a minimal implementation. The figure also shows Carrier Board power supply sections assuming a typical system powered by a power source in the 3.0V to 5.25V range

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Figure 4 Basic Module and Carrier Power Path

V_IN_RAW

Active low reset RESET_OUT# RESET_IN# to Carrier Board

Optional I2C_PM Power Common – Mode devices active when V_1V8 PWR_BTN# I2C_PM domain Choke / Filter CARRIER_PWR_ON Power Rail Isolation is high

Optional Hot Swap Optional I2C_PM Controller + FET devices active when V_1V8_ALWAYS CARRIER_PWR_ON Power Rail V_IN is low VDD_IN SMARC Module

Optional Power VIN_PWR_BAD# Module IO Module – Carrier IO Supervisor

Open Drain - pulled low if input power is out of spec LCD_BKLT_EN

CARRIER_PWR_ON

Carrier Board Power Supplies – Enabled by Module CARRIER_PWR_ON signal

USB Power IN OUT V_5V0 Switches FET Switch (if 5V input) EN Buck-Boost Converter (if 3.0 to 5.25V input) Boost converter (if 3.3V input)

IN OUT V_3V3 Mini-PCIe SATA MO-300 Buck Converter (if 5V input) USB Hub EN Buck-Boost (if 3.0 to 5.25V) General Purpose 3.3V FET Switch (if 3.3V input)

IN OUT V_1V8 Module I/O Low voltage I2C and I2S peripherals EN Buck Converter

IN OUT V_1V5 Mini PCIe SATA MO-300 EN Buck Converter

LCD Backlight IN OUT V_BKLT Voltage depends on backlight type EN Boost Converter

For optional I2C_PM Periphals that need to be Optional powered when LDO V_1V8_ALWAYS CARRIER_PWR_ON Is inactive .

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2.3 Module I/O Voltage

The SMARC Module Hardware Specification specifies the use of 1.8V Module I/O

I/O at 1.8V is used in general for low power interfaces. Many contemporary peripherals of interest are available with I/O interfaces that support 1.8V and 3.3V; some are available at 1.8V only, and others at 3.3V only. Specific examples are given in various document sections below.

If devices that support only 3.3V are implemented, a level shifter has to be used to interface them to the SMARC Module.

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2.4 VIN_PWR_BAD#

This optional signal may be used to tell the Module that the input power to the Module is not ready. An open-drain driver should be used.

2.5 CARRIER_PWR_ON

The CARRIER_PWR_ON signal is driven by the Module at a 1.8V level. It is a signal to Carrier that the Carrier board specific power supplies may be enabled. This is illustrated in Figure 4 Basic Module and Carrier Power Path above.

2.6 Reset In to Module

The SMARC RESET_IN# signal may be used to force a SMARC system reset. It is an input to the Module. The signal is pulled up on the Module. If used, by the Carrier board, then an open drain device or switch to GND should be used. A switch example is shown in the following figure. The signal is ESD protected in this example, as the switch (and the switch interaction with humans) introduces an ESD hazard.

Figure 5 Reset Switch

SW1 Panasonic EVQ-PBC04M A1 B1

RESET_IN# MOD A2 B2 G GND V_MOD_IN 3 D21 2 1 TH

1 2 C285 100nF 50V

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2.7 Power Button

SMARC defines a pin to allow the implementation of a Carrier based power button. However - caution - the SMARC Hardware Specification does not define the power up behavior of a Module. The following possibilities exist after a cold power on:

a) Module boots

b) Module waits for a Power Button press to boot

c) The Module is configurable – either behavior a) or behavior b) may be configured

Users are advised to check with your Module vendor on this topic. A Power Button switch example is shown in the figure below. If your Module waits for a Power Button press on power up and you want it to always boot on power up, you have to arrange for a “power button press” on power up, using an open drain device to interface to the SMARC Module.

Figure 6 Power Button Switch

SW2 Panasonic EVQ-PBC04M A1 B1

POWER_BTN# MOD A2 B2 G GND V_MOD_IN 3 D20 TH 2 1

1 2 C284 100nF 50V

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2.8 Force Recovery

Some Modules support a “force recovery” function in which the primary boot media can be re-initialized over a designated I/O interface, such as a USB client interface, asynchronous serial port, or Ethernet port. This is Module specific; refer to your Module documentation for further details.

Figure 7 Force Recovery Switch

SW3 Panasonic EVQ-PBC04M A1 B1

FORCE_RECOV# MOD A2 B2 G GND V_MOD_IN 3 D22 2 1 TH

1 2 C283 100nF 50V

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2.9 Power Up Sequence

The basic power up sequence for SMARC Modules and Carriers is shown in the following two figures. There is a Module design and / or configuration dependence with regard to the power button behavior. Depending on design and / or configuration, the Module may always boot without waiting for a power button press, or it may wait for a power button press. These cases are shown in the figures.

It is recommended to arrange that the main Carrier power supplies not come up until the Module asserts the CARRIER_PWR_ON signal. When this is high, you know that the Module power supplies are all up. If the Carrier power is up before the Module supplies are up, there is a risk that the Carrier circuits will back- feed power to the Module I/O pins, which might interfere with a Module boot.

Figure 8 SMARC Carrier Power up Sequence - No Power Button Case

S5 >> S3 S0 ACPI-State (only for x86 designs)

POWER IN (3-5.25V)

V_MOD_IN (3-5.25V)

POWER_BTN#

CARRIER_PWR_ON

Carrier Power Rails V_5V0 V_3V3 V_1V8 V_1V5

CARRIER_STBY#

RESET_OUT#

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The case of a Module that is designed or configured to wait for a power button press before it comes up is diagramed below. When power is applied to the Module, in this case, only a small portion of the Module is using that power – typically, the Module Power Management section – and that circuitry waits for a power button press. When it sees one, the Module proceeds with the boot. When the main Module power rails are up, the Module asserts CARRIER_PWR_ON. The Carrier should use this signal to enable the various Carrier power rails. However, Carrier circuits that are involved in power management (battery charge level, reset monitors, etc.) may be powered ahead of CARRIER_PWR_ON, coincident with the Module power.

Figure 9 SMARC Carrier Power up Sequence - With Power Button Case

S5 >> S3 S0 ACPI-State (only for x86 designs)

POWER IN (3- 5.25V)

V_MOD_IN (3- 5.25V)

POWER_BTN# NOT x86 chipset Power button signal

CARRIER_PWR_ON

Carrier Power Rails V_5V0 V_3V3 V_1V8 V_1V5

CARRIER_STBY#

RESET_OUT#

2.9.1 CARRIER_STBY# A low level on CARRIER_STBY# indicates that the system is going into the standby state, where only power management functions and system memory are powered. The ACPI equivalent is suspend to ram (S3). This signal can be used to switch off power supplies on the Carrier board that are not necessarily needed during standby. Any devices that should be able to wake the system out of the standby state should use the CARRIER_PWR_ON signal instead.

SMARC Design Guide 2.0 Page 28 of 119 Mar 23, 2017 ©SGeT e.V.

2.10 Boot Selection

2.10.1 Boot Definitions

Most SOCs used on SMARC Modules have the following attributes:

1) An internal ROM exists. The internal ROM code is executed after the SOC comes out of reset. This ROM code is provided by the silicon vendor and is generally not available or visible to users.

2) A set of SOC strap pins is used to select what SOC physical device interface (SD Card, SPI, eMMC, etc.) will be used for the second – stage boot process (also known as BCT or Boot Configuration Table boot). There is no commonality between various SOCs as to how the strap pins are defined.

3) The SOC pin configuration is very flexible – most SOC pins can be used for several functions, and the SMARC Module designer must choose a pin configuration that works for the design at hand. The SOC pin configuration is set by a Boot Configuration Table that is read out from the external boot media (SD Card, SPI, eMMC, etc.).

There are several stages in the boot process:

1) Internal SOC ROM execution

2) second stage boot, from non-volatile memory external to the SOC: BCT is loaded and various other system parameters are set

3) Operating System load

The Operating System load may occur from the same memory as the second stage BCT boot, or the second stage code may pass the Operating System load off to another device, such as a USB drive or SATA drive.

SMARC Design Guide 2.0 Page 29 of 119 Mar 23, 2017 ©SGeT e.V.

2.10.2 SMARC BOOT_SEL Pins

The SMARC Hardware Specification defines 3 SMARC pins, designated BOOT_SEL0# through BOOT_SEL2#, that may be used to tell the Module what physical device to do a BCT boot from. The SMARC BOOT_SELx# pins serve to abstract the SOC – dependent strap definitions into a common SMARC definition. The table below is reproduced from the SMARC Hardware Specification document.

Table 2 Boot Select Pins

Carrier Connection Boot Source

BOOT_SEL2# BOOT_SEL1# BOOT_SEL0# 0 GND GND GND Carrier SATA 1 GND GND Float Carrier SD Card 2 GND Float GND Carrier eMMC Flash 3 GND Float Float Carrier SPI 4 Float GND GND Module device (NAND, NOR) – vendor specific 5 Float GND Float Remote boot (GBE, serial) – vendor specific 6 Float Float GND Module eMMC Flash 7 Float Float Float Module SPI

The Module BOOT_SELx# pins may be set by jumpers on the Carrier Board, as shown in the figure below. The diodes and capacitors are for ESD protection, as the jumpers may experience ESD events.

Alternatively, the BOOT_SELx# pins can be set by low value option resistors to GND on the Carrier. The resistors are either installed (for a GND connection) or not installed, per the table above.

Figure 10 Boot Selection Jumpers

BOOT_SEL2# BOOT_SEL1# BOOT_SEL0# MOD MOD MOD J45 J46 J44 FCI 77311-118-02LF FCI 77311-118-02LF FCI 77311-118-02LF 1 1 1 1 1 1 2 2 2 2 2 2 V_MOD_IN V_MOD_IN 3 V_MOD_IN 3 D23 3 D25 D24 2 1 2/1x2/2.54 2/1x2/2.54

2 1 2 2 1 2/1x2/2.54 THT 2 THT

2 THT 2 R288 2 R289 2 R290

040 1KOhm 1KOhm 040 1KOhm

040 1 2 1 1 2 C286 1 2 1 C288 1 100nF C287 100nF 50V 100nF 50V 50V

SMARC Design Guide 2.0 Page 30 of 119 Mar 23, 2017 ©SGeT e.V.

2.11 RTC Backup Power

The Module RTC (Real Time Clock) circuit requires a backup power source if the Module RTC circuit is expected to keep time in the absence of the primary power source (i.e. the power to Module VDD_IN pins, P147 through P156). The RTC backup power, if used, is applied to the Module VDD_RTC pin, pin S147. The RTC backup power may be provided by a battery or by a large value capacitor, known as a “Supercap”.

If a battery is used, the battery is typically a small lithium coin cell with a capacity of a few hundred mAh. Lithium coin cells offer a high energy density, low self-discharge rate, and are not rechargeable. For safety reasons, they must be protected against charging on the Carrier board by a redundant set of circuit elements – typically either two diodes in series or a diode and a resistor. The resistor, if used, must be large enough to limit the battery charging current to be equal to or lower than the amount specified as allowable by the battery vendor. The safety aspects of lithium battery use is governed by a UL document (UL 1642 Lithium Batteries, www.ul.com).

The Supercap solution differs from the lithium battery solution in that it needs to be charged by the Module (when the Module has its primary power source); hence a blocking diode should not be used with the Supercap.

The time period over which the RTC backup power is effective depends on the Module RTC backup current draw, the exact voltage range over which the Module RTC circuit is functional, on the capacity characteristics of the battery or Supercap, on the drops incurred across the Carrier board circuit protection elements, and on the operating temperature. In general terms, a suitable lithium battery solution can provide RTC backup current on a scale of years; the Supercap solution on a scale of days to weeks.

Figure 11 RTC Backup: Coin Battery / Super Cap

V_3V0_RTC V_3V0_RTC 2

2 R270

040 1KOhm

2 1

2 R269 C

040 1KOhm D12

Vishay BAT54W-V 1

A 1

+ Super Cap 1 C240 BT1 200mF Renata SMTU2032-LF 2 3.3V SMT Elna DSK-3R3H204T614-H2L 2P

- 2

Coin Battery Holder, R/A, SMT

SMARC Design Guide 2.0 Page 31 of 119 Mar 23, 2017 ©SGeT e.V.

2.12 Reserved / Test Interfaces

The Module TEST# pin (pin S157) should normally be left not connected. If pulled low, then Module specific test function(s) may be enabled.

Reserved pins should be left not connected and may be used in future revisions of the SMARC specification.

SMARC Design Guide 2.0 Page 32 of 119 Mar 23, 2017 ©SGeT e.V.

3 DISPLAY INTERFACES

3.1 Module LVDS

3.1.1 NEC 1280 x 768 Single Channel LVDS Example

The Module LVDS interface may be used with single channel LVDS displays. SMARC Modules typically support LVDS 18 bit single channel operation (three data pairs plus one clock pair). They may also support LVDS 24 bit single channel operation (four data pairs plus one clock pair). Recall that there are two 24 bit color mappings in common use: most significant color bits on fourth data pair (sometimes referred to as the standard 24 bit mapping), and least significant color bits on the fourthLVDS data pair (referred to as 24 bit / 18 bit compatible or as 24 bit / 6 bit pack or similar). The standard 24 bit color mapping is more common but is incompatible with the 18 bit packing.

The example below shows an implementation used with an NEC 1280 x 768 single channel LVDS panel (NL 12876AC18-03). This panel uses a discrete wire 30 pin Hirose DF19 series connector. The panel backlight electronics accepts a 12V supply, and panel brightness is controlled by a 3.3V PWM signal. There is no EDID EEPROM on this particular NEC display.

This display happens to support 18 bit, 24 bit / 18 bit compatible and standard 24 bit LVDS packings. The panel also allows the image to be reversed. This can be useful if you find the panel connector orientations to be inconvenient – you can rotate the display 180 degrees, alter the scan direction strap, and have the image appear in the correct orientation. These options are set by pull-up and pull-down choices on connector pins 11, 26 and 27 in the image below. Refer to the display data sheet for further information.

The display LVDS data and clock differential pairs may be connected directly to the SMARC Module. The backlight PWM and panel enable need level translation and / or buffering as shown in the figure.

Figure 12 Module LVDS: NEC Single Channel Display

NEC Panel Connector V_1V8 V_3V3 V_12V0 V_1V8 V_3V3 J2

2 Hirose DF19G-30P-1H

2 R240 1 0 R20 1 1

4 10KOhm 2 C173

0 0 2 4.7KOhm 2 2 2 C116 4 1uF DNI C117 100nF 0 3 1 100nF U9 16V 3 25V 2 25V TI SN74AVC2T244DQ 1 4 1 1 4 5 5 1 VCCA VCCB 8 6 6 LVDS_BKLT_PWM_3V3 7 LCD_BKLT_PWM 2 7 LVDS_BKLT_PWM_3V3 7 MOD A1 B1 LVDS_BKLT_EN_3V3 8 8 2 9 LCD_BKLT_EN 3 6 LVDS_BKLT_EN_3V3 R53 9 MOD A2 B2 2 0 1KOhm 10 10

0 DNI SIX_BIT_PACK# 11 BUFFER_OE# 11 4 OE# GND 5

1 LVDS0_P MOD 12 12 LVDS0_N 13

2 MOD 13 MicroQFN8 14 14

R169 0 LVDS1_P 15 4 MOD 15

0Ohm 0 LVDS1_N MOD 16 16

1 17 17 V_3V3 V_3V3 LVDS2_P MOD 18 18 LVDS2_N MOD 19 19 20 20

2 2 LVDS_CK_P MOD 21 21 R19 R18

2 2 LVDS_CK_N 22

0 4.7KOhm 0 4.7KOhm MOD 22

4 4

0 0 DNI 23 23 LVDS3_P 24 V_3V3 1 1 MOD 24 LVDS3_N U3 MOD 25 25 MODE TI TPS22924C 26 26 SC 27 27 A2 A1 V_3V3_SWITCHED_A VIN_A2 VOUT_A1 28 28 B2 B1 2 2 31 VIN_B2 VOUT_B1 29 29 M1 1 R52 R51 2 2 V_3V3_SWITCHED_A 30 32 C1741 C183 0 1KOhm 0 1KOhm 30 M2 470nF 4 4 1uF 0 DNI 0 1 C138 1 16V 2 6.3V C141

2 1 1 1uF LCD_VDD_EN C2 22uF SMT MOD ON 10V 10V 30/1x30/1.0 2 2 Vih = 1.2 V C1

2 Vil = 0.6V GND 30 Pin, 1mm Pitch, R/A, SMT

R257 2

100KOhm 4 BGA6

SMARC Design Guide 2.0 Page 33 of 119 Mar 23, 2017 ©SGeT e.V.

Power for the display’s logic is gated by the Module LCD_VDD_EN signal, as shown above.

The NEC LVDS display in the example above accepts a 12V feed to power the display’s LED backlight. The SMARC Module provides two backlight control signals, LCD_BKLT_EN and LCD_BKLT_PWM (enable and brightness).

Some displays require a higher voltage feed to their LED backlight electronics. An example of this is given in Section 9.6 High Voltage LED Supply.

SMARC Design Guide 2.0 Page 34 of 119 Mar 23, 2017 ©SGeT e.V.

3.1.2 LVDS Dual Channel example

The schematic example below shows an implementation on the Carrier that can be used either for a dual channel LVDS display or two single channels LVDS displays with common supply voltage. The LVDS signals are routed through common mode chokes to the LVDS connector. All display signals include ESD devices. Supply voltage for LVDS display and backlight can be selected by jumper settings. The control signals for backlight, LVDS display and I2C bus are routed over level shifters from 1.8V on SMARC connector side to the display I/O voltage.

Additional comments to schematic example: • Signal LVDS_VDDEN: If FET power switching is used this signal pin can also be connected to EN_PANELPOWER instead of PG_VPANEL. In this case PU resistor R15 and diode D1 can be removed. • LVDS connector type: Neither connector type nor pinout of the connector underlies any standards specification. So everyone is free to select a suitable LVDS connector for best application fit. • Comment on jumper settings: CN1-JP1: Default: JP1 shorting 1-2 => Panel supply = 3.3V Alternate: JP1 shorting 5-6 => Panel supply = 5.0V CN2-JP2: Default: JP2 shorting 3-4 => Backlight voltage = 12.0V Alternate: JP2 shorting 5-6 => Backlight voltage = 5.0V • Comment on alternate power switching: If leakage currents are not considered as an issue for the design, the load switch might be replaced by a P-Channel FET and N-Channel FET for the Gate control. • Comment on different power rails for both LVDS channels: It might be considered to implement different voltage rails for both channels, which is not covered with this design example. • Comment on ESD-Devices: Place the ESD device close to the LVDS connector and close to the backlight pin header.

In a LVDS implementation with two single LVDS channels, the panel EDID EEPROMs would be in conflict and measures need to be taken to avoid this. One possible solution is that the second LVDS EDID EEPROM could be read over the I2C_GP pin pair rather than the I2C_LCD pin pair.

SMARC Design Guide 2.0 Page 35 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 13 LVDS Dual Channel

DDC_CK I2C_LCD_DAT MOD +V1P8 +VDD_PANEL +VDD_PANEL +VDD_PANEL

5 6 +VDD_PANEL

5 R8 R9 Q5 S1 G1 D2 6 2.2K_+-1% 2.2K_+-1% BSS138DW-7-F_0.2A/50V TVS1 RCLAMP0504FA C17 1 L1 2 DDC_DAT 0.1uF_16V LVDS0_L_0- D1 G2 S2 LVDS0_0- MOD 90_100MHz_0.5A LVDS0_L_0+ DDC_CK

2 LVDS0_0+ 1 MOD 4 3

1 L2 2 DDC_DAT +V1P8 DDC_CK LVDS0_L_1- DDC_DAT LVDS0_1- MOD I2C_LCD_CK MOD 90_100MHz_0.5A LVDS0_L_1+ LVDS0_1+ MOD 4 3 ESD1 LVDS0_L_0+ 1 1 L3 2 LVDS0_L_0- 5 LVDS0_L_2- +VDD_PANEL +VDD_PANEL 2 LVDS0_2- MOD 90_100MHz_0.5A LVDS0_L_2+ LVDS0_L_1+ 4 LVDS0_2+ MOD 4 3 LVDS0_L_1- 3 C8 0.1uF_16V 1 L4 2 C9 0.1uF_16V RClamp7534P.TNT LVDS0_L_3- TVS2 1 2 +VDD_PANEL LVDS0_3- MOD 90_100MHz_0.5A LVDS0_L_3+ TVS3 2 1 ESD2 LVDS0_3+ MOD 4 3 0603-240E2R5PP LVDS0_L_2+ 1 0603-240E2R5PP CN3 R15 LVDS0_L_2- 5 1 L5 2 1 2 100K_+-1% 2 DDC_DAT DDC_CK LVDS0_L_CK- 3 4 4 LVDS0_CK- MOD 90_100MHz_0.5A LVDS0_L_CK+ 5 6 LVDS0_L_0- D1 3 LVDS0_CK+ MOD 4 3 LVDS0_L_0+ 7 8 LVDS_VDDEN A K PG_VPANEL LVDS0_L_1- 9 10 LVDS0_L_1+ USCD022H RClamp7534P.TNT 11 12 LVDS0_L_2+ BKLT0_VDD_EN LVDS0_L_2- 13 14 ESD3 LVDS0_L_CK- 15 16 LVDS0_L_CK+ LVDS0_L_CK+ 1 1 L6 2 C10 0.1uF_16V 17 18 LVDS0_L_3+ LVDS0_L_CK- 5 LVDS1_L_0- LVDS0_L_3- 19 20 2 LVDS1_0- MOD 90_100MHz_0.5A LVDS1_L_0+ LVDS1_L_0- 21 22 LVDS1_L_0+ LVDS0_L_3+ 4 LVDS1_0+ MOD 4 3 23 24 LVDS1_L_1- LVDS0_L_3- 3 LVDS1_L_1+ 25 26 1 L7 2 LVDS1_L_2- 27 28 LVDS1_L_2+ RClamp7534P.TNT LVDS1_L_1- 29 30 LVDS1_L_CK+ LVDS1_1- MOD 90_100MHz_0.5A LVDS1_L_1+ LVDS1_L_CK- 31 32 LVDS1_1+ MOD 4 3 LVDS1_L_3+ 33 34 LVDS1_L_3- ESD4 LVDS1_L_0+ 1 1 L8 2 BH_34_S2.0mm LVDS1_L_0- 5 LVDS1_L_2- 2 LVDS1_2- MOD 90_100MHz_0.5A LVDS1_L_2+ LVDS1_L_1+ 4 LVDS1_2+ MOD 4 3 LVDS1_L_1- 3 +VDD_PANEL +VCC_BKLT 1 L9 2 +VDD_PANEL RClamp7534P.TNT LVDS1_L_3- CN4 LVDS1_3- MOD 90_100MHz_0.5A LVDS1_L_3+ 1 2 BKLT0_EN ESD5 LVDS1_3+ MOD 4 3 3 4 BKLT0_CTRL LVDS1_L_2+ 1 LCD_BKLT0_CTRL 5 6 +VDD_PANEL LVDS1_L_2- 5 LCD_BKLT0_EN 1 L10 2 7 8 2

5 LVDS1_L_CK- 6 4 LVDS1_CK- MOD 90_100MHz_0.5A LVDS1_L_CK+ BH_8_S2.54mm TVS7 C16 3 LVDS1_CK+ MOD 4 3 RCLAMP0504FA 0.1uF_16V

% % RClamp7534P.TNT

0 -

1 -

C R ESD6

0 0 LVDS1_L_CK+ 1

2 1 LVDS1_L_CK- 5 2 LVDS1_L_3+ 4 CN5 LVDS1_L_3- 3 1 2 3 4 +VDD_PANEL RClamp7534P.TNT LCD_BKLT1_CTRL 5 6 +VDD_PANEL LCD_BKLT1_EN 7 8

BH_8_S2.54mm P TVS6 C15

5 RCLAMP0504FA 0.1uF_16V

3 -

4 -

C14 0 C13

0.1uF_16V 2 0.1uF_16V

1 6 BKLT1_CTRL

3 BKLT1_EN

Figure 14 LVDS Dual Channel Power Supply

+V12P0_IN +VLCD_12P0

+V5P0_IN +VLCD_5P0 B1 120_100MHz_5A +V3P3_IN +VLCD_3P3 +VLCD_3P3 B2 120_100MHz_5A

B3 120_100MHz_5A +VLCD_12P0 +VLCD_5P0

- +VLCD_5P0

2 JP1 1

+VLCD_3P3 _

F +VLCD_12P0_F JP2 C1 MINI-JUMP_2_S2.0mm

1 3 5 1 3 5

0.1uF_10V m

1 2 +VLCD_5P0 +VDD_PANEL m

N N

C C U1 PH_6_S2.0mm 2

LCD_PANEL1_VDD_EN S

3 6 _ A C U2 6 MINI-JUMP_2_S2.0mm

2 4 6 2 4 6

2 5 9 H +VCC_BKLT GND VCC Vin2 P +VDD_PANEL_I1N 7 Vin1 Vout LCD_PANEL0_VDD_EN 1 4 EN_PANELPOWER 2 6 R1 +VLCD_5P0 U3 B Y EN PG 3 5 10K_+-1% +VCC_BKL_IN 9 Vcc BLEED Vin2 SN74AUP1T97DCKR 4 1 7 GND Vin1 Vout C2 PG_VPANEL 2 6 EN PG 0.1uF_10V NCP45520IMNTWG-H_ON 3 5 Vcc BLEED LCD_PANEL0_VDD_EN R2 TC1 4 TC2 22uF_25V C3 GND 22uF_25V 100K_+-1% 0.1uF_10V NCP45520IMNTWG-H_ON

LCD_PANEL1_VDD_EN R3 PG_VPANEL 100K_+-1%

+VDD_PANEL +VDD_PANEL +V1P8S +V1P8S C4 C5 C6 C7 0.1uF_10V 0.1uF_10V 0.1uF_10V 0.1uF_10V

1 1

U4 1 1 1 1 U5

A B A B

12 C C 12 C C OE C C 10 OE C C 10 2 V V 2 V V LCD0_BKLT_EN MOD A1 B1 LCD_BKLT0_EN LCD1_BKLT_EN MOD A1 B1 LCD_BKLT1_EN 3 9 3 9 LCD0_BKLT_PWM MOD A2 B2 LCD_BKLT0_CTRL LCD1_BKLT_PWM MOD A2 B2 LCD_BKLT1_CTRL 4 8 4 8 LCD0_VDD_EN MOD A3 B3 LCD1_VDD_EN MOD A3 B3 5 7 LCD_PANEL0_VDD_EN 5 7 LCD_PANEL1_VDD_EN A4 B4 A4 B4 6 6 GND GND TXB0104_QFN12 TXB0104_QFN12

SMARC Design Guide 2.0 Page 36 of 119 Mar 23, 2017 ©SGeT e.V.

3.1.3 Display Parameters and EDID

Flat panel display parameters (horizontal resolution, vertical resolution, pixel clock rate, blanking periods, etc.) may be hard-coded into a boot-loader or they may be read by boot-loader code from an industry standard data structure known as EDID (Extended Display Identification Data). EDID data is stored in an EEPROM accessed via I2C. The EDID EEPROM may reside on the display assembly or elsewhere in the path between the SOC and the display – on the Carrier or on a display adapter assembly.

If the EDID EEPROM resides on the display, then the cabled interface to the display must include the SMARC Module I2C_LCD interface. The interface should be level translated and possibly buffered. The I2C voltage levels on the display are most likely to be at 3.3V levels. A set of back-to-back FETs may be used for I2C level translation, as shown in the figure immediately below. Alternatively, a device such as the Fairchild FXMA2102 I2C buffer / level translator may be used. There is a circuit example using the FXMA2102 later in this document.

In the display interface example above, with the 30 pin Hirose DF19 series connector, pins 9 and 10 could be used for the buffered I2C_LCD clock and data, respectively.

The figure below shows an EDID EEPROM implementation that may be used on a Carrier. It might be advantageous to use a socket for the EEPROM to allow display parameters to be swapped out. Alternatively, system software could update the EEPROM if the EEPROM WP (Write Protect) pin is set to enable writes. Or, the system designer could implement an EEPROM programming header for update purposes.

Caution: if there is an EDID EEPROM on the Carrier and on the display, there will be an I2C address conflict unless one of the two is disabled or set to an alternate address. VESA EDID EEPROMs are expected at 7 bit I2C address 0x50.

There are many EDID editors available, some for free. It can be very useful to have access to one if you are trying to adapt a new panel, and if your SMARC Module software knows what to do with EDID data. Alternatively, your SMARC Module and / or Carrier board vendor may well be able to help with display adaptations.

Figure 15 Carrier EDID EEPROM

V_3V3

V_1V8

2 2

1 2

2 2

4 4

0 0

2 2

4 4

0 0

R R

5 2

Q3 Q3 1

1 1

I2C_LCD_CK 3 6 MOD 4 1

V_1V8 DiodesInc BSS138DW-7-F

Q4 2 Q4 5

I2C_LCD_DAT 6 3 MOD 1 4 V_3V3 V_3V3 V_3V3 DiodesInc BSS138DW-7-F U13

Atmel AT24HC02 2

I2C_EDID_CK 6 8 2

2 SCL VCC

2 2

0 I2C_LCD_DAT 5 0

m m

2 SDA

h h

I I

5 0

2 2

4 3

0 0

4 N N

O O

4 4

0 D 4 4

2 K 2

D D

R 0 0

0 0

R R

1 1

1 7 1 1 I2C_WP WP I2C_ADDR_A0 1 A0 I2C_ADDR_A1 2 A1 1 3 4 C118 I2C_ADDR_A2 2 A2 GND 100nF

25V h

2 2

2 2 2

R 0 m m SOIC8

h h

0 9

2 2

O O

K 1

6 5

0 0

K K

2 2

4 4

R 0

9 9

R 0 R 0

. I2C Addr :0x50

4 4

. .

2 2

1 1 1 (7 bit Address)

SMARC Design Guide 2.0 Page 37 of 119 Mar 23, 2017 ©SGeT e.V.

3.2 HDMI

Note: a license may be needed to market HDMI capable products. Check with the HDMI organization (www.hdmi.org) and with your SMARC Module vendor.

The SMARC HDMI data pairs may be routed directly from the SMARC Module pins to a suitable Carrier HDMI connector. Since HDMI is a hot-plug capable interface, it is important for the Carrier to implement ESD protection on all of the HDMI lines. The ESD protection on the data lines must be low capacitance so as not to degrade high speed signaling. The data lines must route through the ESD protection device pins in a no-stub fashion. The ESD protection should be located close to the HDMI connector.

The SMARC pins HDMI_CTRL_CK and HDMI_CTRL_DAT require level translation from V_1V8 to the 5V levels that HDMI uses on those pins. These lines also require pull-up resistors to V_1V8 (the pull-ups are not included on the SMARC Module, because integrated HDMI protection devices such as the Texas Instruments TPD12S016 include the pull-ups in their parts). And, finally, 5V power switching / current limiting to the HDMI connector is required on the Carrier.

The ESD protection, level translation and power switching / limiting are all dealt with in integrated devices such as the TI TPD12S016. A circuit diagram is shown in the following figure. The TPD12S016 must be placed close to the HDMI connector, and the HDMI data traces routed in daisy chain fashion (and as differential pairs) from the SMARC Module pins, to and through the TPD12S016 pins, and on to the HDMI connector pins. The TPD12S016 pin-out is specifically designed to facilitate this.

Figure 16 HDMI Implementation

HDMI_D2_P MOD HDMI_D2_N MOD

HDMI_D1_P MOD HDMI_D1_N MOD

HDMI_D0_P MOD HDMI_D0_N MOD

HDMI_CK_P MOD HDMI_CK_N MOD

Layout Note : The HDMI trace pairs are to be routed

V_5V0 V_1V8 from the SMARC connector, through the TPD12S016 pads and to the HDMI connector,

2 2 1 without any stubs R3 C31 2 R4 2 4.7KOhm 0 0 100nF 4 4.7KOhm 4

DNI 0 0 25V U22 1 1 2 TI TPD12S016 24 VCCA 11 VCC5V 1 C155 CT_HPD 12 1uF CT_HPD 16V LS_OE 5 2 LS_OE J25 R96 2 1 4 10 HDMI_HPD_CONN 0402 HPD_A- HPD_B- FCI 10029449-001TLF 0Ohm HDMI_HPD 23 HDMI_D2_P 1 MOD D2+ TMDS_DATA2_P 22 HDMI_D2_N 2 D2- TMDS_DATA2_SHLD 3 TMDS_DATA2_M 21 HDMI_D1_P 4 D1+ TMDS_DATA1_P 20 HDMI_D1_N 5 D1- TMDS_DATA1_SHLD 6 TMDS_DATA1_M 18 HDMI_D0_P 7 D0+ TMDS_DATA0_P 17 HDMI_D0_N 8 D0- TMDS_DATA0_SHLD 9 TMDS_DATA0_M 16 HDMI_CK_P 10 CLK+ TMDS_CLK_P 15 HDMI_CK_N 11 CLK- TMDS_CLK_SHLD 12 TMDS_CLK_M 1 7 13 CEC_A CEC_B CEC 14 RSVD HDMI_CTRL_CK 2 8 HDMI_DDC_SCL_5V0 15 MOD SCL_A SCL_B SCL 16 SDA HDMI_CTRL_DAT 3 9 HDMI_DDC_SDA_5V0 17 MOD SDA_A SDA_B DDC/CEC_GND 18 5V 6 19 GND_6 HPD 4 3 2 1 14 H H H H GND_14 M M M M 19 13 V_5V0_HDMI GND_19 5V_OUT

SMT 3 2 1 0 1 1 2 2 2 2 C216 C32 19/1/0.5 TSSOP24 10uF 100nF 16V 2 25V 2 HDMI, R/A, SMT

SMARC Design Guide 2.0 Page 38 of 119 Mar 23, 2017 ©SGeT e.V.

3.3 DisplayPort (DP++)

DisplayPort is directly supported by a dual-source DDI. ESD protection, DC blocking capacitors and hot plug detect are the only components required.

The DisplayPort differential data pairs (Lane [0..3]) are AC coupled off Module with capacitors C19-C26. Place the AC blocking capacitors close to the DisplayPort connector. The Aux differential pair is AC coupled on the Module. ESD clamping diodes D1, D2 and D3 protect the Module from external ESD events and should be placed near the DisplayPort connector. The pin-out of the ESD clamp diodes allows for a trace to run under the chip connector to two pins. The Carrier provides up to 500 mA of 3.3V power to the DisplayPort connector. Diode D71 prevents back feeding of power in the event that the monitor is powered up when the Carrier is powered down. Config lines 1 and 2 are pulled to ground per the VESA specification. The DisplayPort Hot Plug Detect signal is buffered by U50 which prevents back feeding of power from the display to the Module as well as level translation to 3.3V levels. R14 connect logic and chassis ground together. Other techniques may be used depending on the overall grounding strategy.

Note: The reference schematics assume that the Module’s DisplayPort is dual-source capable – dual source indicates that the Module can output DisplayPort or HDMI/DVI based on the DDC_AUX_SEL signal. Figure 17 DisplayPort ++

D1 Rclamp 0524P

100n J3 DP0_LANE1_C- 1 10%50V Molex 47272-0001 10 C19 DP0_LANE0_C+ 1 DP0_LANE1_C+ 2 DP0_LANE0+ MOD ML_Lane0+ 9 2 C20 DP0_LANE0_C- 3 GND DP0_LANE0_C- 4 DP0_LANE0- MOD C21 DP0_LANE1_C+ 4 ML_Lane0- 7 DP0_LANE1+ MOD ML_Lane1+ DP0_LANE0_C+ 5 5 C22 DP0_LANE1_C- 6 GND 6 DP0_LANE1- MOD C23 DP0_LANE2_C+ 7 ML_Lane1- D2 DP0_LANE2+ MOD ML_Lane2+ Rclamp 0524P 8 C24 DP0_LANE2_C- 9 GND DP0_LANE2- MOD ML_Lane2- C25 DP0_LANE3_C+ 10

3 DP0_LANE3+ MOD 11 ML_Lane3+ C26 DP0_LANE3_C- 12 GND DP0_LANE3_C- 1 DP0_LANE3- MOD 13 ML_Lane3- 10 DP0_AUX_SEL MOD DP0_Config2 14 Config1 DP0_LANE3_C+ 2 15 Config2 9 DP0_AUX+ MOD AUX CH+ DP0_LANE2_C- 4 16 17 GND 7 DP0_AUX- MOD DP0_HPD_C 18 AUX CH- DP0_LANE2_C+ 5 V_3V3 Hot Plug 6 19 0.5A V3.3_S0_DP_3 20 Return DP_PWR FB4 D71 C6

S1 S1 S2 S2 S3 S3 S4 60R@100MHz MBR130LSFT1 R16 R15 S4 100n 3 i max. 500 mA 1M 5M1 1%

D3 Rclamp 0524P V_1V8

V3.3_S0_DP_3 1 C305 10 10n DP0_HPD_C 2 5 9 DP0_CTRLDATA_AUX- 4 4 2 DP0_HPD_B R32 DP0_HPD_C DP0_HPD MOD 7 0R DP0_CTRLCLK_AUX+ 5 U50 6 NC7SZ125 1 R46 5% 100k 3 R14 1% 0R

3 5%

3.3.1 HDMI over DP++

A Dual-mode source Module requires level shifters on the Carrier to convert the low-swing AC coupled differential pairs from the video source to HDMI compliant current mode differential outputs. The example schematics use a Chrontel CH7318C translator which supports data rates up to 1.65GB/s per lane. FET based passive level translators can be used for lower data rates. The DisplayPort AUX channel is configured as a DDC interface for HDMI. Further information on pre- emphasis as well as output current trim capabilities of the CH7318C can be found in the Chrontel datasheet.

SMARC Design Guide 2.0 Page 39 of 119 Mar 23, 2017 ©SGeT e.V.

ESD clamping diodes D159, D160 and D161 protect the Module from external ESD events and should be placed near the HDMI connector. The pin-out of the ESD clamp diodes allows for a trace to run under the chip connector to two pins. HDMI uses I2C signaling for the DDC. Resistors R1319 and R1322 provide the necessary pull-up. The FET U35 provides the Hot Plug Detect signal The Carrier provides 5V power to the HDMI connector. A series diode (D72) should be used to prevent back feeding of power in the event that the monitor is powered up when the Carrier is powered down. The HDMI Hot Plug Detect signal is buffered by two FETs U32 and U33 which prevent back feeding of power from the display to the Module as well as level translation to 3.3V levels.

Note: The reference schematics assumes that the Module’s DDI ports are dual-source capable – dual source indicates that the Module can output DisplayPort or HDMI/DVI based on the DDC_AUX_SEL signal. Figure 18 HDMI over DP++

U364 V_5V0

DP0_LANE0+ C1081 DP0_LANE0_C_+ 39 22 DP0_LANE2_EXT_+ DP0_CTRLCLK_EXT R1322 MOD IN_D1+ OUT_D1+ R1%2K21S02 DP0_LANE0- C100N02V16 C1078 DP0_LANE0_C_- 38 23 DP0_LANE2_EXT_- MOD IN_D1- OUT_D1- C100N02V16 DP0_CTRLDAT_EXT R1319 R1%2K21S02 DP0_LANE1+ C1077 DP0_LANE1_C_+ 42 19 DP0_LANE1_EXT_+ MOD IN_D2+ OUT_D2+ DP0_LANE1- C100N02V16 DP0_LANE1_C_- 41 20 DP0_LANE1_EXT_- C1076 IN_D2- OUT_D2- MOD C100N02V16 DP0_LANE2+ C1074 DP0_LANE2_C_+ 45 16 DP0_LANE0_EXT_+ MOD IN_D3+ OUT_D3+ J118 DP0_LANE2- C100N02V16 DP0_LANE2_C_- 44 17 DP0_LANE0_EXT_- C1073 IN_D3- OUT_D3- DP0_LANE2_EXT_+ 1 MOD C100N02V16 TMDS_DAT2+ 2 SHLD_D2 DP0_LANE3+ C1072 DP0_LANE3_C_+ 48 13 DP0_LANE3_EXT_+ DP0_LANE2_EXT_- 3 MOD IN_D4+ OUT_D4+ TMDS_DAT2- DP0_LANE3- C100N02V16 C1071 DP0_LANE3_C_- 47 14 DP0_LANE3_EXT_- MOD IN_D4- OUT_D4- DP0_LANE1_EXT_+ 4 C100N02V16 TMDS_DAT1+ 5 SHLD_D1 DP0_AUX+ 9 28 DP0_CTRLCLK_EXT DP0_LANE1_EXT_- 6 MOD SCL SCL_SINK TMDS_DAT1- DP0_AUX- 8 29 DP0_CTRLDAT_EXT DP0_LANE0_EXT_+ 7 MOD SDA SDA_SINK TMDS_DAT0+ 8 V_5V0 SHLD_D0 DP0_HPD3_3 DP0_HPD_LS 7 30 DP0_HPD_EXT R1331 HPD HPD_SINK DP0_LANE0_EXT_- 9 R1%0R0S02 TMDS_DAT0- DP0_LANE3_EXT_+ 10 TMDS_CLK+ 2 VCC1 11 V_3V3 SHLD_CLK V_3V3 11 DP0_LANE3_EXT_- 12 VCC2 TMDS_CLK- 15 13 VCC3 CEC

F15 DP0_HDMI_LS_OE# 25 21 V_3V3_S0_HDMI PFUSE0_4A R1316 OE# VCC4 FB179 14 LCB140R03 Reserved R1%4K7S02 26 DP0_CTRLCLK_EXT DP0_CTRLCLK_C 15 20 VCC5 FB177 SCL MH1 DNI DP0_HDMI_LS_I2C_EN 32 33 LCB140R03 DDC_EN VCC6 DP0_CTRLDAT_C 16 21 DP0_CTRLDAT_EXT FB178 SDA MH2 40 17 22 VCC7 LCB140R03 GND_DDC MH3 10 46 NC VCC8 V_5V0_S0_HDMICON 18 23

C1075 C100N02V16

C1080 C100N02V16

C1079 C100N02V16

C1070 C100N02V16 VCC5 MH4

R1318 R1%0R0S02 DP0_HPD_EXT 19 24 HPD BO1 DP0_HDMI_LS_PC0 3 1 TRIM GND1

C1082 C47PS02

C1083 DP0_HDMI_LS_PC1 4 5 C47PS02 HPDEN GND2 J_TH_HDMI 12 V_5V0_S0_HDMICON_F GND3 GND_HDMI DP0_HDMI_LS_REXT 6 18 SHIELD_GND REXT GND4 24

R1333 GND5 R1%20K0S02 31 GND6

FB176 36 LCB140R03 GND7 DP0_HDMI_LS_TEST1 34 37 CCT1 GND8 DP0_HDMI_LS_TEST0 35 43 CCT2 GND9

R1332 R1%1K21S02 49 GND10 STP10 V_5V0_S0_HDMICON 27 GND11 CH7318C D72 MBR130LSFT1 GND_HDMI

C1069

C1068 C10US05V6

C100N02V16

V_1V8

V_3V3 DP0_AUX_SEL R1321 MOD R1%100KS02

D160 D159 FOR TEST PURPOSE ONLY D161

R1330 R1%1K50S02

R1328 R1%1K50S02

R1327 R1%1K50S02

R1326 R1%1K50S02

R1325 R1%1K50S02 V_1V8 DP0_LANE2_EXT_- 1 DP0_CTRLCLK_C 1 DP0_LANE3_EXT_+ 1 10 10 10 DP0_LANE2_EXT_+ 2 DP0_CTRLDAT_C 2 5

DNI

DNI DNI DP0_LANE3_EXT_- 2 2 9 9 9 DP0_LANE1_EXT_- 4 DP0_HPD_EXT 4 DP0_HDMI_LS_I2C_EN DP0_LANE0_EXT_+ 4 DP0_HPD 3 4 1 6 DP0_HPD3_3 7 7 MOD DP0_HDMI_LS_PC0 7 U35 DP0_LANE1_EXT_+ 5 V_5V0_S0_HDMICON 5 DP0_HDMI_LS_PC1 DP0_LANE0_EXT_- 5 BSS138DW-7F 6 6 DP0_HDMI_LS_TEST0 6 DP0_HDMI_LS_TEST1

3 8

3 8 TVS_RCLAMP0524P TVS_RCLAMP0524P TVS_RCLAMP0524P NOTE44

R1324 R1%1K50S02

R1323 R1%1K50S02

R1365 R1%1K50S02

R1366 R1%1K50S02

Place ESD-protection diodes close to connector use wide traces with minimum 2 VIAs to GND-plane

DNI DNI

3.4 Embedded DisplayPort (eDP)

The reference schematic provides a generic eDP interface. The eDP connector used in the design is an example only. Other connectors can be used based on the design requirements. JP83 selects 3.3 or 5V for the panel power. R1125 ensures that panel power is disabled when the Module is powering up and before the signal is actively driven. The panel control signals eDP_BKLT_EN, eDP_BKLT_CTRL as well as eDP_HPD are 3.3V level signals, check your panel specifications for correct voltage levels and provide translation if necessary. The reference design supports individual backlight control signals. It should be noted that some panels handle these functions over the AUX channel.

The traces from JP83 and associated FETs to the eDP connector carry power to the panel. The traces should be routed with appropriate thickness to handle the current expected. eDP_TX and eDP_AUX differential pairs should be routed as high speed differential pairs. The panel control signals are low speed and do not require any additional care.

SMARC Design Guide 2.0 Page 40 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 19 Embedded DisplayPort (eDP)

V5/V3.3_S0_eDP_PWR C419 C100N03X7R C421 C100N03X7R C423 C100N03X7R J212 eDP C422 C10US06V25 40 RSVD_1 39 C100N03X7R H_GND_2 C892 eDP_TX3-_C 38 eDP_TX3- MOD Lane3_N C890 eDP_TX3+_C 37 eDP_TX3+ MOD V12_S0_eDP_PWR 36 Lane3_P C100N03X7R C418 C100N03X7R C891 eDP_TX2-_C 35 H_GND_5 eDP_TX2- MOD C630 C100N03X7R C888 eDP_TX2+_C 34 Lane2_N eDP_TX2+ MOD C639 C100N03X7R 33 Lane2_P C100N03X7R C637 C100N03X7R C889 eDP_TX1-_C 32 H_GND_8 eDP_TX1- MOD C886 eDP_TX1+_C 31 Lane1_N C420 C10US05V16 eDP_TX1+ MOD Lane1_P 30 C100N03X7R H_GND_11 C887 eDP_TX0-_C 29 eDP_TX0- MOD C885 eDP_TX0+_C 28 Lane0_N eDP_TX0+ MOD 27 Lane0_P C100N03X7R C883 eDP_AUX+_C 26 H_GND_14 eDP_AUX+ MOD C882 eDP_AUX-_C 25 AUX_CH_P MOD eDP_AUX- 24 AUX_CH_N C100N03X7R H_GND_17 23 VCC_3V3 22 LCD_VCC_18 Q68A 7 21 LCD_VCC_19 JP83 1 8 V5/V3.3_S0_eDP_PWR 20 LCD_VCC_20 JMPRM254RED_LF 19 LCD_VCC_21 J104 18 LCD_Self_Test(NC) XST1X3S LCD_GND_23 QIRF7329 17 LCD_GND_24 VCC_5V0 16 2 LCD_GND_25 15 LCD_GND_26 eDP_HPD 14 eDP_HPD MOD Q68B 13 HPD 6 12 BL_GND_28 3 5 11 BL_GND_29 C898 10 BL_GND_30 R1123 eDP_BKLT_EN 9 BL_GND_31 R1%200K03 C1US03V6 LCD0_BKLT_EN MOD QIRF7329 eDP_BL_PWM 8 BL_ENABLE(NC) LCD0_BKLT_PWM MOD BL_PWM_DIM(NC) 4 7 R1124 6 RSVD_34 5 RSVD_35 43 R1%10K03 BL_PWR_36 M3 VCC_12V 4 44 3 BL_PWR_37 M4 Q69 BL_PWR_38 V12_S0_eDP_PWR 2 42 BS138 BL_PWR_39 M2 LCD0_VDD_EN MOD 1 41 RSVD_40 M1 JEDP_40 R1125 R1%10K03 SHLDGND

3.5 MIPI DSI

The LVDS signal lines may alternatively be used to support up to two MIPI DSI (Display Serial Interface) displays. DSI is a high-speed differential bus and includes one clock lane and up to four data lanes. There is no AC coupling required. VDD and Backlight signals are the same is in LVDS mode. It is recommended to check with your SMARC Module vendor if MIPI DSI is supported by the used SMARC Module.

Figure 20 MIPI DSI

DSI_D0+ DSI_D0+ DSI_D0- DSI_D0-

DSI_D1+ DSI_D1+ y E DSI_D1-

DSI_D1- a

p s

D DSI_D2+ DSI_D2+

i O

DSI_D2- DSI_D2- D

S C

DSI_D3+ DSI_D3+ D

R I

DSI_D3- DSI_D3-

M M

S DSI_CLK+ DSI_CLK+ DSI_CLK- DSI_CLK-

DSI_TE DSI_TE

SMARC Design Guide 2.0 Page 41 of 119 Mar 23, 2017 ©SGeT e.V.

4 LOW / MEDIUM SPEED SERIAL I/O INTERFACES

4.1 Asynchronous Serial Ports

4.1.1 RS232 Ports

The SMARC Module asynchronous serial ports run at 1.8V logic levels. The transmit and receive data lines from and to the Module are active high, and the handshake lines are active low, per industry convention.

If the asynchronous ports are to interface with RS232 level devices, then a Carrier RS-232 transceiver is required. The logic side of the transceiver must be able to run at 1.8V levels. The selection of 1.8V compatible transceivers is a bit limited, although more are appearing with time. Two such devices are the Texas Instruments TRS3253E, and the Maxim MAX13235E, illustrated in the figures below. The TI part is more cost effective, but has a top speed of 1 Mbps. The MAX 13235E can operate at maximum speeds over 3 Mbps (but your SMARC Module may or may not - check with your Module vendor). The transceivers invert the polarity of the incoming and outgoing data and handshake lines.

Figure 21 Asynchronous Serial Port Transceiver – RS232 – TRS3253E

V_5V0 V_1V8

1 1 C93 C92 100nF 100nF J40 U35 2 25V 2 25V TI TRS3253EIRSM JST SM05B-SRSS-TB C259 TRS3253E_C1+_1 29 27 SER0_RXD_RS232 1 1 2 C1+ VCC 1 SER0_TXD_RS232 2 47nF 2 16V TRS3253E_C1-_1 31 15 SER0_RTS_RS232# 3 C1- VL 3 SER0_CTS_RS232# 4 TRS3253E_C2+_1 4 1 30 TRS3253E_V+_1 330nF C252 5 1 C2+ V+ 5

1 2 C253 2 1

330nF M M 2 3 TRS3253E_V-_1 330nF C254 2 C2- V-

TRS3253E_C2-_1 1 2 5/1/1x5/1.0

7 6 SMT SER0_TX 4 25 MOD DIN1 DOUT1 SER0_RTS# 5 23 MOD DIN2 DOUT2 5 Pin, 1mm Pitch, R/A, SMT SER1_TX 7 22 MOD DIN3 DOUT3 V_1V8 V_1V8 SER0_RX 14 21 J39 MOD ROUT1 RIN1 JST SM05B-SRSS-TB SER0_CTS# 13 20 MOD ROUT2 RIN2

2 2 SER1_RX 12 19 SER1_RXD_RS232 1 MOD ROUT3 RIN3 1 11 18 2 R12 2 R10 SER1_TXD_RS232 2

0 0 ROUT4 RIN4 2 4 4.7KOhm 4 4.7KOhm 10 17 3 0 0 DNI ROUT5 RIN5 3 4 1 1 R167 4 FORCEON_1 9 6 SER0_1_INVALID#1 2 GPIO10 5 FORCEON INVALID# 0402 MOD 5 28

SER0_SER1_XCVR_OFF# 2 1 FORCEOFF# 0Ohm DNI M M

2 16 5/1/1x5/1.0 NC_16 7 6 2 R48 SMT 0 24

4 1KOhm NC_24 0 32 26 NC_32 GND

1 8 33 5 Pin, 1mm Pitch, R/A, SMT NC_8 TPAD

QFN32

Pin 6 of U35 (INVALID#) may be connected to a GPIO of the SMARC Module (GPIO10 in this example) but it has to be checked if this GPIO is not needed for another function.

SMARC Design Guide 2.0 Page 42 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 22 Asynchronous Serial Port Transceiver – RS232 – MAX13235E

V_5V0 V_1V8

U70 1 C462 1 C463 MAX13235E 47nF 1uF 16V 2 16V 2 2 19 1 C460 C1+ VCC 47nF 4 11 2 16V C1- VL

5 3 1 C461 C2+ V+ 330nF J60 16V 6 7 2 0603 C2- V- SM05B-SRSS-TB 1 C464 1 C465 330nF 330nF V_1V8 SER2_TX 13 17 SER2_TX_RS232 SER2_RX_RS232 1 MOD T1IN T1OUT 16V 16V 1 SER2_RTS 12 8 SER2_RTS_RS232 2 0603 2 0603 SER2_TX_RS232 2 MOD T2IN T2OUT 2 SER2_RTS_RS232 3 3 2 SER2_RX 15 16 SER2_RX_RS232 SER2_CTS_RS232 4 MOD R1OUT R1IN 4 2 R460 SER2_CTS 10 9 SER2_CTS_RS232 5 0 MOD R2OUT R2IN 5 4 4.7KOhm

1 0 DNI

M M 1 TP5

1 READY_SER2 READY

7 FORCEON_SER2 14 6 FORCEON SER2_FORCEOFF 20 18 FORCEOFF GND

2 R461

4 1KOhm TSSOP20

4.1.2 RS485 Half-Duplex

A half-duplex RS485 asynchronous serial port implementation is shown below. This hardware implementation is suitable for multi-drop RS485 networks. The Maxim MAX13451E transceiver accepts 1.8V logic I/O and has other, flexible features of interest such as internal termination options.

Multi-drop RS485 nodes should be strung together in daisy chain fashion using shielded twisted pair cable with a defined differential impedance (usually 120 ohms; sometimes 100 ohm cables are used). The two end-points of the system should be resistively terminated across the pair. The termination value should equal the differential impedance of the twisted pair cable used. The Maxim transceiver allows the termination to be enabled or disabled on the TERM# pin, and can be selected to be 100 ohms or 120 ohms via the TERM100 pin state. These pins can be controlled by Carrier GPIOs if desired.

The RS485 driver is enabled when the SMARC SER2_RTS# signal is asserted low (if the resistor options in front of the XOR gate are loaded as shown, such that the XOR gate inverts the SER2_RTS2# signal for the RS485_DE2 function).

A suitable, likely application specific, software driver is required to make the multi-drop RS485 network work.

SMARC Design Guide 2.0 Page 43 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 23 Asynchronous Serial Port Transceiver - RS485 – Half Duplex

V_5V0 V_1V8

1 C466 1 C467 100nF 100nF 25V 25V 2 2 V_1V8 U71 Maxim MAX13451EAUD+

RS485_DE2 1 4 J61 DE VCC RS485_RE2 2 6 JST SM06B-SRSS-TB RE VL

2 2 2 2 1 SER2_TX 3 10 RS485_SER2_P 1

m m m m

2 4 5 MOD DI A

2 2 2 2 2

h h h h

6 6 6

6 0 0 0 0 2

O O O O

4 4 4

4 4 4 4

K K K K 3

R 0 0 R 0 R 0

R 0 0 0 0 SER2_RX 7 12 RS485_SER2_N 3 1 1 1 1 MOD RO B 4

1 1 1 1 I I 4

N N 5 7

D D 5 M1 6 8 9 FAULT_2 6 M2 FAULT TP6 SRL_2 14 SRL INV_2 8 1x6-1.0 INV RA TERM_2 5 11 TERM GND TERM100_2 13 15 TERM100 T_PAD

2 2

m m

h h

7 8

2 2 TSSOP14

6 6

O O

0 0

4 4

4 K 4 K

0 0 0 0

R R

1 1

V_1V8

1C468 100nF

2 25V RS485_DE2 2 2

2 2

h R472

0 0

O 4 4 10KOhm

0 0

R 0 J62 1 U72

1 5 Fairchild NC7SZ86P5X 3M 961204-6300 1 SER2_RTS 1 MOD 4 1 2 2 1 2

3 4 RS485_RE2 2 3 3 4 1015-2777 2

0 R471

SC70-5 2

4 0 4/2x2/2.54

0 R D 100Ohm

0 0 ST

Jumper Jumper 01-02 03-04 State Open Open RS485 receiver disabled Open Closed RS485 receiver always enabled Closed Open RS485 receiver enbled when transmitter disabled Closed Closed Invalid

SMARC Design Guide 2.0 Page 44 of 119 Mar 23, 2017 ©SGeT e.V.

4.2 I2C Interfaces

4.2.1 General

The I2C bus is a versatile low bandwidth multi-drop bus originally defined by Philips (now NXP). It is a two wire bus (clock and data) that relies on the use of open-drain drivers and passive pull-ups. The bus can be single master or multi-master. SMARC Modules are always I2C masters. Whether or not they allow other masters is Module implementation dependent. Most SMARC systems use the I2C bus as a way for the SMARC I2C Masters to interface to a variety of I2C Slave peripherals. The standard I2C interface operation speeds are 100 kHz and 400 kHz. Some implementations allow faster speeds.

4.2.2 I2C Level Translation, Isolation and Buffering

FETs may be used to perform I2C level translation, as shown in this figure. This arrangement provides no buffering. It can provide isolation to prevent one side of the bus dragging down the other if one of the rails is collapsed. The rail that is to collapse should be the rail driving the FET gates.

Figure 24 I2C Power Domain Isolation – using FETs

V_3V3

V_1V8

R Q31 Q31 R

3 I2C_GP_SCL 6 I2C_GP_SCL_3V3

4 MOD 1 DiodesInc BSS138DW-7-F V_1V8

5 Q32 2 Q32

3 I2C_GP_DAT 6 I2C_GP_DAT_3V3

4 MOD 1 DiodesInc BSS138DW-7-F

SMARC Design Guide 2.0 Page 45 of 119 Mar 23, 2017 ©SGeT e.V.

The circuit shown just below can provide power domain isolation, voltage level shifting and I2C bus buffering. The Fairchild FXMA2102 power rails VCCA and VCCB can be at the same voltage level or at different levels, over a range of 1.65V to 5.5V. Either rail can come up before the other.

If you have many I2C devices, it is a good idea to split them up into segments with up to about 6 devices on each segment, and isolate the segments with a bi-directional I2C buffer such as the FXMA2102. I2C bus performance degrades with too much capacitive loading.

Figure 25 I2C Power Domain Isolation and Buffer – Fairchild FXMA2102

V_1V8 V_3V3 MOD I 2C_GP_CK

I 2C_GP_DAT

MOD 1 1 2 2

m m

h h 7 6

2 2

8 8

0 0

I I

0 0

O O

1 1

4 4

8 9

4 4

N N

K K

0 0

8 8

0 K 0

R R

0 0

D D

1 1

1 1 U29 0

R R

1 V_3V3 V_1V8 2 2 Fairchild FXMA2102 1 1

1 8 VCCA VCCB

2 7 I2C_IO_3V3_CK A0 B0 1 3 6 I2C_IO_3V3_DAT 1 C68 A1 B1 C69 100nF 100nF 25V 25V 2 1 2 0Ohm 5 4 2 R122 0402 OE GND Level shifted I2C

MicroPak-8

SMARC Design Guide 2.0 Page 46 of 119 Mar 23, 2017 ©SGeT e.V.

4.2.3 I2C_PM Bus EEPROMs

The SMARC I2C_PM bus is special in that it is used on the Module for power management functions, and it always runs from a 1.8V rail on the Module. The 1.8V voltage rail requirement on the I2C_PM bus allows it to be powered from a simple, low quiescent current linear or buck switching regulator from V_MOD_IN.

On the Module, since it is used for power management, it is “on” even when the Carrier power may be off (i.e. the CARRIER_PW_ON signal may be low, and Carrier circuits that are not involved in power management are powered off).

If the I2C_PM bus is used on the Carrier for functions that are not power management functions, then it needs to be isolated from the Module by a set of back to back FETs, as shown in the following figure. The V_1V8 in the figure is a Carrier board power rail that may be collapsed; the Module side of the I2C_PM must not be dragged down.

Figure 26 I2C_PM EEPROM: Carrier Power Domain

V_1V8

2 2

7 6

2 2

1 1

0 0

3 3

4 4

0 0

R R

5 2

Q18 Q18 0

1 1

I2C_PM_CK 3 6 I2C_PM_CAR_SCL MOD 4 1

DiodesInc BSS138DW-7-F

V_1V8

Q17 5 Q17 2

I2C_PM_DAT 3 6 I2C_PM_CAR_SDA MOD 4 1

DiodesInc BSS138DW-7-F

V_1V8 I2C_PM EEPROM

V_1V8 U42 Atmel AT24C32D

2 2 2

m m m 6 8

2 3 9

2 2 2 h h h SCL VCC

1 1 0

0 0

O O O

3 3 3

4 4 4 5

K K K

R 0 R 0 R 0 SDA

0 0 0

1 1 1

7 WP_PWR WP PWR_BOARD_ID_A0 1 A0 PWR_BOARD_ID_A1 2 A1 3 4 PWR_BOARD_ID_A2 2 A2 GND 1 C267

100nF 0 R314 4 10KOhm TSSOP8 25V 2 0

2 2 2 I2C Address : 0x57

m m m

1 0 5

2 2 2

h h h

1 1 1

0 0 0

O O O

3 3 3

4 4 4

K K K (7-bit format)

0 0 0

R R R

0 0 0

1 1 1

I I

N N

D D

SMARC Design Guide 2.0 Page 47 of 119 Mar 23, 2017 ©SGeT e.V.

The SMARC I2C_PM bus may be used on the Carrier for power management functions, such as interfacing to a battery charger or battery fuel gauge. In this case, the power circuits and the I2C_PM interface to the SMARC Module need to be powered whenever power is on. A local low quiescent current low drop out linear regulator is needed to provide 1.8V for the Carrier board “Module domain” devices.

Figure 27 I2C_PM EEPROM: Module Power Domain

U39 V_MOD_IN Maxim MAX1818

V_1V8_LDO

1 IN OUT 6 2 1 R295 1 4 R318 C272 1uF 3 2 1 2 SHDN# POK 2 R319 27 0402 25V 2 1 0402 4.7uF C 22.6KOhm 2 0Ohm 100KOhm 2 10V 040 4 5 GND SET 1 1V8_LDO_SET

SOT23 2

2 R320

51.1KOhm

040 1 I2C_PM EEPROM

U41

Atmel AT24C32D

m m

m I2C_PM_CK 6 8

h h

h MOD SCL VCC

30 30

30 I2C_PM_DAT 5

040

R R

R MOD SDA

10K

1 1

7 WP_PWR WP PWR_BOARD_ID_A0 1 A0 PWR_BOARD_ID_A1 2 A1

PWR_BOARD_ID_A2 3 4 2 A2 GND 1 C266 2 R303 100nF

040 10KOhm

TSSOP8 25V 2

2 2

2 I2C Address : 0x57

30 30

30 (7-bit format)

040

10K

DN DN

The SMARC Module specification recommends - but does not require - that Carriers have a parameter EEPROM on the I2C_PM bus, preferably configured as shown here, in the “Module Power Domain”. This, in principle, allows the Module to query the Carrier I2C_PM EEPROM before asserting the CARRIER_PWR_ON signal that enables the main Carrier board power feed.

SMARC Design Guide 2.0 Page 48 of 119 Mar 23, 2017 ©SGeT e.V.

4.2.4 General I2C Bus EEPROMs

The other SMARC I2C buses (I2C_LCD, I2C_GP, I2C_CAM) operate at 1.8V. The power domain isolations described in the previous section do not apply. A simple sample EEPROM circuit is shown for reference.

Figure 28 I2C_GP EEPROM

V_1V8

2 2

0 0 V_1V8

N U10 D Atmel A T24H C02 I2C_GP _CK 6 8 MOD SCL VCC I2C_GP _DAT 5 MOD SDA

7 W P _GENERIC WP GEN_BOAR D_ID_A0 1 A0 GEN_BOAR D_ID_A1 2 A1 GEN_BOAR D_ID_A2 3 4 2 A2 GND 1

C101 R225 0 100nF 10KOhm 4

0 SOIC8 25V 2 1

2 2 I2C Address : 0x56

0 0 (7-bit form at)

D D

SMARC Design Guide 2.0 Page 49 of 119 Mar 23, 2017 ©SGeT e.V.

4.2.5 I2C Based I/O Expanders

I2C based “I/O Expanders” are available from Texas Instruments, NXP and others. Multiple expanders may be put onto the same I2C bus by configuring the I/O expander I2C address straps. These devices are an easy and cost effective way to realize additional I/O on SMARC systems.

On the device shown in the figure, the I/O ports on the right are all in a high impedance “tri-state” mode when the device powers up. This allows the designer to tie the I/O lines through resistor pull-ups or pull- downs to define a power up state for these lines, before the I2C interface and before software are active. Wider (x16) devices are also available.

Figure 29 I2C Device: I/O Expander

V_1V8 V_1V8

2 1

h h C75

O O U34

4 4 100nF

0 0 25V 2 TI TCA9554

N N 16

D D VCC 4 IO_EXP_0 P0 5 IO_EXP_1 P1 I2C_GP_DAT 15 6 IO_EXP_2 MOD SDA P2 I2C_GP_CK 14 7 IO_EXP_3 MOD SCL P3 9 IO_EXP_4 P4 10 IO_EXP_5 P5 GP_EXP1_ID_A0 1 11 IO_EXP_6 A0 P6 GP_EXP1_ID_A1 2 12 IO_EXP_7 A1 P7 GP_EXP1_ID_A2 3 A2 13 INT# 8 GND

2 2 TSSOP16

K K I2C Address : 0x20

0 R

1 1 (7-bit format)

SMARC Design Guide 2.0 Page 50 of 119 Mar 23, 2017 ©SGeT e.V.

4.2.6 Other I2C Devices

There is a very wide variety of I2C peripherals available on the market. Since SMARC Modules offer up to four I2C buses (not counting the HDMI private I2C bus), it is easy to incorporate I2C devices into a SMARC system. A few schematic examples are given here, and further suggestions are listed in the table at the end of this section.

Figure 30 I2C Device: Accelerometer

V_1V8

1 C72 100nF 2 25V V_3V3 V_1V8 V_1V8

U32

2 STMicro LIS302DL 2

5 1 1 4

h I2C_GP_DAT R143 1 2 0Ohm h

I C73 I

0 MOD 0402 C221 1 0

1 VDD_IO 1

4 100nF 4

K 10uF K

0 25V 0

1 16V 2 2 1

1 I2C_GP_CK 1 2 0Ohm 1 MOD R140 0402 6 VDD

I2C_LCD_DAT 1 2 0Ohm DNI MOD R141 0402 ACCL_I2C_SDA 13 DNI SDA/SDI/SDO R145 I2C_LCD_CK 1 2 0Ohm DNI ACCL_I2C_SCL 14 8 LIS302DL_INT1 1 2 GPIO10 MOD R142 0402 SCL/SPC INT1 0Ohm MOD ACCL_I2C_ADD 12 9 LIS302DL_INT2 1 2 GPIO11 SDO INT2 0Ohm MOD V_1V8 ACCL_I2C_SEL V_1V8 7 CS R144 V_3V3 DNI

2 2 3

8 6 GND_2 RSRVD_3

0 0 4

4 O GND_4

0 K

0 5

1 GND_5

1 1 11 10 GND_10 RSRVD_11 15 THRM_PAD

2 LGA14

1 I2C Address : 0x1C (7-bit format)

Figure 31 I2C Device: Accelerometer and Magnetometer

I2C_GP_CK 1 2 0Ohm DNI MOD R134 0402 I2C_CAM_CK 1 2 0Ohm I2C_ACC_CK MOD R131 0402 U30 STMicro LSM303DLHC V_3V3 I2C_GP_DAT R133 1 2 0Ohm DNI 2 14 MOD 0402 SCL VDD I2C_CAM_DAT R132 1 2 0Ohm I2C_ACC_DAT 3 1 MOD 0402 SDA VDD_IO V_1V8 1 C71 1 C220 100nF 10uF DNI 0Ohm 2 1 INT2 4 25V 16V 0402 R137 INT2 2 2 GPIO11 DNI 0Ohm 2 1 INT1 5 6 0402 R138 INT1 C1 C70 1 1 C200 100nF GPIO10 DNI 0Ohm 2 1 DRDY 9 8 4.7uF 25V 0402 R139 DRDY RSVD_8 2 10 2 10V RSVD_10 12 11 SETP RSVD_11 C251 1 220nF 16V 2 13 7 SETC GND GND

LGA14

I2C Address : 0X19 (Accel) I2C Address : 0X1E (Magnet) (7-bit format)

SMARC Design Guide 2.0 Page 51 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 32 I2C Device: Gyroscope

V_1V8

1 1

m I2C_GP_CK R127 1 2 0Ohm DNI m

2 MOD 0402 2

4 I2C_CAM_CK 1 2 0Ohm I2C_GYRO_CK 4

K R130 K

0 MOD 0402 0 U31

0 0 V_3V3

9 9 V_1V8

1 1 STMicro L3G4200D

R 2 R 2 1 VDD_IO I2C_GP_DAT R128 1 2 0Ohm DNI 2 16 MOD 0402 SCL/SPC VDD I2C_CAM_DAT R129 1 2 0Ohm I2C_GYRO_DAT 3 MOD 0402 SDA/SDI/SDO 1 C209 1 C210 1 C219 SDO/SAO 4 15 SDO/SA0 RSVD_15 100nF 100nF 10uF 5 16V 16V 16V CS 2 2 2

8 RSVD_8 9 RSVD_9 GPIO10 R136 1 2 DATA_READY 6 10 MOD 0402 DRDY/INT2 RSVD_10 DNI 11 0Ohm RSVD_11 GPIO11 R135 1 2 INT1_GYRO 7 12 MOD 0402 INT1 RSVD_12 DNI 13 0Ohm GND 14 PLLFILT 1 1 C250

h R191 2 470nF

I LGA16 4 25V

0 0 1 2

1 C212 2 10nF 1 I2C Address : 0X69

16V m 2

h R192 2

4 (7-bit format)

1 2

The table below gives a small sampling of other 1.8V I/O I2C devices that are available. The list is meant to just give the reader an idea of what types of devices are available.

Table 3 I2C Device Examples - 1.8V I/O

Function Device Description Vendor Vendor P/N

ADC 8-channel, 12-bit SAR ADC Analog Devices AD7291 with temperature sensor DAC Quad, 16-bit DAC Analog Devices AD5696R

LED driver 7-bit LED driver with intensity Texas Instruments TCA6507 control

Proximity / Button Four Channels, Capacitive Semtech SX9500 sensor Proximity/Button Solution

Temperature Temperature Monitor, ±1° C On Semiconductor NCT72 Sensor

UART 128 Word FIFOs Maxim Integrated MAX3108

SMARC Design Guide 2.0 Page 52 of 119 Mar 23, 2017 ©SGeT e.V.

4.3 Touch Screen Controller Interfaces

4.3.1 General

The two most popular touch technologies used with SMARC systems are summarized in the following table.

Table 4 Popular Touch Technologies Technology Notes Resistive Low cost; rugged. Display clarity and contrast may be compromised by the resistive touch overlay. Usually used with a stylus but may be used with bare fingers. Multi- touch is possible but not common. More straightforward to implement than capacitive touch. Projected Higher cost, higher barrier to entry and better quality and user experience than Capacitive resistive touch. Multi-touch capable. Excellent optics.

There are many other touch technologies, some better suited to certain situations such as user’s wearing gloves and so on. An overview may be found on the EloTouch website: www.elotouch.com under “Touchscreens”.

4.3.2 Interface Types / Driver Considerations

Various host interface types are used by touch screen controllers. A given controller may implement one or more of the following interfaces: USB client, I2C, asynchronous serial port, I2S, SPI, or other interface.

USB interfaces for touch screen controllers are attractive as there is the potential that the software effort is minimal: the touch screen controller may act as a USB HID (Human Interface Device) class device, and the operating system at hand may be able to understand the generic touch HID implementation directly. However, for more advanced touch implementations, such as multi-touch (the ability to track and decipher multiple, simultaneous touch hits on a screen), a more specialized driver is usually necessary. The driver is often touch controller vendor specific. Additionally, a touch controller vendor may offer multiple hardware interfaces, but the driver may be optimized for one particular hardware interface. The conclusion is: check out the software driver situation before going down a particular hardware path.

4.3.3 Touch Controller Modules / ICs / Screens

Table 5 Touch Controller Module / IC / Screen Vendors

Vendor Notes Web Link Atmel Key vendor of touch screen controller ICs for projected www.atmel.com capacitive screens.

Atmel is a silicon vendor, and generally will not help directly with touch screen integration issues, unless your company is a Tier 1 company. Atmel has a network of partners that they will steer you to for help with integration issues. Some of the partners from Atmel’s list are included in this list. Data Modul Selection of touch screen panels, overlays and www.data-modul.com

SMARC Design Guide 2.0 Page 53 of 119 Mar 23, 2017 ©SGeT e.V.

controller modules for projective capacitive technology and for resistive touch screens.

Company is based in Germany and has a presence in the USA. Products are marketed under the “Easy Touch” trade mark. EloTouch Elo offers a variety of finished touch panels. They also www.elotouch.com offer a popular controller chip for resistive touch panels, under the marketing name “AccuTouch COACh V Controller Chip”. Pixcir Vendor of controller ICs for projected capacitive www.pixcir.com screens. Based in China and in Switzerland. Precision Touch modules and touch overlay screens. Based in www.pdaatl.com Design Marietta, Georgia, USA. Associates Touch Touch overlays, modules and integration services. www.touchinternational.com International One of the larger and better known companies in this field. Based in the state Texas, USA.

The Touch International website has an overview of various touch technologies. MSC Vendor of its own product group of Touch Screen www.msc-technologies.eu Technologies Panels, Overlays and Controller Cards for PCAP (Projected Capacitive) Touch Technology; also offers other touch technologies, TFT panels and display systems.

MSC has its own sales presence in Central Europe and is marketed by Avnet / Avnet Embedded in all other countries of the world.

Also check with your SMARC Module vendor or your SMARC Carrier design partner – some of them have in-house solutions for particular display panels.

Also remember to consider the availability of software drivers for the choices that you are making.

SMARC Design Guide 2.0 Page 54 of 119 Mar 23, 2017 ©SGeT e.V.

4.3.4 I2C Interface to Touch Controller

Atmel is a popular choice for projected capacitance touch controllers. Atmel supplies USB and I2C drivers for the mXT1664S touch screen controller. Multi-touch is supported in the I2C driver but not, as of this writing apparently, in the USB driver.

The circuit shown below provides buffering and level translation for a SMARC interface to an I2C interfaced touch controller board. The Atmel mXT1664S can be configured for 1.8V I2C operation, and hence this voltage translation may not be necessary in a custom design. However, off-the-shelf touch controller modules may not be configured for 1.8V I/O (and the particular touch module behind this example was not). In any case, some buffering when cabling to an external board is not a bad thing to have, for robustness.

Figure 33 Touch Screen Connector – I2C Interface

V_1V8 V_3V3

1 C470 C473 1

2 100nF 100nF 2 25V 25V

m m

3 2 2 6

2 2

h h

8 8

0 0

O O

4 4

K K

0 0

R R

0 0

1 1

1 1 U73 TI SN74AVC1T45

6 1 VCCB VCCA

GPIO10 0Ohm 1 DNI 2 TS_GPIO_1V8 4 3 MOD 0402 R475 B A GPIO1/CAM1_PWR# 0Ohm 1 2 R476 MOD 0402 2 5 GND DIR

SOT553

V_1V8 V_3V3

1 C471 C474 1 V_3V3 V_5V0

2 100nF 100nF 2 25V 25V

m m

4 2 2 7

2 2

h h

8 8

0 0 1 1

O O

4 4 C476 C477

4 4

K K R 0 R 0 100nF 100nF

0 0

1 1 25V 25V J63

1 1 2 2 U74 Molex 53261-1071 TI SN74AVC1T45 1 1 1 6 2 VCCA VCCB 2 3 TS_GPIO 3 GPIO6/TACHIN 0Ohm 1 DNI 2 RESET_1V8 3 4 TS_RST 4 MOD 0402 R477 A B 4 5 RESET_OUT# 0Ohm 1 2 R478 5 MOD 0402 5 2 6 DIR GND 6 7 7 8 SOT553 8 9 11 9 SH1 10 12 10 SH2 V_1V8 V_3V3

10/1/1x10/1.25 SMT 1 1 C472 C475 100nF 100nF 2 2

25V m

8 9

25V 2 2

2 h

8 8

0Ohm h I2C_CAM_CK 2 0 0

4 4

1 2 R479 O

4 4 MOD 0402 O

0 0

R R

I2C_CAM_DAT 0 1 2 R480 U75 0 MOD 0402 1

0Ohm Fairchild FXMA2102 1 1

1 8 VCCA VCCB DNI I2C_LCD_CK 0Ohm 2 7 I2C_TS_CK MOD 1 0402 2 R481 A0 B0 I2C_LCD_DAT 3 6 I2C_TS_DAT MOD 1 0402 2 R482 A1 B1 0Ohm DNI 1 2 0Ohm 5 4 R485 0402 OE GND

MicroPak-8

SMARC Design Guide 2.0 Page 55 of 119 Mar 23, 2017 ©SGeT e.V.

4.4 I2S Interfaces

4.4.1 General Information

The I2S (Inter IC Sound) bus specification was initially released in 1986 by Philips (NXP) and later revised in 1996. I2S is a synchronous serial bus used for interfacing digital audio devices such as Audio CODECs and DSP chips. Generally PCM audio data is transmitted over the I2S interface. The I2S bus may have a single bidirectional data line or two separate data lines. The signals constituting the I2S bus are a serial clock/ bit clock (output from the master), a left right clock (output from the master) that indicates the channel being transmitted and a single bidirectional data line or two data lines - one input and one output. A SMARC Module can generally be configured as I2S master or slave. SMARC Modules may support up to three independent I2S interfaces each having separate input and output data lines.

4.4.2 Cirrus Logic I2S Audio Example

An example of an I2S based audio circuit using the Cirrus Logic WM8904 CODEC is given below.

The circuit uses a SMARC I2S interface for the audio PCM data, and a SMARC I2C interface to allow a path for software setup of registers within the CODEC.

Figure 34 I2S Audio Codec Cirrus Logic WM8904

V_1V8_S0_I2S_CODEC

120 FB9 V_1V8_S0_I2S_CPVDD 2A 0603 MAX 5.86 mA

9 5

2 2

3 3

0 0

2 2

4 4

C 0 C 0 V_1V8_S0_I2S_CODEC V_1V8_S0_I2S_CODEC V_3V3_MIC

u n

V 0

0 0

6 5

1 0

1 MAX 1,05 mA MAX 0.76 mA MAX 0.01 mA 120 FB27 GND GND 2A 0603

2 2

4 2

0 0 ZNL18

2 6

4 4

2 2

C 0 C 0

8 9 0 0 Place Microphone decoupling cap and FB as close as posible to codec WM8904 V_3V3_MIC

1 1

4 4 120 FB11 V_1V8_S0_I2S_AVDD C 0 C 0

V V 2A 0603 n n

0 0

MAX 4,41 mA 0 0

5 5

0 1

0 0

2 2

V V

n n 0R R40

4 4

1 1

0 0

0 0 DNI

2 2

4 4

5 5

0 0 1% 0402

C 0 C 0 V_3V3_S0 V_3V3_MIC

1 1 GND

GND GND GND_AUDIO 3 U60

u n

V 0 0 0 U57

6 5 1 0 7 6

1 CPVDD V_DCVDD 23 4 1 8 AVDD V_DBVDD V_VIN_1 V_VOUT_8 GND_AUDIO GND_AUDIO 19 V_3V3_MIC_FB 2 7

3 V_VIN_2 V_VOUT_7 V_MICVDD 2

8 0 6

1 NC_GPIO1_I2S 1 4 NC CT IRQ/GPIO1 22 C 0

1 5

3 5 2 2

20 V_MICBIAS_I2S 4u7 C294 8 4 ON GND 0 0

MICBIAS ZNL16 2 3 10V 0402 4 9 4 4 I2C_GP_CK 0R 1% 0402 R54 I2C_WM8904_CK 2 V_VBIAS THMPAD_9 C 0 C 0

MOD SCLK Place Both Microphone decoupling caps as close as posible to codec WM8904 u

6 I2C_GP_DAT 0R 1% 0402 R49 I2C_WM8904_DAT 3 21 VMIDC_I2S 4u7 C295 1

MOD SDA VMIDC 2 4 TPS22965

10V 0402 V V

C 0

n u

GND 0 6

GND_AUDIO 1 1 LINE_IN_RIGHT_I2S 25 13 HEADPHONE_OUT_LEFT_I2S 5 1 IN1R/DMIC_DAT2 HPOUTL GND GND GND

V MIC_RIGHT_I2S 24 15 HEADPHONE_OUT_RIGHT_I2S n

0 IN2R HPOUTR 0

14 HEADPHONE_GND_AUDIO_FB 1 HPOUTFB LINE_IN_LEFT_I2S 27 IN1L/DMIC_DAT1 CODEK_OPTION_SW_I2S_HDA# GND

2 2

3 4 MIC_LEFT_I2S 26 8 CPCA_I2S 2u2 C200 0 0

6 6 IN2L CPCA 4 4 10 CPCB_I2S 16V 0402 C 0 C 0 CPCB AUDIO_MCK_R 28 MCLK

V V

n n

0 0

11 CPVOUTP_I2S 4u7 C296 0 0 V_1V8_S0_I2S_CODEC

CPVOUTP 5 5

0 0

I2S0_CK 29 12 CPVOUTN_I2S 10V 0402 1 1 MOD BCLK/GPIO4 CPVOUTN

C I2S0_LRCK 30 4u7 C189 C 0R R39

R MOD LRCLK R V_1V8_S0 DNI V_1V8_S0_I2S_CODEC

_ I2S0_SDOUT 32 5 10V 0402 _ 1% 0402

T MOD DACDAT DGND T

I2S0_SDIN 31 9 E

I MOD ADCDAT CPGND L

R U58 22 GND AGND _ T T T 1 8

LINE_OUT_RIGHT_I2S 18 33 U U LINEOUTR GND_PAD V_VIN_1 V_VOUT_8 O O 2 7 LINE_OUT_LEFT_I2S 16 _ _

5 V_VIN_2 V_VOUT_7

LINEOUTL E E

8 0 V_3V3_S0 6

N N

1 LINE_OUT_GND_AUDIO_FB 17 GND 4 CT

C 0 LINEOUTFB O O

2 2

3 5 2 2

H H

7 9

ON GND 0 0

P P

2 1

4 4

WM8904 D D 4 9 V_VBIAS THMPAD_9 C 0 C 0

A A

GND_AUDIO V

E E

2 2

H H

5 6 ZOBEL NETWORKs

0 0

4 4 TPS22965

1 1

4 4

V V

C 0

n u

2 2 (reduce high frequency switching noise from charge pump)

C 0 C 0

0 6 1 GND

1 1

I2C Address: 0x1A 0 0

5 1

4 4

0 R 0 GND GND GND

V (7-bit format) ZNL17 n

V V

n n

0 0

5 5 Place ZOBEL Network as close as possible to codec

0 0

1 1 1 ZNL9 GND

R R Place Charge pump caps as close as posibe to Codec % %

0 0

1 1

2 2

_ V_1V8_S0_I2S_CODEC V_1V8_S0_I2S_CODEC

E GND_AUDIO GND_AUDIO

_ T

T T

2 7

2 2

U U

9 9

0 0

1 1

4 4

O O

R 0 C 0

_ _

E E

N N

I I

L L D

5 Y1 0

9 5

2 2

2 3 ZOBEL NETWORKs

0 0 0 12MHz 50ppm

1 1

0 4 4 (reduce high frequency switching noise from charge pump) GND

1 R 0 R 0 1 4 EN V_VCC

OSC

9 0 2 3 AUDIO_MCK_OSC 0R R295 AUDIO_MCK_R

1 4 GND OUT DNI

R 0 1% 0402

R R

% %

0 0

1 1

I 2 2 DNI

D AUDIO_MCK 0R R315 GND_AUDIO GND_AUDIO MOD

% 1% 0402

GND GND ZNL38 Place R295 and R315 with shared pad with minimum stub

SMARC Design Guide 2.0 Page 56 of 119 Mar 23, 2017 ©SGeT e.V.

4.4.3 Texas Instruments TLV320AIC3105 I2S Audio Example

An alternative I2S audio CODEC example from TI is shown below. As in the WM8904 example, the I2S carries the PCM audio from and to the SMARC Module, and the I2C is used for chip setup parameters.

Figure 35 I2S Audio CODEC: Texas Instruments

V_3V3

FB2 2 1

1 1 1.2A C147 C8 I2S0_SDIN DNI 0Ohm 2 1 1uF 100nF 1 90mOhm MOD 0402 R86 C218 16V 25V 10uF 120Ohm I2S1_SDIN 0Ohm 2 1 R84 I2S_SDIN 2 2 MOD 0402 16V I2S2_SDIN DNI 0Ohm 2 1 2 MOD 0402 R80 V_3V3_AUD GND_AUDIO_1 GND_AUDIO_1 I2S0_CK DNI 0Ohm 2 1 R85 MOD 0402 J8 I2S1_CK 0Ohm 2 1 R81 I2S_CK MOD 0402 TI TLV320AIC3105 I2S2_CK DNI 0Ohm 2 1 1 1 1 1 1 MOD 0402 R77 C6 C145 C7 C146 C214 I2S_SDIN 5 25 100nF 1uF 100nF 1uF 10uF DOUT AVDD 25V 16V 25V 16V I2S_SDOUT 4 18 2 2 2 2 2 16V DIN DRVDD_18 I2S_CK 2 24 BCLK DRVDD_24 V_1V8 I2S0_LRCK DNI 0Ohm 2 1 R88 I2S_LRCK 3 MOD 0402 WCLK GND_AUDIO_1 I2S1_LRCK 0Ohm 2 1 I2S_LRCK AUDIO_MCLK_R 1 7 MOD 0402 R83 MCLK IOVDD V_1V8 I2S2_LRCK DNI 0Ohm 2 1 R79 I2C_CODEC_DAT 9 MOD 0402 SDA C5 1 C144 1 I2C_CODEC_CK 8 32 SCL DVDD 100nF 1uF 25V 16V C4 1 C143 1 2 2 20 HP_COM HPLCOM 100nF 1uF I2S0_SDOUT DNI 0Ohm 2 1 CODEC_RESET# DNI0Ohm 1 2 AUDIO_RESET# 31 19 HP_LEFT 25V 16V MOD 0402 R87 MOD 0402 R89 RESET# HPLOUT 2 2 22 I2S1_SDOUT 0Ohm 2 1 R82 I2S_SDOUT CAR_RESET_OUT# 0Ohm 1 2 MOD 0402 MOD 0402 R65 HPRCOM I2S2_SDOUT DNI 0Ohm 2 1 23 HP_RIGHT MOD 0402 R78 HPROUT LINE_1_IN_LEFT C178 470nF MIC1L 10 1 2 MIC1L/LINE1L LINE_1_IN_RIGHT C179 470nF MIC1R 11 27 LEFT_LOP 1 2 MIC1R/LINE1R LEFT_LOP 28 LEFT_LOM LEFT_LOM I2C_GP_DAT DNI 0Ohm 1 2 R75 LINE_2_IN_LEFT C180 470nF MIC2L 12 29 RIGHT_LOP MOD 0402 1 2 MIC2L/LINE2L RIGHT_LOP LINE_2_IN_RIGHT 470nF MIC2R 13 30 RIGHT_LOM I2C_CAM_DAT 0Ohm 1 2 R74 I2C_CODEC_DAT C181 MIC2R/LINE2R RIGHT_LOM MOD 0402 1 2 14 6 MIC3L/LINE3L/MICDET DVSS 16 I2C_GP_CK DNI 0Ohm 1 2 HP_MIC C208 100nF HP_MIC_C MOD 0402 R76 1 2 MIC3R/LINE3R 1 2 21 I2C_CAM_CK 0Ohm I2C_CODEC_CK 1 MOD 0402 R73 DRVSS 17 0Ohm 1 2 R70

2 R265 AVSS1 0402 0 2KOhm 26 4 AVSS2 J9 J10 0 15 33 MICBIAS T_PAD JST SM03B-SRSS-TB JST SM03B-SRSS-TB 2 MICBIAS_CODEC GND_AUDIO_1 1 1 QFN32 LINE_2_IN_LEFT 1 LINE_1_IN_LEFT 1 2 2 GND_AUDIO_1 LINE_2_IN_RIGHT 2 LINE_1_IN_RIGHT 2 3 3 3 3 I2C Addr :0x58

2 1

2 1 (7 bit Address)

M M

M M SMT SMT

5 4

5 4 3/1/1x3/1.0 3/1/1x3/1.0

GND_AUDIO_1 GND_AUDIO_1

HP_COM 0Ohm DNI J7 R72 0402 1 2 0Ohm CUI SJ-43516 R71 0402 V_1V8 1 2 HP_MIC 1 2 0Ohm DNI JACK1_R 1 1 R68 0402 1 2 0Ohm JACK4_R 4 4 R69 0402 HP_RIGHT 3 3 1 Y2 C213 6 10nF Abracon ASEMB-12.000MHZ 6 16V 5 5 2 DNI 4 3 OSC_OUT 0Ohm 2 1 AUDIO_MCLK_R VDD OUT 0402 R67 HP_LEFT 2 2 DNI 1 2 STBY GND 6/1/3.5mm SMTRA QFN4 V_1V8

AUDIO_MCLK 0Ohm 2 1 R66 MOD 0402 D5 Semtech RCLAMP0504P

5 V D1 1 D2 3 D3 4 D4 6 2 NC 7 TAB

GND_AUDIO_1

Figure 36 Audio Amplifier: Texas Instruments

V_5V0

FB3 1 2

1.2A 90mOhm 1 C215 1 C150 1 C11 1 C149 1 C10 1 C148 1 C9 10uF 1uF 100nF 1uF 100nF 1uF 100nF 2 16V U21 16V 25V 16V 25V 16V 25V 2 2 2 2 2 2 TI TPA2016D2 L1 GND_AUDIO_1 13 16 1 2 J15 GND_AUDIO_1 GND_AUDIO_1 GND_AUDIO_1 AVDD NC_16 OUTR_P_F 4 20 JST SM02B-SRSS-TB RIGHT_LOP C153 1 2 1uF INR+ PVDDL_4 NC_20 5 PVDDL_5 50mOhm 1 1

2 11 1.7A PVDDR_11 2 12 2 R46 2

PVDDR_12 L2 2 1KOhm 1

040 1 1 M DNI 1 2 OUTR_N_F C231 C230 M

1 15 10 OUTR_P 1nF 1nF

INR+ OUTR+ SMT 4 RIGHT_LOM C151 1 2 1uF INR- 14 9 OUTR_N 2 2 3 INR- OUTR- 50mOhm 1x2-1.0 1.7A LEFT_LOP C154 1 2 1uF INL+ 1 6 OUTL_P INL+ OUTL+ L3 GND_AUDIO_1 2 7 OUTL_N GND_AUDIO_1 INL- OUTL- 1 2 OUTL_P_F J16 2 JST SM02B-SRSS-TB

R47 2 1KOhm 50mOhm 1 040 1 2 0Ohm 18 DNI R94 0402 SDZ 1.7A 1

1 3 2 AGND 2

17 8 L4 2 LEFT_LOM C152 1uF INL- 1

1 2 SCL PGND 1 1 M 1 2 C228 C229 M 19 21 OUTL_N_F

SDA TH_GND 1nF 1nF 4 SMT 3 2 2 50mOhm 1x2-1.0 I2C_GP_CK 1 2 0Ohm DNI QFN20 MOD R91 0402 1.7A I2C_CAM_CK R90 1 2 0Ohm I2C_AMP_CK MOD 0402 GND_AUDIO_1 GND_AUDIO_1 GND_AUDIO_1 I2C_GP_DAT 1 2 0Ohm DNI MOD R92 0402 I2C_CAM_DAT 1 2 0Ohm I2C_AMP_DAT MOD R93 0402 SMARC Design Guide 2.0 Page 57 of 119 Mar 23, 2017 ©SGeT e.V.

4.4.4 lntel High Definition Audio over I2S2

The HDA interface uses the same pins as I2S2 in SMARC 2.0 specification. At the time of writing HDA is still the preferred Audio Interface for x86 based Modules, even though I2S is getting integrated in the latest x86 SoC generations. There's a minor conflict with regards to voltage levels of the shared HDA and I2S audio interfaces. SMARC defines the I/O levels of HDA to be 1.5V to comply with the HDA specification. Nevertheless, there's a trend to run the HDA interface at 1.8V in order to save cost for additional voltage regulators. Most of chip vendors as well as codec vendors allow either voltage to be used. Please check with your Module vendor if 1.5V or 1.8V are supported and use an audio codec that is capable to support the regarding I/O voltage.

The example schematic shows a simple resistor option (R126 and R127) to support both I/O levels within one design. HDA_SDI signal should have a damping resistor close to the audio codec. It's a good practice to also reserve space for series damping resistors at the other HDA interface lines. Depending on Carrier board implementation it might be useful to also apply series resistors there to improve EMI and signal integrity.

Figure 37 HD Audio

X2 t V_1V8 V_HDA 5 u

O HP_JD ) R126 4

e R5%0R0S03 3 e

i DNI 2 n

f 0603 o

V_HDA 1 i

R138 R137 6 p

2 2

m 33Ohm 0 0 33Ohm

a V_1V5 U20 4 4

0 0

XAUDJACK_2503AP_6P_LC (

2 2

V_3V3 CS4207-CNZ H

R127 R139 0 0 R140 C139 C138

4 4

R5%0R0S03 C150 C151 15kOhm 0 0 15kOhm 100p 100p 3 38 HDA_HP_L 0603 100nF 100nF C137 C136 AGND_HDA 16V 16V VL_HD HPOUT_L 100nF 100nF 9 39 C149 AGND_HDA 16V 16V 100nF VD HPREF 16V 1 40 HDA_HP_R AGND_HDA AGND_HDA V_3V3 V_3V3_FILT VL_IF HPOUT_R AGND_HDA FB1 25 VA 4.7uF X1 35 HDA_LINE_L 5 1.2A 90mOhm C153 C154 C131 10V R131 0402 560Ohm 100nF 100nF 24 LINEOUT_L1+ 34 4.7uF LINE_OUT1_JD 4 t VA_REF LINEOUT_L1- u

3 O C152 16V 16V C114 C132 10V R132 0402 560Ohm

10uF 10uF 2 10V 10V HDA_VBIAS29 36 HDA_LINE_R 1 e VBIAS LINEOUT_R1+ 37 R130 R129 C134 C133 6 n

LINEOUT_R1- 2 2

L 47kOhm 0 0 47kOhm 2.7nF 2.7nF

4 4

46 0 0 XAUDJACK_2503AP_6P_LC HDA_VHP+ 44 VA_HP C155 HDA_VHP- 41 VHP_FILT+ 31 100nF VHP_FILT- LINEOUT_L2+ 30 AGND_HDA 16V LINEOUT_L2- AGND_HDA AGND_HDA C117 C118 10uF 10uF HDA_FLY+ 45 32 X3 10V 10V C119 FLYP LINEOUT_R2+ 33 5 2.2uF LINEOUT_R2- LINE_IN_JD 4 n

10V 3

HDA_FLY_C 43 1.0uF 2 e HDA_CLK FLYC 21 HDA_LINEIN_L R144 100Ohm C142 10V 1 n

MOD 0402 i LINEIN_L+ 6

C122 1.0uF L 22 HDA_LINEIN_C C135 2.2uF R146 0402 100Ohm C144 10V 18pF 10V HDA_FLY- 42 LINEIN_C- 1.0uF R145 XAUDJACK_2503AP_6P_BC

DNI FLYN HDA_LINEIN_R 2

23 0 R143 0402 100Ohm C140 10V 0Ohm LINEIN_R+ DNI 4

0 C141 C143 HDA_CLK_R 6 R152 0402 0Ohm 2.7nF 2.7nF R142 R141 V_3V3_FILT HDA_SYNC HDA_SYNC_R BITCLK 2 2

10 0 0 MOD R153 0402 0Ohm 100kOhm 100kOhm HDA_SDI HDA_SDI_R SYNC 4 4 8 0 0 MOD R128 0402 33Ohm AGND_HDA HDA_SDO HDA_SDO_R 5 SDI 17 MOD R154 0402 0Ohm HDA_RST# HDA_RST#_R 11 SDO MICIN_L- 18 HDA_MIC_L MOD R155 0402 0Ohm R136 RESET# MICIN_L+ AGND_HDA 2 HDA_MICBIAS 0 2.67kOhm 16 AGND_HDA 4 MIC_BIAS

0 14 C125 15 GPIO2 19 HDA_MIC_R 1.0uF X4 HDA_SENSEA 13 GPIO3 MICIN_R+ 20 10V 5 e SENSE_A MICIN_R- 1.0uF MIC_JD 4 n

3 h AGND_HDA R150 0402 100Ohm C146 10V 47 1.0uF 2 p R135 R134 R151 R133 48 SPDIF_IN R149 100Ohm C145 10V 1 o 0402 r 2 2 2 2 SPDIF_OUT1

HDA_VCOM c 0 39.2kOhm 0 20kOhm 0 10kOhm 0 5.1kOhm 12 28 6

4 4 4 4 GPIO1/DMIC_SDA2 VCOM

0 0 0 0 27 HDA_VREF+ M 4 VREF+ C147 C148 R148 R147 XAUDJACK_2503AP_6P_PC HP_JD MIC_JD LINE_IN_JD LINE_OUT1_JD DMIC_SCL 2 2 2 26 C129 C130 2.7nF 2.7nF 100kOhm 0 0 100kOhm

GPIO0/DMIC-SDA1 AGND 4 4

1.0uF 10uF 0 0

D 10V 10V AGND_HDA

D E AGND_HDA AGND_HDA

7 9

4 AGND_HDA

M1 MDSP_02 AGND_HDA DNI

AGND_HDA

SMARC Design Guide 2.0 Page 58 of 119 Mar 23, 2017 ©SGeT e.V.

4.4.6 Audio Switch

The following schematic shows an audio switch. This can be used on baseboards which have both codecs I2S and HD Audio to switch between the two of them.

Figure 38 Audio switch

JACK DETECT SIGNALS FOR I2S CODEC (Connected to 4x GPI of I2C Expander)

Adio Codec Multipexor HDA (default) / I2S Codec JACK Signal Function Voltage Log H3 Plug 5V 1 LINE IN LINE_IN_JD V_1V8_S0 Unplug 0 0 Plug 5V 1 JUMPER LINE OUT LINE_OUT_JD J31 Unplug 0 0 1 J31 CODEC Plug 5V 1 P1 MIC (*) MIC_JD CODEK_OPTION_SW_I2S_HDA# 2 OPEN HDA Unplug 0 0 P2 SHORTED I2S Unplug 5V 1

8 HEADPHONES (*) HEADPHONES_JD

2 1044-8634

0 Plug 0 0

R 0 (*) These two JACKs are available via Front Panal Audio Header and plugged Intel HD Audio Front panel dongle V_4V3_AUDIO MAX 43 uA

0 MAX 1.2 uA 1

9 5

2 2

6 3 GND_AUDIO

0 0

2 1

4 4 V_4V3_AUDIO C 0 C 0

u n

V 0

0 0

6 5

1 0

1 V_4V3_AUDIO U51 Line In Jack 3.5 mm V_5V0_S0 GND_AUDIO GND_AUDIO 10 V_V+ U20 Vout = 1,204 * (RA+RB)/RB = 4.28 V MAX 43 uA J24 V_5V0_S0_AUDIO 120 FB28 1 5 LINE_IN_LEFT_HDA 13 12 LINE_IN_LEFT_MUX 1u C216 LINE_IN_LEFT_C 600 FB16 LINE_IN_LEFT 2 V_IN V_OUT NC1 COM1 2 2A 0603 LINE_IN_LEFT_I2S 11 14 16V 0402 420mA 0402 3

3 2 NO1 IN1-2 3

7 9 8 8

2 2 2 2

4 9 3 9 4 LINE_IN_JD 4

0 0 0 0

3 4 FB_V_4V3_AUDIO 2

R 0 2 1 2 1 4

4 4 4 4 6 Port C of HDA codec

EN NR/FB 0

C 0 C 0 C 0 C 0

4 LINE_IN_RIGHT_HDA 1 16 LINE_IN_RIGHT_MUX 1u C217 LINE_IN_RIGHT_C 600 FB21 LINE_IN_RIGHT 5

C 0 NC2 COM2 5 16V 0402 420mA 0402

LINE_IN_RIGHT_I2S 15 2 1

2 RA 3

NO2 0 1

GND 1

V V V V

u n u n

R 0

6 0 6 0

1 0 1 0

1 4

2 2

1 5 1 5

0 0

3 3 0 1054-2371

0 0

1 1

TPS73101 5 k LINE_OUT_LEFT_HDA 5 4 LINE_OUT_LEFT_MUX

2 2

4 4 1 NC3 COM3

C 0 C 0 6 LINE_OUT_LEFT_I2S 3 NO3 GND_AUDIO

V V

p p

0 GND_AUDIO GND_AUDIO GND_AUDIO GND_AUDIOGND_AUDIO 0 0 LINE_OUT_RIGHT_HDA 9 8 LINE_OUT_RIGHT_MUX 0 0

2 NC4 COM4 5 5

0 0

1 1

4 LINE_OUT_RIGHT_I2S 7 6

R 0 NO4 IN3-4

GND_AUDIO 2 GND_AUDIO GND_AUDIO RB GND

7 TS3A44159

% V_4V3_AUDIO

2 MAX 1.2 uA AUDIO_JACK_SENSE# GND_AUDIO

0 7

GND_AUDIO 2 2

7 3

0 0 Line Out Jack 3.5 mm

2 1

4 4

C 0 C 0 J43

3 C57 100u LINE_OUT_LEFT_C 600 FB22 LINE_OUT_LEFT 2

V u n 2

V 0

0 0

6 5 B 10V 420mA 0402 1 0 3

1 3 LINE_OUT_JD 4 4 Port D of HDA codec C56 100u LINE_OUT_RIGHT_C 600 FB24 LINE_OUT_RIGHT 5 HDA / I2S Audio codec LEDs indication GND_AUDIO GND_AUDIO 5 U52 B 10V 420mA 0402

2 4

2 2 1

8 8 10 0 0 R216 1

2 2 V_V+ 4 4 C 0 C 0 5k11 1% MIC_RIGHT_HDA 1u 16V C223 0402 MIC_RIGHT_HDA_C 13 12 MIC_RIGHT_MUX 0402 NC1 COM1

V V

p p

0 0

V_3V3_S5_LED MIC_RIGHT_I2S 1u 16V C307 0402 MIC_RIGHT_I2S_C 11 14 0 0

NO1 IN1-2 5 5

0 0

1 1 GND_AUDIO MIC_LEFT_HDA 1u 16V C308 0402 MIC_LEFT_HDA_C 1 16 MIC_LEFT_MUX NC2 COM2 MIC_LEFT_I2S 1u 16V C309 0402 MIC_LEFT_I2S_C 15 GND_AUDIO GND_AUDIO NO2

3 9 2

2 2 2

1 6 1

0 0 0 LINE_OUT_GND_AUDIO_FB 0R R114

2 1 2

4 4 4

R 0 R 0 R 0 V_MICBIAS_HDA 5 4 V_MICBIAS 1% 0402 NC3 COM3 V_MICBIAS_I2S 3 NO3 ZNL22 Route LINE_OUT_GND_AUDIO_FB close to LINE OUT GND_AUDIO

0 9 8

R R

0 % % % NC4 COM4 audio signals, to reduce noise

0 0

1 1 1

5 5 7 6

7 7 NO4 IN3-4

V 2 I2S CODEC 3 HDA CODEC GND Front panel Analog Header

Y A Y D44 D D45 TS3A44159

_ V_1V8_S0

2 V_4V3_AUDIO C225 LED_I2S_CODEC# I GND_AUDIO GND_AUDIO

4 5

_ LED_HDA_CODEC# 2 2

0 0

1u 2

2 2

4 4

7 3 MAX 1.2 uA 0

R 0 R 0

16V 4

R 0

Q8 N 6 0402 O Port B of HDA codec

CODEK_OPTION_SW_I2S_HDA# 1 I

1 1

2 2

BSS138W T

7 8

0 0

P Q2

2 1

4 4 GND_AUDIO

SOT323 O

2 C 0 C 0

BSS138DW 2 2

% %

k k

600 FB14 k 2 1 1

2 2

E SOT363 J10 0

0 D 420mA 0402

u n

V 0 1 0 0 MIC_LEFT 1 2

C 6 5 P1 P2 GND 1 0 1 600 FB15 MIC_RIGHT 3 4 FPAH_PRESENCE# 3 P3 P4 420mA 0402 HEADPHONE_OUT_RIGHT 5 6 MIC_JD Q2 GND P5 P6 5 GND_AUDIO GND_AUDIO U19 AUDIO_JACK_SENSE# 7 8 BSS138DW HEADPHONE_OUT_RIGHT_MUX C358 100u 600 FB47 P7 P8 NC 10 HEADPHONE_OUT_LEFT 9 10 HEADPHONES_JD SOT363 V_V+ B 10V 420mA 0402 P9 P10

4 2 HEADPHONE_OUT_LEFT_HDA 13 12 HEADPHONE_OUT_LEFT_MUX C359 100u 600 FB48 4

NC1 COM1 R 0

B 10V 420mA 0402 4 1 2

HEADPHONE_OUT_LEFT_I2S 11 14 R

GND NO1 IN1-2

% Port A of HDA codec 1 HEADPHONE_OUT_RIGHT_HDA 1 16 NC2 COM2 2 20k

HEADPHONE_OUT_RIGHT_I2S 15 k

9 2 0 4 NO2 0 HEADPHONE_GND_AUDIO_FB 0R R55 3 21 5 4 1% 0402 NC3 COM3 3 ZNL19 NO3 Route HEADPHONE_GND_AUDIO_FB close to HEADPHONEGND_AUDIO V_5V0_S0 9 8 audio signals, to reduce noise NC4 COM4 7 6 V_5V0_S0 NO4 IN3-4

1 4 2 R 0 GND

3 TS3A44159

2 4 V_5V0_S0

C 0

0 % GND_AUDIO GND_AUDIO

R 0 1 U13 To HDA kodek 2 6 SENSE_A_HDA 3 V_V+ NO GND_AUDIO Q6 CODEK_OPTION_SW_I2S_HDA# 1 CODEK_OPTION_SW_I2S#_HDA_5V0 1 5 AUDIO_JACK_SENSE#

R BSS138W IN COM %

SOT323 1 3 4 AUDIO_JACK_SENSE_I2S 2 GND NC To I2S kodek TS5A4624 GND_AUDIO GND_AUDIO 4.5 SPI Interfaces

4.5.1 General

The SPI (Serial Peripheral Interface) is a full duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of a serial clock line (generated by the master); data output line from the master; a data input line to the master and one or more active low chip select signals (output from the master).

Clock frequencies from 1-100MHz may be generated by the master depending on the maximum frequency supported by the components in the system. SMARC Modules running a 1.8V I/O interface are generally limited to about a 50 MHz clock rate on this interface.

The SMARC Module will always be the SPI master. SMARC Modules may support a Carrier SPI Boot option.

SMARC Design Guide 2.0 Page 59 of 119 Mar 23, 2017 ©SGeT e.V.

4.5.2 SMARC Implementation

Each SPI device requires a chip select, a clock, a data in line and a data out line. The device I/O level must of course be compatible with the SMARC Module I/O level.

The Winbond W25Q64FW is an example of a 1.8V I/O compatible SPI Flash device. The figure below illustrates a socket implementation for a SPI Flash memory.

Figure 39 SPI Flash Socket

V_1V8

C64 1

2 100nF 2 25V

2 R180 2 2 R181

4 10KOhm 4 10KOhm

0 J33 0 Lotes_ACA-SPI-004-T01

1 1 SPI0_CS0# 1 5 SPI0_DO MOD 1 5 MOD SPI0_DIN 2 6 SPI0_CK MOD 2 6 MOD SPI0_WP# 3 7 SPI0_HOLD 3 7 4 8 4 8

2 R182 R179

2 8-1.27 2

4 10KOhm SMT 4 10KOhm

0 DNI 0 DNI

1 1

SMARC Design Guide 2.0 Page 60 of 119 Mar 23, 2017 ©SGeT e.V.

4.5.3 SPI Device Examples – 1.8V I/O

The table below shows a small sample of the devices available on the market with a 1.8V SPI interface. It is only a sample and is meant to give an idea of the type of devices available. Remember to check the software driver situation before settling on a particular device.

Table 6 SPI Device Examples - 1.8V I/O

Function Device Description Vendor Vendor P/N

ADC 8-channel, 12-bit SAR ADC Analog Devices AD7298 with temperature sensor DAC Quad, 16-bit nano DAC Analog Devices AD5686R

Flash Memory 64 Mbit SPI Flash memory Winbond W25Q64FW

IO Expander 8-bit GPIO expander with Exar XRA1404 integrated level shifters

Temperature Digital thermometer Maxim Integrated DS1722 Sensor ±2 °C resolution Range - 55°C to +120 °C Touch Screen 4 wire resistive touch screen Texas Instruments TSC2008-Q1 Controller controller UART bridge UART with 128 Word FIFOs Maxim Integrated MAX3108 and support for 9-bit multi-drop mode data filtering

SMARC Design Guide 2.0 Page 61 of 119 Mar 23, 2017 ©SGeT e.V.

4.6 CAN Bus

4.6.1 General

The CAN (“Controller Area Network”) bus is a differential half duplex data bus used in automotive and industrial settings. A CAN bus uses shielded or unshielded twisted differential pair wiring, terminated in the pair differential impedance of 120 ohms at the endpoints of the bus. Nodes on the bus are arranged in daisy-chain fashion, although stubs of up to 0.3 meters are allowed at each node. The standard allows data rates of up to 1 Mbps, with a maximum bus length of 40 meters at that rate. Various slower rates are defined, along with longer and longer bus lengths allowed as the data rates go down. A bus rate of 250 kbps is in common use in automotive situations. With CAN FD also faster baud rates are possible.

The two lines in a CAN twisted pair are referred to as CAN_H and CAN_L (for CAN High and CAN Low). There are two bus states on the CAN physical layer: the Dominant state and the Recessive state. In the Dominant state, CAN_L is pulled to GND through an open drain driver and CAN_H is pulled to the CAN Vcc through an open drain driver. In the Recessive state, CAN_L and CAN_H are not actively driven and they are pulled to a voltage of (Vcc / 2) by passive components. Hence the CAN bus is essentially a differential open-drain bus. On the system logic side of a CAN transceiver, the CAN Dominant state is a logic low and the Recessive state a logic high.

The CAN protocol has features important to a real time environment:

 Nodes are prioritized: CAN nodes are assigned an 11 bit identifier o The lower the ID number, the higher priority  Latency time is guaranteed  Data packets are limited to 8 bytes maximum o Higher level protocols take care of handling large data sets  The bus has Multi-master capability  There are error detection and signaling features

The CAN bus base standard is defined by ISO 11898-1:2003, available for a fee from the ISO (www.iso.org). There are some very helpful CAN application notes from Texas Instruments (a vendor of CAN MAC and transceiver devices) available for free. These include “Introduction to the Controller Area Network (CAN)”, TI document number SLOA101A, and “Controller Area Network Physical Layer Requirements”, document number SLLA270. The original CAN bus protocol definition by Bosch is also freely available on the web (CAN Specification, Version 2.0 © 1991 Robert Bosch GmbH).

Various connectors are used in CAN bus implementations. The use of DB-9 connectors is fairly common. The TI application note (SLLA270) referenced above has pin-out information for a couple of common CAN connector implementations.

SMARC Design Guide 2.0 Page 62 of 119 Mar 23, 2017 ©SGeT e.V.

4.6.2 SMARC Implementation

The SMARC specification allows for up to two logic level CAN ports. The ports run at the Module I/O voltage (typically 1.8V) and consist of an asynchronous CAN TX line and an RX line from and to the SMARC Module CAN protocol controller.

A Carrier based CAN transceiver is required to create a SMARC system CAN implementation. CAN PHYs are available from Texas Instruments, On Semiconductor, NXP, Freescale, Microchip and numerous other vendors. The logic interface for CAN PHYs is typically suited for 3.3V logic I/O, so level translation is required if the SMARC Module is running 1.8V I/O.

Precautions must be taken to prevent a CAN system from sending out frames or blocking a CAN-Bus unintentionally, for example during reset and power down. During power down, CAN Transceivers are designed to be HIGH-Z. During power up or reset, they must be put into a “listen only mode”. It is the responsibility of the application software to activate the CAN-transceiver after all initialization is done.

A SMARC Carrier board CAN transceiver implementation is shown below. This example shows two 60 ohm terminations (or 120 ohms across the CAN pair). This is appropriate only if the node is an end-point, and intermediate nodes should not be terminated.

The example transceiver TJA1051 has a “silent input pin”. If left open, the transceiver enters “listen only mode”. Using a GPIO allows the application software to set the can transceiver into “normal mode = able to send” by pulling “silent” low. A pull down resistor on the gate of T1 is necessary to disable the transceiver in case of a CPU reset or power fail.

It is recommended to use GPIO8 as CAN0_EN and GPIO9 as CAN1_EN.

Figure 40 CAN Bus Implementation

Level Shift CAN Ports Connector V_1V8

V_1V8

1 U3 IC TJA1051/T3 SMT SO8_150 4.5-5.5 5 1 C4 + OE# D1 2 CAN_TX_3V3 100nF 16V U1 4 A 3 CAN_TX_3V3 1 6 CAN_L 1 CANx_RX_M MOD 2 Y - CAN_RX_3V3 4 TXD CANL 7 CAN_H 3 74LV1T125 RXD CANH 2 3 5 V_5V0 V_3V3 C2 VCC VIO 2 1 10uF 2 8 R1 PESD1CAN bi dual 50nA

1 V_3V3 GND S 60.4R V_3V3 C1 C6 U2 2 1 100nF

1 100nF 16V 1 1 5 2 OE# + 2 CANx_TX_M MOD C3 C5 3 A 4 CAN_RX_3V3 R2 4n7 - Y 100nF 16V

2 60.4R 2

1 74LV1T125 R3 X1A 2.2k A5 2 A9 A4 A10

1 GPIO_x MOD 3 A8 R4 A3 4.7k T1 CAN_H A7 1 CAN_L A2 A11 2 BSS138 A6 A1

2 CON DSUB-M/F 9pol UNC clip 90

4.6.3 Isolation

Some CAN transceiver application notes show optical isolation between the CAN protocol controller and the CAN transceiver. See, for example, NXP (Philips) application note AN96116 for the PCA82C250 CAN transceiver. They suggest using the 6N137 optical transceivers. Be careful to take into account the I/O levels and current sink / source requirements of the various devices in the chain.

SMARC Design Guide 2.0 Page 63 of 119 Mar 23, 2017 ©SGeT e.V.

5 HIGH SPEED SERIAL I/O INTERFACES

5.1 USB

5.1.1 General

The USB (Universal Serial Bus) is a hot-pluggable general purpose high speed I/O standard for computer peripherals. The standard defines connector types, cabling, and communication protocols for interconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer rates as high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses four pins: a power supply pin (5V), a differential pair (D+ and D- pins) and a ground pin. Additionally a fifth pin, USB ID (mostly used in devices supporting USB-OTG), may also be used which indicates whether the device operates in Host mode or a Client/Device mode.

SMARC Modules support up to six independent USB 2.0 busses, designated USB0 to USB5. Of these, SMARC USB0 and USB3 can be configured as a host, client or OTG port. OTG operation is optional. SMARC USB1, USB2, USB4 and USB5 are always hosts. A USB host is usually the smarter device – a host computer for example. A USB client is usually a peripheral device, such as a camera, printer or mass storage device. USB clients are often based on microcontrollers that include USB client interface hardware.

USB3.0 Super Speed is supported on USB2 and USB3 and defines data rates up to 5 Gbps. Therefore these ports have two additional differential signal pairs SSRX and SSTX.

USB3 may also support a USB3.0 OTG port.

5.1.2 USB0 Client / Host Direct From Module

The figure below shows a USB-OTG implementation on the USB0 port terminated on a micro USB Type A/B connector

The ESD diodes should be placed close to the connector, and the USB traces routed as differential pairs in “no stub” fashion – the traces should go through the pads of the ESD protection devices, without introducing a stub. If the client device is bus powered, the Carrier can supply 5V, 500mA power to the client device. The Module USB0_EN_OC# signal controls the power switch and current limiter, the Texas Instruments TPS2052, which in turn supplies power to a bus-powered client device. Per the USB specification, bus powered USB 2.0 devices are limited to a maximum of 500 mA. The TPS2052 limits the current and can stand an indefinite short circuit to GND. The current limiting is somewhat imprecise, and kicks in between 500 mA and 1A.

SMARC Design Guide 2.0 Page 64 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 41 USB0 Client / Host Direct From Module

VBUS_OTG_PWR

J6 Molex 0475900001 FB7 TDK ACM2012-900-2P-T002 1 S1 USB0_DN 1 4 5V S1 MOD OTG_PORT_N 2 S3 D- S2 USB0_DP OTG_PORT_P 3 S2 MOD D+ S3 2 3 4 S4 190mOhm ID S4 5 2x1.2x1.2 GND USB0_OTG_ID MOD 1 C2 D1 100nF TI TPD2E009 25V RA 2 5/1/1x5/0.65 Type AB Micro USB, R/A, SMT 2 1

SOT23 3

Q16 USB_VBUS_OTG FB1 Vishay SI2305CDS-T1-GE3 USB0_VBUS_DET 1 2

MOD 3 2 1.2A

SOT23 2 90mOhm 1

2 120Ohm R262 1 C191 4.7uF 040 1MEGOhm 10V

2 1

CARRIER_PWR_ON 2 Q7 MOD UMT3 ROHM RJU003N03T106 2 1 VBUS_OTG_EN# Q15 1 Vishay SI2305CDS-T1-GE3 SOT23 3 3

R174 2 Q8 2 0402 1 V_5V0 10KOhm UMT3 ROHM RJU003N03T106

1 1 C3 C1 100nF V_3V3 100nF 2 25V 25V 2 U18

TI TPS2052B 2 R1 VUSB_OTG 2 2 IN OUT1 7 4.7KOhm

USB0_EN_OC# 040 DNI MOD 3 EN1 OUT2 6

4 EN2 1

USB0_OC# OC1# 8 1 GND OC2# 5

SO8

R291 1 2 0402 0Ohm

SMARC Design Guide 2.0 Page 65 of 119 Mar 23, 2017 ©SGeT e.V.

5.1.3 USB1 and USB2 Host Ports direct from Module

Carrier board implementation of USB host ports from SMARC USB1 and USB4 is straightforward. An implementation of a dual USB Type A Host port header is shown in the figure below.

If the target USB devices are “down” on the Carrier, then much or all of this circuit may be omitted. The SMARC USB pairs are routed directly to the target device. The ferrite choke in the USB lines, the ESD diodes, and the TPS2052 power switch and associated passives may be eliminated. However, in some cases, it is desirable to have the capability to “power cycle” a USB peripheral under software control. If this is the case, it might be desirable to retain the TPS2052 power switch, or a similar device for 3.3V power switching, with the power control function performed by the USB1_EN_OC or USB4_EN_OC, as appropriate.

Figure 42 USB1 and USB4 Host Ports Direct From Module

J48 TE 5787617-1 FB11 TDK ACM2012-900-2P-T002 USB_VBUS_A4 A1 USB4_DN 2 3 VCCA MOD USB4_DN_CONN A2 USBA_N USB4_DP U DP_CONN A3 MOD SB4_ USBA_P 1 4 A4 GNDA 190mOhm

FB12 TDK ACM2012-900-2P-T002 USB_VBUS_A1 B1 USB1_DN 2 3 VCCB MOD USB1_DN_CONN B2 USBB_N USB1_DP USB1_DP_CONN B3 MOD USBB_P 1 4 B4 GNDB 190mOhm

4 3 2 1

S S S S D27 D26 2PORT TI TPD2E009 TI TPD2E009 4 3 2 1 THT S S S S

2 1 2 1 Dual Stacked, Type A USB, R/A, TH

SOT23 3 SOT23 3

V_5V0 V_3V3 V_3V3

C2901 100nF 2 2

25V R323 2 2 R324

2 0 0 U44 4.7KOhm 4 4 4.7KOhm DNI 0 0 DNI TI TPS2052B 1 1 L14 USB_VBUS_A4_FB 1 2 USB_VBUS_A 2 IN OUT1 7 4 USB4_EN_OC USB_VBUS_A1_FB MOD 3 EN1 OUT2 6 1.7A USB1_EN_OC 50mOhm MOD 4 EN2 1050-8120 C2891 C2921 8 USB2_OC 100nF 47uF OC1# 25V 16V 1 USB1_OC 2 2 GND OC2# 5

SO8

R326 1 0402 2 0Ohm L15 1 2 USB_VBUS_A1 R325 1.7A 1 0402 2 50mOhm 0Ohm 1050-8120 C2911 C2931 100nF 47uF 16V 25V 2 2

SMARC Design Guide 2.0 Page 66 of 119 Mar 23, 2017 ©SGeT e.V.

5.1.4 USB 3.0 A USB 3.0 port consists of a USB 2.0 port and a set of unidirectional SuperSpeed signals. The following example shows an implementation of a stacked dual USB 3.0 connector that is utilizing USB2 and USB3 without using the optional OTG capabilities of USB3.

Place the ESD diodes as close as possible to the connector. For SuperSpeed Signals, ESD diodes with optimized package and low I/O capacitance should be used to create only minimal impact on signal integrity. Also the common mode chokes should be selected carefully. Ensure that their differential mode cutoff frequency is well above the maximum frequency of 2.5 GHz of a USB3.0 signal.

Each USB 3.0 port should be able to supply up to 900mA and should be decoupled with at least 120µF of low ESR capacitance. Figure 43 USB 3.0 host dual

FB3 TDK ACM2012-900-2P-T002 MOD USB3- 4 3 X5 VCC_USB3 MOD USB3+ 1 2 1 FB10 USB3-_CON 2 P1_VCC 190mOhm Murata DLP11TB800UL2L USB3+_CON 3 P1_USB2.0_D- 2x1.2x1.2 USB3_SSRX- 4 3 4 P1_USB2.0_D+ MOD D4 D3 P1_GND USB3_SSRX+ USB3_SSRX-_CON USB3_SSRX-_CON 1 6 MOD 1 2 1 10 5 USB3_SSRX+_CON 2 9 USB3_SSRX+_CON 6 P1_USB3_SSRX- 2 5 VCC_USB3 3 8 7 P1_USB3_SSRX+ USB3_SSTX- USB3_SSTX-_CON USB3_SSTX-_CON P1_GND_DRAIN MOD 4 3 4 7 8 3 4 USB3_SSTX+_CON 5 6 USB3_SSTX+_CON 9 P1_USB3_SSTX- USB3_SSTX+ P1_USB3_SSTX+ MOD 1 2 FB6 OnSemi NUP4114 FB9 TDK ACM2012-900-2P-T002 Murata DLP11TB800UL2L TI TPD4E02B04 VCC_USB2 10 USB2-_CON P2_VCC MOD USB2- 4 3 11 USB2+_CON 12 P2_USB2.0_D- USB2+ 1 2 FB8 13 P2_USB2.0_D+ MOD D5 Murata DLP11TB800UL2L P2_GND USB2_SSRX- USB2_SSRX-_CON USB2_SSRX-_CON 190mOhm MOD 4 3 1 10 14 2x1.2x1.2 USB2_SSRX+_CON 2 9 USB2_SSRX+_CON 15 P2_USB3_SSRX- H1 USB2_SSRX+ P2_USB3_SSRX+ H1 MOD 1 2 3 8 16 H2 USB2_SSTX-_CON 4 7 USB2_SSTX-_CON 17 P2_GND_DRAIN H2 H3 USB2_SSTX+_CON 5 6 USB2_SSTX+_CON 18 P2_USB3_SSTX- H3 H4 P2_USB3_SSTX+ H4 USB2_SSTX- MOD 4 3 TI TPD4E02B04 Molex 0484060003 USB2_SSTX+ MOD 1 2 FB7 Murata DLP11TB800UL2L

V_5V0

C8 4.7uF U2 16V 2 9 V5_USB3_SW FB4 VCC_USB3 3 IN OUT1 2.5A IN USB3_OC# ESD protected by D3 10 40mOhm C10 USB3_EN_OC# FAULT1# MOD 4 + C9 100nF EN1 8 V5_USB2_SW Panasonic 16SVP180MX 16V USB2_EN_OC# OUT2 MOD 5 EN2 6 USB2_OC# 1 FAULT2# 11 GND 7 USB23_ILIM PAD ILIM

TI TPS2561DRC R154

2 VCC_USB2

51kOhm 0 FB5

0 2.5A 40mOhm + C11 C12 D6 Panasonic 16SVP180MX 100nF DCDS2C05GTA 16V IEC 61000-4-2, level 4 compliant R152 0402 0Ohm

R153 0402 0Ohm

5.1.5 USB 3.0 OTG

USB3 may support OTG functionality, depending on Module’s capabilities. Check with your Module’s vendor manual whether USB3 supports OTG.

Please note that dual role devices should have a VBUS capacitance that is in a range of 1.0µF to 6.5µF.

The ESD diodes should be placed as close as possible to the connector. Take care that VBUS and ID pins are also protected against ESD events as they are directly connected to the SMARC 2.0 Module. The Module will control the power switch by driving USB3_EN_OC#. It will be driven low in order to cut-off power to VBUS as it is required for client mode.

SMARC Design Guide 2.0 Page 67 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 44 USB 3.0 OTG

D7 USB3_OTGID 1 6 T1 Alpha & Omega AO3413 2 5 USB3_VBUS 2 3 USB3_VBUS_DET MOD 3 4 FB12 X6 FBD90R0A33S05D OnSemi NUP4114 USB3_VBUS 1 R156 VBUS 2

USB3- 4 3 USB3-_CON 2 1MegOhm 0

MOD 1 D- 4

USB3+_CON 3 0 1 2 USB3_OTGID 4 D+ MOD USB3+ 5 ID GND MOD

D8 3 C159 USB3_SSTX-_CON 6 USB3_SSTX- 4 3 USB3_SSTX-_CON 1 10 USB3_SSTX+_CON 7 SSTX- 10nF MOD FB13 16V USB3_SSTX+_CON 2 9 SSTX+ T2 USB3_SSTX+ 1 2 3 8 8 1 CARRIER_PWR_ON MOD Diodes DMN63D8LW MOD FBD80R0A10S04 4 7 GND_D 5 6 USB3_SSRX-_CON 9 11 USB3_SSRX- 4 3 USB3_SSRX-_CON USB3_SSRX+_CON 10 SSRX- SHLD 12 2 MOD FB14 USB3_SSRX+_CON SSRX+ SHLD USB3_SSRX+ 1 2 TI TPD4E02B04 MOD USB3_MICROAB FBD80R0A10S04

V_5V0

C156 4.7uF U21 16V 2 9 V5_USB3_SW FB11 USB3_VBUS 3 IN OUT1 2.5A IN USB3_OC# 10 40mOhm USB3_EN_OC# 4 FAULT1# MOD C157 C158 EN1 8 4.7uF 100nF 5 OUT2 16V 16V EN2 6 1 FAULT2# 11 GND 7 USB3_ILIM PAD ILIM

TI TPS2561DRC R155

51kOhm 0

R157 0Ohm 0402

SMARC Design Guide 2.0 Page 68 of 119 Mar 23, 2017 ©SGeT e.V.

5.1.6 USB Hub On Carrier

Additional USB ports may be implemented on a SMARC Carrier board using a USB hub to interface with one of the SMARC USB ports (usually USB1 or USB2, saving the SMARC USB0 for possible client or OTG use). The USB 2.0 compliant (and 480 Mbps capable) family of hubs from Microchip / SMSC (www.microchip.com or www.smsc.com) is recommended. Parts with two, three, four or seven downstream ports are available.

A Carrier hub implementation example using the seven port SMSC USB2517i is shown in the two figures below. There are three configuration straps on this particular SMSC hub, designated CFG_SEL[2] through CFG_SEL[0]. The options need to be considered carefully. The example schematic has the 2:0 configuration straps set to binary 110, which, per the SMSC data sheet, sets the hub to the following:

 SMSC hub defaults in effect  Other strap options disabled  Hub LED pins configured to indicate USB speed  Individual port power switching  Individual port over-current sensing  External EEPROM not used  External I2C interface not used

Although the sample schematic shows the external EEPROM and I2C interfaces, they are not used. Note that the “DNI” designation on the schematic stands for “Do Not Install” – i.e. the part is not loaded, in this example.

If implementing such a hub (or any piece of configurable silicon), it is wise to keep your options open and have all strap options accessible for re-configuration by option resistors or other means. It may keep you out of trouble and save a board spin.

Since the hub operates at 3.3V, the signals from the SMARC Modules that are at 1.8V (RESET_OUT# and the I2C_GP_ signals, if used) levels need to be level shifted to 3.3V to interface to the hub.

In this example, there are 7 down-stream ports. Two of them are used for off-Carrier cabled connections. These nets are designated with USB_HUB2_ and USB_HUB3_ prefixes. Since they are used for cabled connections, these are protected by a USB power switch (U19, in the second figure below). Four of the other hub ports are assumed to go to on-Carrier destinations (such as mini-PCIe cards, or a touch controller, or other on-Carrier USB peripheral). One of the 7 down-stream ports is not used.

The behavior of a USB port, at least initially, may differ slightly depending on whether that port is direct from the SMARC Module or whether the port is through a hub. With software adjustments, or “tweaking”, the direct and through – the –hub ports may appear virtually identical to a client device.

SMARC Design Guide 2.0 Page 69 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 45 USB Hub (1 of 2)

V_3V3

U16 SMSC USB2517I-JZX 1 1 1 1 1 1 1 1 1 C201 C202 C132 C131 C130 C129 C128 C127 C125 4.7uF 4.7uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 5 62 PLLFILT VDD33_5 PLLFLT 10V 2 10V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 10 VDD33_10 24 VDD33_24 46 25 CRFILT VDD33_46 CRFILT 52 VDD33_52 Power 1 C176 1 C177 57 1uF 1uF VDD33_57 64 65 16V 16V VDD33_64 GND_PAD 2 2 V_3V3

R170 VBUS_DET_HUB 44 0402 VBUS_DET 2 1 0Ohm Upstream USB1_DP_HUB 59 MOD USBDP_UP USB1_DN_HUB 58 MOD USBDM_UP V_3V3 2 USBHUB1_DN_IO1_P USBDP_DN1/PRT_DIS_P1 1 USBHUB1_DN_IO1_N R36 USBDM_DN1/PRT_DIS_M1 OCS_1 28 2 0402 1 OCS_N1# Downstream1 LED_A_N1#/PRTSWP1 51 V_3V3 4.7KOhm LED_B_N1#/BOOST0 50 29 USBHUB1_PRTPWR_IO1 2 R39 1 PRTPWR_1 0402 4.7KOhm 4 USBHUB2_DN_TYPEA0_P USBDP_DN2/PRT_DIS_P2 3 USBHUB2_DN_TYPEA0_N USBDM_DN2/PRT_DIS_M2 OCS_2 27 49 OCS_N2# Downstream2 LED_A_N2#/PRTSWP2 48 LED_B_N2#/BOOST1 26 USBHUB2_PRTPWR_TYPEA0 PRTPWR_2

7 USBHUB3_DN_TYPEA1_P USBDP_DN3/PRT_DIS_P3 6 USBHUB3_DN_TYPEA1_N USBDM_DN3/PRT_DIS_M3 OCS_3 22 47 OCS_N3# Downstream3 LED_A_N3#/PRTSWP3 34 LED_B_N3#/GANG_EN 23 USBHUB3_PRTPWR_TYPEA1 PRTPWR_3 V_3V3 9 USBHUB4_DN_MPCIe0_P USBDP_DN4/PRT_DIS_P4 8 USBHUB4_DN_MPCIe0_N R31 USBDM_DN4/PRT_DIS_M4 2 1 OCS_4 21 33 0402 OCS_N4# Downstream4 LED_A_N4#/PRTSWP4 V_3V3 32 4.7KOhm LED_B_N4# 20 USBHUB4_PRTPWR_MPCIe0 2 R29 1 PRTPWR_4 0402 4.7KOhm V_3V3 12 USBHUB5_DN_MPCIe1_P USBDP_DN5/PRT_DIS_P5 11 USBHUB5_DN_MPCIe1_N R32 USBDM_DN5/PRT_DIS_M5 2 1 OCS_5 35 31 0402 OCS_N5# Downstream5 LED_A_N5#/PRTSWP5 V_3V3 18 4.7KOhm LED_B_N5# 30 USBHUB5_PRTPWR_MPCIe1 2 R30 1 PRTPWR_5 0402 4.7KOhm V_3V3 54 USBHUB6_DN_IO2_P USBDP_DN6/PRT_DIS_P6 53 USBHUB6_DN_IO2_N R33 USBDM_DN6/PRT_DIS_M6 2 1 OCS_6 38 17 0402 OCS_N6# Downstream6 LED_A_N6#/PRTSWP6 V_3V3 16 4.7KOhm LED_B_N6# 39 USBHUB6_PRTPWR_IO2 2 R38 1 PRTPWR_6 0402 V_3V3 V_3V3 V_3V3 4.7KOhm V_3V3 56 USBDP_DN7/PRT_DIS_P7 55 2 2 2 R34 USBDM_DN7/PRT_DIS_M7 R42 R40 2 1 OCS_7 37 15 2 2 2 R41 0402 OCS_N7# Downstream7 LED_A_N7#/PRTSWP7 0 4.7KOhm 0 4.7KOhm 0 4 4 4 4.7KOhm V_3V3 14 0 0 DNI 0 4.7KOhm LED_B_N7# DNI V_3V3 V_3V3

36 1 1 1 PRTPWR_7

2 40 SDA_NON_REM

2 2 R35 SDA/SMBDATA/NON_REM1

4 4.7KOhm 41 SCL_CFG_SEL0

0 SCL/SMBCLK/CFG_SEL0

R28 2 R27 0 DNI

0 4 EEPROM/Config

4.7KOhm 4.7KOhm 1 0 R61 DNI 0 1 2 CFG_SEL2 13 42 CFG_SEL1 0402 CFG_SEL2 HS_IND/CFG_SEL1

1 1 1KOhm

2 2 NON_REM0 45 R63

SUSP_IND/LOCAL_PWR/NON_REM0 R64 R62 2

2 2 0 1KOhm

0 0

1KOhm 1KOhm 4

4 4 HUB_RESET# 43 0 DNI RESET_N# 0 0 2 XTALIN

1 1

R60 2 61

z 0 1 1 XTALIN/CLKIN Misc

1KOhm C124 C190 2

0 R263

100nF 18pF 4 E 1MEGOhm

1 25V 50V M

2 2 1

2 XTALIN2 1 60 XTALOUT R264 19 63 USB_RBIAS 2 1 1 TEST RBIAS 0402 C189 18pF 12KOhm 2 50V QFN64

V_3V3

2 V_3V3 2 2

R253 2 V_3V3

2 2

0 R252 R251

0 0

10KOhm 4

10KOhm 4 10KOhm 4 0 U14 DNI 0 0 DNI DNI DNI Atmel AT24HC02

1 R171

V_1V8 1 1 1 0Ohm C188 I2C_GP_CK_3V3 1 2 6 8 100nF 0402 SCL VCC I2C_GP_DAT_3V3 2 5 16V 2 1 0402 SDA R172

2 1 0Ohm C187 DNI R37 2 100nF U17 7 EEP_WP 0 WP 4.7KOhm 4 16V TI SN74LVC1T45 0 2 USBHUB_ID_A0 1 DNI A0 2 1 1 6 USBHUB_ID_A1 VCCA VCCB A1 USBHUB_ID_A2 3 4 2 RESET_OUT# 3 4 HUB_RESET# A2 GND 1 MOD A B C126 5 2 R256 2 2

2 DIR GND 2 100nF 4 10KOhm DNI 25V 2 0 R255 2 SOIC8

2 2 DNI 0 R250 R254 DNI

0 0

10KOhm 1

10KOhm 4 10KOhm 4 SC70-6 0 DNI DNI 0 DNI 0

SMARC Design Guide 2.0 Page 70 of 119 Mar 23, 2017 ©SGeT e.V.

Figure 46 USB Hub (2 of 2)

J4 TE 5787617-1 FB8 TDK ACM2012-900-2P-T002 USBHUB2_VBUS_A0 A1 USBHUB2_DN_TYPEA0_N 2 3 VCCA USBHUB2_DN_TYPEA0_CONN_N A2 USBA_N USBHUB2_DN_TYPEA0_P USBHUB2_DN_TYPEA0_CONN_P A3 USBA_P 1 4 A4 GNDA 190mOhm

FB9 TDK ACM2012-900-2P-T002 USBHUB3_VBUS_A1 B1 USBHUB3_DN_TYPEA1_N 2 3 VCCB USBHUB3_DN_TYPEA1_CONN_N B2 USBB_N USBHUB3_DN_TYPEA1_P USBHUB3_DN_TYPEA1_CONN_P B3 USBB_P 1 4 B4 GNDB

190mOhm

3 1 4 2

S S S S D2 D3

2PORT

4 1 2

TI TPD2E009 TI TPD2E009 3

S S S THT S

2 1 2 1 Dual Stacked, Type A USB, R/A, TH

SOT23 3 SOT23 3

V_5V0 V_3V3

L12 1 2 USBHUB3_VBUS_A1

1.7A 2 2 50mOhm

C1331 1 1 2 R44 2 R43 1050-8120 C134 C205

100nF 4.7KOhm 4.7KOhm 100nF 47uF 040 25V 040 16V

2 25V 2 2

1 1

U19 TI TPS2052B

USBHUB3_VBUS_A1_FB 2 IN OUT1 7 L11 USBHUB3_PRTPWR_TYPEA1 USBHUB2_VBUS_A0_FB 1 2 USBHUB2_VBUS_A0 3 EN1 OUT2 6 USBHUB2_PRTPWR_TYPEA0 4 EN2 1.7A 50mOhm 1 OCS_3 1050-8120 1 OC1# 8 C135 C206 1 5 OCS_2 100nF 47uF GND OC2# 16V 25V 2 2

SO8

SMARC Design Guide 2.0 Page 71 of 119 Mar 23, 2017 ©SGeT e.V.

5.2 GBE

5.2.1 GBE Carrier Connector Implementation Example

SMARC Modules include GBE MAC / PHYs but do not include the isolation magnetics. If the SMARC GBE is used, then the Carrier must include GBE compatible magnetics with 1:1 turn ratios. Usually RJ45 jacks with integrated magnetics are used. An example is given in the following figure.

Figure 47 GBE without POE

There are two kinds of 1000Base-T Line Driver implementations. The current mode line drivers pull current from one side of the magnetic. To generate the IEEE-specified five level pulse amplitude modulated (PAM) signals two 50 Ohm termination resistors to center tap voltage are required. They are placed in parallel to the output impedance at line driver side. The magnetic center taps are connected to each other and to the center tap reference voltage. This voltage can be provided by the GBE PHY to the magnetic with the GBE_CTREF pins at the SMARC Module.

Voltage mode line driver use series resistors to generate the PAM signal at the magnetic. They are more power efficient, but even more complex. The line driver enables the internal series resistors at the transmit signal pairs.

SMARC Design Guide 2.0 Page 72 of 119 Mar 23, 2017 ©SGeT e.V.

For most voltage mode PHYs the center taps at the magnetic can be connected to each other and clamped by separate or combined capacitors. They are not connected to any center tap voltage provided by the PHY. There are some voltage mode PHYs available, that do not allow to combine the center taps, due to different voltage levels at RX and TX pairs. This PHYs do not provide the usage of RJ45 connectors with integrated magnetics.

See SMARC Module documentation for selected GBE PHY and line driver version.

Figure 48 GBE separate magnetic for current and voltage mode line driver

SMARC Design Guide 2.0 Page 73 of 119 Mar 23, 2017 ©SGeT e.V.

5.2.2 GBE Mag-Jack Connector Recommendations

SMARC GBE Mag-Jack (magnetics integrated into an RJ45 jack housing) should meet the following general characteristics:

 The turn ratios should be 1:1  An integrated common mode choke should be included  Termination resistors on the primary side (i.e. the Ethernet cable side) should be included  The secondary side transformer center-taps may be tied together or may be brought out separately. If they are brought out separately, they are tied together on the Carrier PCB.  The secondary side center-taps need to be tied to the SMARC GBE_CTREF voltage, with bypass capacitors connected to GND.

Mag-Jacks (and RJ45 jacks in general) are available in tab-up and tab-down configurations. The pin order on the Mag-Jack reverses between the tab-up and tab-down configurations. One of them may work better for your layout than the other (although since only four pairs are involved, this may not be a major concern). Tab-up is generally more common; tab-down parts do exist; most tab-down parts target low- profile needs in which part of the Mag-Jack connector height is hidden by a Carrier PCB cutout.

Table 7 Recommended Gigabit Ethernet Connectors with Magnetics

Manufac Manufacturer Description turer P/N Bel Fuse L829-1J1T-43 Tab Up, 1:1 turns ratio, 3 LEDs, 0.950” depth Pulse JK0-0136NL Tab Up, 1:1 turns ratio, 3 LEDs, 1.30” depth Tyco 1840437-1 Tab Down, 1:1 turns ratio, 3 LEDs, special low profile feature Wurth 7499111447 Tab Up, 1:1 turns ratio, 4 LED

Note that POE (Power Over Ethernet) capable jacks are slightly different – they have extra pins to bring the POE power into the system. A GBE POE jack may be used in a non-POE system, but not the other way around. A GBE POE example is given later in this Design Guide.

SMARC Design Guide 2.0 Page 74 of 119 Mar 23, 2017 ©SGeT e.V.

5.2.3 GBE LEDs

Mag-Jack LED implementations vary widely. There does not seem to be any common standard, so be aware.

The SMARC GBE status LED outputs are open drain outputs that are capable of sinking a minimum of 24 mA. They may be connected directly to the cathode of GBE status LEDs as shown in the following figure. Make sure the resistors can handle the expected power dissipation.

Figure 49 GBE LED Current Sink

MAG JACK Bel Fuse L829-1J1T-43 or similar

V_3V3

YEL Direct from 68 OHM SMARC Module GBE_ACT#

V_3V3

ORG GRN GBE_LINK_100# 68 OHM Direct from SMARC Module

GBE_LINK_1000# 68 OHM

SMARC Design Guide 2.0 Page 75 of 119 Mar 23, 2017 ©SGeT e.V.

Some integrated GBE Mag Jacks have a pair of opposing (cathode to anode) diodes, as shown in the figure below. In this case, Carrier board buffers are recommended, as the SMARC Module status LED lines can sink current but cannot source it.

Figure 50 GBE LED Current Sink / Source

MAG JACK Bel Fuse 0826-1X1T-GH-F or similar V_3V3

Direct from SMARC Module YEL GBE_ACT# 68 OHM

V_3V3

GBE_LINK_100# 68 OHM Fairchild NC7SZ125

V_3V3 GRN ORG

GBE_LINK_1000# Fairchild NC7SZ125

SMARC Design Guide 2.0 Page 76 of 119 Mar 23, 2017 ©SGeT e.V.

5.2.4 GBE software-defined Pins

The Precision Time Protocol (PTP) (according to IEEE 1588) is used to synchronize clocks throughout a computer network. If it is implemented in the hardware of the Ethernet controller clock accuracy in the sub-microsecond range can be achieved.

The Ethernet controller usually has several GPIO pins whereof one can be connected to the GBE_SDP pin. This pin can be used as output and distribute synchronized clocks or trigger impulses. When used as input it can synchronize the internal clock of the controller to external clocks for example from GPS receivers. Such a system could serve as a master clock.

These functions depend highly on the used Ethernet controller and wiring – check with your Module vendor.

5.3 PCIe

5.3.1 General

PCI Express (or PCIe) is a scalable, point-to-point serial bus interface commonly used for high speed data exchange between a PCIe host, or root, and a target device. It is scalable in the sense that there may be link widths, per the PCIe specification, that are x1, x2, x4, x8, x16 or x32. SMARC currently calls out x1, x2 and x4 operation. Up to four PCIe x1 links may be implemented on a SMARC Module. There are three generations of PCIe defined, with each successive generation offering a speed increase, per the table below. The PCIe generation that may be supported on a particular SMARC Module is design and SOC dependent.

Table 8 PCIe Data Transfer Rates PCIe Link Speed Encoding / Net Data Transfer Generation (x1 link) Overhead Rate 1 2.5 GT/s 8b/10b 20% 250 MB/s 2 5.0 GT/s 8b/10b 20% 500 MB/s 3 8.0 GT/s 128b / 130b 1.54% 985 MB/s

PCI Express is defined in a series of documents maintained by the PCI Special Interest Group (www.pcisig.org). The three most important documents to obtain are the Base Specification, the Card Electromechanical (CEM) Specification (which describes slot cards) and the Mini Card Electromechanical Specification (which describes the small format cards commonly referred to as Mini-PCIe cards).

The four possible PCIe links on a SMARC Module are designated with net name prefixes PCIE_A_, PCIE_B_, PCIE_C_ and PCIE_D_. Each of the four has the following signal set (x in the table below designates A, B, C or D).

Table 9 SMARC PCIe Signal Summary

Signal Description Signal Type Notes PCIE_x_TX+ Data out of Module Differential pair Capacitively coupled – on PCIE_x_TX- Module PCIE_x_RX+ Data into Module Differential pair Capacitively coupled – off PCIE_x_RX- Module PCIE_x_REFCK+ Reference clock out of Differential pair No caps needed PCIE_x_REFCK- Module PCIE_x_RST# Active low output to reset the Single ended PCIE_x device

SMARC Design Guide 2.0 Page 77 of 119 Mar 23, 2017 ©SGeT e.V.

5.3.2 PCIe x1 Device Down on Carrier

An example of a PCIe x1 “device down” on the Carrier is shown below. Coupling caps on the SMARC PCIe TX and PCIe reference clock pairs are not needed on the Carrier. Coupling caps on the SMARC PCIe RX pair (TX pair from the Carrier PCIe device) are needed. They should be placed close to the Carrier device PCIe TX pins. Use 0402 package 0.2 uF X7R or X5R dielectric discrete ceramic capacitors. Do not use a capacitor array. Place the parts in a way to preserve the symmetry of the differential pair. Usually they are placed close to the Carrier device TX pins to avoid a via transition.

Figure 51 Interfacing a PCIe x1 Carrier Board Device

PCIE_TX+ PCIE_RX+ PCIE_TX- PCIE_RX-

PCIE_RX+ PCIE_TX+ PCIE_RX- PCIE_TX-

PCIE_REFCK+ PCIE_REFCK+

PCIE_REFCK- PCIE_REFCK- PCIedevice

SMARC MODULE PCIE_RST# PCIE_RST#

SMARC Design Guide 2.0 Page 78 of 119 Mar 23, 2017 ©SGeT e.V.

5.3.3 Mini-PCIe

A SMARC Mini-PCIe implementation example is shown below. Mini-PCIe cards are defined to have pins for PCIe x1 and also a USB interface. A given card generally uses only one or the other. If you know exactly what Mini-PCIe card you plan to use, it is possible to omit either USB or PCIe. Generally, Mini- PCIe 802.11 WiFi cards use the PCIe interface and cellular modem cards use the USB interface.

Figure 52 Mini-PCIe Slot

V_3V3

1 C236 1 C17 1 C16 1 C15 22uF 100nF 100nF 100nF 6.3V 25V 25V 25V 2 2 2 2

V_1V5 J20 Molex 67910-0002 1 1 1 1 C235 1 C234 C12 C13 C14 PCIE_WAKE# 1 2 100nF 100nF 100nF MOD WAKE# 3.3V_AUX_2 22uF 22uF 3 4 6.3V 6.3V 25V 25V 25V COEX1 GND4 2 2 2 2 2 5 6 R95 COEX2 1.5V_6 DNI PCIE_A_CKREQ# 7 8 V_SIM_PWR 0402 CLKREQ# UIM_PWR 2 1 9 10 SIM_DATA 0Ohm GND9 UIM_DATA PCIE_A_REFCK_N 11 12 SIM_CLK MOD REFCLK- UIM_CLK PCIE_A_REFCK_P 13 14 SIM_RST MOD REFCLK+ UIM_RST 15 16 V_SIM_VPP GND15 UIM_VPP 17 18 RSVD17 GND18 V_3V3 19 20 RSVD19 W_DISABLE# R2 21 22 PCIE_A_RST# 2 1 GND21 PERST# 0402 PCIE_A_RX_N 23 24 MOD PERN0 3.3V_AUX_24 4.7KOhm PCIE_A_RX_P 25 26 DNI MOD PERP0 GND26 MOD 27 28 GND27 1.5V_28 29 30 GND29 SMB_CLK I 2C_PM_CK_3V3 PCIE_A_TX_N 31 32 MOD PETN0 SMB_DATA I 2C_PM_DAT_3V3 Level translated I2C_PM bus PCIE_A_TX_P 33 34 MOD PETP0 GND34 35 36 USBHUB5_DN_MPCIe1_N V_3V3 GND35 USB_D- 37 38 USBHUB5_DN_MPCIe1_P GND37 USB_D+ From USB Hub 39 40 3.3V_AUX_39 GND40 41 42 3.3V_AUX_41 LED_WWAN# 43 44 C18 1 C19 1 C233 1 C232 1 GND43 LED_WLAN# 100nF 100nF 22uF 22uF 45 46 RSVD45 LED_WPAN# 25V 25V 6.3V 6.3V 47 48 2 2 2 2 RSVD47 1.5V_48 49 50 RSVD49 GND50 51 52 RSVD51 3.3V_AUX_52 S1 S2 S1 S2

52/1/2x26/0.80 RA Mini-PCIe, R/A, SMT

Full Mini card Latch Half Mini card Latch

J22 J23 Mini_PCIE_latch Mini_PCIE_latch S1 S2 S1 S2 S1 S2 S1 S2 DNI S3 S4 S3 S4 S3 S4 S3 S4

ST ST

SIM Card Holder, ST, SMT J19 Molex 47023-0001

V_SIM_PWR 1 4 VCC GND SIM_RST 2 5 V_SIM_VPP C238 1 1 C21 RESET VPP 10uF 100nF SIM_CLK 3 6 SIM_DATA CLK IO 1 1 C237 25V 25V C20 2 2 100nF 10uF 25V 6/2x3/2.54 25V 2 2 ST

SMARC Design Guide 2.0 Page 79 of 119 Mar 23, 2017 ©SGeT e.V.

5.3.4 PCIe Reference Clock buffer

The SMARC 2.0 Specification calls for three copies of the PCIe reference clock pairs to be brought out of the Module. This clock is a 100MHz differential pair and is sometimes known as a "hint" clock. The clock allows the PLL in the target PCIe device to lock faster onto the embedded clock in the PCIe bit stream. If the Carrier Board implements only three PCIe devices or slots, then the PCIe reference clock pairs from the Module may be routed directly to that devices or slots. However, if there are four PCIe devices or slots on the Carrier Board, then one of the Module's PCIe reference clock should be buffered. A device which meets the jitter requirements for the intended PCI Express generation must be used. The IDT9DB233, IDT9DB433, IDT9DB844 have two, four and eight differential output replicas of the input clock, respectively. Each target device (PCIe "device down" chip, slot, Express Card slot, Mini-PCIe device, M.2 device, PEG slot) should get an individual copy of the reference clock. Similar parts may be available from other vendors. The PCIe Clock buffers have both PLL and bypass modes. In some situations it is preferable to operate the clock buffer in bypass mode. The reference clock pairs should be routed as directly as possible from source to destination.

The following notes apply to Figure 53 PCIe Clock buffer. Each clock pair is routed point to point to each connector or end device using differential signal routing rules.

Each clock output pair in the example shown is terminated close to the IDT9DB433 buffer pins with a series resistor (shown as 33 ohms) and a termination to GND (shown as 49.9 ohms), per the vendor's recommendations. Other vendors may have different recommendations, particularly in regard to the source termination to GND. SMBUS software can enable or disable clock-buffer outputs. So the SMBUS pins of the clock buffer should be connected to the I2C_PM pins of the SMARC Module. Configuration resistors or alternatively the SMBUS also allow software to put the clock buffer into "Bypass Mode", which experience has shown is needed in some Carrier situations. Disable unused outputs to reduce emissions. The CLKREQ0# and CLKREQ1# should be pulled low to enable the corresponding clock buffer outputs. For applications in which power management is not a concern, these inputs may be tied low to permanently enable the outputs.

SMBCLK and SMBDAT need to be connected to a 3.3V I2C bus as described in chapter 4.2.2. Figure 53 PCIe Clock buffer

V_3V3 V_3V3

FB1 FB3

120-Ohms@100MHz 120-Ohms@100MHz C1 C2 C6 C7 10uF 100n 10n 10uF

V_3V3 U1 FB2 IDT9DB433 1 28 VDDR VDDA 120-Ohms@100MHz 5 6 R9 33 C3 C4 C5 PCIE_CLK_1+ 11 VDD DIF_1 7 R10 33 10uF 100n 10n PCIE_CLK_1- 16 VDD DIF_1# 18 VDD DIFFERENTIAL 9 24 VDD CLOCK BUFFER DIF_2 10 VDD DIF_2# 2 20 PCIE_A_REFCK_P MOD 3 SRC_IN DIF_5 19 PCIE_A_REFCK_N MOD SRC_IN# DIF_5# 13 23 R11 33 I2C_PM_SCL_3V3 PCIE_CLK_6+ 14 SMBCLK DIF_6 22 R12 33 I2C_PM_DAT_3V3 PCIE_CLK_6- 17 SMBDAT DIF_6# V_3V3 V_3V3 V_3V3 SMB_ADR_TRI 8 OE1# R14 R15 R16 R17 21 26 R1 R2 R3 OE6# IREF 49.9 49.9 49.9 49.9 47K 47K 47K 12 BYP#_HIBW_LOBW R13 475 PCIE_CLK_REQ1# PCIE_CLK_REQ6# 27 GNDA 25 4 PD# GND 15 GND

V_3V3 V_3V3

R5 R7 SMBus Addres selection PLL Operating mode selection 10K 10K Assembled part Address OPEN Assembled part Mode R6 DA/DB R8 Bypass R5 + R6 DC/DD R6 R8 R7 + R8 PLL 100M Hi BW R5 D8/D9 R7 PLL 100M Lo BW 10K 10K OPEN

SMARC Design Guide 2.0 Page 80 of 119 Mar 23, 2017 ©SGeT e.V.

5.4 SATA

5.4.1 General

Serial ATA (or SATA) is a high speed point to point serial interface that connects a host system to a mass storage device such as rotating hard drive, solid state drive or an optical drive. Data and clock are serialized onto a single outbound differential pair and a single inbound pair. Data link rates of 1.5, 3.0 and 6.0 Gbps are defined by the SATA specification. A SATA link is AC coupled, but the coupling capacitors are defined in the SMARC specification to be on the Module, for both SATA transmit and receive pairs.

Table 10 SATA SSD Form Factors Format Notes IC (chip level) Smallest form factor. Densities to 64GB. mSATA Small form factor SATA module, defined in the SATA specification (search for “mSATA” MO-300 in the specification). SLC and MLC versions are generally available. The mSATA form factor is roughly 30mm x 51mm x 3.5mm (see the specification for exact dimensions). Slim SATA Small form factor solid-state SATA modules that use a standard SATA connector (7 pin MO-297 data / GND section and 15 pin power section). The connector is compatible with the connector used on larger format (2.5”) hard drives used in PC systems. Available in SLC and MLC versions. Form factor is defined by JEDEC MO-297. CFast Removable card format with SSD interface; similar to popular Compact Flash (parallel interface) cards. Form factor is roughly 36mmx 43mm x 3.6mm. SSD 1.8” Solid State Disk in traditional 1.8” format that was originally used for rotating drives SSD 2.5” Solid State Disk in traditional 2.5” format that was originally used for rotating drives

Table 11 SATA SSD Vendors Vendor Link SATA Products Greenliant www.greenliant.com Chip-level SLC and MLC NAND flash with SATA interface. Innodisk www.innodisk.com mSATA / MO-300 Slim SATA / MO-297 CFast SSD 2.5” Intel www.intel.com mSATA / MO-300 SSD 1.8” SSD 2.5” SMART Modular www.smartm.com mSATA / MO-300 Slim SATA / MO-297 SSD 1.8” SSD 2.5” Swissbit www.swissbit.com mSATA / MO-300 Slim SATA / MO-297 CFast SSD 1.8” SSD 2.5” Transcend www.transcend-info.com mSATA / MO-300 Slim SATA / MO-297 SSD 1.8” SSD 2.5” Virtium www.virtium.com mSATA / MO-300 Slim SATA / MO-297 SSD 1.8” SSD 2.5”

SMARC Design Guide 2.0 Page 81 of 119 Mar 23, 2017 ©SGeT e.V.

5.4.2 mSATA / MO-300

A popular SATA form factor for SMARC systems is the mSATA / JEDEC MO-300. This is physically the same as a mini-PCIe card, and uses the same Carrier socket, but the mini-PCIe pinout is re-purposed for SATA use. A schematic example is shown below. The pin names within the J21 connector box outline below are the mini-PCIe pin names. The net connections outside the box show the appropriate connections for mSATA / MO-300 SATA use. Coupling capacitors are not needed on the Carrier SATA TX and RX pairs. mSATA / MO-300 SATA is described in the Serial ATA Revision 3.1 specification document – search for “mSATA”.

Figure 54 mSATA / MO-300

V_3V3

C24 1 C23 1 C29 1 C28 1 C27 1 100nF 100nF 100nF 100nF 100nF 25V 25V 25V 25V 25V 2 2 2 2 2 J21 Molex 67910-0002

1 2 WAKE# 3.3V_AUX_2 V_1V5 3 4 COEX1 GND4 5 6 COEX2 1.5V_6 7 8 CLKREQ# UIM_PWR 9 10 GND9 UIM_DATA 1 1 1 11 12 C22 C26 C25 REFCLK- UIM_CLK 100nF 100nF 100nF 13 14 25V 25V 25V REFCLK+ UIM_RST 2 2 2 15 16 GND15 UIM_VPP 17 18 RSVD17 GND18 19 20 RSVD19 W_DISABLE# 21 22 GND21 PERST# SATA_RX_P 23 24 MOD PERN0 3.3V_AUX_24 SATA_RX_N 25 26 MOD PERP0 GND26 27 28 GND27 1.5V_28 V_3V3 29 30 GND29 SMB_CLK SATA_TX_N 31 32 MOD PETN0 SMB_DATA SATA_TX_P 33 34 MOD PETP0 GND34 35

2 36 GND35 USB_D-

m 37 38

6 h

2 GND37 USB_D+ O

26 39 40 R

040 3.3V_AUX_39 GND40

100 41 42 3.3V_AUX_41 LED_WWAN# 1 43 44 GND43 LED_WLAN# 45 46 RSVD45 LED_WPAN# 47 2 48 RSVD47 1.5V_48 49 50 RSVD49 GND50 SATA_PRSNT_DET 51 52 TP1 RSVD51 3.3V_AUX_52 S1 S2 D9 TP_SMD_35 S1 S2 LTST-C190KGKT 52/1/2x26/0.80 RA

1 Mini-PCIe, R/A, SMT SATA_ACT# MOD

J24 Mini_PCIE_latch S1 S2 S1 S2 S3 S4 S3 S4 ST 2/2x1/24.2 According to the mSATA specification SATA_RX_P (positive signal) has to be connected to Pin 23 of the Mini-PCIe socket although this is used as a negative signal with PCIe. The same applies to SATA_RX_N and Pin 25 vice versa. Nevertheless SATA_TX_N and SATA_TX_P use the right polarity of the socket (Pin 31 and 33).

5.5 M.2 The M.2 form factor is a specification for mobile expansion cards and is supposed to replace the Mini PCIe cards and mSATA cards. The M.2 is a smaller form factor in both size and volume. It is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution. PCIe, SATA, USB 3.0 and SDIO are provided through the M.2 connector. It is up to the manufacturer of the M.2 host or device to select which interfaces are to be supported. The M.2 connector has different

SMARC Design Guide 2.0 Page 82 of 119 Mar 23, 2017 ©SGeT e.V.

keying notches that denote various purposes and capabilities of M.2 hosts and modules, preventing plugging of M.2 modules into feature-incompatible host connectors.

M.2 cards are available in various physical sizes, starting from 2230 wireless cards, up to 22110 SSDs. Carrier Board designers must provide a stand-off for each physical card size they would like to support.

The module stand-off should be directly connected to Carrier board’s GND, as it is part of the M.2 Electrical and Thermal Ground Path.

5.5.1 B keying M.2 Key B sockets support a wide range of add on cards, like SSDs, GPS and WiFi devices. Some high-speed interfaces like SATA and PCIe share the same pins at the M.2 Key B connector. The desired interface configuration can be decoded by CONFIG_[0-3] which are either tied to GND or left floating by the M.2 card.

At the time of writing, a majority of medium-speed (SATA) SSDs implement dual-keying which allows to plug them into Key B and Key M sockets. High-End SSDs often come in a Key-M only format, as they rely on a PCIe x4 link.

Figure 55 M.2 Key B

M.2 Socket 2: Key B V_3V3 FB15 TDK ACM2012-900-2P-T002 MOD USB4+ 4 3 X1 C165 C164 C163 C162 C161 C160 USB4+_M2 7 2 10nF 10nF 100nF 100nF 10uF 10uF USB4-_M2 USB_D+ M.2 Slot B VCC_3p3 MOD USB4- 1 2 9 4 16V 16V 16V 16V 10V 10V USB_D- Platform Pinout VCC_3p3 70 VCC_3p3 72 PCIE_A_REFCK+ VCC_3p3 MOD 55 74 PCIE_A_REFCK- 53 REFCLKp VCC_3p3 MOD REFCLKn

PCIE_A_TX+/SATA_TX+ 49 64 PCIE_A_TX-/SATA_TX- 47 PETp0/SATA_A+ COEX1_1p8 62 PETn0/SATA_A- COEX2_1p8 60 PCIE_A_RX+/SATA_RX- 43 COEX3_1p8 X2 PCIE_A_RX-/SATA_RX+ 41 PERp0/SATA_B- M2_UIM_PWR C1 PERn0/SATA_B+ 59 VCC ANTCTL0_1p8 61 C166 M2_UIM_RST C2 PCIE_B_TX+/USB2_SSTX+ 37 ANTCTL1_1p8 63 100nF RESET PCIE_B_TX-/USB2_SSTX- 35 PETp1/USB30_TX+/SSIC_TX+ ANTCTL2_1p8 65 M2_UIM_CLK C3 PETn1/USB30_TX-/SSIC_TX- ANTCTL3_1p8 CLK PCIE_B_RX+/USB2_SSRX+ 31 M2_UIM_DAT C7 PCIE_B_RX-/USB2_SSRX- 29 PERp1/USB30_RX+/SSIC_RX+ 36 M2_UIM_PWR I/O SH1 PERn1/USB30_RX-/SSIC_RX- UIM_PWR M2_UIM_DAT UIM_VPP SH1 34 0402 C6 SH2 UIM_DATA 32 M2_UIM_CLK VPP SH2 SH3 PCIE_WAKE# UIM_CLK M2_UIM_RST SH3 MOD 54 30 R185 C5 SH4 52 PEWAKE#_3p3 UIM_RESET 0Ohm GND SH4 PCIE_A_RST# 50 CLKREQ#_3p3 66 Molex 788000001 MOD PERST#_3p3 SIM_DETECT_1p8

RESET_OUT# 67 25 V_3V3 MOD RESET#_1p8 DPR_1p8

I2C_GP_CK R186 0Ohm I2C_CLK_M2 40 21 M2_CONFIG0 MOD 0402 0 I2C_GP_DAT R187 0Ohm I2C_DAT_M2 42 GPIO0_(GNSS_SCL/SIM_DET2)_1p8 CONFIG_0 69 M2_CONFIG1 R181 4 MOD 0402 0 DNI I2C_ALERT#_M2 GPIO1_(GNSS_SDA/UIM_DAT2)_1p8 CONFIG_1 M2_CONFIG2 2 MOD GPIO8 R162 0402 0Ohm 44 75 10kOhm 46 GPIO2_(GNSS_IRQ/UIM_CLK2)_1p8 CONFIG_2 1 M2_CONFIG3 48 GPIO3_(SYSCLK/GNSS_0/UIM_RST2)_1p8 CONFIG_3 I2S2_CK DNI M2_I2S_CK GPIO4_(TX_BLK/GNSS_1/UIM_PWR2)_1p8 MOD R188 0402 0Ohm 20 I2S2_SDI DNI M2_I2S_SDI GPIO5_(AUDIO0/RFU)_1p8 SATA_SEL MOD R189 0402 22Ohm 22 56 I2S2_SDO DNI M2_I2S_SDO GPIO6_(AUDIO1/RFU)_1p8 MFG_DAT MOD R190 0402 0Ohm 24 58 I2S2_LRCK DNI M2_I2S_LRCK GPIO7_(AUDIO2/RFU)_1p8 MFG_CLK MOD R191 0402 0Ohm 28 10 GPIO8_(AUDIO3/RFU)_1p8 76 V_3V3 V_3V3 V_3V3 V_3V3 V_1V8 26 GPIO9_(LED1#/DAS_DSS#)_3p3 H1 77 GPIO10_(W_DISABLE_2#)_1p8 H2 R192 0402 10kOhm 23 GPIO11_(WoWWAN#)_1p8 3

4 GND 5 R178 R175 R180 R179 4

2 GND 2 V_3V3 8 11 10kOhm 10kOhm 10kOhm 10kOhm

6 W_DISABLE_1#_3p3 GND 27 3 M2_PWROFF# GND R169 0402 10kOhm 6 33 FULL_CARD_PWROFF#_1p8/3p3 GND 39 M2_DEVSLP GND M2_CONFIG0 M2_CONFIG1 M2_CONFIG2 M2_CONFIG3 R184 0402 0Ohm 38 45 2 5 2 5 DEVSLP_3p3 GND 51 68 GND 57 T1A T1B T2A T2B

1 SUSCLK_3p3 GND 71 Diodes BSS138DW-7-F Diodes BSS138DW-7-F Diodes BSS138DW-7-F Diodes BSS138DW-7-F 4 GND 73 GND TE Connectivity 2199230-5 connector height: 4.2mm M2 V_3V3 V_3V3

STANDOFF M3x0.5 Tapped C174

2.45mm Shoulder Height 4 R182 100nF

0 SMT 2 10kOhm 16V 1 U3 V_3V3 V_3V3 M2_CONFIG0 1 5 M2_CONFIG3# 2 3 4 M2_SSIC

6 C171 C170 C169 C172 C168 C167 Fairchild NC7SZ08 100nF 100nF 100nF 100nF 100nF 100nF 16V 16V 16V 16V 16V 16V M2_CONFIG3 2

T3A

0 0 Diodes BSS138DW-7-F

1 6 1

1 6 U1 1 U2

D D D

V V V

V V V V_3V3 V_3V3 PCIE_A_TX+ PCIE_A_TX+/SATA_TX+ PCIE_B_TX+ PCIE_B_TX+/USB2_SSTX+ MOD 19 3 MOD 19 3 PCIE_A_TX- B0_P A0_P PCIE_A_TX-/SATA_TX- PCIE_B_TX- B0_P A0_P PCIE_B_TX-/USB2_SSTX- MOD 18 4 MOD 18 4 B0_N A0_N B0_N A0_N C173

PCIE_A_RX+ 17 7 PCIE_A_RX+/SATA_RX- PCIE_B_RX+ 17 7 PCIE_B_RX+/USB2_SSRX+ 4 R183 100nF MOD MOD 0 PCIE_A_RX- B1_P A1_P PCIE_A_RX-/SATA_RX+ PCIE_B_RX- B1_P A1_P PCIE_B_RX-/USB2_SSRX- 2 MOD 16 8 MOD 16 8 10kOhm 16V B1_N A1_N B1_N A1_N U4 SATA_TX+ USB2_SSTX+ M2_CONFIG3 MOD 15 MOD 15 1 5 SATA_TX- C0_P USB2_SSTX- C0_P M2_CONFIG0# MOD 14 MOD 14 2 C0_N C0_N 3 4 M2_USB3 SATA_RX- USB2_SSRX+ 3 MOD 13 MOD 13 SATA_RX+ C1_P USB2_SSRX- C1_P MOD 12 MOD 12 Fairchild NC7SZ08 C1_N 2 C1_N 2 M2_SSIC XSD XSD M2_CONFIG0 5 9 SATA_SEL 9 M2_USB3 SEL SEL

D D T3B

D D D

N N N

P P Diodes BSS138DW-7-F

H G G G

H G G G NXP CBTL02043A NXP CBTL02043A

1 0 1 5

2 2 1

SMARC Design Guide 2.0 Page 83 of 119 Mar 23, 2017 ©SGeT e.V.

5.5.2 M keying M.2 Key M is intended for use with SSD Cards. The connection can either be done by PCIe x4 or a single SATA lane. In this example schematic both PCIe and SATA is connected to the M.2 socket according to the M.2 specification. The M.2 SSD decides with configuration pins, which interface should be used for this regarding SSD. It is recommended to check with your SMARC Module vendor if PCIe x4 is supported by the used SMARC Module, if PCIe x4 SSD will be connected. Other PCIe devices could only be used if a PCIe bridge is implemented on the Carrier board. Both used interfaces by the M.2 SSD and the SMARC Module must match.

Figure 56 M.2 Key M

V_1V5

Mounting holes for M.2

U27 5 38 PCIE_A_RX_P VDD_5 B0+ MOD 8 37 PCIE_A_RX_N DR8 DR9 VDD_8 B0-

R MOD

7 7 13 36 PCIE_A_TX_C_P C100NS02V50_X7R PCIE_A_TX_P

X X VDD_13 B1+ MOD 0R R179 0R R180

_ _ C365 100n

0 6 18 35 PCIE_A_TX_C_N C100NS02V50_X7R PCIE_A_TX_N R1%0R0S02 R1%0R0S02

5 VDD_18 B1-

1 MOD

7 C366 100n

8 20

3 VDD_20

0 C

S 30 34 SATA_RX_C_N C10NS02 SATA_RX_N VDD_30 C0+ n MOD

0 C367 10n

0 u 40 33 SATA_RX_C_P C10NS02 SATA_RX_P

1 0 VDD_40 C0- MOD

1 C 42 32 SATA_TX_C_P C10NS02 C368 10n SATA_TX_P C VDD_42 C1+ MOD 31 SATA_TX_C_N C369 10n C10NS02 SATA_TX_N C1- MOD C370 10n DR10 DR11 SATA_SW_PCIE_RX_P 2 29 7 A0+ B2+ 0R R181 0R R182 SATA_SW_PCIE_RX_N 3 28 7 A0- B2- R1%0R0S02 R1%0R0S02 SATA_SW_PCIE_TX_P 6 27 7 A1+ B3+ SATA_SW_PCIE_TX_N 7 26 7 A1- B3-

11 25 A2+ C2+ 12 24 A2- C2- 15 23 A3+ C3+ 16 22 A3- C3-

EN_M2_SATA_PCIE# 9 1 7 SEL GND_1 4 GND_4 21 10 GND_21 GND_10 39 14 GND_39 GND_14 41 17 GND_41 GND_17 43 19 HIGH : SATA TH_PAD GND_19 V_3V3 UPI3PCIE3412 LOW : PCIE V_3V3_M2

0R R498 1 A R1%0R0S02

R R

7 7

X X

_ _

0 0

6 6

5 5

1 1

1 2 6 5

V V

1 1 0 0

2 2

5 5

4 4 4 4

0 0

C C C C

S S

N N

U U

0 0

u u

n n

0 0

1 1

0 0

1 1

C C

0 0

C C

1 1

V_3V3_M2

J34 V_3V3_M2 74 75 M2_CONFIG_2 3V3_74 GND_75 72 73 C10NS02 3V3_72 GND_73 70 71 C394 10n 3V3_70 GND_71 V_3V3_M2

2 2

0 0 68 69 M2_CONFIG_1

S S SUSCLK PEDET 0 0 66 67 K K CONNECTOR_KEY_66 NC_67

0 0

1 1 64 65 4 3 CONNECTOR_KEY_64 CONNECTOR_KEY_65

5 % 5 %

4 1 4 1 62 63

R R R R CONNECTOR_KEY_62 CONNECTOR_KEY_63 60 61 CONNECTOR_KEY_60 CONNECTOR_KEY_61 2 2 2 2

0 0 0 0

58 59 S S S S

NC_58 CONNECTOR_KEY_59 0 0 0 0

56 57 K K K K NC_56 GND_57 0 0 0 0

1 1 1 1 54 55 PCIE_A_REFCK_P 0 4 2 3 PEWAKE# REFCLK_P MOD 6 % 8 % 8 % 8 %

4 1 4 1 4 1 4 1

CLKREQ_M2# 52 53 PCIE_A_REFCK_N R R R R R R R R CLKREQ# REFCLK_N MOD RESET_OUT# R455 50 51 MOD PERST# GND_51 R1%0R0S02 48 49 SATA_SW_PCIE_TX_P NC_48 PET0_P/SATA_A+ 46 47 SATA_SW_PCIE_TX_N NC_46 PET0_N/SATA_A- 44 45 EN_M2_SATA_PCIE# NC_44 GND_45 7 42 43 SATA_SW_PCIE_RX_P NC_42 PER0_P/SATA_B- 40 41 SATA_SW_PCIE_RX_N

NC_40 PER0_N/SATA_B+ 3 SSD_DEEP_SLEEP 38 39 M2_CONFIG_3 DEVSLP GND_39 Q63 36 37 PCIE_B_TX_P M2_CONFIG_2 NC_36 PET1_P MOD QBSS138W R456 34 35 PCIE_B_TX_N NC_34 PET1_N MOD M2_CONFIG_1 1 R1%0R0S02 32 33 UART_RXD GND_33 30 31 PCIE_B_RX_P 2 NC_30 PER1_P MOD 28 29 PCIE_B_RX_N NC_28 PER1_N MOD

7 26 27

_ NC_26 GND_27

1 24 25 PCIE_C_TX_P V NC_24 PET2_P 5 MOD

S 22 23 PCIE_C_TX_N

8 U NC_22 PET2_N MOD

3 1 20 21 C C NC_20 GND_21

18 19 PCIE_C_RX_P 3V3_18 PER2_P u MOD

0 16 17 PCIE_C_RX_N 1 3V3_16 PER2_N MOD 14 15 3V3_14 GND_15 12 13 PCIE_D_TX_P 3V3_12 PET3_P MOD 10 11 PCIE_D_TX_N- DAS/DSS#/LED1# PET3_N MOD 8 9 NC_8 GND_9 6 7 PCIE_D_RX_P NC_6 PER3_P MOD 4 5 PCIE_D_RX_N 3V3_4 PER3_N MOD 2 3 3V3_2 GND_3 1 M2_CONFIG_3 GND_1

JM2MINI_M-KEY

5.5.3 E keying M.2 Key E is intended for use with Wireless Connectivity cards, which are WiFi / Bluetooth cards in most of the cases. WiFi is utilizing either PCIe or SDIO connection to the host system. It is recommended to check with your SMARC Module vendor if SDIO could be used for WiFi devices as well.

USB or UART+I2S are used to connect the Bluetooth Interface IC to the Host system. NFC capable add- in cards may also require an I2C connection. Please be aware that the I/O voltage of I2C was changed from 3.3V to 1.8V per ECN after the official M.2 specification release.

Figure 57 M.2 Key E M.2 Socket 1: Key E

V_3V3

FB15 X11 TDK ACM2012-900-2P-T002 C165 C164 C163 C162 C161 C160 MOD USB4+ 4 3 2 10nF 10nF 100nF 100nF 10uF 10uF USB4+_M2 3 M.2 Slot 1 - SDIO Pinout VCC_3P3 4 16V 16V 16V 16V 10V 10V USB4-_M2 USB_D+ K ey E VCC_3P3 MOD USB4- 1 2 5 72 USB_D- VCC_3P3 74 VCC_3P3 DNI PCIE_B_REFCK+ I2C_ALERT#_M2 MOD 47 62 R162 0402 0Ohm GPIO8 MOD PCIE_B_REFCK- 49 PCIE_REFCLK+ ALERT#_1P8_OD 60 I2C_GP_CK MOD C MOD

PCIE_REFCLK- 2 I2C_CLK_1P8_OD

I I2C_GP_DAT 58 MOD PCIE_B_RX+ I2C_DAT_1P8_OD MOD 41 PCIE_B_RX- PCIE_RX0+ MOD 43 PCIE_RX0- 0

e 71 I RSVD/PCIE_REFCLK1+ PCIE_B_TX+ 35 C 73

MOD P PCIE_B_TX- 37 PCIE_TX0+ RSVD/PCIE_REFCLK1- M2 MOD PCIE_TX0- 1 65

e PCIE_WAKE# 55 I RSVD/PCIE_RX1+ 67 STANDOFF MOD PEWAKE0#_3P3_OD C RSVD/PCIE_RX1- 53 P M3x0.5 Tapped PCIE_B_RST# CLKREQ0#_3P3_OD 2.45mm Shoulder Height MOD 52 59 PERST0#_3P3 RSVD/PCIE_TX1+ 61 SMT RSVD/PCIE_TX1- 1 SDIO_CK_1V8 9 SDIO_CMD_1V8 11 SDIO_CLK_1P8 68 SDIO_D0_1V8 13 SDIO_CMD_1P8 UIM_PWR_SNK/CLKREQ1# 66

M SDIO_D1_1V8 15 SDIO_DAT0_1P8 I UIM_SWP/PERST1# 70 SDIO_DAT1_1P8 U IM_PWR_SRC/GPIO1/PEWAKE1# SDIO_D2_1V8 O 17 I

SDIO_D3_1V8 19 SDIO_DAT2_1P8 D

S SDIO_RST#_1V8 23 SDIO_DAT3_1P8 48 D10 V_3V3 SDIO_RESET#_1P8 COEX1_1P8 SDIO_WAKE#_1V8 21 46 DLED0603RED SDIO_WAKE#_1P8_OD COEX2_1P8 44 COEX3_1P8 50 R158 0402 220Ohm I2S2_CK 8 M SUSCLK_3P3 6 M2_LED1_WIFI MOD PCM_CLK/I2S_SCK_1P8 M LED1#_3P3_OD

I2S2_LRCK O M2_LED2_BT MOD 10 16 R159 0402 220Ohm PCM_SYNC/I2S_WS_1P8 C LED2#_3P3_OD I2S2_SDI R161 22Ohm I2S2_SDI_M2 12 S 56 D9

MOD 0402 I I2S2_SDO 14 PCM_IN/I2S_SDI_1P8 W_DISABLE1#_3P3 54 DLED0603RED MOD PCM_OUT/I2S_SDO_1P8 W_DISABLE2#_3P3

SER2_TX MOD 32 1 SER2_RX UART_TXD_1P8 GND MOD 22 7 SER2_RTS# 36 UART_RXD_1P8 GND 18 MOD UART_RTS_1P8 GND SER2_CTS# 34 T 33 MOD UART_CTS_1P8 R GND

PCIE_WAKE# UART_WAKE# A R160 0402 0Ohm 20 39 UART_WAKE#_3P3_OD U GND 45 GND 51 64 GND 57 42 RSVD GND 63 40 VENDOR_DEF3 GND 69 38 VENDOR_DEF2 GND 75 VENDOR_DEF1 GND

TE Connectivity 2199230-6 connector height: 4.2mm

V_3V3 V_1V8 V_3V3 V_1V8

C167 C166 C169 C168 100nF 100nF 100nF 100nF 16V 16V 16V 16V U1 U2

11 1 11 1 VCCB VCCA 12 VCCB VCCA 12 OE OE SDIO_D0 SDIO_D0_1V8 SDIO_CMD SDIO_CMD_1V8 MOD 10 2 MOD 10 2 SDIO_D1 B1 A1 SDIO_D1_1V8 SDIO_CK B1 A1 SDIO_CK_1V8 MOD 9 3 D11 MOD 9 3 SDIO_D2 B2 A2 SDIO_D2_1V8 PCIE_WAKE# SDIO_WAKE# B2 A2 SDIO_WAKE#_1V8 MOD 8 4 8 4 DNI SDIO_D3 B3 A3 SDIO_D3_1V8 SDIO_PWR_EN B3 A3 SDIO_PWR_EN_1V8 SDIO_RST#_1V8 MOD 7 5 MOD 7 5 R163 0402 0Ohm B4 A4 DBAT54 B4 A4

D D

N N

G G R164

NXP NTS0104GU12 NXP NTS0104GU12 0 0Ohm

6 6

RESET_OUT# MOD

6 MEMORY CARD INTERFACES

6.1 SD Card

The SD (Secure Digital) Card is a non-volatile memory card format used as mass storage memory in portable devices. The SD standard is maintained by the SD Card Association. SMARC Modules support SD cards over the SMARC SDIO interface. The interface may be used in a 4 bit or 1 bit mode. If used in 1 bit mode, the least significant bit (SDIO0) should be used. Most SMARC Modules offer a SDIO BCT boot and an SDIO OS boot. Since SD cards can (usually) be inserted and removed by the user, it is important to implement ESD protection on all the SD lines.

Figure 58 Micro SD Card Implementation

V_3V3

C 0 V_3V3_SDCARD

0 U4

6 1 2 7 IN OUT1 GND 6 NC

7 OUT2 6

0 SDIO_PWR_EN 3 0

MOD EN1 7

C 0

2 4 0

1 EN2 MTP23 4

C 0 V_3V3

2 2 8 SDCARD_OC#

0 0 OC1#

0 1 5 0

R 0 R 0 NC

6 GND OC2# 5

10k R441SDCARD_OC# 1

9 1 GND_PAD 1 1% 0402 V_3V3

TPS2066 GND

0 0 GND

GND GND GND 7

R 0

% k J11

4 SDIO_CLK 0 R44 5 4 MOD CLK V_VDD SDIO_CMD 0 1% 0402 R45 3 MOD CMD SDIO_D[0] 1% 0 R46 0402 7 S1 MOD DAT0 S1 SDIO_D[1] 0 1% 0402 R47 8 S2 MOD DAT1 S2 SDIO_D[2] 1% 0 R48 0402 1 S3 MOD DAT2 S3 SDIO_D[3] 0 1% 0402 R49 2 S4 MOD CD/DAT3 S4 1% 0402 SDIO_CD# 0 R48 9 6 MOD DETECT_SWITCH VSS 1% 0402 10 DETECT_LEVER

1 4 GND GND

R 0

GND

V_3V3 U70 5 1 V_VCC IO1

1 V_3V3 2 3

0 IO2

1 4 4 U71

C 0 IO3 2 6 V_3V3_SDCARD 1 5 GND IO4 IO1 V_VCC

V 3

IO2 0

5 SRV05-4

2 4

C 0

1 SOT23-6 0 IO3

1 4 6 2

R GND GND 0 IO4 GND

SRV05-4 5

D SOT23-6 1 GND GND

4 J9 SDIO_WP 1 MOD P1 2 P2

GND

7 CAMERA INTERFACES

7.1 General

The SMARC specification allows for up to two serial (MIPI CSI) cameras to be interfaced to the SMARC Module. The defined CSI0 interface supports up to two differential data lanes (CSI0_D[0:1]+/- signals). CSI1 may be implemented with up to four differential data lanes (CSI1_D[0:3]+/- signals) to support higher resolution cameras. The Module camera interface is at CSI voltage levels.

7.2 Camera Data Interface Formats

There are a wide variety of data formats that are used to convey camera data to a host system. A complete description of these formats is very much beyond the scope of this design guide. Briefly stated, camera data formats may be divided into two groups: “raw” and “processed”. The raw camera data formats need to be adjusted for camera and sensor specific characteristics (non-linearities, sensor pixel quirks, color corrections and so on). Using the raw format requires an additional level of software complexity that is beyond many users. Unless you have a specific need for a particular camera that outputs “raw” sensor data, it is best to stick with cameras that include a processor on the camera module that convert the camera sensor data to a standard format such as RGB or YUV, JPEG or others. The “Bayer” format is one of the numerous raw formats that you may wish to avoid. A variation on the above is that some cameras offer “raw” RGB, meaning that the pixel data is sorted into RGB elements but sensor nonlinearities are not processed in the camera IC.

7.3 Camera Sensors and Camera Module Vendors

Table 12 Camera Sensors

Vendor Link Aptina www.aptina.com OmniVision www.ovt.com Exmor

Table 13 Camera Module Vendors

Vendor Link Leopard Imaging www.leopardimaging.com KaiLap kailaptech.com Chicony www.chicony.com.tw Truly Opto www.trulyopto.com Sunny Optical Technology www.sunnyoptical.com/en/ Sharp www.sharp-world.com e-con Systems www.e-consystems.com/

7.4 Serial Camera Interface Example

The figure below illustrates a CSI implementation on a SMARC Carrier. The OV3640 is a 3.1 Mega-pixel CMOS sensor from OmniVision which supports both serial and parallel camera interfaces. Here, the

output of the sensor is connected to CSI0 interface of the SMARC Module. I2C_CAM is the control interface used for configuring the sensor. CAM_MCK is the master clock output from the SMARC Module.

Figure 59 Serial Camera Implementation

CSI0_D0_P CSI0_D0_N

CSI0_D1_P

CSI0_D1_N 1.5V 2.8V CSI0_CK_P 1.8V CSI0_CK_N

E MIPI CSI MIPI (2 Lanes)

6 O

CAM_MCK XVCLK 3

C I2C_CAM_DAT SDA R

A I2C_CAM_CK SCL M

S GPIO2/CAM0_RST RESET_B

GPIO0/CAM0_PWR PWDN

7.5 Other Camera Options

SMARC systems have the option of using the dedicated SMARC camera interface pin set. For a dedicated system produced in high volume, this is likely to be the most cost effective option. However, other options exist. USB cameras are becoming very popular. They enjoy good software support and are becoming more and more cost effective as time passes. However, the bandwidth of a HS USB interface (480 Mbps) is less than what is possible with the SMARC CSI camera interfaces.

8 GPIO

8.1 SMARC Module Native GPIO

SMARC Modules support twelve general purpose I/O pins: GPIO0 to GPIO11. Each of these can be configured as an input or output pin. The SMARC specification recommends the use of GPIO0 to GPIO5 as outputs and the use of GPIO6 to GPIO11, as inputs. SMARC Modules support five dedicated GPIOs (GPIO7 to GPIO11). The other seven GPIOs are multiplexed pins supporting functions like Camera Power Enable, Camera Reset, Tachometer input, PWM output etc. SMARC Modules generally allow the GPIO to be configured to generate an interrupt.

SMARC Modules use a GPIO voltage level of 1.8V.

8.2 GPIO Expansion

For a low cost, easy way to implement additional GPIO ports, see Section 4.2.5 I2C Based I/O Expanders.

9 CARRIER POWER CIRCUITS

9.1 Power Budgeting

One of the early steps in a SMARC Carrier design is to develop a power budget and a strategy for meeting that budget. All the power rails need to be identified and worst-case current consumptions listed. A spread-sheet is usually developed. The power circuits should be designed to meet the worst case numbers, but the actual system power consumption will usually turn out to be quite a bit less than the total indicated by the total worst case numbers for each individual rail. Once there is an understanding of the amount of power required, a plan can be developed for meeting the requirements. A sample power budget sheet is shown in the table below. This example is hypothetical and serves to illustrate the process. This example assumes that the SMARC Module is to be supplied by a fixed 5V DC source. A variable battery power source would result in a different sheet.

Table 14 Hypothetical Power Budget Example – Part 1

12V 5V 3.3V 1.8V 1.5V Power Notes Current Current Current Current Current Display Backlight 0.6A 7.2W USB 2.0A 10.0W 4 devices USB 3.0 1.8A 9.0W 1 device SMARC Module 1.2A 6.0W Mini PCIe Module 1.0A 1.0A 4.8W Audio Circuits 0.5A 0.1A 2.7W Misc. Carrier Circuits 0.5A 0.2A 2.0W

Current Subtotals 0.6A 5.5A 1.5A 0.3A 1.0A

Power Totals 7.2W 27.5W 5.0W 0.5W 1.5W 41.7W

The total shown is a worst case value, and power circuits should be designed to handle the worst case. However, experience shows that typical average system power consumptions are significantly less, on the order of 50% of worst case. The total above does not account for power conversion losses. These are added in a later section, when this hypothetical example is continued.

Many SMARC Module vendors offer evaluation platforms, and it is worth the time and effort to roughly prototype the target system with available hardware and software. This can validate power estimates and have other benefits, such as allowing performance benchmarks to be carried out before committing to the full system design.

9.2 Input Power Sources Table 15 Input Power Source Possibilities Power Source Voltage Notes 3.3V Fixed 3.3V +/- 5% Possible, but not a common choice, as often there are significant power requirements for USB (5V at up to 500 mA for each external USB 2.0 port) and the display backlight supply (12V at up to 600 mA is common), requiring up (boost) conversion. Some SMARC Modules may not support 3.3V power input. 5V Fixed 5.0V +/- 5% Common choice – allows some of the higher power consuming devices (USB, SMARC Module) to be fed directly without conversion. Other, lower current devices require power conversion. 12V Fixed 12V +/- 5% Allows display backlight to be powered directly, without conversion (if the display backlight accepts 12V). Requires buck conversion of 12V to 5V for Module and for Carrier USB and other functions. Power “Brick” Various ranges Various output levels are available. The voltage regulation available from a power brick is often not good, and it is best not to rely on the brick output to feed any circuit that needs to be 6V, 9V, 12V, 14V supplied with a voltage regulated over a relatively tight range. Usually the brick output voltage is down converted and regulated on a Carrier board design. Battery - 3.6V nominal 4.2V fully charged; 3.0V discharged. Most SMARC Single Level Modules operate directly from this range (check with your Lithium Ion Cell vendor). Battery – 7.2V nominal 8.4V fully charged; 6.0V discharged Two Level Lithium Ion Cells Battery – 10.8V nominal 12.6V fully charged; 9.0V discharged Three Level Lithium Ion Cells Wide Range DC 10V – 30V Wide range input power supply is possible. Note that to (Typical) handle higher voltages, parts rated for use at the higher voltages must be used. Power Over 48V IEEE802.3af POE standard allows 12.5W load power Ethernet IEEE802.3at POE standard allows 25.5W load power

The POE supply output is transformer isolated from the GBE lines, with 1500V DC isolation. POE supply output voltages are design specific – 24V, 12V and 5V outputs are common. Automotive 12V nominal When the engine is off, the supply battery voltage is 12V nominal. During engine cranking, the supply can dip to 6V. When the engine is running, the DC level can be up to about 16V, with a 14.4V level being typical. Transients in excess of +/- 100V are common. A user may disconnect the battery and reconnect it with the polarity reversed. All in all, it’s a harsh environment that needs careful attention.

A basic strategy is to have an input network with good transient and reverse polarity protection, and then use a rugged switching supply that can handle an input range from 6V to 24V, and deliver a 5V output to the SMARC Carrier.

9.3 Power Budgeting, Continued – Fixed 5V Power Source

Once a power budget is in hand, a power architecture can be developed. Let’s assume that the input power source is to be 5V fixed, and the power budget per voltage rail is as per the hypothetical example given in Table 14 Hypothetical Power Budget Example above. Next, one has to decide how to realize the various power rails. Here we assume that switch mode power converters are used to create all rails from the 5V source. The efficiency (or inefficiency) of the power converters must be accounted for, as shown in the following table.

Table 16 Hypothetical Power Budget Example – Part 2

Voltage Current Power Derived Efficiency Power From Current From Rail From Assumption 5V Input 5V input rail 12V 0.6A 7.2W 5V (Boost) 90% 8W 5V 5.5A 27.5W 100% 27.5W 3.3V 1.5A 5.0W 5V (Buck) 90% 5.6W 1.8V 0.3A 0.5W 5V (Buck) 90% 0.6W 1.5V 1A 1.5W 5V (Buck) 90% 1.7W

Total 43.4W 8.7A

Other factors can make the process a bit more complex than this example. If some power rails are to be created with linear supplies from a higher voltage rail, for example, then the entire current used by the lower rail needs to be added to the current budget of the higher voltage source rail. If the primary source rail varies (such as from a battery) the extremes of the source rail must be taken into account.

9.4 Fixed 5V DC Power Input Circuit Example

The power entry connector for this fixed 5V power source example is shown in the figure immediately below. There are two paths, given net names V_MOD_IN and V_CARRIER_IN. Both carry 5V in from a single bench supply. The nets are separated to allow separate current (and power) measurements of the SMARC Module and the Carrier board. If this separate measurement capability is not needed, then the separate entries could be combined into a single net.

Figure 60 5V Input Connector

V_MOD_IN

C358 1 1 C347 1 C301 100uF 22uF 100nF 10V 25V 25V 2 2 2 J52 Molex 39303045 1 V_CARRIER_IN 1 2 2 3 3 4 1 1 4 C357 1 C348 C302 22uF 100uF 100nF 25V 25V 4/1/1x4/4.2 2 2 2 10V THT 4 Pin, 0.4mm Pitch, TH

The following figure illustrates a power switch used to hold off most Carrier board circuits from being powered until the Module asserts the “CARRIER_PWR_ON” signal. Some Carrier circuits, such as those involved in power management and those that are in the “Module Power Domain” as defined by the SMARC specification, may be powered whenever the Module has power, before (and after) the assertions of CARRIER_PWR_ON.

Figure 61 5V Carrier Power Switch

V_CARRIER_IN V_5V0

1 1 1 1 C363 C364 Note: C362 C361 1uF 1uF Rise Time = 475 us 100nF 100nF 16V 16V 25V 25V 2 2 U54 2 2 TI TPS22965 C365 4 6 VBIAS CT 1 2 220pF 50V 1 7 VIN_1 VOUT_7 2 8 VIN_2 VOUT_8

5 GND CARRIER_PWR_ON 3 9 MOD ON T_PAD

SON8

The following three figures illustrate buck (or step-down) switching converters that create 3.3V, 1.8V and 1.5V from the V_CARRIER_IN 5V power source. Since the power needs on these rails are modest, integrated switchers with internal power FETs are well suited to the job. They are physically small and robust. The parts shown are from Texas Instruments, although similar parts exist from other vendors.

The figures show three separate enables for the three supplies, with net name designations V_3V3_EN, V_1V8_EN and V_1V5_EN. Sources for these nets are not shown. These enable pins should be driven to the “enabled” state when signal CARRIER_PWR_ON is high. They could be driven by CARRIER_PWR_ON, or by V_5V0, or by other Carrier circuitry. If the situation demands aggressive power management, it may be desirable to have Carrier I/O circuits that allow the various enables to be brought low if the power rail is not needed. If this is done, the designer should arrange that the enables do not go high before CARRIER_PWR_ON is high.

The LEDs and signal FETs on the right side of the three figures are optional. The LED lights up as a status indicator when the power rail (V_3V3, V_1V8 or V_1V5) is up. The FET prevents leakage from the main power rails (V_MOD_IN and V_CARRIER_IN) when the switchers are powered down. Rail V_MOD_IN_LED ties to V_MOD_IN through a removable jumper. Removing the jumper prevents the LEDs from burning power in standby states (and in all states).

Figure 62 3.3V 2A Buck Converter

1 L18 2 1.5uH 4.4A

U48 TI TPS63020 V_MOD_IN_LED BUCKBOOST_3V3_SYS_L1 8 6 BUCKBOOST_3V3_SYS_L2 L1_8 L2_6 9 7 L1_9 L2_7 V_3V3 2

V_CARRIER_IN R352 2 100Ohm 10 4 040 VIN_10 VOUT_4

11 5 1 VIN_11 VOUT_5

2 1 1 1 1 1 1 C300 C322 C321 C320

C324 C323 VINA_3V3SYS_BUCK 1 100nF 10uF 10uF 10uF 2 VINA 3 R362

10uF 10uF 25V 16V 16V 16V T

3 DIO_3V3_SYS 562KOhm 2 2 2 2 K 2 16V 2 16V FB 060 12 D30 G 1 EN D35

C299 1 14 DIO_3V3_SYS_RC 100nF PG 190K

C A C 25V 2 13 - PS/SYNC 2

2 NXP 1N4148 2

R344 LTST 2 2 GND R349 10KOhm 100KOhm 040 15 040

PGND 1 1 1 LED_3V3 V_3V3_EN Vih >= 1.2V 3 Vil <= 0.4V PG_3V3 2 Q22 ROHM RJU003N03T106 UMT3 1

Figure 63 1.8V Buck Converter

V_CARRIER_IN V_1V8 V_MOD_IN_LED U49 TI TPS62020

L19 2 2 8 V_1V8_SW 1 2

VIN_2 SW_8 2 10uH R353 3 7 100Ohm VIN_3 SW_7 3A 040

1 2

C325 1 1 V_1V8_EN 1 5 C352 10uF EN FB 2 R363 33pF 16V 2 604KOhm 50V 040 2 6 10 2

MODE PGND_10 T 9 1 PGND_9 1 C326 4 11 FB_TPS62020 22uF D31 KGK GND TH_PAD

6.3V 190

- 2

SON10 1 C337 LTST 2 R364 100pF

232KOhm 50V 040

2 1 1 LED_1V8 GND 3

2 Q28 ROHM RJU003N03T106 UMT3 1

Figure 64 1.5V Buck Converter

V_CARRIER_IN

1 1 1 C344 C346 C295 22uF 22uF 100nF U46 V_MOD_IN_LED 25V 25V 25V 2 2 2 TI TPS53310

13 4 2 VIN_13 VBST 14 R350 2 VIN_14 1 100Ohm C296 V_1V5 040 V_3V3 100nF 25V 1 12 2 L16 VDD 5 V_1V5_SW 1 2 1 SW_5 C312 6 1uH 2 1uF SW_6 T 9.6A K

7 R355 C341 2 16V G 2 V_1V5_EN 1 SW_7 D28 EN 0402 1 1 2 1 1 2 2 20Ohm R357 1 C345 C343 C342 2.2nF 190K

4.02KOhm 22uF 22uF C

040 22uF

2 50V - SYNC 25V 2 25V 2 25V

10 TPS53310_FB 1 2 FB

R359 LTST 1 2 PS_R 8

0402 PS

2 2

57.6KOhm 1 1

C336 2 2 R356 R358 LED_1V5

11 9 100pF 2.67KOhm 040

AGND COMP 2 040 4.02KOhm 1 C340 1 3 TPS53310_COMP 1 2 15 PGND_15 2.2nF 16 50V 2 Q20 PGND_16 17 3 PG_1V5 UMT3 ROHM RJU003N03T106 TH_PAD PGD

1 QFN16

Many LCD backlights require a 12V power source. If the system power source is a fixed 5V supply, or a battery supply well under 12V, then a boost converter circuit is needed. An example is shown here:

Figure 65 12V Boost Converter for Backlight Power

L21 1 2 V_12V_SW

V_CARRIER_IN 6.8uH 2 2 U51

V_CARRIER_IN TI TPS61087DRC V_12V0 2

R335 2 R336 D38 040 0Ohm 040 0Ohm

8 IN SW_6 6 2

DNI 1

1 1 SW_7 7 2 V_12V_EN 3 Vishay SS23-E3/52T EN 2 R368 1 1 1 1 2 V_12V_FB 154KOhm C330 C329 C328 C327 FB 040 V_12V_FREQ 9 10uF 10uF 10uF 10uF FREQ R369 1 25V 25V 25V 25V 1 1 1 TPS61087_COMP 1 2 2 2 2 2

C349 C332 COMP 0402 2

2 22uF 1uF 5 PGND 33.2KOhm 2

R337 2 25V 2 25V 4 10 TPS61087_SS 2 2 R338 AGND SS

0Ohm 2 R370

0Ohm 11 1 1 040 040 THERM_PAD C306 DNI C356 17.8KOhm

100nF 2.7nF 040 1 1 25V 50V 2 2 1 VSON10

9.5 Power Hot Swap Controller

Hot swap controller circuits can be used to control the system power supply rise time. This may be desirable when plugging circuits in live to low impedance sources, such as a battery. The figure below illustrates a high-side protection controller circuit using TI LM5060. The N-Channel MOSFET isolates the input supply (V_BRD_IN) from rest of the board (V_HTSWP_OUT). The circuit limits the in-rush current and provides a power good signal once the output voltage reaches the input voltage. An option is provided to enable LM5060 (HTSWAP_EN) from a CPLD as well as using a switch / jumper.

Figure 66 Hot Swap Controller

V_BRD_IN V_HTSWP_OUT Q27 SUM40N10-30-E3

Vishay/Siliconix

G 2

2 V_3V3_PWRUP 2 R372 2 2 R374

U53 10Ohm 040

7.5KOhm 2 m

040 1 C359 9

TI LM5060 h

10nF 2

040

1 R

50V 0

2 h 1 10 2 8 DNI 1

SENSE GATE O

1 34 040

C335 R 100nF 2 9 10K 50V 1 2 VIN OUT

4 8 HTSWP_PGD#

2 UVLO nPGD

2 R375 7 TIMER 040 49.9KOhm 3 1 OVP C360

1 68nF 5 6 16V 2 EN GND Note : 2

OVP : @ 33.5 V 2 R373

UVLO : @ 9.3V 6.8KOhm MSOP10

040

1 2

2 R371

040 3.6KOhm 1

3V3 Power Up Supply

V_3V3_PWRUP V_3V3_PWRUP V_BRD_IN V_3V3_PWRUP U76 TI LM9036

8 1 1 1 VIN VOUT C309 C310 100nF 100nF

1 1 2 2 25V 25V 4 5 C478 2 2 C479 NC_4 NC_5

100nF 22uF 3 3 50V 25V

R376 R377 2 2 6 2 060 47KOhm 47KOhm 060 GND_2 GND_6 U52 3 7

GND_3 GND_7 1 1 5 TI SN74AHC1G00 HTSWP_EN_HOLD# 1 4 HTSWP_EN SOIC8 2

C307 1 100nF SC70 3

25V 1

2 D39 2

SW4 R354 E-Switch 400MSP1R1BLKM7QE PWR_SWITCH_STATE 0402 2 1 1KOhm 1 1 2 0402 1

1 C308 2 R340 0Ohm D40 100nF 3 1 2 25V 0402 2 R341 0Ohm

DNI 2

J50 FCI 77311-118-02LF

1 1 2 2

2/1x2/2.54 ST

9.6 High Voltage LED Supply

Some LCD panels have multiple sets of series LED strings that are to be driven by a high voltage LED supply. Vendors such as TI and Analog Devices provide the ICs for these supplies. A schematic example using a TI / National high voltage LED supply is given below.

The LED brightness can be controlled either using PWM control (if the IC VDDIO pin is set LOW) or by I2C (if VDDIO is HIGH). A level translator needs to be used for signals VSYNC and PWM.

Figure 67 LP8545 LED Backlight Power

V_1V8

2 R345

4 10KOhm 2

1 Q26 Vishay SI2305CDS-T1-GE3 Logic State Function 3 BKLT_REF 0 PWM 1 I2C 3

BKLT_REF_SEL 2 Q23 ROHM RJU003N03T106

U50 V_5V0 1 National LP8545

8 22 VDDIO VLDO 1 R334 C331 LCD_VS_3V3 1 2 VSYNC 19 23 1uF 0402 VSYNC VIN 25V 0Ohm 2 V_1V8 V_1V8 V_1V8 V_3V3

6 V_CARRIER_IN GD

2 2 2 2 V_31V9_BKLT

2 R347 2 R346 C304 U45 C303 DiodesInc DFLS230L

0 0 100nF 100nF C354 L20

4 10KOhm 4 10KOhm TI SN74AVC2T244DQ

0 0 25V 25V LCD_BKLT_EN 4 1 2 1 2 DNI 1 1 EN 15uH A C

1 1

2 10uF 1 VCCA VCCB 8 50V D37 1 C338 1 R327 2 C353 0 100pF 10uF LCD_VS 2 7 1KOhm 4 MOD A1 B1 0 24 50V 50V SW BKLT_SW 2 2 LCD_BKLT_PWM 1 MOD 3 A2 B2 6 1 1 DNI C339 C355 R333 100pF 10uF BUFFER5_OE# I2C_GP_CK 1 2 BKLT_I2C_SCL_R 10 50V 50V 4 OE# GND 5 0Ohm SCLK 2 2 I2C_GP_DAT BKLT_I2C_SDA_R 11 1 0Ohm 2 SDA R332 R329 R330 21 2 FB DNI 0402 2 1 2 0402 1 2 0Ohm 0Ohm R331 0 0Ohm 4 0 12 OUT1 LCD_CA1 2 13

1 LCD_BKLT_PWM_3V3 LCD_CA2 PWM OUT2 C305 14 LCD_CA3 1 2 OUT3 16 LCD_CA4 OUT4 100nF 17 LCD_CA5 Optional 25V OUT5 18 LCD_CA6 C313 R366 OUT6 1 2 FILTER 20 1 2 0603 FILTER 7 1uF 120KOhm FAULT 16V 15 GND_L

9 R365 GND_S 1 2 ISET 3 0402 ISET 1 31.6KOhm GND_SW R367 1 2 FSET 5 25 0402 FSET TH_PAD 470KOhm

1.25MHz,100mA@33V I2C Address : 0x2C(7-bit format)

9.7 3.0V to 5.25V Power Input Example

The circuits shown below illustrate buck-boost switching converters that generate 5V and 3.3V from the V_CARRIER_IN power source (3.0V to 5.25V). Since the power needs on these rails are modest, integrated switchers with internal power FETs are well suited to the job. They are physically small and robust. The parts shown are from Texas Instruments, although similar parts exist from other vendors.

The figures show separate enables for the 5V and the 3.3V supplies, with net name designations V_5V0_EN and V_3V3_EN. Sources for these nets are not shown. These enable pins should be driven to the “enabled” state when signal CARRIER_PWR_ON is high. They could be driven by CARRIER_PWR_ON, or by V_CARRIER_IN, or by other Carrier circuitry. If the situation demands aggressive power management, it may be desirable to have Carrier I/O circuits that allow the various enables to be brought low if the power rail is not needed. If this is done, the designer should ensure that the enables do not go high before CARRIER_PWR_ON is high.

Figure 68 5V, 2A Buck-Boost Converter

L17 1 2 3.3uH 8.4A

U47 TI TPS63020 V_MOD_IN_LED

BUCKBOOST_5V0_SYS_L1 8 6 BUCKBOOST_5V0_SYS_L2 L1_8 L2_6 9 7 2 L1_9 L2_7

V_5V0 R351 2 100Ohm V_CARRIER_IN 040

10 4 1 VIN_10 VOUT_4 11 5

VIN_11 VOUT_5 2 1 1 1 1 1

1 1 C297 C315 C314 C317 C316 2 2 VINA_5V0_SYS_BUCK 1 R360 100nF T

C319 C318 VINA 10uF 10uF 10uF 10uF K G 10uF 10uF 3 DIO_5V0_SYS 040 1.82MEGOhm 25V 16V 16V 16V 16V D29 FB 2 2 2 2 2 2 16V 2 16V 1

1 12 1 D36

C298 EN 190K 2 R328 C 100nF 14 DIO_5V0_SYS_RC - 0Ohm PG 040 25V 13 C A

DNI 2 PS/SYNC

LTST 2 2 NXP 1N4148

2 2 R361 1 GND 200KOhm R343 2

15 040

PGND 10KOhm 040 LED_5V0

V_5V0_EN 1 1 3

2 Q21 PG_5V0 UMT3 ROHM RJU003N03T106

Figure 69 3.3V 2A Buck-Boost Converter

1 L18 2 1.5uH 4.4A

U48 TI TPS63020 V_MOD_IN_LED BUCKBOOST_3V3_SYS_L1 8 6 BUCKBOOST_3V3_SYS_L2 L1_8 L2_6 9 7 L1_9 L2_7 V_3V3 2

V_CARRIER_IN R352 2 100Ohm 10 4 040 VIN_10 VOUT_4

11 5 1 VIN_11 VOUT_5

2 1 1 1 1 1 1 C300 C322 C321 C320

C324 C323 VINA_3V3SYS_BUCK 1 100nF 10uF 10uF 10uF 2 VINA 3 R362

10uF 10uF 25V 16V 16V 16V T

3 DIO_3V3_SYS 562KOhm 2 2 2 2 K 2 16V 2 16V FB 060 12 D30 G 1 EN D35

C299 1 14 DIO_3V3_SYS_RC 100nF PG 190K

C A C 25V 2 13 - PS/SYNC 2

2 NXP 1N4148 2

R344 LTST 2 2 GND R349 10KOhm 100KOhm 040 15 040

PGND 1 1 1 LED_3V3 V_3V3_EN Vih >= 1.2V 3 Vil <= 0.4V PG_3V3 2 Q22 ROHM RJU003N03T106 UMT3 1

9.8 12V Input

There are many choices for switching power supply circuits to step a 12V input down to lower voltages for SMARC use. An integrated switcher possibility from TI is shown in the following figure.

Figure 70 12V Step Down Switcher

V_12V0

R574 DNI 1 0402 2 1 C570 1 C576 200KOhm 4.7uF 1uF 25V 16V R572 DNI 1 0402 2 2 2 0Ohm

U81 TI TPS53318

1 2 V_12V0 C575 19 18 VREG_5V_REG 1uF 2 R571 VDD VREG 16V 100KOhm

2 0402 040 2

R575 200KOhm MODE_5V_REG 20 1 1 0402 2 MODE 2 R570 R576 1 2 210KOhm TRIP_5V_REG 21 100KOhm 0402 TRIP 040 R577 1 2 619KOhm RF_5V_REG 22 3 PG_SWITCHER

0402 RF PGOOD 1 2 EN R573 C578 R582 4 VBST_5V_REG VBST_5V_REG_C 1 2 LL_5V_REG_R2 VBST 0402 0402 2 1 1 2 1 0Ohm 100nF 3.01Ohm C577 1 FB_5V_REG DNI 470pF VFB 25V 50V 2 DNI 5 ROVP_5V_REG ROVP V_5V0 V_12V0 L24 12 6 LL_5V_REG 1 2 VIN_12 LL_6 13 7 6.8uH C574 C573 C572 C571 VIN_13 LL_7 13.5A 1 1 1 1 14 8 22uF 22uF 22uF 22uF VIN_14 LL_8 1 1 1 1 15 9 R583 C580 C581 C582 C583 25V 25V 25V 25V VIN_15 LL_9 1 2 LL_5V_REG_R1 1 2 100uF 100uF 100uF 100uF

16 10 0402 2 2 2 2 2 VIN_16 LL_10 25V 25V 25V 25V 2

17 11 1.5KOhm C579 2 2 2 2 2 VIN_17 LL_11 2 1 100nF R581 R580

C584 040 25V 71.5KOhm 040 71KOhm 23 1nF

GND 1 50V 1 2

QFN22

2 2

R579 2 R578 040

10KOhm 040 10KOhm

1 1

9.9 Wide Range Power Input

In some applications it is desirable to allow for a wide range power input. This is the case in certain industrial and automotive settings. Since SMARC systems operate at low voltages (5V and under, apart from LCD backlight considerations), it is straightforward to implement a wide range buck converter. The figure below shows an example implemented with the Linear Technologies LTC3879. Similar parts are available from other vendors. The Texas Instruments TPS40170 is another part to consider for this application. The TPS40170 allowable input range spans 4.5V to 60V. If you are targeting the higher input ranges, be sure that components exposed to the input voltage are adequately rated for that high voltage.

Figure 71 Wide Range Power Input Switcher

Note: Place CIN, COUT,MOSFETs,DB and inductor all in one compact area. V_IN_10-30V V_IN_10-30V

R564

1 0402 2 2 2.2Ohm 2 C538 1 1 C505 5

4.7uF 1 1 1 0 2 100nF C539 C540 C541 R560 50V R530 U80 Renesas RJK0451DPB 50V 4.7uF 4.7uF 4.7uF 1Ohm

0Ohm 121 2 040 2 LT LTC3879 50V 50V 50V

Q51 2 2 2 1 V_IN_10-30V 1 R549 10 15 4 1 2 VIN TG 0402 1 C549 LFPAK 22uF

2 1.82MEGOhm 1 V_5V0

3 2 C504 1 50V 100nF 2 2 R552 7 50V ION L22 2 14 1 2

040 40.2KOhm SW 1 4.7uH 1 C562 9 220nF 17A RUN 25V 1 1 1 1 1 16 2 C560 C557 C558 C559 C561 2 3 BOOST 47uF 47uF 47uF 47uF 47uF D55 5 10V 10V 10V 10V 10V 2 R524 C522 2 2 2 2 2 DNI R558 1 2 1 040 10KOhm TRACK/SS Q48 0402 2 1 100nF Renesas RJK0451DPB

1 V_INTVCC_5V0 C 1 20KOhm 12 4 1 1 BG V_INTVCC_5V0 C547 C556 2 820pF 47pF LFPAK

5 D57

3 2 2 50V 2 50V ITH 1 R553 2 2

A 1 1 C566

210KOhm 040 C564 2 22pF 11 4.7uF R567 INTVCC 11KOhm COG 1 10V 040 3 2 2 50V VRNG 1 2 8 VFB R556 2 4 20KOhm MODE 2 DNI 040 R519

2 2 1 PGOOD 0402 R562 2 1 1.5KOhm 100KOhm 040 6 SGND 1 17 13 Note : TH_PAD PGND Route the VFB line away from noise sources, such as the inductor or the SW line.

1053-6883 QFN16

If the load on the Carrier 3.3V is high, it may be worth having a second wide input range switcher per the above figure, configured for the 3.3V output.

9.10 Power Monitoring

The SMARC specification document defines a VIN_PWR_BAD# input. Its use is optional. If VIN_PWR_BAD# is held low by a Carrier or power supply circuit, the Module assumes that the source power is not ready and does not boot.

VIN_PWR_BAD# is typically generated by a power monitor / reset generator IC, such as those shown in the figure below. This figure shows two of them, although this is not really necessary if the Module and the Carrier circuits are powered by a single source and you don’t want to keep them separate.

Figure 72 Power Monitor - Incoming Power

V_MOD_IN 2 V_MOD_IN 2 R451 4.7KOhm 040 DNI

U68 1 TPS3803-01 2 1 C450 100nF R452 3 4 3 V_3V0-5V25_PG VIN_PWR_BAD R450 25V VDD RESET 0402 60.4KOhm 2 2 1 060 0Ohm 1

NC 1 V_MOD_SNS 5 2

SENSE GND 2

R457 3 SC70-5

47KOhm 060

1 V_MOD_IN 2 R453 V_CARRIER_IN 2 4.7KOhm

040 DNI

U69 1

2 1 TPS3803-01 C451 R456 3 100nF 4 3 V_5V0_DCIN_PG R454 60.4KOhm 25V VDD RESET 0402 060 2 2 0Ohm 1 1

1 NC V_CARRIER_SNS 5 2

SENSE GND 2 SC70-5 R455 3

47KOhm 060 1

9.11 Power Over Ethernet

Power may be delivered to a SMARC system over the Gigabit Ethernet cabling, cohabiting with the GBE data traffic. The 48V DC power is extracted from the isolated GBE cabling by a diode bridge and a specialized transformer isolated switching power supply. POE is defined by the IEEE 802.3af and IEEE 802.3at standards. The 802.3af payload power is limited to 12.5W and the 802.3at to 25.5W.

Many semiconductor vendors offer POE solutions. Designing a POE power supply is a little trickier than designing your average switching supply, as the POE supply is transformer coupled, there are isolation requirements to meet, and some sort of DC isolated feedback mechanism must be incorporated. If your product volume is high, it may be worth the trouble of implementing your own Carrier-down circuit. See Texas Instruments and Micro-Semi for POE IC solutions. Even if you don’t go for the do-it-yourself approach, there are some very instructive Application Notes available from these vendors

In many cases it is more straightforward to make use of a POE module, available from various vendors. One attractive POE module line comes from Silver Telecom (www.silvertel.com). IEEE 802.at compliant modules with output voltage options of 24V, 12V or 5V are available. The sample circuit below uses a Silvertel module with a 12V output. The 12V output cannot be fed directly to a SMARC Module – a step down converter would be needed. However, many SMARC systems incorporate LCD displays that utilize 12V backlights – hence the POE output option of 12V may make sense. If not, then the 5V POE output option could be considered (and the 5V POE module output can be fed directly to the SMARC Module).

Note that for POE use, a particular type of GBE jack is required, to get access to the DC power coming in over the isolated GBE lines. The example shown here uses a Pulse Electronics JXK0-0190NL GBE POE Mag-Jack. Similar parts are available from Bel-Fuse, Tyco and others – but beware of differing PCB footprints.

Figure 73 GbE with PoE

V_3V3

GBE_CTREF MOD

C157 1 C40 1 C39 1 C38 1 C37 1 C36 1 1uF 100nF 100nF 100nF 100nF 100nF 16V 2 25V 2 25V 2 25V 2 25V 2 25V 2

J28 Pulse JXK0-0190NL

13 R275 GREEN_A GBE_LINK_ACT# 1 2 GBE_LINK_ACT_R# 14 MOD 0402 GREEN_K 68Ohm GBE_MDI0_P 11 MOD MD1+ 12 MDCT1 GBE_MDI0_N 10 MOD MD1-

GBE_MDI1_P 4 MOD MD2+ 6 MDCT2 GBE_MDI1_N 5 MOD MD2-

GBE_MDI2_P 3 MOD MD3+ 1 MDCT3 GBE_MDI2_N 2 MOD MD3- V_3V3 GBE_MDI3_P 8 MOD MD4+ 7 MDCT4 GBE_MDI3_N 9 2 1 MOD MD4- R272 C34 1KOhm 2 100nF U57 V_POE1_P 17 VDC1+

040 2 25V FAIRCHILD NC7SZ125 V_POE1_N 18 VDC1-

1 V_POE2_P 19 VCC VDC2+ V_POE2_N 20 VDC2-

GBE_LINK1000# GBE_LINK1000_BUF# 68Ohm 1 2 R274 GBE_LINK1000_BUF_R# 16 MOD IN OUT 0402 DLED_16 SHIELD_22 22 15 21 DLED_15 SHIELD_21

OE# GND 20/1PORT RA SOIC8

RJ45 with Magnetics/POE, R/A, TH

V_3V3

2 1 C35 R271

2 100nF 1KOhm U58 2 040 25V FAIRCHILD NC7SZ125

1 VCC

GBE_LINK100# GBE_LINK100_BUF# MOD IN OUT

OE# GND

SOIC8

PS1 Silvertel AG9330

2 4 AUX1+ NC

D13 1 AUX1- Comchip CDBHD2100-G V_12V0 V_POE1_P 1 3 V_POE_IN_P AC + V_3V3 3 12 AC - VIN+ +VDC_12 V_POE1_N 2 4 13 +VDC_13 1 C241

1mF 2 D14 D15

AL m h Littelfuse SMAJ58CA 2 2 Comchip CDBHD2100-G 12.5x13.5 R273 O V_POE2_P 1 3 10 040 -VDC_10 150

AC + 6 9 1 VIN- -VDC_9 U23 Sharp PC817X1NIP0F V_POE2_N 2 AC - 4 V_POE_IN_N R97 1 4 T2P_CLASSIFICATION# 1 2 GPIO11 0402 MOD 14 11 AUX_DC+ ADJ 0Ohm

8 AUX_DC_8- 7 5 2 3 AUX_DC_7- AT-DET

PDIP4

9.12 Li-ION Battery Charger

9.12.1 General

Caution: improper battery charging can be a serious safety hazard. This section serves as a brief introduction to what is involved in designing a battery management system, but it is not enough to go on. Other source materials, from IC companies, battery vendors and the technical literature will be necessary for you to implement a safe and effective system.

Lithium Ion batteries have a fully charged cell voltage of 4.2V, nominal cell voltage level of 3.7V, and a depleted voltage of 3.0V. They are used in series combinations and parallel combinations. The voltages for various series combinations are shown in the following table.

Table 17 Lithium- Ion Battery Cell Voltages

Series Cells Nominal Voltage Fully Charged Fully Depleted 1 3.7V 4.2V 3.0V 2 7.4V 8.4V 6.0V 3 11.1V 12.6V 9.0V 4 14.8V 16.8V 12.0V

Battery capacities are measured in Ampere-Hours (Ah). A fully charged battery with a 2Ah capacity can deliver 2A for 1 hour, or 1A for 2 hours and so on. The capacity is sometimes designated ‘C’ in battery data sheets.

Lithium-ion batteries are typically charged in two phases: a constant current portion (for the deeply depleted battery) and a constant voltage portion (when the charging process nears completion).

The constant current charging is typically done at a maximum constant current equal to the battery capacity – for example, a 2Ah battery is charged at a maximum charging current of 2A. The constant voltage portion is done at the cell fully charged voltage – 4.2V for a single series cell, 8.4V for two series cells, and so on. The battery data sheet and vendor’s application notes should of course be consulted for more specific recommendations that apply to the situation at hand.

The battery temperature should be monitored during charging and use. The charging is disabled if the battery temperature exceeds a threshold set by the battery charger implementation.

9.12.2 Battery Charger Circuit Example

A battery charger implementation is shown in the following four figures. This example uses Texas Instruments parts. Similar devices are available from Linear Technology, Maxim integrated, Analog Devices and others.

The first of the four figures shows the overall charging system in block diagram format. The actual circuit schematics are shown in the three subsequent figures.

Caution: many of the component values shown here need to be adjusted to suit the details of the situation at hand – the number of series cells, the battery capacity, the battery thermistor particulars.

With reference to the following four figures:

 FETs Q40 and Q46 form an analog switch that the charger IC can use to gate power from the external DC adapter into the system. Charger current is sensed through RS1. The FETs are turned off if the charger voltage is too high, too low or if the current draw is excessive.

 FET Q47 is turned on by the charger IC to allow battery power to be delivered to the target system.

 FET Q47 is off when Q40 and Q46 are on.

 The charger IC includes charge pumps to drive the N channel FET gates to a sufficiently high voltage to turn them on.

 The charger IC in this example has an internal switch-mode power supply, with internal high side FET, that are used when charging the battery. The external components of this supply are L1 and D53 in the diagrams.

 Battery charging current is measured through RS2.

 It is important to monitor the battery temperature. Usually an NTC (negative temperature coefficient) thermistor attached to or internal to the battery is used for this. The charger IC has support for the thermistor.

 A fuel gauge IC is used to collect information about battery charge levels. The gauge tracks current into and out of the battery, via sense resistor RS3. This sense resistor is in series with the battery GND terminal. The gauge has an I2C interface to the SMARC Module.

 There are three status signals from the charger system to the SMARC Module: CHARGING#, BATLOW# and CHARGER_PRSNT#.

Figure 74 Li-ION Battery Charger - Block Diagram

Q40 Q46

RS1 DC Adapter Power Supply

Adaptor Current Sense path

D52A

Temp Sense path Battery Charger Q47 Charging Current Sense path Charging D52B Supply

D53

1/2/3 Cell Li-Ion or Li-Polymer RS2

I2C_PM Fuel Gauge To SMARC Connector

RS3

Bat-Pack System Negative GND

Main Supply Path

Battery Charging Path

Current Sense Paths

Supply to the IC

Battery Temperature Sense

Figure 75 Li-ION Battery Charger - Schematic

J64 F1 KYCON KLDHCX-0202-B POLYFUSE 1 2 BAT_CHG_IN 1 1

1 1 C500 C503 3 3 22uF 100nF C 25V 50V D50 2 2 2 2

A 3/1Port RA 5A, DC Adaptor

V_BAT_CHARGE_A Q40 Q46

TI CSD16406Q3 TI CSD16406Q3 3 V_CHARGER_IN 3 VSYS_CHGIN I1 RS1 I2

10mOhm

5 2 2 5

E1 E2 Route Differentially (Kelvin Routing) 1

1 2512

2 4 4 C515 1 1

1 1 C534 m C513 C501 C502

C535 QFN-8 h QFN-8 1 2 1 2 2 1 1 2 22uF 22uF 2.2uF C529 O

2.2uF 2 C528 53 1 25V 25V

50V R 100nF 100nF 2 50V 2 4.7nF 470nF 040 C509 2 2

DNI 2 25V 25V R500 2 50V 25V 2 499K 100nF 1 U77

040 0Ohm 25V 2 1 C526 1 C527 VDD_ACIN_RC GND_CHR TI BQ24171 10uF 10uF 2

1 25V 25V 2 C508

2 2 2 ACN 5 2 R509

GND_CHR ACN PVCC_2 2 2 100nF 100KOhm

040 5 5 R544 R543 3 25V PVCC_3 1 5

3.9Ohm 3.9Ohm 6

1 080 080 ACP

ACP 1 1 R536 V_SYS_B2B 4.02KOhm 1 R542 2 CMSRC 7 19 BATDRV 1 2 EN_VDD_BAT 4 Q47 0402 CMSRC BATDRV# 0402 TI CSD25401Q3 D53 1KOhm R522 C A SON8 VDD_AON BQ24171_ACDRV_R 4.02KOhm 1 R541 2 ACDRV 8 0402 0402 ACDRV 1 2 10KOhm 1 2 3 V_BAT GND_CHR L1 1 BQ24171_SW 1 2 CHG_BAT I1 RS2 I2 VREF_3V3 12 SW_1 10mOhm V_BAT VREF 24 3.3uH 3 SW_24 8.4A E1 E2 D52 2512 1 1 1 2 1 C531 2 Route Differentially C525 C524 1uF 2 (Kelvin Routing) 10uF 10uF 2 R533 25V 25V

16V 2 R516 2 C532 2 2

040 232KOhm 100KOhm 21 BTST C510

040 BTST 1 2 1 2 1 13 47nF 1 ISET ISET 16V

17 100nF 2 GND_CHR 2 ACSET ACSET 16 SRP 25V

SRP 2 2 R540 R539

22.1KOhm 040 040 32.4KOhm

4 15 1 1 AVCC SRN AVCC SRN GND_CHR GND_CHR 1 C511 1 C512 1 R537 2 0402 C530 V_BAT 100nF 100nF 1 20 REGN 25V 25V

2 10Ohm C533 REGN 2 2 2 1uF 1

2 R538

1uF 2 ResA 2 25V

Ichg = 0.4V/(20x10mOhm) = 2A 243KOhm ResB 040

2 R511 GND_CHR GND_CHR VREF_3V3 GND_CHR

( Charging Current ) 1 100KOhm

OVPSET 18 040

OVPSET

1 2

2 R515 14 BQ_FB FB

2 100KOhm

R535 040

2.21KOhm 2

040 1

2 R510

1 10 R526 GND_CHR TS 100KOhm BAT1_TS+ 1 2 BQ_TS 22 040 0402 PGND_22 11 23 BQ_TTC 1

0Ohm VDD_AON TTC PGND_23 2

V_CARRIER_IN R534 2 9 25 R525 1 C514 STAT AGND 0402 6.81KOhm 2 1 040 100nF 0Ohm 25V GND_CHR

1 2 2

2 QFN24 2 2 R512 R506 GND_CHR

040 100KOhm 040 100Ohm GND_CHR

GND_CHR

1 1

BQ24171_STAT 2 V_CARRIER_IN

VDD_AON LOW: CHARGING LTST-C190KGKT

D51 2 HIGH: CHARGE_COMPLETE/SLEEP

2 R514 2

040 100KOhm 2

1 R513 1

CHARGER_LED 040 100KOhm

3 1

Q43 2 CHRG_LED ROHM RJU003N03T106 Over Volt. Protection Configuration Feedback Resistor Divider Config. UMT3 3 1 Charging Voltage Value of ResA No: of Cells Value of ResB Q42 2

ROHM RJU003N03T106 1 UMT3 5V 243K 1 (4.2V) 100K CHARGER STAT to CPU R502 1 0402 2 1MEGOhm CHARGING MOD 12 727K 2 (8.4V) 299K LOW: CHARGING 3 FLOAT: CHARGE_COMPLETE/SLEEP Q41 2 ROHM RJU003N03T106 UMT3 16 1M 3 (12.6V) 499K 1

R501 1 0402 2 1MEGOhm

Figure 76 Battery Fuel Gauge

V_BAT V_BAT_2 V_BAT_3

2 2 2

R547 R545

6 6 R546 6

2 100Ohm 100Ohm 100Ohm

120 120 120

2 R551 DNI DNI

1 1

18.7KOhm 1

040 1

BQ27510_REGIN

2 G 2 R548 U79

040 1.82MEGOhm TI BQ27510-G2

V_1V8_LDO 3

5V1LT1

1 C BQ27510_VCC 2 3 4 R550 1 REG25 REGIN 5 1 2 BAT1_TS+ C536 1 5 4 D 0402

2 C537 VCC BAT 1 1 33nF C521 BZX84 47Ohm

470nF i

m C520

3 2 h 25V 100nF

2 6.3V m 100nF O 52 2 25V

040 25V R 2 2

1 nSe 10K BI/TOUT O

1 9 TS BATLOW BQ27510_BI MOD BQ27510_TS R528 R507 I2C_PM_CK 1 2 I2C_PM_CK_FG1 11 7 BQ27510_SRP 1 2 BQ27510_SRP_RS BAT_PACK Negative MOD 0Ohm SCL SRP 0402 3 I2C_PM_DAT 1 2 I2C_PM_DAT_FG1 10 MOD 0Ohm SDA 1 C518 100Ohm

100nF 2

R527 I2 Q45 2 BATLOW 12 1 25V E GND_BAT

BAT_LOW/BAT_GD C519 2 m

h 2

ROHM RJU003N03T106 3

100nF O S

UMT3 25V m R 6 2 1 C517 251

VSS 10 1 13 8 100nF

TH_PAD SRN 25V 1 I1 2 E R508 BQ27510_SRN 1 2 BQ27510_SRN_RS 0402 SON12 100Ohm I2C Address : 0x55 (7-bit format)

A comparator circuit such as the one shown below may be used to provide an indication to the SMARC Module that the battery charger power source is present. This circuit may be incorporated into some battery charger ICs.

Figure 77 Charger Present Detection

R521 2 0402 1 V_BAT V_CHARGER_IN 100KOhm

V_1V8_LDO

2 2 C516

U78 2 R504 2 R503 1 2 CHARGER_PRSNT MOD

1MEGOhm 1MEGOhm OnSemi NCS2200SQ2T2 040 040 100nF

5 25V 3 1 1 VCC CHARGER_IN 3 IN+ 1 CHARGER_PRSNT 2 Q44 OUT BATTERY_IN 4 IN- 2

VEE 2

2 1 2 R518 2 R517

SC70-5 040

100KOhm 040 100KOhm

1 1

10 THERMAL MANAGEMENT

10.1 General

SMARC Modules generally have modest power dissipations. In a production environment, heat-sinking is usually necessary to keep the Module electronics die temperatures within limits, at the higher operating temperatures.

10.2 Heat Spreaders

Heat spreaders are available from SMARC Module vendors. Their purpose is to present a uniform thermal interface that is the same across various Module designs. A heat spreader is not a full heat sink – the heat spreader top surface is meant to be in contact with a system specific heat sink, such as the wall of an enclosure or other heat sink.

The figure below diagrams a typical heat spreader suitable for an 82mm x 50mm SMARC Module. The diagram plan view shows the heat spreader surface that the Module interfaces to. “TIM” is an abbreviation for “Thermal Interface Material” - a thermally conductive, compliant material to bridge the small gap between the heat-spreader surface and the surface of the system SOC. The Module is 82mm x 50mm, but the heat spreader is sized at 82mm x 42mm to allow the Module edge fingers to mate to the Carrier board MXM3-style socket. The heat spreader top, or “far side” surface, is 6mm above the Module PCB surface.

Figure 78 Heat Spreader Example – 82mm x 50mm Module

Table 18 Heat Spreader Hole Types

Figure Notation Hole / Standoff Type Notes Holes marked ‘A’ Clearance holes for M2.5 These holes coincide with the SMARC mounting screws; 3mm tall clearance holes for 82mm x 50mm Modules standoffs Holes marked ‘B’ Module design specific holes and standoffs X-Y locations of these holes are also Module design specific. The TIM location is design specific. Holes marked ‘C’ M3 thread in heat spreader These holes allow either a heat sink to be attached to the heat spreader, or they can allow the heat spreader (and the SMARC Module / Carrier assembly) to be secured to an enclosure wall or other heat-sinking structure.

10.3 Heat Sinks The figure below shows a heat sink that can be added to the heat spreader described in the figure above. This add-on heat sink attaches to the heat spreader through the ‘C’ holes marked on the heat spreader drawing above. A thermal interface material – thermally conductive paste, grease, or a gap pad – is needed between the heat spreader and the add-on heat sink, on the heat spreader “far” side.

Figure 79 Heat Sink Add-On to Heat Spreader

The best thermal transfer characteristics are usually obtained by a stand-alone heat sink. An example is shown in the following figure. The heat sink is secured to the SMARC Module through two design – specific interior holes (and design specific standoffs) that are straddling the TIM (the TIM in the figure is the square piece of foam that contacts the SMARC SOC). The four corner holes and standoffs coincide with the four SMARC Module holes (for 82mm x 50mm Modules). M2.5 screws pass through the heat- sink corner holes and standoffs, and pass through the SMARC Module, and catch the threads in the corresponding Carrier board hardware. Check with your SMARC Module vendor for the heat sinks that they offer.

Figure 80 Stand-Alone Heat Sink

10.4 Thermal Resistance Calculations

It is easy to estimate the thermal performance of a SMARC system if you have thermal resistance data from the vendors. The vendor sources can include silicon vendors, SMARC Module and Carrier board vendors and heat sink vendors.

Thermal resistance is a simple concept, analogous to Ohm’s law and electrical resistance. Thermal resistance is expressed in degrees Celsius per Watt (0C/W). If a particular thermal interface has a thermal resistance of 8 0C/W and the source device dissipates 4W, then there will be a temperature rise of 8 * 4 = 32 0C across that interface.

Some hypothetical thermal parameters are given in the table below, followed by some sample calculations for various situations. The calculations are just estimates, which can be useful for design guidance. The estimates should be followed up by measurements on physical samples. It may be useful to use thermal CAD simulations as well – after the “back of the envelope” calculations and before building hardware.

Table 19 Hypothetical Thermal Parameters

Parameter Symbol Value (Hypothetical) 0 Max SOC junction Temperature(Tj) TJ-MAX 90 C 0 Thermal Resistance, CPU Junction to ambient (θJA) θJA 12 C/W 0 Thermal Resistance, CPU Junction to case (θJC) θJC 0.4 C/W 0 TIM interface (CPU to heat spreader or sink) θTM1 0.5 C/W 0 Heat Spreader θHS 0.1 C/W 0 TIM interface (heat spreader to add-on heat sink) θTM2 0.4 C/W 0 Add-on Heat Sink - still air (natural convection) θHS1 4 C/W 0 Stand-alone Heat Sink – still air (natural convection) θHS2 3 C/W SOC maximum power dissipation WSOC-MAX 5W Maximum Environmental Temperature TOP-MAX To be calculated

Sample Calculations Using Hypothetical Thermal Parameters

No heat sink at all

TOP-MAX = TJ-MAX – θJA * WSOC-MAX = 90 – 12 * 5 = 30 0C

Heat Spreader + Add-On Heat Sink

TOP-MAX = TJ-MAX – (θJC + θTM1+ θHS + θTM2+ θHS1) * WSOC-MAX = 90 – (0.4 + 0.5 + 0.1 + 0.4 + 4 ) * 5 = 63 0C

Heat Spreader + Stand-alone Heat Sink

TOP-MAX = TJ-MAX – (θJC + θTM1+ θHS2) * WSOC-MAX = 90 – (0.4 + 0.5 + 3 ) * 5 = 70.5 0C

11 CARRIER PCB DESIGN RULE SUMMARY

11.1 General – PCB Construction Terms

The Table and Figure below serve to define and illustrate some terms used in describing PCB construction and in trace impedances

Table 20 PCB Terms and Symbols

Term / Symbol Definition Stripline Outer layer traces routed a fixed distance above an internal plane layer

Asymmetric Inner layer signal traces, mounted a fixed distance to a Primary Reference Microstrip Plane (H1 or H3 in the figure below) and mounted a larger distance to a Secondary Reference Plane (H2 or H4 in the figure) H Distance (or “height”) of a trace to the reference plane(s) – H0, H1, H2 etc. in the figure W The width of the trace. Outer layer traces generally need to be a bit wider than inner layer traces to meet the same impedance. It is best to arrange that all inner layer traces for a given impedance class have the same width. T The thickness of the trace. Inner layer traces are generally thinner than outer layer traces. G The gap (or space) between two traces that are part of an edge-coupled differential pair. P The pitch (or center-to-center distance) between two traces that are part of an edge-coupled differential pair.

P = G + W for a given differential pair.

A fairly common mistake in PCB design and fabrication is to get the pitch and the gap confused. Clearance (Not shown in the figure) The distance to “other” traces and features (vias, holes, pours) on the same layer The dielectric constants of the materials used in the PCB construction  Trace impedance Zo

Single Ended – trace that is single ended, not part of a differential pair SE Differential Ended – trace pair that are used for differential signaling DE

Figure 81 PCB Cross Section – Striplines and Asymmetric Microstrips

Stripline Traces

Trace Trace L1 - copper

Prepreg - Dielectric H0 

PLANE L2 - copper

W H1  Core - Dielectric

G Trace Trace T L3 - copper

P H4

 Prepreg - Dielectric Asymmetric Microstrip Traces

Trace Trace L4 - copper

Core - Dielectric H3 

PLANE L5 - copper

 Prepreg - Dielectric

Trace Trace L6 - copper

11.2 Differential Pair Cautions

Modern high speed interfaces (CSI, GBE, HDMI, LCD LVDS, PCIe, SATA and USB) must be routed as differential pairs over a ground plane. They should be routed as a pair on the same layer (edge-coupled pairs) and not as pairs on different layers (known as broad-side coupled pairs) that follow the same X-Y path. There should be a minimum of layer transitions – ideally, just two (SMARC connector to internal layer, and internal layer to the destination connector or IC).

For edge coupled differential pairs, there are several parameters of interest:

 Differential impedance: the impedance of the trace pair as seen by a differential driving source.

 Single impedance: the impedance of one of the traces in the pair, if it were removed from the pair and driven by a single ended source.

 Gap: the inside edge to inside edge spacing between the traces in a differential pair. Labeled ‘G’ in the figure above.

 Pitch: the center-to-center distance between the pairs in a differential pair. Labeled ‘P’ in the figure above.

It is fairly common for people to mix up the Gap and the Pitch. Make sure you don’t make this mistake.

11.3 General Routing Rules and Cautions

 High speed differential signals must be routed as differential pairs. o Keep the pairs symmetrical o Stubs are not allowed o Avoid tight (right angle) bends o Match the pair lengths, on each layer used  Routing with reference to a GND plane is preferred: o If GND plane referencing is not possible, then routing against a well bypassed power plane will have to suffice.  Do not route over plane splits.  Layer transitions should be minimized. Ideally, there are a maximum of two vias per net: a transition at the SMARC connector to get to an inner layer, and a transition at the destination device, to get to the device pins.  If a layer change is made and the layer change results in a reference plane change, then the two reference planes should be tied together in the same vicinity as the trace layer via. If the two reference planes are at different potentials, then they should be tied together through a “stitching capacitor”. The stitching cap isolates the DC potential between the planes but allows the high speed return currents associated with the trace. If the two reference planes are at the same potential, then they should be tied together with a “stitching via” – a seemingly useless via, except that it allows the high frequency trace return currents to flow between the reference planes. Following this advice results in lower EMI (as “loop area” is reduced) and better signal integrity.  Controlled impedance design must be used: o All traces have a single ended (SE) impedance. o Differential pair traces have a SE impedance, and the pair has a differential (DE) impedance. o Recommended SE and DE impedances are given in the following sections of this Design Guide.  Differential pairs have pair matching requirements (the two traces that make up a pair need to be matched to a certain tolerance). There are also group matching requirements: if more than one pair is needed for the function, then there are group matching requirements as well (for example LVDS[0]+/- needs to match LVDS[1]+/1 and LVDS[2]+/- and so on).  The propagation speed of inner layer traces and outer layer traces is different.  Differential pairs that are part of a common group (for example, the four LVDS data pairs in a 24 bit LVDS implementation) should be routed such that each pair in the group has the same per- layer routing length as the others.  Routing on inner layers may reduce EMI. It is said that good EMI characteristics may be obtained by careful outer layer routing as well.  Routing high speed traces across plane splits should be avoided. If it cannot be avoided, then stitching caps to bridge the split should be used.  Cross-talk effects result from traces running in parallel, too close and for too long, either side by side on the same layer, or directly above / beneath each other on adjacent inner layers. For the same layer case, the mitigation is to increase the spacing to other traces. For the adjacent layer case, the traces on the adjacent layers should not run in parallel. Ideally, they are routed orthogonal to each other. If orthogonal routing is not possible, they should be at least 30 degrees off from each other.  IC power pins need to be properly bypassed, as close as possible to the power pin.

11.4 Trace Parameters for High-Speed Differential Interfaces

Routing rules for high speed differential traces are summarized in the table below. Some notes on the table:

 The “Max Symbol Rate” in the chart below is not the data transfer rate. It is the maximum transition rate on a single differential pair of the link, including the link encoding overhead. o For example: 24 bit LCD LVDS is packed into four lanes. Including the control bits, there are actually 28 bits packed into the four LVDS lanes. There is no encoding overhead in LCD LVDS – it is just raw data – because there is a separate LVDS clock. So the “symbol rate” on an LVDS differential data pair, for a 40 MHz LVD clock, is (28 bits x 40 MHz / 4 lanes) = 280 Mbps.  The “Sym Width” is the width of the pair Symbol, in ps. It is the inverse of the Max Symbol Rate. o Recall that the propagation speed of a micro-strip (outer layer) trace signal is about 150 ps / inch, and for a stripline (inner layer) trace signal, about 180 ps / inch. o The differential pair length mis-match, when expressed in units of time, needs to be small compared to the Symbol Width.  Lengths are shown in mils (thousandths of an inch, or 0.0254 mm). The American convention for the decimal point and comma meaning is used. The 5,000 mil max length is 5.0 inches or 127 mm.  “Pair Match” refers to the length matching of the two parts of the differential pair.  Group Match refers to the length matching of the different pairs in a group.  N/A means “Not Applicable”.  “TX/RX Match” means the length matching between the TX and RX pairs.

Table 21 High-Speed Differential Trace Parameters

Interface Max Symbol Rate Sym Zo Zo Max Pair Group TX / RX (approximate) Width Diff SE Length Match Match Match

(ps) (ohms) (ohms) (mils) (mils) (mils) (mils) PCIe 8 Gbps (Gen 3) 125 85 50 5,000 < 5 N/A < 2000 5 Gbps (Gen 2) 200 (+-15%)  10,000 2.5 Gbps (Gen 1) 500 12,000 SATA 6 Gbps (Gen 3) 167 85 50 3,000 < 5 N/A < 2000 3 Gbps (Gen 2) 333 (+-20%) (+-15%) 6,000 1.5 Gbps (Gen 1) 667 8,000 HDMI 3.4 Gbps (HDMI 1.3) 294 90 45 5,000 < 10 < 830 N/A 1.6 Gbps (HDMI 1.2) 625 1.6 Gbps (HDMI 1.1) 625 1.6 Gbps (HDMI 1.0) 625 CSI 1 Gbps (CSI-2) 1000 90 45 9,000 < 100 < 100 N/A 208 Mbps (CSI) 4808 LVDS 770 Mbps (24b 110 MHz) 1299 100 50 6,750 < 20 < 20 N/A 280 Mbps (24b 40 MHz) 3571 (+-20%) USB 2.0 480 Mbps (HS) 2083 90 45 10,000 < 100 N/A N/A 12 Mbps (FS) 23333 USB 3.0 5 Gbps N/A 85 50 4,500 < 5 N/A N/A (+-10%) (+-15%) GBE 250 Mbps N/A 100 50 4,000 < 5 < 30 N/A DP++ 8.1 Gbps N/A 85 50 3,200 < 5 < 1000 N/A (+-10%) (+-10%)

Reference Plane: GND is preferred Clearance to other traces: 20 mil or more SMARC Design Guide 2.0 Page 116 of 119 Mar 23, 2017 ©SGeT e.V.

Max Vias: Three maximum; two or less preferred

11.5 Trace Parameters for Single Ended Interfaces

Table 22 Single Ended Trace Parameters

Interface Zo Max SE Length

(ohms) (mils) General 50 12,000 SD Card 50 4,000

11.6 PCB Construction Suggestions

PCB construction suggestions with trace width and gap parameters are given in the following three tables for four, six and eight layer PCBs. These are meant as a starting point. It is wise to plan ahead with your PCB fabricator and get their input.

Four layer construction is difficult since the high speed signals should be referenced against a GND plane, and the four layer construction offers only a single trace layer that is GND referenced.

Table 23 PCB Construction Example - 4 Layers

Layer Use Layer Copper Plane SE Diff Diff Diff Thickness Ref 50 Ohm 90 Ohm 92.5 Ohm 100 Ohm

(mils) (ounces) W (mils) W / G (mils) W / G (mils) W / G (mils) SM 0.8 L1 Sig Cu 1.6 0.5 + plating L2 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10 Prepreg 2.9 L2 PWR Cu 1.2 1.0

Core 50.0

L3 GND Cu 1.2 1.0 Prepreg 2.9 L4 Sig Cu 1.6 0.5 + plating L3 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10 SM 0.8

Finished Thickness: 63.0 mil Impedance tolerance: +/- 10%

Table 24 PCB Construction Example - 6 Layers

Layer Use Layer Copper Plane SE Diff Diff Diff Thickness Ref 50 Ohm 90 Ohm 92.5 Ohm 100 Ohm

(mils) (ounces) W (mils) W / G (mils) W / G (mils) W / G (mils) SM 0.8 L1 Sig Cu 1.6 0.5 + plating L2 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10 Prepreg 2.9 L2 PWR Cu 1.2 1.0 Core 3.0 L3 Sig Cu 0.6 0.5 L2/L5 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0

Prepreg 42.0

L4 Sig L6 0.6 0.5 L5/L2 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0 Core 3.0 L5 GND Cu 1.2 1.0 Prepreg 2.9 L6 Sig Cu 1.6 0.5 + plating L5 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10 SM 0.8

Finished Thickness: 62.2 mil Impedance tolerance: +/- 10%

The eight layer example below shows an 80 mil (2mm) PCB thickness. This is often desirable for Carrier boards, and can be arranged for the four, six or eight layer versions. The thicker PCB makes for a more rugged system: the stiffness of a sheet of material (PCB or other sheet material) is proportional to the cube of the material thickness.

The eight layer construction below offers the advantage of four signal layers (L1, L2, L6, L8) that are GND referenced. This is best for high speed signals. This construction also makes power distribution very easy.

The Pri/Sec notation in the Plane Ref column below means the following: the plane layer to which the signal is closest is the Primary reference plane. The further plane is the Secondary.

If a high speed signal or signal pair changes reference layers (for example, L6 is referenced to L7 and L3 is referenced to L2 - so if you transition from L6 to L3, you are changing reference planes) it is recommended to put in a stitching via or via pair. The stitching vias are single net vias (GND) that tie the two reference planes together (L2 to L6) for the high frequency return signals that are trying to follow the path of the signal traces. You will have better signal integrity and fewer EMI issues if you do this. It is not necessary if reference planes are not being changed (for example, a transition from L1 to L3 keeps both referenced to L2, hence there is no reference plane transition).

Table 25 PCB Construction Example – 8 Layers

Layer Use Layer Copper Plane SE Diff Diff Diff Thickness Ref 50 Ohm 90 Ohm 92.5 Ohm 100 Ohm

(mils) (ounces) Pri/Sec W (mils) W / G (mils) W / G (mils) W / G (mils) SM 0.8 L1 Sig Cu 1.6 0.5 + plating L2 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10 Prepreg 2.9 L2 GND Cu 1.2 1.0 Core 3.0 L3 Sig Cu 0.6 0.5 L2/L4 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0 Prepreg 10.0 L4 PWR Cu 1.2 1.0

Core 38.0

L5 PWR Cu 1.2 1.0 Prepreg 10.0 L6 Sig Cu 0.6 0.5 L7/L5 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0 Core 3.0 L7 GND Cu 1.2 1.0 Prepreg 2.9 L8 Sig Cu 1.6 0.5 + plating L7 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10 SM 0.8

Finished Thickness: 80.6 mil Impedance tolerance: +/- 10%