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Low-Power IP Blocks Prepare for 5G SEPTEMBER 2017 DesignNewswww.eedesignnewseurope.com electronics europe Design Low-power IP blocks prepare for 5G european business press Scalable Automotive Network Solutions Cost-Efficient • Real-Time • Flexible Microchip has been delivering robust, automotive-qualified CAN, LIN, Ethernet, MOST® technology and USB solutions to automotive suppliers for over ten years. Our MOST technology and USB solutions are the de facto standards for in-vehicle infotainment and consumer device connectivity worldwide. If your automotive design requires in-vehicle transport of audio, video, control or Ethernet packet data, we offer solutions which work reliably over UTP, coax and optical physical layers with guaranteed low latency. Software stacks are also available from Microchip, as well as third parties, allowing you to focus your efforts on application software development. Application Examples Body control Rear-view camera Top-view camera LTE/3G connectivity HMI Infotainment head unit Ambient LED lighting Exterior LED lighting Smart sensors www.microchip.com/automotive The Microchip name and logo, the Microchip logo and MOST are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks are the property of their registered owners. © 2017 Microchip Technology Inc. All rights reserved. MEC2155Eng04/17 COVER FEATUREARTICLES eeDn's columns ADC, RF-FE, low-power IP blocks 17 Maximize run time in automotive 4 EDN.comment battery stacks, as cells age Can we do better? for 5G comms by Samuel Nork and Tony Armstrong, 6 Pulse Belgium-based nano-electronics and digital Linear Technology “Superballistic” electron flow verified, in graphene; Heat technology research body imec has disclosed 21 Smarter power for the front-end of pipes integrated in PCB layers boost thermal performance; Intel’s Movidius Myriad X VPU hosts Neural Compute details of two key building blocks (as IP) for the internet of things Engine; Embedded FTP server for simple data exchange; future 5G applications featuring record low by Eric Djakam, Texas Instruments Power management is key to Qualcomm’s 10nm, 48 core power consumption; an ADC and a 60-GHz RF 23 Simulation-derived FIT rates improve ARM server chip; USB scopes gain automated waveform front-end. failure analysis accuracy analysis & tabulation; Automotive Grade Linux speeds The first IP block is a fast and compact by Viktor Preis, Frederico Ferlini & in-car infotainment developments; TI packages DLP Pico projector display tech for low-cost processors; “5G RF successive approximation analogue-to-digital Robert Schweiger, Cadence For Dummies” E-Book; Cypress smart home platform converter, for smartphone applications in the 26 Eight steps to better ADAS software gets an ear for Siri; Secure Cortex-M4F MCU integrates below-6GHz band; the compact, low-cost, by Dr. Alexander Hertz, Tasking, & Mark contactless interface; Mesh networking capability added low-power and high-speed (300 Msample/ Forbes, Altium to Bluetooth sec) ADC (pictured on the cover page) meets 29 5G challenges demand a new kind of 19 Analog Tips the requirements of multimode multiband 5G processor A dual-channel ADC… or is it a quad? by Umesh Jayamohan, Analog Devices communication. The ADC has a reduced core by Emmanuel Gresset, CEVA Online – Memory Matters area of 350 x 325 µm when fabricated in 16- 32 Micro-Ohms make the difference 2017 Silicon Valley Flash Memory Summit Survives the Fire nm CMOS. It achieves a dynamic low power in MOSFETs for critical automotive and; consumption of 3.6 mW at 300 Msample/sec applications QLC NAND takes storage to the next level and low-frequency signal to noise and distortion by Georges Tchouangue & Eiji Shimada, by William Wong, Electronic Design ratio (SNDR) of 70.2 dB at 204 Msample/sec. Toshiba Electronics Europe 33 Product Roundup The compact, energy efficient and low-cost radio TinyCircuits’ mini open-source functional blocks; IP cores front-end (TRX) operates at 60GHz. The chip for video bridging in FPGA; Power inductor terminations features 8-way calibration-free beamforming ONLINE THIS MONTH aid AOI & 3D PCBs; System-on-module, smallest with i.MX6ULL; 2A, 2MHz, 60V multi-mode step-up DC/DC; at RF frequencies to support a large number of Motor-driver IC PCB layout guidelines (Part 1) Powering datacentres & ‘microgrids’ from HV DC; 14- antennas, making the technology attractive for Motor-driver IC PCB layout guidelines, Part 2 bit, bipolar input, dual simultaneous sampling ADC DAS; fixed wireless access and small cell backhaul. Differential current sensor IC combines accuracy & 4.8 Interview: Refined ReRAM enters the storage wars The on-chip transmit-receive switching allows kV isolation; 100W, 1/32nd-brick DC-DC; Wireless power Over-the-air BLE test systems solve demo sends 33W; Voice capture kit accesses Alexa sharing of the antenna array between transmit wireless quality issues 2 Voice Service; High-side, 76V current sense amp uses and receive mode. The 9.6 mm chip is Virtualised ECUs with Renesas R-Car: small shunts; Linear FET combines low RDS(on) with implemented in 28 nm CMOS and consumes new challenges and opportunities large SOA; FPGA-to-fibre 14 Gbps FMC kit; 20V, 20A 231 mW in receive and 508 mW in transmit Prevent overloads with safety capacitors: monolithic synchronous buck regulator; 32 x 8 x 2.75 mm mode (0.9V supply). Full item here. a 12-point checklist power-on-package regulator for high-current processors 3 DesignNews SEPTEMBER 2017 www.eedesignnewseurope.com Can we do better? DesignNews by Graham Prophet, Editor EUROPE am often asked why I harbour a certain amount intent. Step 2 - transfer that into a format that is also the question of where and when the of negative sentiment about the software still looks and reads like plain language, but with design takes place. We have always, on this designI process. A simplistic answer might be; a restricted vocabulary in which every terms publication, prized the process of design; but look at the big picture; consider the plethora has a precise meaning: a very (very) high level we have a situation where, if we are honest, we of tools, analysis software, and checkers of programming language, if you like. From that should admit that a significant proportion of all sorts that are on offer in the market. Any point on, no human intervention is allowed; by software projects are hardly designed at all. They process which requires that much inspection however many steps it takes, and with formal are executed ad-hoc, such design processes and rectification to reach its goals must have a verification at each stage, a hierarchy of tools as do exist being carried out on-the-fly as the question mark against its fitness for purpose. would take the code to an executable form, fully job proceeds. The result is then bug-fixed and Contrast the process within the hardware automated. Changes allowed only by returning to massaged until it more-or-less works, and is domain. We have been designing ICs for the highest, plain-language level. released, with the comfort blanket that software about as long as we have been working with EDA offers the user an unspoken pact. It says, is infinitely fixable, and there’s always another compiled language computing. Faced with the “do only things that the automatics understand release. The fact that in the IoT world fixes are consequences of Moore’s Law, EDA has evolved and can handle, and together we can crank out even easier, as every product holds its code in a hierarchical approach that abstracts the design something that stands a chance of working.” flash and allows over-the-air updates, simply activity away from the low-level detail, and that No such deal is on offer to the software coder: adds to the pressure to sign-off version 1.0 – and makes (some sort of) an attempt at correct-by- by contrast, the software world has prized the stores up problems for the connected world we construction flow. It’s still a long, long way from freedom to do anything and everything that are creating. flawless algorithm-in/geometry-out, but it at can conceivably be coded. Which leads to Right now, there is an added risk in the “teach least has aspirations in that direction. Coding, by the situation that, after over half a century of our kids to code” movement, compounded by contrast, has gone almost nowhere; the Fortran compiled-language computing, you cannot – technically-illiterate politicians leaping on the writer of 1957 would find much of C, 60 years in the most commonly-used language in the bandwagon, with no understanding that the key later, immediately familiar. (C++, to be fair, might embedded space – tell a computing device to engineering skills are applied more in the sitting- take him/her a day or two.) add two numbers without first laboriously telling and-thinking phase (we used to give it labels What – you might well ask – would a more it what sort of numbers they are going to be, and such as ‘systems analysis’) than in the coding optimum flow look like? I imagine something like carefully specifying where they should be stored. itself. this (which I recognise is hopelessly idealised); Is it appropriate to ask, “what’s wrong with this To crystallise the second of these concerns; we Step 1 - write the architectural description in picture?” should be carrying out our creativity in sentences plain language, followed by a long period of Accepting that programmers are not likely to that end with a (.) Whereas we are encouraged, contemplation and consideration of whether happily accept working in a more constrained and even compelled, to do so in sentences that that description correctly captures the design space, and as I have written here before, there end with (;) 4 DesignNews SEPTEMBER 2017 www.eedesignnewseurope.com Model 71861 4-Channel 200 MHz A/D with DDC, Kintex UltraScale FPGA - XMC Features I Complete radar and software radio interface solution I Supports Xilinx Kintex UltraScale FPGAs I Four 200 MHz 16-bit A/Ds I Four multiband DDCs (digital downconverters) I Optional 5 GB of DDR4 SDRAM I Sample clock synchronization to an external system reference I LVPECL clock/sync bus for multimodule synchronization I PCI Express (Gen.
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