DOCSLIB.ORG

On Using the System Management Mode for Security Purposes

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
On Using the System Management Mode for Security Purposes On Using the System Management Mode for Security Purposes William Augusto Rodrigues de Souza Thesis submitted to the University of London for the degree of Doctor of Philosophy 2016 On Using the System Management Mode for Security Purposes Department of Mathematics Royal Holloway, University of London Seeing much, suffering much and studying much are the three pillars of learning. (Benjamin Disraeli) Declaration of Authorship I, William Augusto Rodrigues de Souza, hereby declare that this thesis and the work presented in it is entirely my own. Where I have consulted the work of others, this is always clearly stated. Signed: (William Augusto Rodrigues de Souza) Date: Summary Computer systems are by design insecure and therefore are many security issues around them. So, security practitioners are always trying to enhance security and performing verification tasks to minimise the risk of potential threats become suc- cessful attacks. These tasks are usually performed by security tools. Thus concepts as: isolation, privilege and view are important in the context of computer systems. Security tools must have good isolation, privilege and view of the system. Then, security tools must operate isolated, have high privilege and must have a global view of the system, but also good ability to view and act timely in its own environment to enhance the chances of success when performing their tasks and for not being hit by the problems they are trying to solve. In this context, this research investigates the System Management Mode (SMM) in the context of Intel processors, current security tools capitalising on SMM and attacks and misuses of SMM to establish a set of requirements and then design a generic architecture for SMM-based security tools. That generic architecture is tested by building a proof of concept to measure the integrity of a file of the Xen hypervisor. This measurement is limited to the minimum necessary to prove the concept of the architecture. The problem context addressed is a cloud computing environment, compris- ing of one or more machines (chipsets). Each chipset hosts in its main memory (DRAM) a virtualised environment comprising of one manager virtual machine, one or more guest virtual machines and a hypervisor. We address our research in- vestigation in two levels: the vertical and the horizontal security level. The vertical security level puts the problem in context, relating it to security issues on: cloud, chipset, memory, virtualisation layer and cache memory. The horizontal security level considers the research problem in its environment, relating it to security is- sues on components of the bootup process and the processor, such as: Intel VMX, TXT and SGX, BIOS and so on. First, we investigate the SMM, its resources and components. Then, we analyse SMM-based security tools and the opportunities to improve them. We also analyse SMM attacks and how to thwart them. From the acquired knowledge, we establish a set of requirements to use SMM for security purposes. Having the requirements, we design a generic architecture for SMM-based security tools. To test the architec- ture, we build a proof of concept comprising of a module to probe chipsets and a SMM-based hypervisor integrity measurement tool. The implementation of that architecture was done in a proof of concept de- signed to have two modules: a manager and an agent. The manager module is used for learning about and researching on the target machine, as for probing, set- ting and clearing registers related to SMM. The manager can be used in the target i machine or in a machine with the same chipset of the target machine. So, it can be deployed in main memory. The agent basically comprises of two parts: a basic code embodying management functions and a payload, where the security functions are implemented. So the use of a payload is what makes the architecture generic since any security task might be implemented and added in the agent by changing the payload. We conclude that any security tool can capitalising on SMM resources provided that it meets the set of requirements established in this research: small, fast, per- sistent, cooperative, isolated, resistant, complete and SMI-independent (meaning that it can be started by any System management interruption, which occur in the chipset); and stick to the proposed generic architecture. ii Acknowledgments My heartfelt thanks to my supervisor Dr. Allan Tomlinson for his guidance, encourage- ment, patience and dedication. I would like to also thank my examiners Professor William Buchanan and Professor Lorenzo Caballaro for taking the time to examine my thesis. I gratefully acknowledge all professors, specially Professors Chris Mitchell and Carlos Cid, colleagues and staff at ISG and at the Department of Mathematics for making my life easier and for all support, guidance and fruitful discussions. I would like to also thank all support and encouragement I received from The Centre for Naval System Analysis of Brazilian Navy. I am also so grateful for all support and understanding received from my family. iii Contents 1 Introduction1 1.1 Motivation.................................. 1 1.2 Limits and Scope .............................. 3 1.3 Significance ................................. 8 1.4 Research Questions............................. 9 1.5 Contribution................................. 11 1.6 List of Publications............................. 12 1.7 Overview of the Research ......................... 13 2 Background 15 2.1 Introduction................................. 15 2.2 Definitions.................................. 17 2.3 Context and Technologies ......................... 19 2.4 Environment and Technologies...................... 35 2.5 Data Integrity with Hash Functions.................... 39 2.6 Related work: System Executive Software Integrity Issues . 40 2.7 Discussion.................................. 43 2.8 Summary................................... 44 3 The System Management Mode (SMM) 45 3.1 Introduction................................. 45 3.2 Components................................. 46 3.3 SMM operation and relations ....................... 54 3.4 Security implementations using SMM.................. 58 3.5 Launching attacks using SMM resources................. 62 3.6 Discussion.................................. 66 3.7 Summary................................... 66 4 Requirements 69 4.1 Introduction................................. 69 4.2 Threat model................................. 69 4.3 Assumptions................................. 72 4.4 Requirements for using SMM for security purposes.......... 72 4.5 Discussion.................................. 74 4.6 Summary................................... 76 5 A Generic Architecture for SMM-Based Security Tools 79 5.1 Introduction................................. 79 v CONTENTS 5.2 Requirements Specification ........................ 79 5.3 General Architecture............................ 82 5.4 Architecture Design............................. 82 5.5 Discussion.................................. 97 5.6 Summary................................... 99 6 Implementation and Evaluation - Manager Module and SBST 105 6.1 Introduction.................................105 6.2 Functions in the Manager Module ....................108 6.3 Manager Module Computational Experiments . 117 6.4 SBST Implementation and Evaluation ..................130 6.5 SBST Limits and Constraints........................132 6.6 Manager Limits and Constraints .....................133 6.7 Discussion..................................133 6.8 Summary...................................133 7 Conclusion 135 7.1 Directions for Future work.........................137 7.2 Investigate the interaction of an SBST with technologies in the chipset137 7.3 Investigate the Impact of SMI Latency..................137 7.4 Optimize the Proof of Concept Execution Time . 138 7.5 Embed the Tool in a BIOS to Test It in a More Realistic Scenario . 138 A Specific SMM Registers 139 A.1 Chipset 1 Specific Registers ........................139 A.2 Chipset 2 System Management RAM Control register . 148 Bibliography 155 vi List of Figures 1.1 Machine and Chipset 1............................. 4 1.2 Machine and Chipset 2............................. 5 1.3 First set of machines used in the experiments................ 5 1.4 Second set of Machines used in the experiments .............. 6 1.5 General architecture .............................. 8 2.1 Security Context................................. 16 2.2 The Cloud Reference Model (figure from [131])............... 21 2.3 Virtualisation Layer............................... 24 2.4 Consolidation.................................. 24 2.5 Containment................................... 25 2.6 Full virtualisation (figure from[140])..................... 28 2.7 Paravirtualisation (figure from [140])..................... 29 2.8 Hardware-assisted virtualisation (figure from [140])............ 30 2.9 Xen Architecture ................................ 31 2.10 Intel Hub Architecture, based on [57]..................... 32 2.11 The Intel Platform Controller Hub ...................... 33 2.12 Ring security scheme, based on [57] ..................... 35 2.13 The PI and UEFI layers, based on [153].................... 37 2.14 TPM Overview (figure from [54]) [57] .................... 39 3.1 SMM components................................ 47 3.2 SMRAM space for 32-bit machines...................... 48 3.3 SMRAM space for 64-bit machines...................... 49 3.4 SMRAM control register...........................
Load more

Recommended publications
  • Intel's SL Enhanced Intel486(TM) Microprocessor Family
    Intel's SL Enhanced Intel486(TM) Microprocessor Family http://www.intel.com/design/intarch/applnots/7014.htm Intel's SL Enhanced Intel486(TM) Microprocessor Family Intel's SL Enhanced Intel486™ Microprocessor Family Technical Backgrounder June 1993 Intel's SL Enhanced Intel486™ Microprocessor Family With the announcement of the SL Enhanced Intel486™ microprocessor family, Intel Corporation brings energy efficiency to its entire line of Intel486™ microprocessors. SL Technology, originally developed for mobile PCs, now provides superior power-management features for desktop computer systems. Such energy-efficient systems will be designed to meet or exceed the Energy Star guidelines set by the Environmental Protection Agency. The EPA's Energy Star program is aimed at reducing power consumption of desktop computer systems, thereby reducing their impact on the environment. In addition, SL Enhanced Intel486™ microprocessors will enable a new class of notebook systems -- high-performance Intel486™ DX2 CPU-based notebooks with color displays that do not sacrifice battery life. The SL Enhanced Intel486™ microprocessor family is available in a complete range of price/performance, package and voltage options. This flexibility allows PC makers to develop products that meet the mobile and desktop needs of all their customers in the mobile and desktop markets, from low-cost, entry-level Intel486™ SX microprocessor-based systems to high-performance, high-end Intel486™ DX2 microprocessor-based systems. Since the SL Technology in SL Enhanced Intel486™ microprocessors is the same as in Intel SL CPUs, computer manufacturers with prior experience developing systems based on existing SL BIOS will be able to incorporate System Management Mode's (SMM) power-management features into new systems.
    [Show full text]
  • Rochyderabad 27072017.Pdf
    List of Companies under Strike Off Sl.No CIN Number Name of the Company 1 U93000TG1947PLC000008 RAJAHMUNDRY CHAMBER OF COMMERCE LIMITED 2 U80301TG1939GAP000595 HYDERABAD EDUCATIONAL CONFERENCE 3 U52300TG1957PTC000772 GUNTI AND CO PVT LTD 4 U99999TG1964PTC001025 HILITE PRODUCTS PVT LTD 5 U74999AP1965PTC001083 BALAJI MERCHANTS ASSOCIATION PRIVATE LIMITED 6 U92111TG1951PTC001102 PRASAD ART PICTURES PVT LTD 7 U26994AP1970PTC001343 PADMA GRAPHITE INDUSTRIES PRIVATE LIMITED 8 U16001AP1971PTC001384 ALLIED TOBBACCO PACKERS PVT LTD 9 U63011AP1972PTC001475 BOBBILI TRANSPORTS PRIVATE LIMITED 10 U65993TG1972PTC001558 RAJASHRI INVESTMENTS PRIVATE LIMITED 11 U85110AP1974PTC001729 DR RANGARAO NURSING HOME PRIVATE LIMITED 12 U74999AP1974PTC001764 CAPSEAL PVT LTD 13 U21012AP1975PLC001875 JAYALAKSHMI PAPER AND GENERAL MILLS LIMITED 14 U74999TG1975PTC001931 FRUTOP PRIVATE LIMITED 15 U05005TG1977PTC002166 INTERNATIONAL SEA FOOD PVT LTD 16 U65992TG1977PTC002200 VAMSI CHIT FUNDS PVT LTD 17 U74210TG1977PTC002206 HIMALAYA ENGINEERING WORKS PVT LTD 18 U52520TG1978PTC002306 BLUEFIN AGENCIES AND EXPORTS PVT LTD 19 U52110TG1979PTC002524 G S B TRADING PRIVATE LIMITED 20 U18100AP1979PTC002526 KAKINADA SATSANG SAREES PRINTING AND DYEING CO PVT LTD 21 U26942TG1980PLC002774 SHRI BHOGESWARA CEMENT AND MINERAL INDUSTRIES LIMITED 22 U74140TG1980PTC002827 VERNY ENGINEERS PRIVATE LIMITED 23 U27109TG1980PTC002874 A P PRECISION LIGHT ENGINEERING PVT LTD 24 U65992AP1981PTC003086 CHAITANYA CHIT FUNDS PVT LTD 25 U15310AP1981PTC003087 R K FLOUR MILLS PVT LTD 26 U05005AP1981PTC003127
    [Show full text]
  • Over View of Microprocessor 8085 and Its Application
    IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 6, Ver. II (Nov - Dec .2015), PP 09-14 www.iosrjournals.org Over view of Microprocessor 8085 and its application Kimasha Borah Assistant Professor, Centre for Computer Studies Centre for Computer Studies, Dibrugarh University, Dibrugarh, Assam, India Abstract: Microprocessor is a program controlled semiconductor device (IC), which fetches, decode and executes instructions. It is versatile in application and is flexible to some extent. Nowadays, modern microprocessors can perform extremely sophisticated operations in areas such as meteorology, aviation, nuclear physics and engineering, and take up much less space as well as delivering superior performance Here is a brief review of microprocessor and its various application Key words: Semi Conductor, Integrated Circuits, CPU, NMOS ,PMOS, VLSI I. Introduction: Microprocessor is derived from two words micro and processor. Micro means small, tiny and processor means which processes something. It is a single Very Large Scale of Integration (VLSI) chip that incorporates all functions of central processing unit (CPU) fabricated on a single Integrated Circuits (ICs) (1).Some other units like caches, pipelining, floating point processing arithmetic and superscaling units are additionally present in the microprocessor and that results in increasing speed of operation.8085,8086,8088 are some examples of microprocessors(2). The technology used for microprocessor is N type metal oxide semiconductor(NMOS)(3). Basic operations of microprocessor are fetching instructions from memory ,decoding and executing them ie it takes data or operand from input device, perform arithmetic and logical operations and store results in required location or send result to output devices(1).Word size identifies the microprocessor.E.g.
    [Show full text]
  • Appendix D an Alternative to RISC: the Intel 80X86
    D.1 Introduction D-2 D.2 80x86 Registers and Data Addressing Modes D-3 D.3 80x86 Integer Operations D-6 D.4 80x86 Floating-Point Operations D-10 D.5 80x86 Instruction Encoding D-12 D.6 Putting It All Together: Measurements of Instruction Set Usage D-14 D.7 Concluding Remarks D-20 D.8 Historical Perspective and References D-21 D An Alternative to RISC: The Intel 80x86 The x86 isn’t all that complex—it just doesn’t make a lot of sense. Mike Johnson Leader of 80x86 Design at AMD, Microprocessor Report (1994) © 2003 Elsevier Science (USA). All rights reserved. D-2 I Appendix D An Alternative to RISC: The Intel 80x86 D.1 Introduction MIPS was the vision of a single architect. The pieces of this architecture fit nicely together and the whole architecture can be described succinctly. Such is not the case of the 80x86: It is the product of several independent groups who evolved the architecture over 20 years, adding new features to the original instruction set as you might add clothing to a packed bag. Here are important 80x86 milestones: I 1978—The Intel 8086 architecture was announced as an assembly language– compatible extension of the then-successful Intel 8080, an 8-bit microproces- sor. The 8086 is a 16-bit architecture, with all internal registers 16 bits wide. Whereas the 8080 was a straightforward accumulator machine, the 8086 extended the architecture with additional registers. Because nearly every reg- ister has a dedicated use, the 8086 falls somewhere between an accumulator machine and a general-purpose register machine, and can fairly be called an extended accumulator machine.
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Iocheck: a Framework to Enhance the Security of I/O Devices at Runtime
    IOCheck: A Framework to Enhance the Security of I/O Devices at Runtime Fengwei Zhang Center for Secure Information Systems George Mason University Fairfax, VA 22030 [email protected] Abstract—Securing hardware is the foundation for implement- Management Mode (SMM), a CPU mode in the x86 archi- ing a secure system. However, securing hardware devices remains tecture, to quickly check the integrity of I/O configurations an open research problem. In this paper, we present IOCheck, and firmware. Unlike previous systems [11], [12], IOCheck a framework to enhance the security of I/O devices at runtime. enumerates all of the I/O devices on the motherboard, and It leverages System Management Mode (SMM) to quickly check checks the integrity of their corresponding configurations and the integrity of I/O configurations and firmware. IOCheck does not rely on the operating system and is OS-agnostic. In our firmware. IOCheck does not rely on the operating system, preliminary results, IOCheck takes 4 milliseconds to switch to which significantly reduces the Trust Computing Base (TCB). SMM which introduces low performance overhead. In addition, IOCheck is able to achieve better performance compared to TXT or SVM approaches. For example, the SMM Keywords—Integrity, Firmware, I/O Configurations, SMM switching time is much faster than the late launch method in Flicker [10], [13]. We will demonstrate that IOCheck is able to check the integrity of array of I/O devices including the BIOS, I. INTRODUCTION IOMMU, network card, video card, keyboard, and mouse. With the increasing complexity of hardware devices, Contributions. The purpose of this work is to make the firmware functionality is expanding, exposing new vulner- following contributions: abilities to attackers.
    [Show full text]
  • A Simulator for the Intel 8086 Microprocessor
    Rochester Institute of Technology RIT Scholar Works Theses 1988 A Simulator for the Intel 8086 microprocessor William A. Chapman Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Chapman, William A., "A Simulator for the Intel 8086 microprocessor" (1988). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. A SIMULATOR FOR THE INTEL 8086 MICROPROCESSOR by William A. Chapman A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering Approved by: Professor Ken Hsu ':"(':":T~h":"e~sJ.';":·S=--=-A-d'=""v-i:-s-o-r-)------- Professor James R. Schueckler Professor _~~ _ Professor __~__:--:~-=- _ (Department Head) DEPARTMENT OF ELECTRICAL ENGINEERING COLLEGE OF ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY ROCHESTER, NEW YORK MAY, 1988 Abstract This project was originally suggested by J. Schueckler as an aid to teaching students the Intel 8086 Assembly Language. The need for such a tool becomes apparent when one considers the expense of providing students with dedicated hardware that rapidly becomes obsolete, but a Simulator which could be easily updated and runs on a general purpose or timesharing computer system would be accessible to many students for a fraction of the cost. The intended use of the Simulator therefore dictated that it precisely model the hardware, be available on a multiuser system and run as efficiently as possible.
    [Show full text]
  • Lambert-Mastersreport-2016
    Copyright by Timothy Michael Lambert 2016 The Report Committee for Timothy Michael Lambert Certifies that this is the approved version of the following report: Enterprise Platform Systems Management Security Threats and Mitigation Techniques APPROVED BY SUPERVISING COMMITTEE: Supervisor: Suzanne Barber Elie Jreij Enterprise Platform Systems Management Security Threats and Mitigation Techniques by Timothy Michael Lambert, B.S.E.E., M.B.A. Report Presented to the Faculty of the Graduate School of The University of Texas at Austin in Partial Fulfillment of the Requirements for the Degree of Master of Science in Engineering The University of Texas at Austin December 2016 Dedication For Jake Lambert, whose life and passing spurned the author’s commitment to enter and dedication to complete this degree program. Acknowledgements I would like to express special thanks to my family and employer, Dell Technologies, Inc., for allowing me the time to pursue my educational and professional interests via this superb graduate program. Additionally, I would like to thank my supervisor, Dr. Suzanne Barber, and reader, Elie Jreij, who is a professional mentor in this research area. v Abstract Enterprise Platform Systems Management Security Threats and Mitigation Techniques Timothy Michael Lambert, MSE The University of Texas at Austin, 2016 Supervisor: Suzanne Barber Developers and technologists of enterprise systems such as servers, storage and networking products must constantly anticipate new cybersecurity threats and evolving security requirements. These requirements are typically sourced from marketing, customer expectations, manufacturing and evolving government standards. Much ongoing major research focus has been on securing the main enterprise system purpose functionality, operating system, network and storage.
    [Show full text]
  • Broadwell Skylake Next Gen* NEW Intel NEW Intel NEW Intel Microarchitecture Microarchitecture Microarchitecture
    15 лет доступности IOTG is extending the product availability for IOTG roadmap products from a minimum of 7 years to a minimum of 15 years when both processor and chipset are on 22nm and newer process technologies. - Xeon Scalable (w/ chipsets) - E3-12xx/15xx v5 and later (w/ chipsets) - 6th gen Core and later (w/ chipsets) - Bay Trail (E3800) and later products (Braswell, N3xxx) - Atom C2xxx (Rangeley) and later - Не включает в себя Xeon-D (7 лет) и E5-26xx v4 (7 лет) 2 IOTG Product Availability Life-Cycle 15 year product availability will start with the following products: Product Discontinuance • Intel® Xeon® Processor Scalable Family codenamed Skylake-SP and later with associated chipsets Notification (PDN)† • Intel® Xeon® E3-12xx/15xx v5 series (Skylake) and later with associated chipsets • 6th Gen Intel® Core™ processor family (Skylake) and later (includes Intel® Pentium® and Celeron® processors) with PDNs will typically be issued no later associated chipsets than 13.5 years after component • Intel Pentium processor N3700 (Braswell) and later and Intel Celeron processors N3xxx (Braswell) and J1900/N2xxx family introduction date. PDNs are (Bay Trail) and later published at https://qdms.intel.com/ • Intel® Atom® processor C2xxx (Rangeley) and E3800 family (Bay Trail) and late Last 7 year product availability Time Last Last Order Ship Last 15 year product availability Time Last Last Order Ship L-1 L L+1 L+2 L+3 L+4 L+5 L+6 L+7 L+8 L+9 L+10 L+11 L+12 L+13 L+14 L+15 Years Introduction of component family † Intel may support this extended manufacturing using reasonably Last Time Order/Ship Periods Component family introduction dates are feasible means deemed by Intel to be appropriate.
    [Show full text]
  • A Viga T Ing R T Ificia L N Te Ll Igence
    July 24, 2018 Semiconductor Get real with artificial intelligence (AI) "Seriously, do you think you could actually purchase one of my kind in Walmart, say in the next 10 years?" NTELLIGENCE I "You do?! You'd better read this report from RTIFICIAL RTIFICIAL cover to cover, and I assure you Peter is not being funny at all this time." A ■ Fantasies remain in Star Trek. Let’s talk about practical AI technologies. ■ There are practical limitations in using today’s technology to realise AI elegantly. ■ AI is to be enabled by a collaborative ecosystem, likely dominated by “gorillas”. ■ An explosion of innovations in AI is happening to enhance user experience. ■ Rewards will go to the problem solvers that have invested in R&D ahead of others. Analyst(s) AVIGATING AVIGATING Peter CHAN T (82) 2 6730 6128 E [email protected] N IMPORTANT DISCLOSURES, INCLUDING ANY REQUIRED RESEARCH CERTIFICATIONS, ARE PROVIDED AT THE Powered by END OF THIS REPORT. IF THIS REPORT IS DISTRIBUTED IN THE UNITED STATES IT IS DISTRIBUTED BY CIMB the EFA SECURITIES (USA), INC. AND IS CONSIDERED THIRD-PARTY AFFILIATED RESEARCH. Platform Navigating Artificial Intelligence Technology - Semiconductor│July 24, 2018 TABLE OF CONTENTS KEY CHARTS .......................................................................................................................... 4 Executive Summary .................................................................................................................. 5 I. From human to machine .......................................................................................................10
    [Show full text]
  • Intel® E7501 Chipset for Embedded Computing
    Product Brief Intel® E7501 Chipset for Embedded Computing Product Overview The Intel® E7501 chipset represents the next step in high-performance chipset technology, supporting single- and dual-processor platforms optimized for the Intel® Xeon™ processor and Low Voltage Intel® Xeon™ processor. It also supports uni-processor platforms optimized for the Intel® Pentium® M processor. The design delivers maximized system bus, memory, and I/O bandwidth to enhance performance, scalability, and end-user productivity while providing a smooth transition to next-generation technologies. Features that Maximize Performance of an Intel® E7501 Chipset-based Platform I Dual Intel Xeon processors and a 400/533 MHz I Single or dual DDR266 memory channels system bus provide up to 4.3 GB/s of available provide up to 4.3 GB/s of memory bandwidth bandwidth I Three hub interface 2.0 connections provide Intel in I Intel Pentium M processors and a 400 MHz multiple high-bandwidth I/O configuration Communications system bus provide up to 3.2 GB/s of available options, yielding up to 3.2 GB/s of I/O bandwidth bandwidth Features Benefits Supports one or two Intel® Xeon™ processors I Intel® NetBurst™ microarchitecture and the Hyper-Threading Technology of or Low Voltage Intel® Xeon™ processors the Intel Xeon processor combine to deliver world-class performance. Supports one Intel® Pentium® M processor I New microarchitecture supports low power and high performance. 400/533 MHz system bus capability I Up to 4.3 GB/s system bus bandwidth for increased memory and I/O throughput. Intel hub architecture 2.0 connection I Point-to-point connection between the MCH and up to three P64H2 hub to the Memory Controller Hub (MCH) devices provides up to 3.2 GB/s of bandwidth.
    [Show full text]
  • C:\Andrzej\PDF\ABC Nagrywania P³yt CD\1 Strona.Cdr
    IDZ DO PRZYK£ADOWY ROZDZIA£ SPIS TREFCI Wielka encyklopedia komputerów KATALOG KSI¥¯EK Autor: Alan Freedman KATALOG ONLINE T³umaczenie: Micha³ Dadan, Pawe³ Gonera, Pawe³ Koronkiewicz, Rados³aw Meryk, Piotr Pilch ZAMÓW DRUKOWANY KATALOG ISBN: 83-7361-136-3 Tytu³ orygina³u: ComputerDesktop Encyclopedia Format: B5, stron: 1118 TWÓJ KOSZYK DODAJ DO KOSZYKA Wspó³czesna informatyka to nie tylko komputery i oprogramowanie. To setki technologii, narzêdzi i urz¹dzeñ umo¿liwiaj¹cych wykorzystywanie komputerów CENNIK I INFORMACJE w ró¿nych dziedzinach ¿ycia, jak: poligrafia, projektowanie, tworzenie aplikacji, sieci komputerowe, gry, kinowe efekty specjalne i wiele innych. Rozwój technologii ZAMÓW INFORMACJE komputerowych, trwaj¹cy stosunkowo krótko, wniós³ do naszego ¿ycia wiele nowych O NOWOFCIACH mo¿liwoYci. „Wielka encyklopedia komputerów” to kompletne kompendium wiedzy na temat ZAMÓW CENNIK wspó³czesnej informatyki. Jest lektur¹ obowi¹zkow¹ dla ka¿dego, kto chce rozumieæ dynamiczny rozwój elektroniki i technologii informatycznych. Opisuje wszystkie zagadnienia zwi¹zane ze wspó³czesn¹ informatyk¹; przedstawia zarówno jej historiê, CZYTELNIA jak i trendy rozwoju. Zawiera informacje o firmach, których produkty zrewolucjonizowa³y FRAGMENTY KSI¥¯EK ONLINE wspó³czesny Ywiat, oraz opisy technologii, sprzêtu i oprogramowania. Ka¿dy, niezale¿nie od stopnia zaawansowania swojej wiedzy, znajdzie w niej wyczerpuj¹ce wyjaYnienia interesuj¹cych go terminów z ró¿nych bran¿ dzisiejszej informatyki. • Komunikacja pomiêdzy systemami informatycznymi i sieci komputerowe • Grafika komputerowa i technologie multimedialne • Internet, WWW, poczta elektroniczna, grupy dyskusyjne • Komputery osobiste — PC i Macintosh • Komputery typu mainframe i stacje robocze • Tworzenie oprogramowania i systemów komputerowych • Poligrafia i reklama • Komputerowe wspomaganie projektowania • Wirusy komputerowe Wydawnictwo Helion JeYli szukasz ]ród³a informacji o technologiach informatycznych, chcesz poznaæ ul.
    [Show full text]