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Qoriq ® Qonverge ® B4860 Baseband Processor QorIQ Qonverge Platform QorIQ Qonverge B4860 Baseband Processor Base station system-on-chip enables processing of three 20 MHz sectors of LTE Overview Target Applications The QorIQ Qonverge B4860 device is a multi- each of the air interface standards in single and Macrocell base stations standard wireless base station system-on-chip multi-mode operations. Layer 2 and transport (SoC) based on 28 nm process technology. The processing are implemented using a mix of • LTE (FDD and TDD) B4860 reduces overall power consumption for e6500 64-bit dual threaded Power Architecture • LTE Advanced high-end wireless macro base stations to deliver cores, data path and security accelerators. • WCDMA the industry’s highest performance solution. The multicore SoC includes 10 programmable The B4860 is perfectly suited to meet the cores based on a StarCore flexible vector performance demands of wireless operators processor (FVP), 64-bit Power Architecture® for LTE, WCDMA and LTE-Advanced macro cores, as well as CoreNet and Multi-Accelerator base stations. It includes a combination of fully Platform Engine (MAPLE) technologies. The programmable StarCore FVP cores, Power B4860 targets broadband wireless infrastructure Architecture cores and powerful baseband and builds upon our proven success of acceleration to provide cost-effective, best- existing multicore SoCs and DSPs in wireless in-class performance, power efficiency and infrastructure markets. connectivity. With four dual-threaded e6500 64-bit cores operating at up to 1.8 GHz and The B4860 is designed to adapt to the rapidly six SC3900FP DSP cores at up to 1.2 GHz, changing and expanding standards of LTE the B4860 provides the required programmable (FDD and TDD), LTE-Advanced including 3GPP performance. Additionally, the MAPLE hardware LTE Rel.10/11 and WCDMA, as well as provide accelerators target processing of baseband simultaneous support for multiple standards. functions, such as FEC decoding and encoding, FFT, PDSCH and PUSCH embedded data Layer 1 is implemented using a mix of StarCore flows, WCDMA chiprate and MiMO equalization, SC3900FP high-performance FVP cores and allowing base station manufacturers to deliver the MAPLE baseband accelerator platform, higher throughputs, lower latencies and better which provides a highly efficient hardware spectral efficiency. implementation of standardized algorithms for QorIQQorIQ Qonverge Qonverge B4860 Block B4460 Diagram Block Diagram Power Architecture® e6500 Power Architecture e6500 StarCore StarCore Dual Thread Core Dual Thread Core SC3900FP FVP Core SC3900FP FVP Core 64-bit 64-bit 32 KB 32 KB 32 KB 32 KB DDR3/3L DDR3/3L L1 D Cache L1 I Cache L1 D Cache L1 I Cache 32 KB 32 KB 32 KB 32 KB 2048 KB Memory Memory L1 D Cache L1 I Cache L1 D Cache L1 I Cache Power Architecture e6500 L2 Cache Power Architecture e6500 Controller Controller Dual Thread Core Dual Thread Core 512 KB 512 KB 2048 KB L2 Cache 32 KB 32 KB 32 KB 32 KB L1 D Cache L1 I Cache L1 D Cache L1 I Cache L3/M3 Cache L3/M3 Cache MAPLE-B3 Baseband CoreNet Coherency Switching Fabric Accelerator 2x EQPE2 2x DEPE Frame Manager Security Monitor Queue Test 2x eTVPE2 USB eOpenPIC Parse, Classify, Distribute Mgr. DMA DMA Port/ 8x eFTPE2 1588® support RapidIO SAP Power Management 2x PUPE2 Buffer Message Debug eSDHC eSPI 2x PDPE2 Mgr. Manager (Aurora) 10G/2.5G/1G 2.5G/1G 2.5G/1G (RMan) OCeaN Pre 1x CRPE2 44 GPIO SRIO PCIe Boot SEC 2 1x TCPE SRIO Loader 4x I C 10G/2.5G/1G 2.5G/1G 2.5G/1G 5.3 IFC 3x CRCPE 2x DUART Clocks/Reset 8x CPRI 16-Lane 10 GHz SerDes Timers Core Complex (CPU, FVP, L1 and Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements While the four Power Architecture cores offer - Up to 32 MAC/cycle of 16-bit and up to • Four I2C Interfaces industry-leading processing capacity and a major 16 FLOP/cycle • Four UART ports leap in available processor performance for layer - Eight instructions per cycle 2 and layer 3 in many throughput-intensive, - Up to eight data lanes vector in a single • 182 32-bit timers packet-processing networking applications, raw instruction (SIMD8) • 44 general-purpose I/Os CPU processing power is not enough to achieve - State-of-the-art support for control code multi-Gb/s data rates. To address this, the with branch prediction Software B4860 uses Freescale Data Path Acceleration - Fully featured memory management unit • Development tools from Freescale and Architecture (DPAA), which significantly reduces and logical to real address translation partners data plane instructions per packet and enables more CPU cycles to work on value-added - Clustered L2 cache allowing strict Eclipse IDE allocation or full sharing services rather than repetitive low-level tasks. Compilers Combined with specialized accelerators for - Hardware support for L1 and L2 cache cryptography and pattern matching, the B4860 coherency Debuggers allows the user’s software to perform complex MAPLE baseband accelerators Profiling, critical code analysis, call tree, packet processing at high data rates. - FEC accelerators for LTE, LTE-Advanced trace points and WCDMA The B4860 offloads performance and latency- Nexus trace viewer, code viewer, critical layer 1 functions to MAPLE-B3, ›› Turbo decoder with rate de-matching performance view, trace analyzer and HARQ combining which integrates highly optimized and flexible Scripting for post-process trace and ›› Turbo encoder with rate matching accelerators. The smart partitioning introduced performance data in B4860 provides an excellent balance ›› Viterbi decoder Register analyzer between OEM intellectual property, hardwired - FFT/iFFT accelerators and algorithms implemented on the - DFT/iDFT Device and core simulators fully programmable StarCore FVP and is highly - MiMO equalizer MMSE-based supporting efficient in terms of power dissipation and silicon Operating systems IRC, SIC and PIC area utilization. BSP and device drivers - Matrix inversion and multiplication QorIQ Qonverge B4860 - PUSCH data path embedded flow • B4860QDS board: Software and reference - PDSCH data path embedded flow application development system Processor Features - WCDMA/HSPA+ chip rate and path • Freescale’s optimized software reference search libraries for LTE and WCDMA layer 1 PHY Hardware - CRC functions • Integrated processor cores and accelerators • CoreNet: Internal cache coherent switch fabric General for layer control and transport processing enabling full cache coherent system • 1020-pin FC-PBGA package, 1 mm pitch Four e6500 dual-threaded, 64-bit Power • Two DDR-3/3L controllers: 64-bit, 1.867 GHz Architecture cores (each with 512 KB L3 cache) • Core voltage: VID - Dual threading with simultaneous multi • ECC support for on-chip and off-chip • I/O voltage: 1, 1.2, 1.35, 1.5, 1.8 and 2.5 threading (SMT) memories nominal - 128-bit AltiVec SIMD unit • High-speed interfaces multiplexed into 16 • Industrial temperature range - 40-bit physical addressing SerDes 10G ports • 12.3 MB internal memory - Fully featured MMU with a 1024-entry Two 10 G/2.5 G/1 G Ethernet controllers eight-way set-associative cache • Debug ports: Test access port and boundary - Core virtualization supporting hypervisor Four 2.5 G/1 G Ethernet controllers scan architecture compliant with IEEE Std. 1149.1™, 1149.6™ and Nexus IEEE-ISTO 5001 and logical to real address translation ® IEEE 1588v2 support trace support - Clustered L2 cache allowing strict Two x4 Serial RapidIO controllers 5G allocation or full sharing • Lead-free ROHS compliant (Gen II) - Hardware support for L1 and L2 cache coherency Eight CPRI v4.2 controllers 9.8G DPAA (frame manager, queue manager, Four-lane PCI Express® 5G (Gen II) buffer manager) for IP packed acceleration Eight Aurora: Tracing/debug Security protocol accelerators: SNOW-3G, Kasumi, ZUC, IPSec, DES, 3DES, AES, • Trust architecture with secure boot MD5, SHA-1/2, HMAC • One serial port interface (eSPI) • Integrated DSP cores and baseband • One eSD/eMMC interface accelerators for layer 1 processing • One IFC: 16-bit integrated NAND/NOR flash Six StarCore SC3900FP FVP controller or general-purpose interface programmable cores • One USB 2.0 interface For more information, visit freescale.com/QorIQQonverge Freescale, the Freescale logo, AltiVec, CodeWarrior, StarCore and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet and QorIQ Qonverge are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2012-2013, 2015 Freescale Semiconductor, Inc. Document Number: B4860FS REV 3 .
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