DOCSLIB.ORG

Coppola Marchese Unixworld.Pdf

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Coppola Marchese Unixworld.Pdf - Given a budget of around 98000, Francis Marchiseand Jean Coppola (left)ol Pace Uni- versity created an AT-based 386 workstation with exceptional f loating-point performance. TURBOGHARGING YOUR 386 Build a 386 from scratch, or inrease performa,nce on a budget chip, and the software must be Weitek .fi', _/crn F. Coppola and, Francis T Marchese compatible to recognize it. Srtren writ- I t : ve bousht a 386 machine tional floating-point power for computa- ing your own code, this is not a big prob- f .rnning UNH, and you wanl tionally intensive applications such as lem because compilers are available I - improve i1s per[ormance ray tracing, cellular automata, and that support Weitek. I rci add some neat features. molecular modeling. Although the Weitek was excellent - j :.,::, vou have a limited budget, so w We would have complete control for our in-house intense floating-point ,n. best price/performance over all the components in the system. applications, we also needed a fast : ::,: If we would have bought a preconfig- numeric co-processor for commercial ', -=:: do you start? Whether you're ured system, it would not be custom- non-Weitek-supported applications, and particular parallel , -,. .:::rg -""our 386SX or building your ized to our needs, nor would possibly computations. A ' ::. stem from modules, you first we be assured of the quality of each daughterboard. wilh sockels for both ' :": ., Sat priorities. As small systems component. chips, can accomplish this task, and j : r ::s at Pace, a New York universiff, Two further considerations: we both chips can reside in the same sys- -: :articuiar goal was to build a 25- chose to stay with the AT-bus architec- tem to accommodate any co-processor- ,.-.- s1'stem that was as powerful as a ture because the Industry Standard specific application. Although a daugh- , :r,station, reasonably priced, yet Architecture (ISA) is still the current terboard is needed for the majority of - =.,',' maintained. slandard and most widespread bus cur- the motherboards. some manufactur- rginally we thought we were allotted rently in use, whereas the percentage of ers have installed both sockets directly. '--. '.Ni for a complete UNX worksta- MicroChannel Architecture machines Instead of installing an Intel 80387 - :, enough to buy a low-end Hewlett- is still small, and the Extended Industry chip, for almost the same price (see :.:iard or Sun. In the end, however, Standard Architecture (EISA) has not table), we purchased a Cyrix FasMath :: actual budget was reduced to caught on yel We also chose the 386 Intel numeric co-processor-which is fully -,:.'-N,i-a real challenge, but we accom- processor because Pace's Motorola Intel-compatible. Cyrix claims this co- :,.hed it by comparison shopping and 6802Gbased workstations have had sev- processor has a greater precision in di- .'. .luating price/performance. After eral problems, not to mention a high- vision, and is faster on single-precision -.:etul thought, we decided to design cost service contract. Here's why we and double-precision computations -C implement our own generic UNX chose what we did. than Intel's. Furthermore, the Cyrlr is ...,rkslalion because: especially good for high performance e The system can be easily main- Co-processors on transcendental functions, and meets ::.ined and upgraded. Local vendors Our primary design objective was to all IEEE specifications. In the near fu- -- -,u1d supply parts for in-house service, have exceptional floating-point perfor- ture, look for a new chip from Cyrlr that :rd a service contract would not be mance, so we chose the Weitek is Weitek compatible, competitively :eeded. mW3167 Abacus numeric cGprocessor. priced, and faster than the Weitek. e AT:bus hardware is compatible Weitek claims its co-processor is capa- The Motherboard ,,i'ith the majority of the existing ma- ble of floating-point speeds 50 times ihines in the university, and could be faster than an Intel 8087 chip and 4 to 5 The most difficult decision was selec! sivapped out in an emergency. times faster than an Intel 80387, thus ap ing a motherboard. Though there are * The 386 will not become obsolete proaching the speed of a V/\X 8600. many manufacturers and models of 386 for several years, and it could provide The Abacus chip provides full 32- and motherboards, not aii support the service for word processing and spread- 64-bit floating-point operation and con- Weitek.'lhese included (but were not sheets in a departmental offlce when it forms to the IEEE standards for float- exclusive to) speciflc models from ALR, is replaced. ing-point arithmetic. However, it AMI, Dell, Everex, Intel, Micronics, e The machine can be designed at a requires a special 121-pin socket on the Mylex, and Zenith. Other manufactur- reasonable cost while providing excep motherboard specifically made for this ers such as AST, Compaq, HP and Hauppauge also have versions that are Weitek compatible, but also have two sockets on the board to accommodate both the Weitek and a math coprocessor. Most motherboards have similar throughput performance. We chose the Micronics because it is cleanly engi- Lisl Price I neered, rblatively inexpensive,-and is Description Purchase price Vendor sold by local vendors. Ourlocal vendor S0Y0Micronicscompatible386-25 N/A /$j598 JomDaiaSysten"s had a Micronics compatible that met all B megabytes of RA[/ installed 14838 Valley Blvd., #C of our requirements, came a (expandable and with to 16 megabytes); City of lndustry, CA 91 746 one-year warranty. we pur- Though slots include: I 32-bit, 5 16-bit; B1 B-330-6553 chased this board, in retrospect, we rec- 2 8-bit; Weitek compatible; minus ommend that you purchase a major cache; AMI Bl0S brand name, such as those mentioned Weitek co-processor 3167-25 MHz $2495 i $995 Weitek Corp above, unless you have a dealer with a 1060 E. Arques Ave. good track record that will give you the Sunnyvale, support you need. CA 94086 408-738-8400 Other features to look for when in- Cyrix numeric co-0rocessor 25 MHz vesting in a motherboard are maximum $814 i $600 Cyrix Corp memory capacity, processor speed, wait 1850 N Greenville Ave., #184 states, number and ['pe of expansion Bichardson. TX 75081 slots, and tlpe of RAM. Because most 214-234-8387 versions of UNX require a minimum of Daughterboard for Weitek and 80387 $220 i $200 MicroWay lnc. 4 megabytes of memory, the maximum P.0. Box 79 expansion ability of the motherboard is Kingslon, MA 02364 important. Also, check the maximum 508-746-7341 amount of memory that can go directly Iurbo cool power supply 250 watt $205 i $169 PC Power and Cooling on a motherboard-and if and how much 31510 Mountain Way memory can go on a daughterboard. Bonsall CA 92003 When deciding upon the speed of the 61 9-723-951 3 system, we chose a speed of21MHzin- TEAC 1.2-megaby,te 5 li4-inch N/A / $69 TEAC Corc. ol America stead of 20 or 33 MHz because the floppy disk drive /733 Telegraph price/performance Rd. ratio was the best Montebello CA 90640 when compared to others, especially TEAC 1.4-megabyte 3 1/2-inch N/A / $79 213-727-7682 when considering it would cost thou- floppy disk drive 508-683-8322 sands of dollars more to add the faster Lark Associates 16-bit 2O-megabit/sec $j99 / $j50 Lark Associates Weitek, Cyrix, and RAM for a 33-MHz 1 1 2tloppy12 hard disk conlr0ller 4046 Clipper machine. It was only a few hundred Ct !,-,. Fremont, CA 94538 dollars more fo r a 2*MHz thut a 2UMHz. 415-657 5275 Most boards will have the option of :'"Jl Hewlett-Packard 340-megabyie 1 one or zero wait states, but the RAM has 7-ms $1890 / $1709 Hewlett-Packard ESDI FH hard drive (s-year warranty) to be fast enough to meet that particular 3000 Hanover St manufacturer's specifications if it is to Palo Alto. CA 94304 run at zero wait state. A good number of 41 5-857-1 501 expansion slots is about eight, which ArchiveVP Tape Backup 60-megabyte $975 / $545 Archrve allows for future growth. If you are re- internal DC6004 cartridge c0mpatible 1650 Sunflower Ave. placing an existing system board, make Costa Mesa, CA92626 sure there are enough of the right size BA0-537-2724 bit (8, 16,32) slots. 714-641-1230 When you purchase a motherboard, Paradise VGA Professional Card 512K $649 / $269 Weslern Digital lmaging/Paradise be sure that the Intel 386 chip speed is 256 colors at 600-by-480 resolution 800 E. Middlefield Rd. the same as the advertised speed of the Mouniain View, CA 94043 motherboard. For example, many dealers 41 5-960-3353 are installing 2GMHz chips on 2*MHz 800-356-5787 system boards, and selling them as Princeton Graphics Systems 1 6-inch $1375 / $822 Princeton Graphics Systems "2EMHz systems" to unsuspecting cus- color multisynch monitor tomers. Some motherboards will 1100 Northmeadow Pkwy., Ste. 150 Roswell, GA 30076 "push" the chip and actually benchmark 404-664-1 01 0 at the motherboard speed, but this is not recommended because it will fail lntel UNIX System V/386 Version 3.2 lntel Corp. erratically at a higher rate. System Platform Set Limited $595 i $357 (formerly Bell Teclrnologies) x_T_ clock lL.Id. Software Development Set $565 / $339 3065 Bowers Ave. Hard Disk and Controllers Intel System Platform lVanual Kit $1 00 / $60 Santa Clara, CA 95051 Intel System Development Manual Choosing a hard disk and controller is a Kil $1 00 / $60 408-765-8080 difficult but important decision.
Load more

Recommended publications
  • Tom Kearney Object Name: Sun Sparcstation IPX Vintage: C.1991 Synopsis: Sun Sparcstation IPX
    AccessionIndex: TCD-SCSS-T.20121208.075 Accession Date: 8-Dec-2012 Accession By: Tom Kearney Object name: Sun Sparcstation IPX Vintage: c.1991 Synopsis: Sun Sparcstation IPX. S/N: 600-2791-04 213M1236. Description: The Sun Sparcstation IPX is a workstation introduced by Sun Microsystems in 1991. It was designed to be an entry-level networked workstation. It is based on the SUN4C architecture, enclosed in a lunchbox chassis. It uses a Fujitsu MB86903 or Weitek W8701 40 MHz processor. Weitek provided 80MHz after-market "SPARC POWERuP!" (2000A-080 GCD) processors which worked well in an IPX but required a ROM update to v2.9. It has four 72-pin SIMM slots for memory expansion. The memory uses parity Fast Page Memory (FPM) SIMM's with speeds of 50-80ns. Slots can be filled individually giving a maximum of 64MB memory. Paired memory modules decrease access times via "bank interleaving" resulting in faster memory and overall system performance. Additional 32 and 64MB SBUS "Above Board" RAM expanders will fit and work in the IPX using the 8-pin J101 header which contains additional power and clock signals next to the DMA/Cache controller. The Sparcstation IPX also includes an on-board AMD Lance Ethernet chipset providing 10BaseT networking as standard and 10Base2 and 10Base5 via an AUI transceiver. The OpenBoot ROM is able to boot from network, using RARP and TFTP. Like all other SPARCstation systems, it holds system information such as MAC address and serial number in NVRAM. If the battery on this chip dies, then the system will not be able to boot.
    [Show full text]
  • · Welter ABACUS 3170 FLOATING·POINT COPROCESSOR for SPARC PRELIMINARY DATA May 1989
    · WElTER ABACUS 3170 FLOATING·POINT COPROCESSOR FOR SPARC PRELIMINARY DATA May 1989 The Abac:us 3170 Is a single-c:hip noating-point c:oproc:essor for the Fujitsu 5-20/5-25 and LSI Logic L64801 implementations of the SPARC architec:ture. It inc:orporates a noating-point datapath and a noating­ point c:ontroUer. The Abac:us 3170 provides direc:t interfac:e to the integer unit and memory. It is available in speed grades of 20 and 25 MHz. Related product The Abacus 3171 single­ chip Ooating-point coproc:eaor forCypress 7C601 implementation of SPARe architecture. ( Contents Features 1 Desc:ription System Considerations 8 Spec:ific:ations 10 Pin Configuration IS Physical Dimensions 16 ( Ordering Information 16 Sales Offices back cover USING THIS DATA SHEET In the writing of this data sheet, it was assumed that the user is familiar with the SPARC architecture, as well as the hardware details of its implementation. This data sheet does not cover details that are explained in the following and other related literature: The SPARe Architecture MtD'IUIll, by Sun Microsystems SPARe MB86901 (S-25) High PerjOl7l'lQTlCe 32-Bit RIse Processor, by Fujitsu Microelectronics, Inc. L64801 Hzgh PerjOl7l'lQTlCe Open Architecture RIse Mu:roprocessor, by LSI Logic Corporation. WEITEK Abacus 3170 Floating-Point Coprocessor for SPARC May, 1989 Copyright © WEITEK Corporation 1989 1060 East Arques Avenue Sunnyvale, California 94086 Telephone (408) 738-8400 All rights reserved . WEITEK is a registered trademark of WEITEK Corporation SPARC is a trademark of Sun Microsystems, Inc. WEITEK reserves the right to make changes to these specifications at any time Printed in the United States of America 9089 65432 1 DOC 89XX ("~.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • HP-UX and K4
    HP 3000 Series 920 A new low-cost solution to HP PA-RISC HEWLETT PACKARD A Table of Contents Editor WbrkshtSans 17 General TkacyWesfer HB introducfs HP-PHIGS Vxsbn 2.0 HP f2mmeZs is published monthly for 1 IEP Exemtivc T- Series echedule WPC++1SorftBcnch for objw-~tiwrted Hewiett-PacWl's value-added busi- hcal RTR plxrdwts runwed fmm price I& tlesses to pmvide you with inEodon - about HPf paducts and services ta 17 Apollo help you be more successful. Objenmrb Eor SmanW-80 - rn don Muititcger Systems fa ApMo workmrions For further information on my of the 2 General Da~mmbnWSPwm.39 products and in TWoncafmem0@~farHP3000& obscl1- sewices dim& lhnWC:++ %mian 1.2 obsob$xnce HP Cham&, p1am cantract your HP HPWOO~tmna sales rep. BP XUD and HP 9QBO pi&@- 20 HP-UX c2xooiwmJAMfar-mccsilnd HP ApoMo 9000 Stries 400 intaxfuction See back cmw for subserfption ='ppo* HP-UXReaease7~fbrOrHP9000es30[1 Upm& d Wo~m~ticm. release HIJ tWtBa& dabL and400proClucts LAM comunwith Ad-WnL ~mgtheHPPenrorralVi Note: 1Yb0 all HP comprJSer products Macintosh HPmModelmMm~~ ate sol$ and styy,arred in dl comties. upgrade! IEQ-UX 7.0 prb iae- Please &ck wS$h putlocal IIP sales syilwm PtrsoM lGopnputers oflce* Inmucisg Phe mw3000 I' Rew 24 General H&ett-J%zcm daas mt warrant the Ncw SbmXurd Sdutions RWap far HP~~e8OU)and~L3( 1 M-~B PIUS ~e be remav~dfram price 1u:cumcy 4t.k i@@n p&d Inaadue* Rasase B(M listNd1 in PIP Chmxls ad shall not be Gable HPALWEMOL HP Pamble Plus iwmaries dismtsnm for use made elf ths i$om'on NS ptrfbtmsaGe impmvemdts with 25 Desktop eontaiwd breinIOZ&~'~OR psovidsd MPE XL Rcl~aae2.1 New~HP~386/25;dwktDp~ tn HP CWs$ subw to chge Intmdueing HP CM~C&~X HFSup~~u~aaoasHP~ withut mke.
    [Show full text]
  • Unit 3: Microcomputers and Microprocessors
    Microcomputers and Microprocessors Unit 3: Microcomputers and Microprocessors Introduction This unit focuses on popular microcomputer systems and microprocessors. Lesson 1 of this unit presents the architecture and I/0 communications of microcomputer systems. Microprocessor, the brain of a microcomputer with its functional units, is described in Lesson 2. This lesson also includes description of arithmetic logic unit and control unit in detail. Lesson 3 provides the information of popular microprocessors, namely, CISC, RISC and special purpose of processors. Lesson 1: Microcomputer and Organization 1.1 Learning Objectives On completion of this lesson you will be able to: • understand structure of a microcomputer • understand communication techniques between processor and other devices • understand telecommunications for distant microcomputer. 1.2 Architecture of a Microcomputer The most modern microcomputers utilize a motherboard, a single large circuit board containing the microprocessor unit (MPU), ROM, RAM, and other associated circuits. These elements are linked through a series of parallel metal lines etched into the motherboard called the system bus. The system bus carries three types of information; these are: control, address, and data. Control information is carried by a number of control lines, addresses by a number of address lines and data by data lines. The width of the bus is important to the performance of the computer. The wider the bus, the more information can be carried at one time and the greater the throughput of the system. Most 16-bit microcomputers use 8 or 16-bit buses, 32-bit microcomputers use 8-bit, 16-bit, and 32-bit buses, while 64-bit microcomputers use 16-bit, 32-bit and 64-bit buses.
    [Show full text]
  • The Multititan: Four Architecture Papers
    MultiTitan: Four Architecture Papers: MultiTitan Central Processor Unit MultiTitan Floating Point Unit MultiTitan Cache Control Unit MultiTitan Intra-Processor Bus Digital Equipment Corporation Western Research Laboratory 100 Hamilton Avenue Palo Alto, CA 94301 Version of 5 April 1988 Copyright 1988 Digital Equipment Corporation 1 1. Introduction to the MultiTitan This document is a revised collection of four working architecture documents for the MultiTitan project originally published in 1986. The MultiTitan was a research project at the Western Research Lab from mid 1984 through 1987. Because of delays, primarily due to lack of staff in critical stages of the project, and the consequent loss of research potential in several areas of the program, in January 1988 WRL redirected its efforts beyond the MultiTitan. Since it was research project, it was specifically intended not to be a product in itself, but rather a testbed for many different ideas. Thus ideas proved in the project and experience gained in the project can be useful in future product designs. Research beyond product development is important in that research can afford to try out high payoff but high risk ideas that would be too risky to directly incorporate into products. 2. Research Goals of the MultiTitan There were four main research areas in the MultiTitan. In general each area has the potential to improve system performance by a factor of 2x or more, however specific aspects of each research area may only contribute a few percent. The four areas were: • Small-grain multiprocessing • Architecturally explicit caches • High performance / low cost floating point • Software instruction set architectural definition These four areas will be explained more completely in the next four sections.
    [Show full text]
  • MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor
    Awards ................................................................................................................................................................ Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor ONUR MUTLU ETH Zurich RICH BELGARD ......We are continuing our series of of performance optimization on the com- sions made in the MIPS project that retrospectives for the 10 papers that piler and keep the hardware design sim- passed the test of time. The retrospective received the first set of MICRO Test of ple. The compiler is responsible for touches on the design tradeoffs made to Time (“ToT”) Awards in December generating and scheduling simple instruc- couple the hardware and the software, 2014.1,2 This issue features four retro- tions, which require little translation in the MIPS project’s effect on the later spectives written for six of the award- hardware to generate control signals to development of “fabless” semiconductor winning papers. We briefly introduce control the datapath components, which companies, and the use of benchmarks these papers and retrospectives and in turn keeps the hardware design simple. as a method for evaluating end-to-end hope that you will enjoy reading them as Thus, the instructions and hardware both performance of a system as, among much as we have. If anything ties these remain simple, whereas the compiler others, contributions of the MIPS project works together, it is the innovation they becomes much more important (and that have stood the test of time. delivered by taking a strong position in likely complex) because it must schedule the RISC/CISC debates of their decade. instructions well to ensure correct and High-Performance Systems We hope the IEEE Micro audience, espe- high-performance use of a simple pipe- The second retrospective addresses three cially younger generations, will find the line.
    [Show full text]
  • SMBIOS) Reference 6 Specification
    1 2 Document Identifier: DSP0134 3 Date: 2018-04-26 4 Version: 3.2.0 5 System Management BIOS (SMBIOS) Reference 6 Specification 7 Supersedes: 3.1.1 8 Document Class: Normative 9 Document Status: Published 10 Document Language: en-US 11 System Management BIOS (SMBIOS) Reference Specification DSP0134 12 Copyright Notice 13 Copyright © 2000, 2002, 2004–2016 Distributed Management Task Force, Inc. (DMTF). All rights 14 reserved. 15 DMTF is a not-for-profit association of industry members dedicated to promoting enterprise and systems 16 management and interoperability. Members and non-members may reproduce DMTF specifications and 17 documents, provided that correct attribution is given. As DMTF specifications may be revised from time to 18 time, the particular version and release date should always be noted. 19 Implementation of certain elements of this standard or proposed standard may be subject to third party 20 patent rights, including provisional patent rights (herein "patent rights"). DMTF makes no representations 21 to users of the standard as to the existence of such rights, and is not responsible to recognize, disclose, 22 or identify any or all such third party patent right, owners or claimants, nor for any incomplete or 23 inaccurate identification or disclosure of such rights, owners or claimants. DMTF shall have no liability to 24 any party, in any manner or circumstance, under any legal theory whatsoever, for failure to recognize, 25 disclose, or identify any such third party patent rights, or for such party’s reliance on the standard or 26 incorporation thereof in its product, protocols or testing procedures.
    [Show full text]
  • BLOCK ADJUSTMENT on PERSONAL COMPUTERS Dipl.-Math
    BLOCK ADJUSTMENT ON PERSONAL COMPUTERS Dipl.-Math. Hermann Klein Photogrammetry, Software, Consulting LehenbUhlstr.59, 7253 Renningen West Germany Presented Paper for Commission III Introduction: The enormously increased efficiency concerning computing time, available disk space and the simultaneously drop down of costs have made the IBM PC an interesting computer system to use for both scientific research and engineering applications. Having developed the computer programs PATM for block adjustment with independent models and PATB for block adjustment with bundles, it was now of interest to transfer these programs to personal computer systems. This paper deals with the necessary investigations, the the effort to develop real comfortable and userfriendly PC programs and the capabilities of these PC versions. The IBM PC family: The first IBM Personal Computer was introduced in the fall of 1981. Later, as PC sales zoomed beyond all expectations, this PC became recognized as the standard for all serious desktop computers. From the programmer's side of view, all members of the PC family consists of a processor, memory chips and several circuit chips. All these main components are located on the system board. Other important parts are located on extension boards, which may be plugged into the system board. The central processing unit (CPU) of the PC is the Intel 8088 16-bit microprocessor. It controls the computer's basic operations by sending and recieving control signals, memory addresses and data from one part of the computer to onother along a network of interconnecting pathways called the bus. The microprocessor is tied to at least 64K bytes of memory, some built in ROM programs, such as BASIC and the ROM-BIOS, and some very important support chips.
    [Show full text]
  • Solaris 7 5/99 Online Release Notes (Sunwrdm)
    Solaris 7 5/99 Online Release Notes (SUNWrdm) Sun Microsystems, Inc. 901 San Antonio Road Palo Alto, CA 94303-4900 U.S.A. Part No: 805-6014–10 May 1999 Copyright 1999 Sun Microsystems, Inc. 901 San Antonio Road, Palo Alto, California 94303-4900 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Parts of the product may be derived from Berkeley BSD systems, licensed from the University of California. UNIX is a registered trademark in the U.S. and other countries, exclusively licensed through X/Open Company, Ltd. Sun, Sun Microsystems, the Sun logo, SunDocs, and Solaris are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The OPEN LOOK and SunTM Graphical User Interface was developed by Sun Microsystems, Inc. for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface, which license also covers Sun’s licensees who implement OPEN LOOK GUIs and otherwise comply with Sun’s written license agreements.
    [Show full text]
  • The SPARC Architecture Manual Version 8
    The SPARC Architecture Manual Version 8 Revision SAV080SI9308 SPARC International Inc. 535 Middlefield Road, Suite 210 Menlo Park, CA 94025 415-321-8692 SPARC International, Inc. SPARC is a registered trademark of SPARC International, Inc. The SPARC logo is a registered trademark of SPARC International, Inc. UNIX and OPEN LOOK are registered trademarks of UNIX System Labora- tories, Inc. Copyright 1991,1992 SPARC International, Inc. − Printed in U.S.A. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the copyright owners. Restricted rights legend: use, duplication, or disclosure by the U.S. government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and in similar clauses in the FAR and NASA FAR Supplement. The SPARC Architecture Manual Version 8 Revision SAV080SI9308 1 Introduction This document specifies Version 8 of the Scalable Processor ARChitecture, or SPARC. 1.1. SPARC Attributes SPARC is a CPU instruction set architecture (ISA), derived from a reduced instruction set computer (RISC) lineage. As an architecture, SPARC allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications, including scientific/engineering, programming, real-time, and commercial. Design Goals SPARC was designed as a target for optimizing compilers and easily pipelined hardware implementations. SPARC implementations provide exceptionally high execution rates and short time-to-market development schedules.
    [Show full text]
  • On the Development and Promotion of the Motorola 68000
    Oral History Panel on the Development and Promotion of the Motorola 68000 Participants: Jack Browne Murray Goldman Thomas Gunter Van Shahan Bill Walker Moderated by: Dave House Recorded: July 23, 2007 Austin, Texas CHM Reference number: X4145.2008 © 2007 Computer History Museum Motorola 68000 Microprocessor Oral History Dave House: I’m Dave House from the Computer History Museum and its Semiconductor Special Interest Group. We're here today in Austin, Texas, at Freescale Semiconductor—the former Motorola Semiconductor—with the team that created the Motorola 68000 [microprocessor]. I'm going to ask the various members of the team to introduce themselves now, with a little bit of their background: where they're from, where they went to school, their experience before the 68K and the role that they played in the 68K development. Murray Goldman: Go ahead, Tom. House: You can go ahead, Murray. We'll go around the table this way. Goldman: I'm Murray Goldman. I was born in Pittsburgh, graduated from the University of Pittsburgh in 1961. Went to Bell Telephone Laboratories and I was a member of the technical staff there for six years, working on a giant telephone system which really was a big computer. I didn't really appreciate it at the time. I didn't realize how much and how important it was to my future life, but it was a good experience. I thought I wanted to teach college, so I went back to New York University, taught as an instructor for a couple of years while I got a Ph.D., and decided I really missed industry.
    [Show full text]