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Tom Kearney Object Name: Sun Sparcstation IPX Vintage: C.1991 Synopsis: Sun Sparcstation IPX
AccessionIndex: TCD-SCSS-T.20121208.075 Accession Date: 8-Dec-2012 Accession By: Tom Kearney Object name: Sun Sparcstation IPX Vintage: c.1991 Synopsis: Sun Sparcstation IPX. S/N: 600-2791-04 213M1236. Description: The Sun Sparcstation IPX is a workstation introduced by Sun Microsystems in 1991. It was designed to be an entry-level networked workstation. It is based on the SUN4C architecture, enclosed in a lunchbox chassis. It uses a Fujitsu MB86903 or Weitek W8701 40 MHz processor. Weitek provided 80MHz after-market "SPARC POWERuP!" (2000A-080 GCD) processors which worked well in an IPX but required a ROM update to v2.9. It has four 72-pin SIMM slots for memory expansion. The memory uses parity Fast Page Memory (FPM) SIMM's with speeds of 50-80ns. Slots can be filled individually giving a maximum of 64MB memory. Paired memory modules decrease access times via "bank interleaving" resulting in faster memory and overall system performance. Additional 32 and 64MB SBUS "Above Board" RAM expanders will fit and work in the IPX using the 8-pin J101 header which contains additional power and clock signals next to the DMA/Cache controller. The Sparcstation IPX also includes an on-board AMD Lance Ethernet chipset providing 10BaseT networking as standard and 10Base2 and 10Base5 via an AUI transceiver. The OpenBoot ROM is able to boot from network, using RARP and TFTP. Like all other SPARCstation systems, it holds system information such as MAC address and serial number in NVRAM. If the battery on this chip dies, then the system will not be able to boot. -
Kontron / ICS Advent SB586P(V) Manual (Pdf)
Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Kontron / ICS Advent SB586PV at our website: Click HERE Model SB586P(V) Product Manual MANUAL NUMBER : 00431-027-3C Page - ii FOREWORD This product manual provides information to install, operate and or program the referenced product(s) manufactured or distributed by ICS Advent. The following pages contain information regarding the war- ranty and repair policies. Technical assistance is available at: 800-480-0044. Manual Errors, Omissions and Bugs: A "Bug Sheet" is included as the last page of this manual. Please use the "Bug Sheet" if you experience any problems with the manual that requires correction. The information in this document is provided for reference only. ICS Advent does not assume any liability arising from the application or use of the information or products described herein. This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of ICS Advent, nor the rights of others. -
SOS Internals
Understanding a Simple Operating System SOS is a Simple Operating System designed for the 32-bit x86 architecture. Its purpose is to understand basic concepts of operating system design. These notes are meant to help you recall the class discussions. Chapter 1 : Starting Up SOS 3 Registers in the IA-32 x86 Architecture BIOS (Basic Input/Ouput System) Routines Real Mode Addressing Organization of SOS on Disk and Memory Master Boot Record SOS Startup A20 Line 32-bit Protected Mode Addressing Privilege Level Global Descriptor Table (GDT) More on Privilege Levels The GDT Setup Enabling Protected Mode Calling main() Chapter 2 : SOS Initializations 10 In main() Disk Initialization Display Initialization Setting Up Interrupt Handlers Interrupt Descriptor Table (IDT) A Default Interrupt Handler Load IDT The Programmable Interrupt Controller (PIC) The Keyboard Interrupt Handler Starting the Console Putting It All Together Chapter 3: SOS1 – Single-tasking SOS 16 Running User Programs GDT Entries Default Exception Handler User Programs Executable Format System Calls Creating User Programs The run Command Understanding a Simple Operating System The DUMB Memory Manager Program Address Space Process Control Block Switching to a User Program Kernel-Mode Stack Chapter 4 : SOS2 – Multi-tasking SOS 24 Running Multiple User Programs NAÏVE Memory Manager Programmable Interval Timer (PIT) Process States Timer Interrupt Handler Sleep System Call The run Command Process Queue The Scheduler The Complete Picture ps Command Chapter 5 : SOS3 – Paging in SOS 31 -
· Welter ABACUS 3170 FLOATING·POINT COPROCESSOR for SPARC PRELIMINARY DATA May 1989
· WElTER ABACUS 3170 FLOATING·POINT COPROCESSOR FOR SPARC PRELIMINARY DATA May 1989 The Abac:us 3170 Is a single-c:hip noating-point c:oproc:essor for the Fujitsu 5-20/5-25 and LSI Logic L64801 implementations of the SPARC architec:ture. It inc:orporates a noating-point datapath and a noating point c:ontroUer. The Abac:us 3170 provides direc:t interfac:e to the integer unit and memory. It is available in speed grades of 20 and 25 MHz. Related product The Abacus 3171 single chip Ooating-point coproc:eaor forCypress 7C601 implementation of SPARe architecture. ( Contents Features 1 Desc:ription System Considerations 8 Spec:ific:ations 10 Pin Configuration IS Physical Dimensions 16 ( Ordering Information 16 Sales Offices back cover USING THIS DATA SHEET In the writing of this data sheet, it was assumed that the user is familiar with the SPARC architecture, as well as the hardware details of its implementation. This data sheet does not cover details that are explained in the following and other related literature: The SPARe Architecture MtD'IUIll, by Sun Microsystems SPARe MB86901 (S-25) High PerjOl7l'lQTlCe 32-Bit RIse Processor, by Fujitsu Microelectronics, Inc. L64801 Hzgh PerjOl7l'lQTlCe Open Architecture RIse Mu:roprocessor, by LSI Logic Corporation. WEITEK Abacus 3170 Floating-Point Coprocessor for SPARC May, 1989 Copyright © WEITEK Corporation 1989 1060 East Arques Avenue Sunnyvale, California 94086 Telephone (408) 738-8400 All rights reserved . WEITEK is a registered trademark of WEITEK Corporation SPARC is a trademark of Sun Microsystems, Inc. WEITEK reserves the right to make changes to these specifications at any time Printed in the United States of America 9089 65432 1 DOC 89XX ("~. -
The Bootstrap the Where Are Wenow?
Dedicated Operating System March2011 Prof. Dr.Antônio AugustoFröhlich http://www.lisha.ufsc.br/Guto Getting ready for the OS for the ready Getting [email protected] LISHA/UFSC The Boot: The March 2011 (http://www.lisha.ufsc.br) 1 Dedicated Operating System March2011 ● ● ● BIOSgot the system ready for BIOSbrought the system on ● Lots of “jmp” so far, no calls, why? ● First instruction fetched ● initializedBIOS a complex architecture Where the stack?Where is 0x7c00 BIST, POST, hooks The Bootstrap Where are we now? we are Where (http://www.lisha.ufsc.br) =>Today class 2 EPOS Bootstrap: m src/boot/pc_boot.S e t ; CONSTANTS s ;============================================================ y ; PHYSICAL MEMORY MAP S ; 0x0000 0000 -+-----------------------+ BOOT_IDT ; | IDT (4 K) | g ; 0x0000 1000 -+-----------------------+ BOOT_GDT ; | GDT (4 K) | n i ; 0x0000 2000 -+-----------------------+ t ; : : a ; | BOOT STACK (23 K) | r ; 0x0000 7c00 -+-----------------------+ BOOTSTRAP_STACK e ; | BOOT CODE (512 b) | BOOTSTRAP_CODE p ; 0x0000 7e00 -+-----------------------+ ; | RESERVED (512 b) | O ; 0x0000 8000 -+-----------------------+ DISK_IMAGE ; | DISK IMAGE (608 K) | d ; : : e ; | | t ; 0x000a 0000 -+-----------------------+ a ; | UNUSED (384K) | c ; : : i ; | | d ; 0x000f f000 -+-----------------------+ e D March 2011 (http://www.lisha.ufsc.br) 3 EPOS Bootstrap: Notes m e t s Code to be ran at real mode (16 bits) y S Interrupts (IDT) ● g At real mode, always at 0x0000 n ● i At protected mode, anywhere (IDTR) t a Segmentation (GDT) r ● e Always -
Computing :: Operatingsystems :: DOS Beyond 640K 2Nd
DOS® Beyond 640K 2nd Edition DOS® Beyond 640K 2nd Edition James S. Forney Windcrest®/McGraw-Hill SECOND EDITION FIRST PRINTING © 1992 by James S. Forney. First Edition © 1989 by James S. Forney. Published by Windcrest Books, an imprint of TAB Books. TAB Books is a division of McGraw-Hill, Inc. The name "Windcrest" is a registered trademark of TAB Books. Printed in the United States of America. All rights reserved. The publisher takes no responsibility for the use of any of the materials or methods described in this book, nor for the products thereof. Library of Congress Cataloging-in-Publication Data Forney, James. DOS beyond 640K / by James S. Forney. - 2nd ed. p. cm. Rev. ed. of: MS-DOS beyond 640K. Includes index. ISBN 0-8306-9717-9 ISBN 0-8306-3744-3 (pbk.) 1. Operating systems (Computers) 2. MS-DOS (Computer file) 3. PC -DOS (Computer file) 4. Random access memory. I. Forney, James. MS-DOS beyond 640K. II. Title. QA76.76.063F644 1991 0058.4'3--dc20 91-24629 CIP TAB Books offers software for sale. For information and a catalog, please contact TAB Software Department, Blue Ridge Summit, PA 17294-0850. Acquisitions Editor: Stephen Moore Production: Katherine G. Brown Book Design: Jaclyn J. Boone Cover: Sandra Blair Design, Harrisburg, PA WTl To Sheila Contents Preface Xlll Acknowledgments xv Introduction xvii Chapter 1. The unexpanded system 1 Physical limits of the system 2 The physical machine 5 Life beyond 640K 7 The operating system 10 Evolution: a two-way street 12 What else is in there? 13 Out of hiding 13 Chapter 2. -
Protected Mode - Wikipedia
2/12/2019 Protected mode - Wikipedia Protected mode In computing, protected mode, also called protected virtual address mode,[1] is an operational mode of x86- compatible central processing units (CPUs). It allows system software to use features such as virtual memory, paging and safe multi-tasking designed to increase an operating system's control over application software.[2][3] When a processor that supports x86 protected mode is powered on, it begins executing instructions in real mode, in order to maintain backward compatibility with earlier x86 processors.[4] Protected mode may only be entered after the system software sets up one descriptor table and enables the Protection Enable (PE) bit in the control register 0 (CR0).[5] Protected mode was first added to the x86 architecture in 1982,[6] with the release of Intel's 80286 (286) processor, and later extended with the release of the 80386 (386) in 1985.[7] Due to the enhancements added by protected mode, it has become widely adopted and has become the foundation for all subsequent enhancements to the x86 architecture,[8] although many of those enhancements, such as added instructions and new registers, also brought benefits to the real mode. Contents History The 286 The 386 386 additions to protected mode Entering and exiting protected mode Features Privilege levels Real mode application compatibility Virtual 8086 mode Segment addressing Protected mode 286 386 Structure of segment descriptor entry Paging Multitasking Operating systems See also References External links History https://en.wikipedia.org/wiki/Protected_mode -
Coppola Marchese Unixworld.Pdf
- Given a budget of around 98000, Francis Marchiseand Jean Coppola (left)ol Pace Uni- versity created an AT-based 386 workstation with exceptional f loating-point performance. TURBOGHARGING YOUR 386 Build a 386 from scratch, or inrease performa,nce on a budget chip, and the software must be Weitek .fi', _/crn F. Coppola and, Francis T Marchese compatible to recognize it. Srtren writ- I t : ve bousht a 386 machine tional floating-point power for computa- ing your own code, this is not a big prob- f .rnning UNH, and you wanl tionally intensive applications such as lem because compilers are available I - improve i1s per[ormance ray tracing, cellular automata, and that support Weitek. I rci add some neat features. molecular modeling. Although the Weitek was excellent - j :.,::, vou have a limited budget, so w We would have complete control for our in-house intense floating-point ,n. best price/performance over all the components in the system. applications, we also needed a fast : ::,: If we would have bought a preconfig- numeric co-processor for commercial ', -=:: do you start? Whether you're ured system, it would not be custom- non-Weitek-supported applications, and particular parallel , -,. .:::rg -""our 386SX or building your ized to our needs, nor would possibly computations. A ' ::. stem from modules, you first we be assured of the quality of each daughterboard. wilh sockels for both ' :": ., Sat priorities. As small systems component. chips, can accomplish this task, and j : r ::s at Pace, a New York universiff, Two further considerations: we both chips can reside in the same sys- -: :articuiar goal was to build a 25- chose to stay with the AT-bus architec- tem to accommodate any co-processor- ,.-.- s1'stem that was as powerful as a ture because the Industry Standard specific application. -
IMS D7305A IBM 386 PC Occam 2 Toolset Delivery Manual
·. ,i .. W .. ~.~.. mrumos®[] IMS D7305A IBM 386 PC occam 2 Toolset delivery manual INMOS"'Y£'-is a member of the SGS-THOMSON Microelectronics Group © INMOS Limited 1993. This document may not be copied, in whole or in part, without prior written consent of INMOS. •,DIITI11OS·, IMS, and occam are trademarks of INMOS Limited. ~~em is a registered trademark of the SGS-THOMSON Microelectronics Group. INMOS Limited is a member of the SGS-THOMSON Microelectronics Group. WATCOM is a trademark of WATCOM Systems Inc. INMOS document number: 72 TDS 389 01 IContents 1 Introduction . 1 1.1 Layout of this manual . 1 1.2 Prerequisites for running the toolset . 1 1.3 Compatibility with previous releases . 1 2 Installing the release . 3 2.1 Installation . 3 2.2 Hosted and non-hosted tools . 4 2.3 Setting up the toolset for use . 5 2.3.1 Setting the FILES variable . 5 2.3.2 Setting the correct PATH . 5 2.3.3 Configuring the DOS extender . 5 2.3.4 Setting up the iserver . 6 Selecting the required iserver . 6 Special notes for users of the PC-NFS iserver . 7 Notes common to both versions of the iserver . 7 Note for users of the IMS B008 motherboard . 8 2.3.5 Use of the iserver by transputer tool driver programs 8 2.3.6 Setting the board memory size . 9 2.3.7 Setting root memory size for idebug . 9 2.3.8 Setting a file system search path . 9 2.3.9 Setting the device driver and terminal definition file 10 2.3.10 Environment space . -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Microsoft Windows Resource
Chapter 13 Troubleshooting Windows 3.1 This chapter provides information about troubleshooting Microsoft Windows for both general users and experts. If you have trouble installing Windows, or if Windows doesn’t run as well as you expected, this chapter will help you find out why and show you how to isolate and solve common problems. Related Information • Windows User’s Guide: Chapter 15, “Maintaining Windows with Setup” See also Chapter 4, “Troubleshooting,” in the Getting Started booklet • Windows Resource Kit: “The Troubleshooting Flowcharts for Windows 3.1” in “Welcome” Contents of this chapter About Troubleshooting.....................................................................................396 Getting Started with Troubleshooting........................................................396 Creating a “Clean Boot” for Troubleshooting ...........................................398 Troubleshooting Setup......................................................................................399 Troubleshooting TSR s During Setup .........................................................400 Troubleshooting MS-DOS Mode Setup......................................................401 Troubleshooting Windows Mode Setup ....................................................402 Troubleshooting Windows Configuration ........................................................403 Troubleshooting the Desktop Configuration .............................................403 Troubleshooting TSR Compatibility Problems ..........................................404 -
HP-UX and K4
HP 3000 Series 920 A new low-cost solution to HP PA-RISC HEWLETT PACKARD A Table of Contents Editor WbrkshtSans 17 General TkacyWesfer HB introducfs HP-PHIGS Vxsbn 2.0 HP f2mmeZs is published monthly for 1 IEP Exemtivc T- Series echedule WPC++1SorftBcnch for objw-~tiwrted Hewiett-PacWl's value-added busi- hcal RTR plxrdwts runwed fmm price I& tlesses to pmvide you with inEodon - about HPf paducts and services ta 17 Apollo help you be more successful. Objenmrb Eor SmanW-80 - rn don Muititcger Systems fa ApMo workmrions For further information on my of the 2 General Da~mmbnWSPwm.39 products and in TWoncafmem0@~farHP3000& obscl1- sewices dim& lhnWC:++ %mian 1.2 obsob$xnce HP Cham&, p1am cantract your HP HPWOO~tmna sales rep. BP XUD and HP 9QBO pi&@- 20 HP-UX c2xooiwmJAMfar-mccsilnd HP ApoMo 9000 Stries 400 intaxfuction See back cmw for subserfption ='ppo* HP-UXReaease7~fbrOrHP9000es30[1 Upm& d Wo~m~ticm. release HIJ tWtBa& dabL and400proClucts LAM comunwith Ad-WnL ~mgtheHPPenrorralVi Note: 1Yb0 all HP comprJSer products Macintosh HPmModelmMm~~ ate sol$ and styy,arred in dl comties. upgrade! IEQ-UX 7.0 prb iae- Please &ck wS$h putlocal IIP sales syilwm PtrsoM lGopnputers oflce* Inmucisg Phe mw3000 I' Rew 24 General H&ett-J%zcm daas mt warrant the Ncw SbmXurd Sdutions RWap far HP~~e8OU)and~L3( 1 M-~B PIUS ~e be remav~dfram price 1u:cumcy 4t.k i@@n p&d Inaadue* Rasase B(M listNd1 in PIP Chmxls ad shall not be Gable HPALWEMOL HP Pamble Plus iwmaries dismtsnm for use made elf ths i$om'on NS ptrfbtmsaGe impmvemdts with 25 Desktop eontaiwd breinIOZ&~'~OR psovidsd MPE XL Rcl~aae2.1 New~HP~386/25;dwktDp~ tn HP CWs$ subw to chge Intmdueing HP CM~C&~X HFSup~~u~aaoasHP~ withut mke.