High-temperature CVD silicon films for crystalline silicon thin-film solar cells

Dissertation

zur Erlangung des akademischen Grades des

Doktors der Naturwissenschaften (Dr. rer. nat.)

an der Universität Konstanz Fakultät für Physik

vorgelegt von

Sandra Bau

Fraunhofer Institut für Solare Energiesysteme Freiburg

2003 Referenten: Priv. Doz. Dr. Gerhard Willeke Prof. Dr. Wolfram Wettling Contents

1 Introduction 1

2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells 3 2.1 Principle of CSiTF solar cells ...... 3 2.1.1 General ...... 3 2.1.2 CSiTF solar cell components ...... 4 2.2 Thin Film Concepts...... 5 2.2.1 Low-temperature approach...... 6 2.2.2 High-temperature approach...... 7 2.2.3 Transfer techniques ...... 7

3 Chemical vapor deposition (CVD) of silicon 9 3.1 Silicon deposition techniques...... 9 3.1.1 Liquid Phase Epitaxy (LPE)...... 9 3.1.2 Physical Vapor Deposition (PVD) ...... 10 3.1.3 Chemical Vapor Deposition (CVD) ...... 10 3.1.4 Overview on deposition techniques and applications ...... 12 3.2 Deposition principle of silicon by thermal CVD...... 13 3.2.1 Transport ...... 13 3.2.2 Thermal equilibrium conditions ...... 13 3.2.3 Reaction kinetics ...... 15 3.2.4 Chemical yield...... 19 3.3 Reactor design for APCVD...... 20 3.4 APCVD at Fraunhofer ISE...... 21 3.4.1 Reactor design ...... 21 3.4.2 RTCVD100 ...... 22 3.4.3 RTCVD160 ...... 27 3.4.4 Continuous CVD (ConCVD) ...... 28 3.5 Summary ...... 30

4 Process Optimization for RTCVD100 33 4.1 Metrology ...... 33 4.1.1 Thickness measurement ...... 33 4.1.2 Doping control...... 36 4.1.3 Impurity concentration measurements by SIMS ...... 41 4.1.4 Defects...... 42 4.1.5 Lifetime measurement by MW-PCD...... 42

i 4.2 Epitaxial deposition...... 42 4.2.1 Pre-epitaxial sample cleaning...... 43 4.2.2 Thickness uniformity...... 43 4.2.3 Doping of epilayers ...... 46 4.2.4 Crystal quality ...... 48 4.2.5 Lifetime measurements ...... 49 4.2.6 Chemical analysis...... 50 4.2.7 Surface morphology of multicrystalline layers ...... 52 4.3 Silicon deposition on foreign substrates...... 54 4.3.1 Thickness uniformity...... 54 4.3.2 Doping of seeding layers...... 56 4.4 Layer growth in RTCVD160...... 56 4.5 Summary ...... 58

5 Doping of epitaxial silicon layers 61 5.1 Dopant incorporation...... 61 5.2 Doping profiles of epitaxial layers ...... 65 5.3 Experimental carrier concentration profiles ...... 66 5.3.1 Boron diffusion and evaporation...... 66 5.3.2 Background doping and memory effect ...... 68 5.3.3 Doping profile of intrinsic epilayers...... 71 5.3.4 Standard epitaxy...... 76 5.3.5 Deposition with pre-epitaxial diffusion...... 80 5.3.6 High-low deposition...... 81 5.4 Effect of doping profile on solar cell performance...... 82 5.5 Improved gas system design...... 84 5.6 Summary ...... 85

6 Epitaxial thin-film solar cells 87 6.1 Solar cell concept ...... 87 6.1.1 Silicon substrate materials...... 88 6.1.2 Efficiency ...... 89 6.1.3 Epitaxial deposition systems ...... 90 6.1.4 Efficiency table for epitaxial thin-film solar cells...... 90 6.2 Solar cells on Cz-Si substrates ...... 91 6.2.1 Solar cell processing...... 92 6.2.2 RTCVD-process A vs. B...... 93 6.2.3 Epilayer quality ...... 95 6.2.4 Comparison of solar cell technologies ...... 96 6.2.5 Overview on solar cell efficiencies ...... 101 6.2.6 Characterization by lock-in thermography...... 102 6.2.7 Summary ...... 104

ii 6.2.8 Solar cell simulation...... 105 6.3 Solar cells on mc-silicon substrates...... 111 6.4 Solar cells on reclaimed silicon wafers ...... 116 6.5 Front surface texturing for epitaxial cells...... 119 6.6 Innovative solar cell technology by CVD ...... 120 6.6.1 Emitter epitaxy ...... 120 6.6.2 Boron BSF epitaxy and diffusion...... 120 6.6.3 In-situ HCl texturing ...... 121 6.7 Summary ...... 121

7 Silicon thin-film solar cells on insulating substrates 123 7.1 Solar Cell principle and technology ...... 123 7.1.1 Layer system ...... 123 7.1.2 Cell technology ...... 124 7.2 Silicon thin-film solar cells on ceramic substrates ...... 125 7.2.1 Material and solar cell preparation...... 126 7.2.2 Silicon thin-films on silicon-infiltrated silicon carbide ceramics (SiSiC)...... 128 7.2.3 Silicon thin-films on hot-pressed silicon nitride ceramics ...... 132 7.2.4 Silicon thin-films on tape cast silicon nitride ceramics...... 136 7.2.5 Silicon thin-films on SiAlON ceramics...... 141 7.3 Summary ...... 143

8 Summary 145

Deutsche Zusammenfassung 149

Appendix A Abbreviations 153

Appendix B Solar cell fundamentals 155

Bibliography 159

Publications 171

Acknowledgements 173

1 Introduction

The development of renewable energies is motivated by the wish to avoid the problems associated to nuclear and fossil energy production and to use environment-friendly energy sources instead. During the last decade the photovoltaic (PV) market has experienced a steady growth of 15-25% with the growth rate even exceeding 40% in 2000 [1]. In the near future a further increase in growth rate is expected. Despite this rising trend, energy production by photovoltaic sources only plays a minor role with respect to the world’s energy production. At present, PV electric energy is still more costly than grid electricity and government subsidies programs are running to support the application of PV systems. Today’s PV module market is dominated by crystalline silicon solar cells. In 2001, about 91% of the PV market share were held by crystalline silicon, the major part being provided by polycrystalline (48%) and single-crystal (35%) material (Figure 1.1). Silicon solar cell manufacturing benefits from a mature technology and expertise available from microelectronics, non-toxicity, long-term stability and large material abundance of silicon. Thin-film technologies like amorphous silicon (a-Si:H), CIS

(CuInGaSe2) and CdTe make up for only a small fraction of the world’s module market. While the efficiency of a-Si:H modules still ranges on a comparatively low level of 8%, and CIS solar cells have to deal with a possible indium bottleneck, CdTe is the least attractive material due to the high toxicity of Cd and Te. The latter two technologies have just about started pilot-line production.

Si Film a-Si on Cz Slice 0.26% Amorphous Si 4.63% 8.3% Ribbon Si CIS 3.5% 0.18% Cadmium Telluride 0.42%

Single Crystal Si 35.17%

Polycrystal Si 47.54%

Figure 1.1: Market shares of photovoltaic materials (after [2]).

About 40% of the silicon module cost are made up by the silicon wafer [3]. With increasing growth of the photovoltaic market, the demand for crystalline silicon material will rise. Currently, the PV industry obtains silicon wafers and raw material from microelectronic production: off spec, pot-scrap, tops and tails from electronic grade silicon production are used as silicon sources for solar cell manufacturing [4]. The price for a silicon wafer and with that the module price is therefore highly dependent on the microelectronic market. With growing PV industry the need for crystalline silicon 1 2 1 Introduction wafers will permanently rise, while in microelectronics the trend goes to smaller devices and higher device density per wafer i.e. lower material consumption and production. The two counteracting trends led to an imminent silicon feedstock bottleneck for PV applications. Today’s research activities seek to avoid or diminish this shortage by the development of alternative silicon solar cell concepts with reduced silicon consumption and by the establishment of an independent solar grade silicon production [5]. In the long term, thin-film cells (silicon or other materials) are assumed to become the market dominating technology. The concept of crystalline silicon thin-film (CSiTF) solar cells can substantially reduce silicon material consumption and has the potential to reach high efficiencies comparable to wafer silicon solar cells. During the past decade a lot of research has been done on this subject and a large variety of silicon thin-film solar cell concepts have been investigated. At present, none of the approaches has made a final breakthrough to industrial production and the neck-and-neck race continues to push research activities further on. This work deals with the deposition of silicon films for CSiTF solar cells and the realization of this cell concept by different approaches. The following chapter explains the basic components of a crystalline silicon thin-film solar cell and gives an overview on current approaches. In the third chapter, silicon deposition techniques are reviewed and the potential of atmospheric pressure chemical vapor deposition (APCVD) for an application in CSiTF solar cell technology is motivated. The silicon deposition process by chemical vapor deposition is theoretically explained and an example for a silicon growth model is given. Subsequently the silicon deposition and reactor design pursued at Fraunhofer ISE is presented. The APCVD reactor concept is adapted to the needs of photovoltaic industry an therefore differs from commercial reactor configurations. Technical details are discussed and key features of the reactor design are explained. The characterization and optimization of silicon epitaxial layers (epilayers) and silicon layers on foreign substrates (seeding layers) by APCVD is presented in chapter four. Silicon films grown under different process conditions are analyzed and standard processes are defined, which allow for a deposition of silicon layers with well defined properties. The controlled growth of silicon films is a prerequisite for a successful preparation of any device based on these layers and the results obtained during the optimization process are therefore of great importance for the entire work. The detailed characterization of carrier concentration profiles in silicon epilayers by Spreading Resistance Profiling is subject of chapter five. Important insight on the effect of the gas system on carrier concentration profiles and on the mechanisms of boron incorporation during silicon deposition can be obtained from this analysis. Chapter six deals with the preparation of epilayers on different electrically inactive silicon substrates for a preparation of epitaxial silicon thin-film solar cells. The application of industrial type solar cell processing techniques on epitaxial material is a main topic of this work and an extensive investigation of possible interactions between epilayers and different solar cell process steps is carried out. The use of multicrystalline and potential low-cost reclaimed silicon wafers as substrates is studied. In the last chapter, silicon thin-film solar cells on non-conductive ceramic substrates are investigated. Silicon films are prepared on four different ceramic substrates by silicon layer deposition, recrystallization and epitaxy of the base layer. Sample structure and solar cell performance are characterized in detail and the suitability of the applied ceramic substrates is evaluated. 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells

Reduction in final module cost is one of the basic motivations in silicon solar cell research today. Main focus is put on a reduction in electronic grade silicon usage and solar cell concepts consuming less silicon material and ways to bypass the silicon feedstock bottleneck are currently investigated. The concept of crystalline silicon thin-film solar cells tackles this problem by using an active device region which is reduced to a thin layer, only about one tenth of conventional wafer cells. The fundamental principles and different approaches for CSiTF solar cells are reviewed in this chapter.

2.1 Principle of CSiTF solar cells

2.1.1 General Cost-saving is the key word associated to most solar cell research subjects today. Considering the cost breakdown for a commercial silicon PV module, the silicon wafer makes up for 42% of the final module cost, while the remaining 58% are shared by module fabrication and solar cell technology [3]. With increasing growth of silicon module production the consumption of electronic grade silicon for PV applications rises and silicon feedstock is assumed to get short in the future, leading to an increase in material cost. The largest cost-saving potential in silicon module production can be expected from the silicon wafer. Reducing silicon feedstock cost and lowering silicon consumption are two ways to reduce the price for silicon solar cell material. The latter solution is addressed in the following. Conventional silicon solar cells are prepared on silicon wafers of 250-300 µm thickness. The technology used for wafering and the need for mechanical stability of the device determine the wafer thickness. With respect to solar cell performance thinner base layers have the potential to yield similar or even higher efficiencies compared to conventional “thick” wafer cells and therefore many research groups follow a “thin silicon film” approach to reduce material consumption.

- Thin wafers Wire sawing of silicon ingots is state-of-the-art technology for the production of silicon wafers resulting in wafer thickness of 250-300 µm with a kerf loss in the range of 200 µm. From a technical point of view a reduction of kerf loss is difficult to realize, due to an increased danger of wire breakage with decreasing saw wire thickness. Reducing the wafer thickness and therefore increasing wafer output is more feasible and can substantially lower material cost [6], [5] without suffering from efficiency losses. While the production of thin wafers (~100 µm thickness) is already technically feasible, solar cell processing of these wafers is still a problem due to the increased fragility of the material. At present, research activities in this area deal with the development of new wafering technologies and the development of solar cell processes adapted to the properties and needs of thin wafers.

3 4 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells

- Silicon ribbons Silicon ribbon technologies bypass the necessity for ingot production and the associated loss in silicon material. The edge-defined film-fed growth (EFG) by ASE is the most mature ribbon technology. Following this approach, silicon sheets with a thickness of 250-300 µm are directly pulled from the melt, laser cut and used as silicon wafer material. The String Ribbon technique by Evergreen Solar, the Dendritic Web by Ebara, RGS (ribbon growth on substrate) by ECN (Netherlands Energy Research foundation) and SSP (silicon sheets from powder) by Fraunhofer ISE constitute other important silicon ribbon techniques. Higher throughput and further decrease in film thickness are two major issues in silicon ribbon development to become industrially relevant technologies. An overview on this issue can be found in [7].

- Silicon thin-film solar cells The concept of silicon thin-film solar cells is based on the deposition of a thin (<50 µm) active silicon layer on a low-cost substrate. Within this approach the manufacturing of silicon ingots and wafering is avoided and material loss is mainly determined by the chemical yield of the deposition process. Moreover, silicon deposition from a gaseous source is used in most approaches with the silicon-containing source gas being an early element in the chain of silicon ingot production. The benefit from using a crystalline silicon thin-film concept compared to conventional wafer technology is the potential to reach high efficiencies at low material consumption. A detailed overview on crystalline silicon thin-film concepts is given in [8] and [9]. The cost per MWp photovoltaic electric power production is determined by module manufacturing cost, module efficiency and up-time. Therefore the choice of the solar cell concept to be followed is actually a trade-off between the two first aspects.

2.1.2 CSiTF solar cell components The working principle of a solar cell is extensively discussed in various textbooks and shall not be described here [10], [11]1. Instead, the essential features of a CSiTF solar cell will be explained to enable an understanding of the device structure.

Efficiency potential Reducing the thickness of a solar cell results in an increase in open-circuit voltage, if the short-circuit current can be maintained and surface recombination velocities are sufficiently low [12]. So, if efficient light trapping and surface passivation schemes can be provided, a solar cell with reduced thickness can even yield higher efficiencies compared to a corresponding “thick” wafer cell, assuming equal bulk diffusion lengths. This holds especially for low quality material featuring low minority carrier diffusion lengths. The potential of crystalline silicon thin-film solar cells and similarly thin crystalline silicon solar cells is based on these interrelations. An indicator which is often used to qualitatively estimate the potential of a solar cell is the ratio of cell thickness W to bulk diffusion length Ln. Assuming zero surface recombination velocities and active base thickness substantially smaller than bulk diffusion length, the saturation current density is

1 A short introduction to solar cell device physics is given in the appendix. 2.2 Thin Film Concepts 5

proportional to the ratio W/Ln i.e. the lower the base thickness at constant diffusion length, the lower the saturation current [12]. For low quality material, a reduction in base layer thickness is therefore of advantage. As a rule of thumb the effective minority carrier diffusion length in the base should exceed 2-3 times the layer thickness to achieve reasonable efficiencies for CSiTF solar cells. In the appendix, the correlation between saturation current, open-circuit voltage and the ratio W/Ln is derived.

Light trapping Silicon is an indirect semiconductor and a wafer thickness exceeding 140 µm is needed to absorb 90% of the incident photons of the solar spectrum (AM1.5)2. Reducing the active base thickness to 20 µm a fraction of about 75% of the incident photons can be used for photocurrent generation [13]. The photon absorption capacity in a thin film can be increased by increasing the optical path length in the layer. Features leading to such an enhancement are commonly referred to as light trapping schemes. In silicon thin-film solar cells an efficient light trapping is mandatory to achieve high photocurrents despite the reduced absorber thickness. Surface texturing combined with a diffuse back side reflector effectively confines the incident light to the active device region. Apart from increasing the optical path length, the surface texturing also reduces reflection. Similarly, antireflection coatings deposited on the surface of the solar cell decrease the fraction of reflected light which is coupled into the bulk of the device instead.

Surface and bulk passivation With decreasing device thickness surface recombination losses gain in importance and surface passivation schemes are indispensable. While the front surface can be well passivated by oxide or nitride layers, the rear surface of the active base region is given by the highly recombinative substrate surface for thin-film solar cells. Minority carriers reaching this surface quickly recombine and are lost for photocurrent generation. The implementation of a back surface field (BSF), a highly doped region at the back of the base, confines the minority carriers to the lower doped base region, thereby reducing the rear surface recombination losses. Recombination on grain boundaries dominates minority carrier lifetime in polycrystalline silicon thin- film solar cells. Passivation of grain boundaries e.g. by hydrogen is often used to reduce recombination and increase bulk minority carrier lifetime.

2.2 Thin Film Concepts Traditionally, the solar cell concepts for crystalline silicon thin-film cells are divided into the so-called high-temperature and low-temperature approach, according to the maximum temperature the device can tolerate during processing. The threshold temperature is usually determined by the temperature stability of the substrate to be used. Within this classification the transfer (or lift-off) techniques take an exceptional position. Using this approach, epitaxial silicon films are grown at high or medium temperatures on ideal silicon wafers and subsequently transferred to low-cost, mechanically supporting substrates. So, with respect to the host substrate used for silicon deposition, this technique

2 AM1.5: Air Mass 1.5, standard solar spectrum used for terrestrial solar cell calibration. The sunlight passes an air mass which is by factor 1.5 larger compared to vertical incidence. 6 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells belongs to the high-temperature approach although the final supporting substrate is in general a low- temperature material. In the following, the transfer techniques are discussed in a separate section. Common to all approaches is the need for a suitable high-rate silicon deposition tool to satisfy the need for high throughput imposed by industrial production.

2.2.1 Low-temperature approach Within the low-temperature approach, glass is the most prominent and most attractive substrate material. Borosilicate glasses and soda lime glasses are mechanically stable up to 650°C and 550°C respectively, and can be produced on a large scale at comparatively low cost. In addition, plastic films and steel have been investigated as potential low-cost substrates. Silicon deposition and solar cell processing have to be adjusted to the temperature limit imposed by these substrate materials. PECVD, IAD, and HWCVD3 are widely used for the deposition of silicon layers at low temperatures in silicon thin-film solar cell R&D. These techniques are characterized by growth rates in the range of several ten nm/min and the deposited silicon films feature a crystal structure from microcrystalline4 to amorphous. The latter characteristic represents a major drawback of the low-temperature approach, since the minority carrier lifetime in these materials is limited by recombination at grain boundaries. The application of recrystallization steps allows an enlargement of the grain size and therefore an increase in bulk diffusion length. However, due to the temperature restriction, the recrystallization process is confined to few low-temperature techniques e.g. solid-phase crystallization [14], aluminum- induced crystallization [15] or laser-beam crystallization [16]. Up to now, no satisfactory results could be achieved using these methods and therefore only few routes are still pursued. The concept of micromorph silicon tandem cells was introduced by the research group at the Institute for Microelectronics at the University of Neuchâtel [17]. The micromorph tandem structure is composed of a high-bandgap amorphous top and a low-bandgap intrinsic microcrystalline bottom layer, deposited by VHF-PECVD5. Stable solar cell efficiencies of 10.7% and integrated module (24 cm2) efficiencies of 9.8% have been achieved using a 2 µm bottom cell, demonstrating the potential of this concept [18]. Compared to a-Si:H solar cells, the micromorph tandem cells feature an enhanced stability and the potential for higher efficiencies. Using a similar concept, the Kaneka research group achieved initial efficiencies of 14.5% for a 1 cm2 solar cell and 12.3% for an integrated solar cell module with an aperture area of 3738 cm2 [19]. However, only little details concerning deposition or recrystallization techniques and growth rates are disclosed.

3 PECVD: Plasma-Enhanced Chemical Vapor Deposition, IAD: Ion-Assisted Deposition, HWCVD: Hot-Wire Chemical Vapor Deposition. All silicon deposition techniques will be explained in the following chapter. 4 The notation of silicon crystal structures is classified according to the grain size: nanocrystalline (nc) with 1- 100 nm grain size, microcrystalline (µc) with 100 nm-1 µm grain size, polycrystalline with grain size exceeding 1 µm and multicrystalline (mc) with grain size in the mm and cm-range. 5 VHF-PECVD: Very High Frequency Plasma-Enhanced Chemical Vapor Deposition. 2.2 Thin Film Concepts 7

2.2.2 High-temperature approach Temperatures up to the melting point of silicon can be applied within the high-temperature approach. This enables the use of fast silicon deposition techniques like APCVD and liquid-phase recrystallization e.g. by zone-melting, yielding large grain sizes in the mm or even cm-range. Moreover, conventional diffusion and metallization processes are feasible and common silicon solar cell technologies can be used. The large variety of solar cell concepts in the high-temperature approach can be classified according to the substrate in use. The need for high temperature stability restricts the choice of potential substrate materials to few candidates like low-cost silicon and high-temperature ceramics. Using low-cost silicon as substrate material the active silicon base layer can be deposited by epitaxy (epitaxial solar cell) at high temperatures. Potential low-cost silicon materials are e.g. reclaim wafers from microelectronic industry or cast metallurgical-grade (MG) silicon wafers. The epitaxial solar cell represents a silicon wafer equivalent which can be processed by conventional techniques and can therefore be directly introduced into standard industrial production lines, making this structure a very attractive concept. The preparation of epitaxial thin-film solar cells is one of the major subjects of this work and is therefore discussed in detail in chapter 6. Silicon deposition on foreign substrates results in a microcrystalline grain structure and the application of recrystallization steps to increase the grain size becomes indispensable. Low-cost substrates often inhibit high impurity concentrations and diffusion barriers between substrate and active silicon layer are necessary to prevent a contamination of the base layer. At the same time, the diffusion barrier can act as backside reflector, thereby increasing the optical path length and photocurrent generation. Using electrically conductive substrate and barrier layer, a conventional 2-side contact scheme can be applied. Otherwise, alternative contact designs have to be developed e.g. with both contacts located on the front side of the cell. The potential of this concept has been demonstrated by the Mitsubishi Electric Corporation, where an efficiency of 16.45% could be achieved for a silicon thin-film solar cell based on a recrystallized silicon layer on SiO2 encapsulated silicon substrate [20]. The main drawbacks of the high-temperature approach is the lack in adequate high throughput silicon deposition reactors and the substrate and barrier layer question.

2.2.3 Transfer techniques The general concept of transfer techniques is based on the formation of a high-quality single-crystal silicon thin-film on a host-substrate by epitaxy, contact and emitter formation on the epitaxial layer, attachment of the epilayer to a mechanically supporting substrate and separation of the device from the host substrate. To make the transfer technique cost-effective, the host substrate has to be recycled to enable multiple use. Thin silicon films of excellent crystal quality can be prepared by this method and high efficiencies have already been demonstrated. Critical issues of this concept are the detachment procedure, recycling of the host substrate and the need for high throughput silicon deposition.

The Epilift technique The Epilift concept has been introduced by the PV research group at The Australian National University (ANU). A single-crystal silicon wafer covered with a mesh-like oxide layer is used as host substrate. LPE is applied for silicon deposition and selective epitaxial growth occurs on the exposed 8 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells silicon area leading to an epitaxial silicon waffle-grid. Using an interdigitated grid design, solar cell processing is carried out with the epilayer still being attached to the substrate. The epilayer is detached from the substrate by laser cutting, wet-chemical etching or by applying a mechanical force. A detailed description of this method can be found in [21]. Efficiencies of up to 13% have been recently reported on a 1 cm2 solar cell [22].

Porous silicon Several research groups focus on the application of single-crystal substrates with sacrificial porous layer for thin-film formation. In general, at least two layers of different porosity are formed on the substrate surface, with the top and bottom layer featuring low and high porosity respectively. Thermal annealing of the sample under hydrogen leads to a closing of the pores in the top porous layer, which is subsequently used as substrate for epitaxial deposition of a thin silicon film. After epitaxy, emitter contact formation is accomplished on the epilayer surface, a superstrate (usually glass) is attached to the surface and separation of the semi-finite device from the host wafer is done via the second, weak porous layer. After lift-off the host substrate can be reused. Using this approach, the research group at the Bavarian Center of Applied Energy Research (ZAE) introduced the Ψ-process (Ψ: psi for perforated silicon) [23] and the PSI-process (porous silicon) [24]. Solar cells based on so-called QMS-layers (quasi-monocrystalline, referring to the structure of the top porous layer) [25], [26] were presented by the Institute of Physical Electronics and the University of Stuttgart leading to efficiencies up to 16.6% for silicon thin-films transferred to glass superstrates [27]. Using a similar process route, the Sony Corporation (Japan) reported 12.5% efficiency for silicon films transferred to transparent plastic films [28]. 3 Chemical vapor deposition (CVD) of silicon

With the advent of silicon based electronic devices the deposition of silicon layers became a key technology in microelectronic production. Polycrystalline and especially epitaxial silicon layers are widely used e.g. in bipolar and MOS applications. Silicon thin-film solar cells are based on the use of a thin active silicon layer for photocurrent generation and therefore the deposition of silicon films on various substrate materials has also become a major issue in this research area. The silicon deposition techniques used for photovoltaic applications greatly benefit from the expertise in microelectronic industry.

An overview on silicon deposition techniques and applications is given in this chapter. The principles of thermal CVD are explained in more detail in terms of transport phenomena and chemical reactions and common reactor designs for APCVD systems are presented. The chapter closes with a technical description of the APCVD systems developed at Fraunhofer ISE for photovoltaic applications.

3.1 Silicon deposition techniques For the deposition of silicon a large variety of techniques exists which can be roughly categorized by the silicon source in use. In liquid-phase epitaxy (LPE) a melt consisting of silicon and a metal solvent is used as silicon source. The deposition from vapor phase can be split up in two groups: physical vapor deposition (PVD) and chemical vapor deposition (CVD). Physical vapor deposition refers to techniques very similar to evaporation where solid silicon is transferred into the gas phase under high vacuum conditions. Solid-source molecular beam epitaxy (MBE) is the most prominent example to be mentioned in this context. Chemical vapor deposition denotes deposition processes which are based on chemical reactions with the silicon-containing reactants being supplied by a gaseous source. Common methods to activate the chemical reaction are thermal heating of the samples (resistive heating, radiofrequency induction, high-intensity lamps, lasers), plasma and catalytic activation. In plasma- enhanced chemical vapor deposition (PECVD) the activation energy is provided by thermal heating supported by plasma making depositions at low temperatures possible.

3.1.1 Liquid Phase Epitaxy (LPE) In silicon liquid-phase epitaxy a metal solvent saturated with silicon is used as silicon source. Solvents which are typically applied are indium (In) and tin (Sn) or other low-melting metals. Intentional doping of the growing layers is achieved by adding suitable dopants like gallium (Ga) for p-type and indium-phosphite (InP) for n-type layers from In melt. For silicon growth the solvent is heated and brought into contact with silicon bulk material thus producing a silicon saturated melt according to the phase-diagram. When saturation is reached the melt is cooled down resulting in a supersaturation.

9 10 3 Chemical vapor deposition (CVD) of silicon

Silicon samples are introduced into the melt and excessive silicon crystallizes on the free silicon surface. Starting from temperatures well above 900°C the melt is slowly cooled down at rates in the range of few Kelvin per minute and below. The growth process takes place near thermal equilibrium with growth rates in the range of 1 µm/min. For LPE tipping boat or centrifugal systems are traditionally used [29]. Long process cycles and small wafer size capacity result in low throughput. The necessity for solvent metals of high purity (6N) represents a significant cost factor for this technology. Silicon LPE is mainly used in photovoltaic research applications.

3.1.2 Physical Vapor Deposition (PVD)

Molecular Beam Epitaxy (MBE) Silicon deposition by MBE from a solid source is accomplished by electron beam evaporation of silicon in ultra-high vacuum (UHV). Ultra-pure silicon source materials have to be employed to keep the contamination level of the deposited films on a low level. Layer doping is achieved by coevaporation of dopant material e.g. aluminum (Al) for p-type and Ga or antimony (Sb) for n-type doping [30]. Silicon deposition by MBE can be performed in a wide temperature range, from room temperature to temperatures well above 500°C. For the growth of device-quality silicon epilayers, sample temperatures exceeding 450-500°C have to be used. Typical growth rates are 0.6-6 nm/min [30]. The most crucial issue in MBE is the necessity for very clean sample surface, reactor and vacuum conditions to grow high quality epilayers. MBE allows a low-temperature deposition of very thin films on a submicron-scale with sharp transition regions. Applications of MBE include e.g. silicon submicron devices, deposition of metal silicides or heteroepitaxy of thick strained SiGe layers on Si substrates.

Ion-Assisted Deposition (IAD) Similar to MBE, solid silicon is evaporated by electron beam evaporation in IAD. About 1-5% of the evaporated silicon atoms are ionized and accelerated onto the substrate. Due to the kinetic energy of the ions, the substrates can in principle be maintained at lower temperatures for silicon deposition compared to MBE. In [31] epitaxial deposition at 525-650°C with growth rates of 0.06-0.3 µm/min are reported. In silicon thin-film solar cell R&D, IAD is used for the deposition of silicon films on low- temperature substrates.

3.1.3 Chemical Vapor Deposition (CVD)

Thermal Chemical Vapor Deposition Thermal CVD is based on the decomposition of silicon-containing source gases at the heated sample surface and subsequent incorporation of silicon atoms into the growing film. Thermal CVD can be carried out at different operation regimes depending on process temperature and pressure. Atmospheric pressure CVD (APCVD) operates at high deposition temperatures up to 1300°C where deposition rates up to 10 µm/min can be achieved. Trichlorosilane (SiHCl3, TCS) highly diluted in hydrogen is typically used as silicon source gas. In-situ layer doping is achieved by adding suitable 3.1 Silicon deposition techniques 11

dopant gases, e.g. diborane (B2H6) and phosphine (PH3) diluted in hydrogen for p-type and n-type doping respectively. APCVD is in favor of epitaxial depositions because the high process temperature enables an optimal arrangement of deposited atoms in the silicon crystal matrix and crystals with extremely low defect densities can be grown. Typically, silicon epitaxy by APCVD is carried out in a temperature range of 950-1250°C. Compared to other deposition techniques, where high vacuums and therefore complex pumping systems are necessary, little technological effort is needed for CVD at atmospheric pressure and continuous systems are feasible. Most APCVD system can also be operated at reduced pressure (RPCVD). The deposition chemistry is identical to APCVD but the process pressure is reduced to approx. 103–104 Pa. Therefore epitaxial depositions can be carried out at lower temperatures without deterioration of crystal quality. Low-pressure CVD (LPCVD) is mainly applied for the deposition of polysilicon layers. The deposition of epitaxial silicon is also feasible but not widely used. SiH4 typically serves as silicon source gas and B2H6 and PH3 as dopants. At deposition temperatures in the range of 580-630°C and low pressures of 10-100 Pa, polysilicon layers can be grown with deposition rates of 5-20 nm/min [33]. LPCVD is widely used in microelectronic industry for the deposition of polycrystalline silicon and amorphous materials [34]. Ultrahigh-vacuum CVD (UHV-CVD) is operated at still lower pressures than LPCVD (10-1-10-3 Pa). A load-lock is necessary and turbo-molecular pumps are essential to reach the required vacuum. Ultra- clean process conditions are mandatory to enable epitaxial layer growth. Compared to LPCVD the diffusivity of molecules is increased and depositions are possible at low temperatures, down to 550°C [34]. Similar to MBE, UHV-CVD allows an accurately controlled deposition of high quality, thin Si and SiGe epitaxial layers with extremely sharp transitions.

Plasma-Enhanced Chemical Vapor Deposition (PECVD) PECVD is based on the dissociation of a silicon source gas in a plasma and subsequent deposition on a heated substrate. Radio frequency (RF) power in the MHz range is commonly used as excitation source. Sample temperatures below 400°C are feasible which enables the processing of temperature sensitive samples at low thermal budget. The operating pressures range from 10-0.1 Pa and typically silane (SiH4) is used as silicon source gas. Silicon epilayers may be grown but at lower quality compared to thermal CVD because of the reduced deposition temperature. PECVD allows the deposition of a large variety of materials with different properties. It is widely used for the deposition of dielectric layers, hydrogenated microcrystalline (µc-Si:H) and amorphous (a- Si:H) silicon films.

Hot-Wire CVD (HWCVD)

In hot-wire or thermocatalytic (Cat) CVD SiH4 is decomposed by a catalyst, usually a heated tungsten or tantalum wire in a low pressure ambient. During the deposition the substrate temperature is held at a constant level in the range of 200-500°C. Amorphous and microcrystalline silicon layers can be deposited at rates up to 300 nm/min and 60 nm/min respectively. HWCVD has raised increasing interest in the past decade because this method allows the deposition of silicon films with improved electrical stability and at higher growth rates compared to PECVD. 12 3 Chemical vapor deposition (CVD) of silicon

Applications in thin-film solar cells and thin-film transistors (TFTs) are currently under investigation [32].

3.1.4 Overview on deposition techniques and applications The demand for a controlled deposition of epitaxial and polycrystalline silicon layers emerged from VLSI technology and applications. In microelectronic industry the focus for e.g. silicon epilayers is on perfect crystallinity, sharp doping transitions as well as thickness and doping uniformity. Sophisticated deposition techniques have been developed and optimized to accomplish these requirements. Today silicon deposition by CVD is state-of-the-art for all epitaxy processes used in microelectronic production. With the ever decreasing size of microelectronic devices and novel device designs, today’s research activities focus on industrial feasible technologies for very thin epilayers deposited at low temperatures. Silicon deposition technologies have also become an important tool in silicon thin-film solar cell R&D for the formation of thin active base layers. Depending on the solar cell structure and especially on the substrate-type (see section 2.2) different silicon deposition techniques are applied. Similar to microelectronic devices the deposition technique is chosen according to the maximum temperature tolerable for device fabrication.

T [°C] Rate Si-source Si-film Ref. Applications [µm/min]

Liquid Source (LPE)

LPE 950 0.1...1 In solvent Epi-Si [35] Epi-lift, epitaxial thin-film solar cells RLPE6 930 2...4 In solvent Epi-Si [36]

Solid Source (PVD)

MBE >300 0.06...0.12 Solid Si Epi-Si [30] Submicron epitaxial silicon films

IAD 525...650 0.06...0.3 Solid Si Epi-Si [31] Silicon thin-film solar cells on glass, Ψ-process

Vapor Source (CVD)

LPCVD 550...750 0.2 SiH4 Poly-Si [37] Sensors, diodes, transistors, gate electrode in MOS devices, emitter/base contacts in bipolar devices

900...1050 0.1...0.8 SiH2Cl2 Epi-Si [38], [39] Epitaxial thin-film solar cells

APCVD 1170 6...10 SiHCl Epi-Si This work 3 Epitaxial thin-film solar cells, Thin-film solar cells

1000...1200 3...6 SiHCl3 Epi-Si [40] on foreign substrates, QMS and PSI process, bipolar and MOS esp. CMOS applications 950...1050 1...3 SiHCl3 Epi-Si [41]

PECVD 150...450 0.006...0.018 SiH4, SiF4 µc-Si:H, a-Si:H [42]

VHF- 250 0.3 SiH4 µc-Si:H [43] a-Si:H solar cells, micromorph tandem solar cells, PECVD sensors, thin film transistors

HWCVD 250...500 0.06...0.3 SiH4 µc-Si:H, a-Si:H [44]

Table 3.1: Overview on silicon deposition techniques and applications.

6 RLPE: Rapid LPE. 3.2 Deposition principle of silicon by thermal CVD 13

Table 3.1 gives an overview on the most commonly used silicon deposition techniques and main applications with emphasis on silicon solar cell R&D.

3.2 Deposition principle of silicon by thermal CVD The deposition of microcrystalline and epitaxial silicon layers by APCVD for silicon thin-film solar cells is the major subject of this work. This section aims to give an insight on the principles of silicon deposition by thermal CVD with main focus on TCS as silicon source gas. In order to predict deposition rates for a given reactor setup and therefore to optimize process parameters and reactor geometry, adequate growth rate models reflecting real conditions are needed. However, the description of the silicon growth process in CVD is a complex issue where gas transport phenomena have to be coupled to chemical reactions on the substrate surface and in the gas phase. A general model describing the entire deposition process involves the solution of many coupled partial differential equations. Because of the large complexity of the problem many authors restrict themselves to a simplified modeling of specific operating regimes e.g. by neglecting gas flow dynamics. The development of improved models and simulation tools is still a current topic of research [45], [46], [47].

3.2.1 Transport The transport phenomena in fluid dynamics are generally described by simultaneously solving the basic equations for conservation of total mass, momentum, energy and chemical species in three dimensions with the process gas assumed to obey the ideal gas law and further assuming adequate boundary conditions [48], [49]. Neglecting all chemical reactions and temperature fields the transport- problem can be numerically solved for different reactor geometry. Taking into account radiation transport and temperature fields the problem is getting more complex due to the temperature dependence of most physical parameters (e.g. heat capacity, thermal diffusivity, gas density, viscosity etc.) determining the mass transport. The main effect on transport phenomena when chemical reactions are included is the local change in gas composition and therefore the change in all other parameters depending on this variable. Transport and reaction kinetics influence each other and a closed solution of the entire deposition problem can only be obtained if both phenomena are accounted for. For a more qualitative description of gas flow dynamics and to allow for an easy determination of the relevance of different transport phenomena without computational methods, dimensionless numbers (e.g. Reynolds, Damkoler, Peclet, Grashof numbers) have been introduced [50]. These numbers can be calculated from reactor geometry, gas phase composition and properties and depending on their value, conclusions about the gas transport behavior in the CVD reactor can be drawn.

3.2.2 Thermal equilibrium conditions Silicon CVD is traditionally based on the deposition from process gases composed of a silicon precursor and hydrogen carrier gas. In thermodynamic equilibrium the partial pressures of all species present in a gas mixture can be calculated using the Law of Mass Action. Considering e.g. a chemical reaction of two species A and B reacting to species C and D: 14 3 Chemical vapor deposition (CVD) of silicon

aA + bB ↔ cC + dD (3.1) where the lower letters denote the stoichiometry constants. If the system is in equilibrium at a given temperature and pressure, then the value of

[C]c [D]d K(T ) = (3.2) [A]a [B]b is constant. The values in square brackets correspond to the concentration of each specie and K denotes the equilibrium constant. Assuming an ideal gas the concentrations can be replaced by the corresponding partial pressure of each gas component. Calculation of the standard free energy change ∆G0 allows to predict whether a reaction will occur or not:

∆G 0 = −RT ln K (3.3) where R and T denote the gas-constant7 and temperature respectively. The free energy change can be obtained from the standard state Gibbs free energies of formation which are listed in the JANAF tables [51]. For ∆G0<0 the reaction under consideration occurs spontaneously, while in thermal equilibrium the change in standard free energy is zero. For a system containing several gas species the equilibrium composition can therefore be determined as a function of temperature if all possible chemical reactions and their equilibrium constants or Gibbs free energy changes are known. To calculate the partial pressures the free energy of the system has to be minimized [52]. The gas phase composition of a Si-H-Cl-system under atmospheric pressure was calculated at thermodynamic equilibrium using a software package [53] which refers to the JANAF tables. In Figure 3.1 the results are shown for two different Cl/H-ratios8 with temperatures varied between 700°C and 1300°C. In commercial APCVD reactors Cl/H-ratios below 0.1 are typically applied, represented by the graph on the left-hand-side in Figure 3.1. In Figure 3.1 (right) the process conditions are set according to the standard epitaxy process used for the RTCVD100 reactor built at Fraunhofer ISE (see section 3.4.2).

Considering the gas phase composition at low temperatures, SiHCl3 and SiCl4 dominate the gas composition for both process conditions. At high temperatures HCl and SiCl2 are the most abundant species. For low Cl/H-ratios and temperatures above 1100°C SiCl2 is clearly the dominating silicon containing compound whereas different silicon chlorides with similar mole fractions are present for high Cl/H-ratios at elevated temperatures. CVD does not occur at thermal equilibrium conditions and therefore the presented calculations do not represent the actual conditions in the CVD reactor. Nonetheless, some general information on possible effects of temperature on the gas phase composition can be drawn from these calculations.

7 Universal gas constant R=8.315 Jmol-1K-1. 8 The Cl/H-ratio denotes the ratio of chlorine to hydrogen atoms in the gas phase. This ratio is constant throughout the deposition process since neither chlorine nor hydrogen are consumed or produced. Growth- related phenomena often do not depend on gas flow rates but on the gas phase composition and the specification of the Cl/H-ratio to characterize the deposition conditions is more convenient. 3.2 Deposition principle of silicon by thermal CVD 15

0 0 H 10 10 2 H 2 Cl/H = 0.045 SiCl 4 -1 -1 10 HCl 10 SiHCl 3

HCl SiCl 2 -2 -2 SiCl 10 10 3 SiHCl SiH Cl 3 2 2 SiCl 3 -3 -3 SiCl 10 SiCl 10 2 Mole fraction Mole fraction Mole 4 SiH Cl 2 2 Cl/H = 0.43

-4 -4 10 10 SiH Cl SiH Cl 3 3

10-5 10-5 800 900 1000 1100 1200 800 900 1000 1100 1200 Temperature [°C] Temperature [°C]

Figure 3.1: Equilibrium gas phase composition for a Si-H-Cl-system as a function of temperature for a total pressure of 1 atm calculated for different Cl/H ratios.

3.2.3 Reaction kinetics Figure 3.2 shows a simplified schematic model for silicon deposition from the gas phase. First, the precursor has to be transported from the main gas stream to the wafer surface (1). On the substrate surface, the precursor is adsorbed (2) and decomposed into a silicon adatom and reaction byproducts. While the silicon atom migrates on the substrate surface and is finally incorporated into the silicon crystal on an energetically favorable site (3), the byproducts are desorbed from the substrate surface (4). In addition to the deposition process, reactions in the gas phase can occur leading to particle generation, or the adsorbed silicon precursor molecule may be desorbed from the surface without being decomposed. Using chlorine containing silicon precursor gases, silicon etching by HCl is an important chemical side reaction. Hydrogen acts as a catalyst for the chemical decomposition process. The growth rate is determined by the supply of reactants and the velocity of the chemical reactions leading to the decomposition of the silicon precursor on the substrate surface. As already pointed out, both parameters depend on each other. Nonetheless some general statements on the temperature dependence of the growth rate can be made. 16 3 Chemical vapor deposition (CVD) of silicon

Main gas stream

Si Byproducts 1

e 4 c a rf u 3 s le Si Si Si p m a 2 S

Figure 3.2: Simplified schematic of silicon deposition from a gaseous silicon source.

Growth rate dependence on temperature For thermally activated reactions, the reaction rate mostly increases with rising temperature and the dependence of the reaction rate constant from temperature can be described by an Arrhenius function (assuming constant reactant concentrations and pressure) [37]: E k = Aexp(− A ) (3.4) k BT

Where k, A, EA, kB and T denote the reaction rate constant, collisional frequency, activation energy, Botzmann’s constant and temperature. An Arrhenius plot based on experimental values can give information on the activation energy and on changes in reaction mechanisms determining the reaction rate. Figure 3.3 shows a typical Arrhenius plot for CVD at constant pressure.

mass transport limited

Slope= -E /k A B surface reaction limited ln (growth rate) ln (growth

1/T

Figure 3.3: Arrhenius plot for silicon CVD. 3.2 Deposition principle of silicon by thermal CVD 17

Two growth regimes are apparent: at low temperatures (surface reaction limited or kinetically controlled regime), the reaction rate is limited by chemical kinetics and small deviations in temperature result in large changes in growth rate. The slope of the Arrhenius curve gives the activation energy of the dominating chemical reaction. Within this growth regime, the deposition of uniform films requires a highly uniform temperature distribution in the reactor. At higher temperatures (mass transport limited or diffusion-controlled regime), the reaction rate shows only a weak dependence on temperature and small deviations in temperature have only little effect on the growth rate. The high temperature enables fast chemical reactions while the reactant supply is constrained by the feed rate, the transport from main gas stream to reaction site or desorption rate of byproducts. In this case, a homogeneous gas distribution is necessary to grow films of high uniformity.

Modeling of silicon growth rate in a SiHCl3-H2-system Apart from temperature, the gas phase composition (or silicon precursor partial pressure) and the total pressure also influence the deposition rate. In [48] a theoretical growth model is presented and experimentally verified for a silicon deposition process based on the decomposition of TCS in a horizontal atmospheric pressure reactor at high temperatures. Because of the close relation to the CVD process used within this work, the approach by Habuka is discussed in this section to illustrate the dependence of growth rate on temperature and gas phase composition. In [48] a 3-dimensional growth model is applied, including transport phenomena as well as chemical surface reactions. The transport equations are solved using the simulation program FLUENT. The chemical reaction leading to silicon deposition is assumed as a two-step reaction. SiHCl3 molecules impinging on the substrate surface are chemisorbed to yield SiCl2 and HCl. While the SiCl2 is adsorbed on the substrate surface (denoted by the asterisk) the HCl is released into the gas phase:

* SiHCl3 → SiCl2 + HCl ↑ (3.5)

Upon adsorption, the SiCl2 is decomposed by hydrogen to yield solid Si, which is incorporated into the crystal, and gaseous HCl according to the following equation:

* SiCl2 + H 2 → Sisolid + 2HCl ↑ (3.6)

In a simplified form the overall chemical reaction can be described by:

SiHCl3 + H 2 → Si + 3HCl (3.7)

In addition, an etching process of solid silicon by HCl and desorption of SiCl2 from the surface is assumed to occur but not taken into account for growth rate modeling. Gas phase reactions are also ignored. The reaction rate for process (3.5) is assumed to depend on the concentration of TCS at the reaction site and the amount of free surface sites available for an occupation by SiCl2:

Vad = kad (1− Θ)[SiHCl3 ] (3.8)

Vad, kad, Θ and [SiHCl3] denote the mole chemisorption rate, rate constant for chemisorption, fraction of occupied reaction sites and TCS-concentration respectively. Similarly, the reaction rate for process

(3.6) depends on the hydrogen concentration and the amount of surface sites occupied by SiCl2:

V = kr Θ[H 2 ] (3.9) 18 3 Chemical vapor deposition (CVD) of silicon

where V is the mole growth rate and kr is the rate constant for the decomposition process. Both reaction rate constants are assumed to depend on temperature through an Arrhenius function. In a steady state, the change in free surface sites is equal to zero and the fraction of occupied surface sites can be expressed as a function of TCS and hydrogen concentration and the reaction rate constants kad and kr. Combined with eqn. (3.9) an expression for the growth rate can be deduced:

kr kad V = [SiHCl3 ][H 2 ] = k[SiHCl3 ][H 2 ] (3.10) kad [SiHCl3 ] + kr [H 2 ]

In this equation, k denotes the reaction rate constant of the overall reaction leading to silicon deposition. From experimental values, the overall rate constant k and subsequently the reaction rate constants kad and kr are derived. Figure 3.4 illustrates the effect of temperature and Cl/H-ratio on the growth rate, calculated according to eqn. (3.10).

8 1150°C

6 1100°C

4 1050°C

2 1000°C Growth rate [µm/min] Growth 0 0.05 0.10 0.15 0.20 Cl/H-ratio

Figure 3.4: Growth rate depending on temperature and Cl/H-ratio calculated according to eqn. (3.10).

Depending on the Cl/H-ratio the growth rate features three regimes. At Cl/H-ratios below 0.5% the growth rate increases strongly with rising Cl/H-ratio. Small changes in gas-composition result in large changes in growth rate. With further increase of the Cl/H-ratio a saturation is reached, where the growth rate changes only little with Cl/H-ratio and finally the growth rate even decreases with increasing Cl/H-ratio. In this regime the growth rate is comparatively insensitive to the Cl/H-ratio. Operation at high temperatures enables the chemical reactions of adsorption and decomposition to occur very fast. The overall reaction rate for silicon deposition is high and for low Cl/H-ratios the growth rate is limited by the chemisorption process. Providing a larger concentration of TCS consequently results in an increase in growth rate. However, if the Cl/H-ratio exceeds a certain value, the growth rate starts do decrease again. In this regime the reaction rate is limited by the decomposition process: sufficient silicon precursor gas is provided to enable large adsorption and 3.2 Deposition principle of silicon by thermal CVD 19 growth rates but the chemical decomposition of the adsorbed species is hindered by the lack of hydrogen. The validity of the presented model was proved by Habuka in a wide temperature range of 800- 1120°C and gas-compositions with molecular weights between 2.7x10-3 and 11x10-3 kg/mol, covering the operation regimes typically used for industrial APCVD processes. In [54] a similar model is presented to describe the growth rate in a horizontal single-wafer reactor with TCS as precursor gas. The predicted growth rates were also successfully verified by experiments.

3.2.4 Chemical yield The chemical yield denotes the conversion efficiency of silicon contained in the initial gas phase into solid silicon. Comparing the initial Si/Cl-ratio to the final Si/Cl-ratio at deposition temperature under thermal equilibrium gives information about the amount of TCS which is theoretically consumed in reactions leading to silicon deposition. Using TCS as precursor gas the initial Si/Cl-ratio is 0.33. If the final Si/Cl-ratio exceeds this value, etching of silicon dominated the process instead of deposition. For Si/Cl-ratios lower than 0.33 silicon deposition has occurred. The final Si/Cl-ratio depends on process temperature and initial gas composition i.e. Cl/H-ratio. The chemical yield can be defined by initial and final Si/Cl-ratio according to

(Si / Cl) f η Si = 1− (3.11) (Si / Cl)i

Assuming thermal equilibrium, the silicon conversion efficiency can be calculated from the partial pressures of silicon and chlorine containing species as a function of temperature and Cl/H-ratio. In [40] the effect of temperature and Cl/H-ratio on the chemical yield has been evaluated by means of thermal equilibrium calculations. The results are depicted in Figure 3.5.

T [°C] 1300 1200 1100 1000 900 0.001 90 90 T= 900 °C Cl/H T=1000 °C 80 80 T=1100 °C 0.005 T=1300°C 70 70 T=1150 °C T=1200 °C 60 60 0.01 [%] T=1250 °C [%] Si Si η T=1300 °C η 50 50 0.03 40 0.04 40 0.06 30 0.08 30 T=900°C 0.1 0.65 0.70 0.75 0.80 0.85 0.00 0.02 0.04 0.06 0.08 0.10 3 10 /T [°K] Cl/H

Figure 3.5: Dependence of chemical yield on temperature and Cl/H-ratio in thermal equilibrium [40].

The Cl/H-ratio determines the maximum conversion efficiency, which can be reached. The lower the Cl/H-ratio the larger is the chemical yield at a given temperature. With increasing temperature the 20 3 Chemical vapor deposition (CVD) of silicon conversion efficiency rises due to the enhanced reactivity. The largest conversion efficiencies can be achieved at high process temperatures and low Cl/H-ratios.

3.3 Reactor design for APCVD Within this work a thermal APCVD reactor constructed and built at Fraunhofer ISE has been used for silicon deposition. Before describing the deposition systems at Fraunhofer ISE in more detail an overview on the most common commercial APCVD system is given in this section. An extensive description of reactor configurations and CVD equipment is published e.g. in [55] and [56]. In the early sixties, the first stages of silicon deposition technology, vertical (a) and horizontal (b) reactors were widely used. In a horizontal reactor the samples are mounted on a horizontal susceptor and loaded into a quartz tube. The process gas enters on one side of the reactor tube and exits from the other side. Upon passing the heated sample surface, deposition occurs from the silicon containing gas phase. The susceptor is slightly tilted to reduce gas depletion effects. In a vertical setup the gas inlet is located at the top with the gas flowing downwards. Nowadays barrel reactors (c) are the workhorses for silicon epitaxy in microelectronic production. The SiC-coated graphite susceptor used in a barrel reactor has a shape similar to a truncated frustum of a 5- or 6-sided pyramid. The samples are tilted to an angle of 2°-3° from the vertical to reduce particle impinging on the surface and to compensate for depletion effects. A quartz bell surrounds the barrel and banks of halogen lamps are used for heating. The process gas is injected in the top part of the reactor and upon flowing downwards, deposition occurs. A slow rotation of the barrel increases thickness uniformity. A flat, rotating susceptor is used in the pancake reactor (d). This reactor configuration is known to suffer from inhomogeneities in the gas extraction system and their susceptibility to particle contamination. Pancake reactors are mainly used for small diameter wafers.

Figure 3.6: APCVD deposition reactors [37]. 3.4 APCVD at Fraunhofer ISE 21

3.4 APCVD at Fraunhofer ISE At Fraunhofer ISE research activities on crystalline silicon thin-film solar cells have been a major subject since years. The demand for a silicon deposition system adapted to the needs of silicon thin- film solar cell processing and production led to the development and construction of new CVD- systems different from commercial tools. The RTCVD100 reactor was the first apparatus built in this context at Fraunhofer ISE. After years of reliable operation a more sophisticated system was set up, the RTCVD160. The newest stage of development is represented by a continuous system (ConCVD) which was set up in autumn 2002.

3.4.1 Reactor design The development of a silicon deposition reactor ready to meet the demands for a future integration in silicon thin-film solar cell production was the basic motivation for the research activities started at Fraunhofer ISE in this area. The criteria the new deposition reactor had to fulfill can be summarized as follows:

• high throughput (5-10 m2/h)

• high growth rates (≥5 µm/min)

• simple setup with little technological effort • processing of rectangular or square wafers • sufficient layer quality (diffusion length in epitaxial layers exceeding 2-3 times layer thickness) • controllable doping profiles

• high chemical yield (>30%). From all deposition methods presented in section 3.1 APCVD at high temperatures is the method capable to meet most of these demands. In microelectronic industry CVD is the key technology which is commonly used for silicon epitaxial deposition. In this area, excellent crystallographic quality, thickness and doping uniformity in the 2% range and high purity are absolutely necessary [54]. Batch- type systems (barrel reactors) or single-wafer reactors are traditionally used and operation at high gas flow rates enables to achieve the required thickness and doping homogeneity, however at the expense of low chemical yield and therefore at high cost per m2. Regarding the total cost for the entire processed microelectronic device, silicon deposition makes up only a small fraction even if cost- intensive deposition techniques are used. From this point of view, the development of high- throughput, low-cost silicon deposition reactors is of no interest. In contrast to that, the silicon deposition process constitutes a large fraction of the final cost for a silicon thin-film solar cell making the development of a cost-effective silicon deposition reactor an important subject of research. Out of these preliminary settings the first CVD system was developed and built at Fraunhofer ISE which was expected to be capable to fulfill most of the imposed requirements. At present three CVD systems are set up at Fraunhofer ISE representing the progress made in the development on these reactors within the past five years. The deposition principle is based on thermal CVD with trichlorosilane as precursor and hydrogen as carrier gas. In contrast to today’s commercial systems, the design of the first ISE CVD-reactor is more comparable to the early horizontal reactors where a horizontal carrier loaded with wafers is introduced into a quartz tube. An outstanding feature 22 3 Chemical vapor deposition (CVD) of silicon of the ISE reactors is the setup of the wafers which will be discussed in more detail in the following section. Thermal heating of the samples is achieved by lamp fields thus enabling rapid heating and cooling rates, quick temperature response and therefore low thermal budget. Since these elements have been transferred from Rapid Thermal Processing (RTP) technology the reactors were named RTCVD reactors. All deposition processes are computer controlled. Since process development and optimization in the RTCVD100 reactor is one of the major subjects of this work, the technological aspects of this system are described in detail. The successor reactor models (RTCVD160 and ConCVD) are also presented with main focus on the technical improvements made compared to the RTCVD100.

3.4.2 RTCVD100 The RTCVD100 is the first laboratory CVD reactor which has been developed and built at Fraunhofer ISE. Until today a total of 1400 deposition runs have been carried out in this system which proved to be reliable and reproducible in operation. In this section the technical details of the reactor are presented, while deposition characteristics and process optimization are discussed in the following chapter. Figure 3.7 shows a picture (right) of the entire RTCVD100 system and a picture (left, top) and corresponding schematic (left, bottom) of the reactor. The entire unit consists of the reactor with furnace and quartz tube, the gas system and the control unit. All components except control unit are mounted on a single aluminum frame which is horizontally divided into two parts. The upper part forms a closed system with the furnace and the quartz tube inside. The lower half contains electric power supply, thyristors and a separate casing for the TCS gas cylinder. The water-cooled furnace is constructed of anodised aluminium with the interior walls clad with a highly reflective, adhesive film (reflectance approx. 98%). Temperature sensors are integrated into the furnace to prevent the system from over-heating. The horizontal quartz tube passes through circular openings in the front and back walls. Tubes with a diameter of 100 mm are used, giving the reactor its name. The top of the furnace houses a bank of 6 tungsten-halogen lamps each with 4.5 kW nominal electrical power for radiative heating. The optical heating allows for fast heating and cooling ramps and therefore short process cycles. Several deposition runs can be carried out per day enabling a flexible variation of process conditions. The gas system is made from electro-polished stainless steel. The valves are pneumatically operated and controlled by electrical pilot valves. Available process gases are nitrogen to purge the reactor, hydrogen for carrier gas and for purging, trichlorosilane as silicon precursor, diborane at 2500 ppm diluted in hydrogen for p-type boron doping and hydrochloric acid (HCl) for in-situ sample etching and reactor cleaning. Trichlorosilane is a liquid at room temperature and therefore a bubbler system is used with a Source V vaporizer-unit to control the gas flow. The impurity level in hydrogen and nitrogen is specified below 1 ppm and the applied TCS is of semiconductor quality. A palladium membrane cleaning-system for hydrogen is installed to minimize the oxygen concentration in the hydrogen gas. The moisture content in hydrogen is monitored by an additional sensor down to the ppbv (parts per billion volume) range and a particle-filter is implemented in the gas line right before entering the reactor. 3.4 APCVD at Fraunhofer ISE 23

The process gases are mixed before entering the reactor tube via a flange. Additional hydrogen or nitrogen can be introduced by a separate gas line, also via the flange. Exhaust gases leave the system through one single gas line leading to a water-scrubber where they are washed out.

Figure 3.7: Left: Picture (top) and corresponding schematic (bottom) of the RTCVD100 reactor. Right: Entire RTCVD100 system with controlling units, TCS casing and reactor housing. The gas system is located on the rear side and is therefore not visible in the picture.

Process control is realized by a personal computer and a programmable logic controller. Individual deposition programs can be set up by a special software, the programs are downloaded to the controller unit and executed. Process parameters like temperature and gas flows are monitored and recorded during the whole process.

Wafer setup The positioning of the wafers inside the reactor and the geometry of the gas inlet strongly influences the deposition characteristics. The wafer setup developed for the RTCVD100 is illustrated in Figure 3.8. Two horizontal parallel wafer rows and the quartz carrier form a closed reaction volume into which the process gases are introduced during the deposition process. The side walls are formed by the front and back plate of the carrier, the right and left edge rods of the carrier and the substrates themselves. This avoids parasitic depositions on the walls of the outer quartz tube and minimizes the need for a frequent cleaning of the tube. High chemical yields can be achieved since deposition takes place only on wafer substrates and the walls of the carrier. In order to prevent the process gas from 24 3 Chemical vapor deposition (CVD) of silicon leaving the reaction volume (e.g. through small gaps between the samples), a slight over-pressure between the outside and the inside of the carrier is created by narrowing the gas outlet to the outside. The maximum wafer size is limited to a width of 80 mm.

Exhaust funnel

Top wafer row

Bottom wafer row

Quartz rods

Gas inlet

Figure 3.8: Schematic drawing of wafer carrier used for the RTCVD100.

The arrangement of the wafers in relation to the lamp array is asymmetric: the top wafer row is directly heated by the halogen-lamps whereas the bottom wafer row is only heated by thermal radiation of the upper wafers and reflected light from the surrounding furnace (Figure 3.7, left, bottom). A temperature-drop of about 50K from top to bottom is the consequence making a simultaneous process optimization for both wafer rows impossible [40]. In this work the deposition processes were optimized for the top wafer row due to the higher temperature and therefore deposition rate on this site. In addition, the danger of particles falling down on the surface of the wafers is excluded. For gas inlet, a simple quartz tube with round inlet cross section is usually used. To improve the gas distribution, experiments were carried out using a nozzle made out of quartz.

Temperature distribution Gas and temperature distribution are the two governing parameters determining the local deposition rate inside the reactor. The temperature affects both, gas transport and chemical reaction kinetics. The temperature distribution inside the reactor is predefined by the dimensions of the lamp array which is 250 mm long and 120 mm wide. According to this rectangular geometry a temperature distribution profile is expected with a maximum in the middle and decreasing temperature to the boundaries. The injection of gas into the system results in a cooling of the samples where the gas passes, with the cooling being stronger the larger the heat capacity or the total gas flow rate. In [40] temperature profiles were measured in longitudinal direction with two different hydrogen gas flows applied. The measurement was done by moving a thermocouple in 10 mm steps between the two wafer rows and recording the temperature. As expected the maximum temperature was reached in the middle of the furnace. For a low hydrogen gas flow rate of 0.5 sl/min a temperature-drop of approximately 100K was determined over the 3.4 APCVD at Fraunhofer ISE 25

250 mm length of the lamp-field compared to a decrease of almost 270K across the entire length of the substrate carrier (430 mm). An increase in total gas flow rate results in a cooling of the gas injection region and a shift of the maximum temperature in gas flow direction. Figure 3.9 shows two temperature profiles measured in longitudinal direction along the centerline of the furnace for different temperature set-points. For this experiment, the set-point were measured and controlled by a pyrometer, located 50 mm in upstream direction relative to the center of the lamp-field. A medium hydrogen gas flow rate of 3.2 sl/min was applied. Across the entire length of the lamp field, the temperature drops from the center to the edges by 120K and 110K for the high and low temperature respectively. Within a length of 100 mm in the center of the lamp field the temperature variation is determined to 2% in both cases.

1300 Lamps 1200

1100

1000

900 Temperature set point 1170°C

Temperature [°C] 800 950°C

700 Gas flow

Wafers 600 -150 -100 -50 0 50 100 150 Distance from the center of the lamp field [mm]

Figure 3.9: Temperature profile measured by a thermocouple in gas flow direction for two different set-point temperatures.

During the deposition the process temperature is recorded by a thermocouple located between the two rows of samples within the reaction volume. The soldered spot of the thermocouple (position, where the temperature is measured) is located in the back end zone of the substrate carrier in order to prevent any impact on the gas flow and therefore the deposition rate. In general, the measured temperature does not correspond to the absolute temperature of the wafers, but represents an average value depending on the exact position of measurement inside the reactor. The relation between the measured mean temperature and the absolute maximum temperature of the wafers in the middle of the reactor was determined by comparison with pyrometric measurements which were carried out in earlier experiments. For the setup currently used, the difference between absolute maximum value and measured temperature comes up to approximately 100K. In the following all temperature values refer to this absolute maximum temperature. 26 3 Chemical vapor deposition (CVD) of silicon

Process cycle For epitaxial silicon deposition we follow a typical APCVD process [57]. Figure 3.10 illustrates the temperature and gas flow characteristics for a complete process sequence. The individual process steps are denoted by number 1-6 and are explained in the following. In the standby mode the reactor is permanently purged with nitrogen. After the sample carrier is loaded the system further remains in the standby mode for 20 min before the deposition process starts. During this period, air which might have diffused into the system during the insertion of the carrier, is removed by the nitrogen purge gas flow. In the first step of the process sequence (1) the purge gas is switched from nitrogen to hydrogen to create an inert atmosphere inside the reactor. Then the system is heated up with a ramp of 150K/min until the prebake temperature is reached (2). The in-situ hydrogen prebake is typically implemented to remove the native oxide from the sample and thus to generate a clean surface for epitaxial deposition [34]. For the RTCVD100 a 1 min prebake is applied at a temperature identical to the deposition temperature of 1170°C (3). During the prebake, the process gases trichlorosilane, hydrogen and diborane are stabilized into the exhaust. The actual deposition step starts with the injection of the stabilized process gases into the reaction volume (4). The deposition time is adjusted to the thickness of the silicon layer to be grown. After deposition the process gases are switched off and the reaction volume is again purged with hydrogen to remove any remnants of the process gas. An annealing step at a slightly higher temperature is included (5). In the last step, the system is cooled down to 400°C (6) before the heating is completely turned off (END) and the system returns to the standby mode.

1400 3 5 1200 4 1000 END 800 6 START 2 600 400 Standby Deposition

Temperature [°C] 200 Standby 1 0

10 Process gas 8 H 2 6 SiHCl +B H 3 2 6 N 4 2 2 0

Gas flow [l/min] Gas flow 2

0

0 1020304050 Time [min]

Figure 3.10: Temperature and gas flow characteristics of a typical epitaxy process cycle as applied for the RTCVD100 reactor. 3.4 APCVD at Fraunhofer ISE 27

The deposition of silicon on samples with SiO2 encapsulation is usually carried out at lower temperatures, to prevent a damage of the oxide layer by hydrogen etching. In this case the hydrogen prebake is also omitted.

3.4.3 RTCVD160 The RTCVD160 represents an up-scaled version of the RTCVD100 reactor featuring larger wafer size capability, higher throughput and increased chemical efficiency [58]. The optical heating system was enlarged and modified to two vertically mounted arrays 400 mm in length and 250 mm in height. Each array houses 30 linear halogen lamps of 4.5 kW maximum electrical power. The vertical arrangement of the lamps and their control by thyristor units enables the realization of power and therefore temperature profiles in longitudinal direction. The principle of the wafer setup presented in section 3.4.2 was maintained but instead of a horizontal positioning of the wafers a vertical configuration is now used. Figure 3.11 shows the quartz carrier developed for the RTCVD160. Samples of up to 100 mm in width can be mounted in two vertical rows up to a total length of 500 mm. The process gas is first introduced into the gas conditioning zone for homogenizing the gas flow, and then enters the deposition zone, where gas decomposition and silicon deposition occurs at a length of approximately 300 mm. A simple modification of the quartz carrier enables the processing of larger substrates of up to 125 mm in width.

Exhaust funnel

Adapter plates

Gas inlet

Quartz rods

Exhaust zone

Deposition zone

Gas conditioning

Figure 3.11: Quartz sample carrier developed for the RTCVD160.

Both sample rows can be utilized due to the completely symmetric arrangement of wafer rows and lamp arrays. Assuming a length of 300 mm for the deposition zone, 6 wafers of 100x100 mm2 in size can be processed per run. The gas system is adapted to the larger deposition area and additional components have been implemented to improve process flexibility. A maximum diborane flow rate of 1000 sccm/min can be employed and a phosphine (PH3) gas line is built in to enable the deposition of n-type layers. The last major improvement to be mentioned is the extended version of the control software where an arbitrary number and sequence of process steps can now be defined by the user. 28 3 Chemical vapor deposition (CVD) of silicon

In Table 3.2 the main features of the RTCVD100 and RTCVD160 reactors are summarized for comparison.

RTCVD 100 RTCVD 160 Reactor tube Ø [mm] 100 160 Wafer setup Horizontal Vertical Max. wafer width [mm] 80 125 Max. deposition area [cm²] 430 1000 1 lamp-field 2 lamp-fields Heating system Upper wafer row directly heated Both wafer rows directly heated 20 TCS [g/min] 40

5H2i [sl/min] 10

Process gases and 10 H2a [sl/min] 10 maximum flow rates 50 B2H6 [sccm/min] 1000 2HCl [sl/min]2

-PH3 [sccm/min] 100 Effective dep. area [cm²] 50 600

Table 3.2: Specifications of two atmospheric pressure CVD reactors developed and built at Fraunhofer ISE.

While the RTCVD100 was used to investigate the potential of the reactor concept, and is clearly limited in throughput and process flexibility, the RTCVD160 is a powerful tool for laboratory-type silicon deposition. It represents an important step in the development from the purely lab-type RTCVD100 to a large-area continuous silicon deposition reactor which can be implemented in industrial production. More than 100 runs have already been carried out in the RTCVD160 proving its reliable operation and verifying the concept of the reactor system. At present a first optimization cycle for silicon deposition on foreign substrates is completed and characterization of epitaxial processes is under investigation.

3.4.4 Continuous CVD (ConCVD) In industrial production, continuous atmospheric pressure CVD is routinely used for the deposition of

SiO2 layers at low temperatures [59]. Moving-belt systems are employed with nitrogen gas curtains at entrance and exit and sophisticated gas injection systems are implemented in the deposition zone for optimal thickness homogeneity. Only little technological effort is required to operate these systems since no pumping system has to be used. High deposition rates and high wafer throughput make the technology ready for production. Concerning silicon deposition the successful operation of a continuous high temperature CVD for the deposition of polycrystalline silicon layers is reported in [60]. From the technological point of view the feasibility of a continuous high temperature APCVD has already been proved. However, since microelectronic industry has no need for such reactors, their further development has not been promoted to an industrial scale production. 3.4 APCVD at Fraunhofer ISE 29

In cooperation with the company Centrotherm (Blaubeuren, Germany) a continuous silicon CVD machine was designed and built to demonstrate the technical and economical feasibility of this technology for industrial solar cell production. The development of the apparatus (ConCVD) is based on the experiences gained with the fore-runner models RTCVD100 and RTCVD160 with their key features being maintained. In order to fulfill the requirements imposed on the system in terms of high throughput and low cost the following major changes were necessary:

• continuous movement for higher throughput

• gas curtains for separation of reactor atmosphere from laboratory environment • resistance heating for better temperature uniformity and increased electrical power utilization • operation in the depletion regime to increase chemical yield. The ConCVD is an open system where sample carriers are continuously fed into the reactor. Nitrogen gas curtains located at both ends of the machine separate the atmosphere in the interior of the reactor from laboratory environment. The horizontal reactor tube is heated by several resistance heating zones. The sample carriers with vertically mounted samples enter and leave the reactor via gas curtains. Before deposition starts, the samples are heated up under hydrogen atmosphere. Figure 3.12 shows a schematic of the reactor tube and reaction chamber. The reaction chamber, where the deposition takes place, consists of a frame with front and end plate being connected by rods. Together with the moving samples a closed volume is generated into which the process gases are injected. After deposition the samples enter the cooling zone, where they are cooled down before they exit the reactor. The total length of the whole apparatus measures 5.4 m. Samples with a maximum width of 200 mm can be processed and by adjusting the transport speed, layers of nearly arbitrary thickness can be grown.

Gas outlet

Gas inlet

Substrate Tube Reaction chamber

Movement of the sample carrier

Figure 3.12: Schematic of the reactor tube and deposition chamber of the continuous CVD apparatus (ConCVD).

An increase in chemical yield and an improved homogeneity in layer thickness is expected from this reactor design compared to its fore-runner models. The resistive heating provides a uniform 30 3 Chemical vapor deposition (CVD) of silicon temperature distribution throughout the entire reactor. In longitudinal direction thickness homogeneity is achieved by the movement of the samples and for vertical uniformity a gas distribution system will be implemented. The movement further allows the deposition process to be run under depletion conditions, thus drastically increasing the chemical yield. Assuming a realistic average deposition rate of 5 µm/min, a reaction chamber length of 400 mm and a substrate width of 200 mm, the throughput for a 30 µm silicon deposition is calculated to 1.4 m2/h.

Laboratory Reactor

Substrate H2

N2 Jet pump

Figure 3.13: Scheme of nitrogen gas curtain principle as implemented in the continuous silicon CVD reactor.

For a safe operation of the system an absolutely reliable working of the gas curtains must be guaranteed. A malfunction of the gas curtains can result in an out diffusion of the highly toxic and - in the presence of oxygen - explosive process gases into the laboratory environment. Figure 3.13 illustrates the working principle of the gas curtains. Hydrogen coming from the interior of the reactor is prevented from out diffusion first by a pumping system and second by a back pressure of nitrogen gas flowing in opposite direction. For optimal function, i.e. no hydrogen coming out of the system and no nitrogen going into the reactor, the nitrogen flow and the pumping speed have to be adjusted to the out coming gas flow. The pumping system consists of jet pumps which provide continuous pumping and little technological effort since no electrical supply is needed. After testing the transport, heating and pumping system, a first silicon deposition process has been successfully carried out.

3.5 Summary The overview on common silicon deposition techniques given in the first section of this chapter showed that silicon deposition by CVD at atmospheric pressure is the only technique which combines the advantage of high deposition rate (high throughput) and high crystal quality of epilayers. APCVD is therefore a suitable tool for silicon deposition in the high-temperature approach of CSiTF solar cells. The principle of silicon deposition by CVD was discussed by means of thermal equilibrium considerations and by describing a growth model presented in literature. Common APCVD reactor configurations and their characteristics were presented. 3.5 Summary 31

Main topic of this chapter was the introduction of atmospheric pressure CVD reactors designed and built at Fraunhofer ISE. The RTCVD100 was the first silicon deposition reactor constructed at Fraunhofer ISE and the workhorse in this work. Main technical features of this apparatus are: usage of trichlorosilane as silicon precursor and diborane for p-type doping, optical heating by halogen lamps and horizontal wafer setup. The wafer setup consists of two horizontal parallel wafer rows forming (together with the quartz carrier) a closed volume inside the reactor tube. The process gas enters this volume on one side and exits from the other side via quartz tubes. Using this setup, silicon deposition occurs only on the inside of the reaction volume i.e. on the wafers and not on the outer reactor tube. Parasitic deposits and a frequent cleaning of the tube are avoided and the chemical yield is increased. The principle of this setup is a key feature of all CVD reactors designed at Fraunhofer ISE. The RTCVD100 is a lab-type reactor, constructed to evaluate the deposition and reactor principle. The up-scaled successor model, the RTCVD160, is capable to handle larger wafers at higher capacity. The basic principles of the RTCVD100 were maintained. The continuous CVD set up in 2002 has the potential for a throughput larger than 1 m2/h, making this system ready for industrial scale production.

4 Process Optimization for RTCVD100

Detailed knowledge of the CVD system characteristic is necessary if silicon layers with well defined properties are to be deposited. This chapter deals with the characterization of silicon layers grown in the RTCVD100 under different process conditions. Process parameters like total gas flow rate, gas composition and gas inlet geometry are varied and their effect on the deposition characteristics is investigated. Finally optimized deposition processes are set up for epitaxy and silicon deposition on foreign substrates.

4.1 Metrology Every optimization process requires the availability of adequate characterization methods. For the characterization of silicon epilayers and silicon layers on foreign substrates properties like thickness homogeneity, dopant distribution and dopant level as well as crystal quality have to be quantified. Different techniques for the analysis of grown silicon layers are explained with emphasis on the techniques which have been mainly used within this work.

4.1.1 Thickness measurement Measuring the sample weight before and after deposition gives a mean value for the layer thickness. However, no information about thickness homogeneity across the wafer can be drawn from this measurement. Infrared Fourier Spectrometry is commonly used to determine epilayer thickness uniformity [61], [52]. Other methods providing thickness distribution maps are the defect method [57], [62], cross sectioning or surface profiling. Within the frame of this work all these methods have been applied with main focus on the defect method and cross sectioning.

FTIR Thickness measurement by Fourier Transform Infrared Reflectrometry (FTIR) is based on the analysis of the infrared interference spectrum measured on the epi-sample. A Michelson interferometer is generally used for this measurement. The light beams reflected from sample surface and substrate- epilayer interface interfere, giving a spectrum with successive maxima and minima. The interferogram contains central peaks which are associated to the reflection from the sample surface, and side peaks which are attributed to the interfering reflection from the interface. The epilayer thickness can be calculated from the separation of the side peaks. A difference in doping level between substrate and epilayer is necessary to obtain the required change in refractive index at the interface. For FTIR measurements the specific resistivity of the substrate and epilayer must be less than 0.02 Ωcm and greater than 0.1 Ωcm respectively. The epilayer thickness must be in a range between 2 and 30 µm [52]. An improvement to this method is obtained by using the fourier transform of the measured interferogram. In this case, the layer system and the corresponding reflectance spectrum are modeled

33 34 4 Process Optimization for RTCVD100 and fitted to the experimental reflectance spectrum. Advantages of this method are higher reproducibility and the ability to measure layer thickness down to 0.5 µm [61].

Defect method The defect method takes advantage of the growth of epitaxial stacking faults on low quality substrate material. Stacking faults typically nucleate on the site of impurity atoms present on the substrate surface and grow within the closest packed crystal layer which is the {111} layer in silicon. Considering a <100>-oriented silicon substrate, four equivalent {111} layers exist into which the stacking fault can spread out. They intersect the surface in lines or squares with edges along the <100> directions. Within the epilayer the stacking fault has the shape of an inverted pyramid with the apex located at the interface between substrate and epitaxial layer (Figure 4.1) [63]. Measurement of the base length of the square stacking faults visible on the surface gives the thickness of the epilayer [64], [62]. Depending on substrate orientation, the stacking fault appears with different shapes so different conversion factors are required.

ba se leng th a e fac sur er lay layer thickness d epi ce rfa inte e rat bst [100] su [110] d = a 0.5

[110] conversion factor = 0.5

Figure 4.1: Epitaxial stacking fault on <100>-oriented substrate. Measurement of the base length gives the layer thickness.

32

30

28

26

24

Thickness [µm] Defect method 22 Cross section

20 -20 -10 0 10 20 x axis [mm]

Figure 4.2: Comparison of thickness measurement by defect method and direct measurement on the corresponding cross section. 4.1 Metrology 35

The error for measuring the absolute layer thickness depends on the error for measuring the base length of the stacking fault. For a microscope magnification of 50 this systematic error was determined to 2 µm resulting in a 1.4 µm error for depth measurement, assuming square stacking faults. Thin epilayers below 3 µm are difficult to characterize because the small stacking faults are barely visible on the surface. The defect method is non destructive but time consuming since it is not automated. Within this work the validity of this method was verified by comparison with cross section measurements (see next section) and FTIR. Figure 4.2 shows two thickness profiles measured by the defect method and by cross sectioning. Within the error bars the data points are corresponding, thus demonstrating that the defect method can be applied for epilayer thickness measurements. The comparison of FTIR and defect method lead to the same conclusion.

Cross sections Cross sectioning, polishing and preferential etching of the samples enables a direct measurement of the epilayer thickness by microscopy. The visualization of epilayer and substrate are based on the dependence of the etch process on the doping level. The applicability of this method therefore requires a difference in doping level of substrate and epilayer. Silicon layers deposited on foreign substrates are microcrystalline making an identification of the interface between substrate and grown layer easy (Figure 4.3). For an application of this method, the samples were cut in stripes by laser scribing and analyzed by Nomarski microscopy. Polishing of the cutting edge was not necessary. All samples with microcrystalline silicon layer have been characterized using this method since neither FTIR nor defect method can be applied.

Figure 4.3: Cross section of a mc-Si substrate with SiO2 intermediate layer and silicon seeding layer

on top. The interface between SiO2 and seeding layer is clearly visible.

The major disadvantage of the cross sectioning technique for film thickness evaluation are cost and time consumption. In addition, the samples have to be destroyed for the analysis.

Surface profiling At Fraunhofer ISE the applicability of surface profiling for the determination of silicon layer thickness distributions is currently tested. The measurement principle is based on the chromatic abberation of optical lenses. During the measurement the sample is exposed to a white light beam which is split up by chromatic abberation into spectral components with focus points lying in a vertical line. Wavelengths with focus on the surface of the sample are perfectly reflected. The reflected light is analyzed by a spectrometer and the distance between sensor and sample surface is calculated. 36 4 Process Optimization for RTCVD100

The system used for this analysis is the MicroProf® by Fries Research & Technology. Areas of 100x100 mm2 can be scanned and measurements can be carried out at rates up to 1000 Hz. The resolution in lateral and vertical direction are specified to 10 nm and 3 nm respectively. 2D and 3D measurements are possible and values for roughness or waviness are calculated automatically. The major advantage of this method is clearly the short measuring time required. For a 100x100 mm2 sample only about 4 min are needed for scanning the wafer with a lateral resolution of 1 mm. The application of this method for a quantification of silicon layer thickness is not obvious. Special care must be taken of wafer bow, inhomogeneous thickness of the substrate or parasitic deposits on the back side which may falsify the measurement data. Measurement of the sample before and after deposition or the use of uniform substrates with parallel surfaces simplifies the determination of the silicon layer thickness by surface profile measurements. The applicability of surface profiling for thickness measurements of silicon films on different substrtes is currently under investigation.

4.1.2 Doping control For doping control 4-point probe measurements, CV-profiling and Spreading Resistance Profiling (SRP) are commonly used. In the frame of this work, silicon epilayers were characterized by SRP. The application of sheet resistance mapping by 4-point probe measurements in combination with thickness mapping has been evaluated as a tool to determine doping densities and doping homogeneity for large area samples. The principle of 4-point probe measurement and SRP are explained in this section. Since both techniques are based on measuring the resistance between two probes in contact with a semiconductor the expression for the total resistance R between the probes will be given here for better understanding:

R = 2R p + 2Rc + 2Rsp + Rs (4.1) where Rp is the probe resistance, Rc is the contact resistance at the metal/semiconductor interface, Rsp is the spreading resistance and Rs is the resistance of the semiconductor [65].

4-point probe The 4-point probe method allows the measurement of sheet resistance in thin layers. Four electrodes are positioned in line on the surface of the sample and a current is passed through the two outer probes. The voltage drop between the inner pair is typically measured with a potentiometer which draws no current, so that parasitic resistance like contact, probe and spreading resistance can be neglected in this setup. For thin layers on non-conductive substrate and with thickness d smaller than probe spacing s (d ≤ s/2), the sheet resistance can be expressed as π V ρ = (4.2) S ln(2) I assuming infinite lateral extension of the sample. V and I denote the voltage drop across the inner electrodes and the current applied to the outer electrodes, respectively. Correction factors have to be applied to this formula if samples with finite geometry are to be measured [65]. The 4-point probe measurement is typically used for p/n+ or n/p+ systems. For an application on p+/p or n+/n systems the resistance of the substrate must be accounted for [61]. An evaluation of the doping uniformity across a wafer is only possible, if the layer thickness distribution is known. The 4.1 Metrology 37 measurement principle does not give any information on the doping profile, it gives only the average sheet resistance. The potential of sheet resistance mapping for a characterization of specific resistivity in epilayers of inhomogeneous thickness was evaluated. High resistivity (>10 Ωcm) 3” FZ-Si wafers were used as substrates and epilayers were deposited using the maximum possible dopant gas flow. Local 4-point probe measurements were done using the FAKIR system developed at Fraunhofer ISE, Laboratory and Service Center Gelsenkirchen. This high speed system allows for characterization of sample sizes up to 150x150 mm2 with the measurement range being specified to 100 µΩ/sq to 120 MΩ/sq [66]. Sheet resistance measurements were done on a 50x50 mm2 area on the 3” wafer according to the dimensions of the epilayer. The distance between the points of measurement was set to 5 mm which corresponds to an 11x11 matrix for the characterization of the entire area. Figure 4.4 (left) shows the sheet resistance map of such a sample. Interpretation of the measurement is not straightforward because of the p+/p structure of the sample and the associated influence of the conducting substrate to the sheet resistance measurement. However, in a first approximation the substrate was assumed to be isolating thus enabling a separate measurement of the epilayer sheet resistance. An evaluation of the doping distribution from sheet resistance data is now possible, if the layer thickness at each point of measurement is known. The defect method was applied to determine the local layer thickness d(x,y) and in combination with the values of sheet resistance Rsheet(x,y) the specific resistivity was calculated according to

ρ S (x, y) = d(x, y)Rsheet (x, y) (4.3)

In Figure 4.4 (right) the resulting distribution map for the calculated specific resistivity is shown. An inspection of the wafer surface revealed that at the edges of the measurement area the 4 probes were not always positioned within the epitaxial region but in the neighboring substrate region. Consequently the measured values do not display the sheet resistance of the epilayer but the sheet resistance of the substrate alone or a combination of both. The high sheet resistance and the corresponding low specific resistivity at the edges of the graphs in Figure 4.4 are attributed to this effect.

R [Ω/sq] sheet Spec. Res. [Ωcm] 20 20 15 <0.04 17 19 10 21 10 0.04 23 25 0.05 27 0 0

29 30 0.06 >30 y [mm] y [mm] y -10 -10 >0.06

-20 -20

-20 -10 0 10 20 -20 -10 0 10 20 x [mm] x [mm]

Figure 4.4: Left: Sheet resistance map of a highly doped epilayer on a high resistivity FZ-Si substrate. Right: Corresponding map of calculated specific resistivity.

Taking into consideration that the measured sheet resistance does not correspond to the sheet resistance of the epitaxial layer alone, the calculated resistivity values do not represent the specific 38 4 Process Optimization for RTCVD100 resistivity of the epilayer. Nonetheless, the homogeneity obtained in resistivity distribution should reflect the real conditions, assuming a constant influence of the substrate on the measured sheet resistance. Spreading resistance measurements were carried out along the y=0 direction to determine the specific resistivity in the epilayers. Figure 4.5 (left) shows two resistivity profiles measured on 2 positions, 20 mm apart from each other.

30 1 10 x [mm] 28 4-point probe

cm] 0 26 SRP Ω 20 (y=0 mm) 24 0 /sq] 10 Substrate 22 Ω [ 20 sheet

R 18 -1 Epitaxy 10 16

Specific resistivity [ resistivity Specific 14

0 5 10 15 20 25 30 35 -10 0 10 Depth [µm] x axis [mm]

Figure 4.5: Left: Specific resistivity profiles for epilayer on high resistivity substrate measured by SRP at different sample positions. Right: Comparison of sheet resistance values measured by 4-point probe and calculated from spreading resistance profiles.

Both curves are roughly corresponding with slight differences in epilayer thickness. Resistivities in the range of 0.07 Ωcm are measured in the constant epilayer region compared to a mean value of approximately 0.05 Ωcm, calculated from 4-point probe and thickness measurements (Figure 4.4). As already mentioned, this calculation was based on the assumption that the measured sheet resistance is identical to the sheet resistance in the epilayer, which is certainly not correct for the p+/p structure under consideration and a deviation between SRP and the calculated values was therefore expected. Now, instead of comparing the values for the specific resistivity, the sheet resistance was calculated from each SRP curve (substrate included) and compared to the data points obtained from the 4-point probe measurement. The results depicted in Figure 4.5 (right) show that the calculated sheet resistances exceed the measured data by approximately 30%. Possible reasons for this deviation are the unknown impact of substrate, epilayer and highly doped surface layer on sheet resistance measurement. To determine whether the calculated map of specific resistivity in Figure 4.4 (right) corresponds to the real distribution in the epilayer, more data points from SRP measurements are necessary. For a realistic determination of epilayer resistivity from 4-point sheet resistance measurements and epilayer thickness measurements, an ideal sample structure with non-conducting substrate and homogeneous doping density in the epilayer is essential to enable an unambiguous interpretation of the measured sheet resistance values. However, assuming a constant influence of the substrate on the 4- point probe measurement and using epitaxial layers with constant doping densities throughout the entire layer, the calculated distribution of specific resistivity should reflect the real doping distribution in the epilayer. In this case, it might be possible to calibrate the sheet resistance measurement data e.g. 4.1 Metrology 39 by spreading resistance measurements to yield a mapping of the prevailing carrier density. For a verification of this interpretation further experiments have to be carried out. A combination of absolute epilayer thickness measurement by surface profiling and sheet resistance mapping with the FAKIR system could provide a fast and efficient characterization tool for doping density and homogeneity of large area epilayers.

Spreading Resistance Profiling (SRP) Using Spreading Resistance Profiling (SRP), the depth profile of the specific resistivity in a single crystalline silicon layer can be quantified. The method is based on the measurement of the spreading resistance between two probes which are stepped along the beveled sample surface. Comparison of the spreading resistance data with calibration curves gives the specific resistivity at the location of measurement [65]. For depth profiling a small chip is taken from the sample, waxed onto a bevel mount and ground using a diamond slurry. Next, the probes are aligned parallel to the bevel edge and are stepped along the beveled surface, perpendicular to the bevel edge (Figure 4.6).

Beveled surface Bevel edge Probe tips

x α z

Bevel mount

Figure 4.6: Left: Ground sample on bevel mount, the line of measurement is indicated. Right: The probe tips are aligned parallel to the bevel edge and move in a perpendicular line to it.

The depth resolution ∆z is given by the step width ∆x and the bevel angle α according to ∆z = ∆xsinα (4.4) The total resistance between the two probes is again given by (4.3) with the spreading resistance dominating. For a flat, circular ohmic contact to a semi-finite sample the spreading resistance Rsp can be expressed as ρ R = (4.5) sp 2a with specific resistivity ρ and contact radius a. In reality, conductivity-type, resistivity, surface finish and orientation influence the spreading resistance. The two tungsten-osmium probe-tips are roughened such that the actual electrical contact is made by a cluster of microcontacts which are able to penetrate the native silicon dioxide layer present on every silicon surface [67]. The contact area and radius is given by the amount, the shape and the distribution of the microcontacts; they characterize the electrical contact. Roughening of the microcontacts result in a higher penetration and an increase in the number of microcontacts whereas smoothing leads to the 40 4 Process Optimization for RTCVD100 opposite result. The spreading resistance is very sensitive on the condition of the probe-tips making regular qualification and conditioning an absolute necessity for quality control. The spacing between the probes lies generally between 65 to 100 µm and the voltage between the probes is kept at a low value of 5 mV to reduce any influence of contact resistance. The probes are mounted on gravity-loaded probe arms so that the probes impinge the surface with a constant force. The spreading resistance also depends on the probe loading: using low probe loads, the penetration of the spreading resistance is reduced and the measurement is more concentrated on the near-surface layer. For the measurement of ultra-shallow junctions, low probe-loads of 5 g are generally used. Spreading Resistance is a comparison technique. Measured spreading resistance data are compared to calibration curves relating resistivity to spreading resistance. Calibration standards for n- and p-type silicon with <100> and <111> orientation are available from the National Institute of Standards and Technology (NIST). Calibration curves have to be generated for each specific measurement setup (probe-arms, conditioning probes, surface finish, step-width) using the calibration standards. Reconditioning of the probe-tips or changing the probe-load requires a re-calibration. At Fraunhofer ISE a NanoSRP2000 system by Solid State Measurements (Pittsburgh, USA) was set up for measuring doping profiles on epilayers. Typical step widths are 1, 2.5, 5 or 10 µm. Different bevel mounts with angles from 4’ to 11°32’ can be used giving depth resolutions down to 1 nm. Bevel angle and step width are chosen according to the required resolution and measurement depth. The measurement range is specified to a range from approximately 1x1011 cm-3 to the dopant solubility level. Time saving measurements are realized by automated bevel edge alignment, probe calibration and conditioning. Up to 6 samples can be mounted on the sample holder for successive measurements. The analysis software Analysis-NANOSRP enables automated processing of the measured data to yield specific resistivity and carrier density. A typical analysis procedure includes determination of p- and n-type regions, smoothing of the raw profile and calculation of the corresponding profiles for resistivity and carrier densities based on the calibration curves. Field effects from underlying layers influence the spreading resistance data and are therefore taken account of by using adequate correction factors. Finally, the corrected resistivity is converted to carrier densities using Thurber’s empirical curves for boron and phosphorous-doped silicon [68]. The measurement error is associated to the error made for the calibration which is typically in the 5% range. For the characterization of epilayers by SRP a probe-load of 10 g has been used. Unless otherwise stated a step width of 5 µm and a bevel angle of 2°52’ was applied resulting in a depth resolution of approximately 500 nm. Grinding was done by two steps: first, the samples were ground on a granite plate using an Al2O3/glycerin slurry. A fast removal of surface layers is achieved, however at the expense of surface smoothness. Second, the samples were polished on a rotating quartz plate using the typical diamond/oil slurry. The grinding procedure has to be done with great care in order to avoid scratches on the beveled sample surface which might influence the SRP measurement. Grinding of samples with hard ceramic substrates or with silicon carbide intermediate layer is critical, since small bits of the material tend to break out and produce further scratches (Figure 4.7). The bevel angle was measured with a mechanical Tencor alpha-step profiler. For a bevel angle of 2°52’ the standard deviation for angle measurements on monocrystalline beveled samples was determined to 1%. Bevel angle measurement is reliable for monocrystalline epilayers with defect-free, smooth surface but is difficult for multicrystalline or recrystallized samples with rough, facetted 4.1 Metrology 41 surface. For these materials, the specified bevel angle has usually been used for measurement and alignment has been done using the interface between substrate and silicon layer or using the intermediate layer as reference line. Further, a <100> crystal orientation has always been assumed for recrystallized samples. This approximation can be tolerated because the preferential crystal orientation of the recrystallized silicon layers is the <100> orientation [69].

Sample surface Beveled sample Scratches surface

Bevel edge

Bevel edge

Monocrystalline sample α = 2°52‘ 10x magn. Recrystallized sample α = 2°52‘ 10x magn.

Figure 4.7: Left: Beveled Cz-Si sample. The bevel edge is clearly visible as a straight line. Right: Beveled multicrystalline silicon layer. The bevel edge is facetted because of the multicrystalline structure of the layer and scratches are disrupting the beveled surface.

The advantages of the SRP technique are excellent depth resolution and wide range of measurement. However, sample preparation is time consuming and destructive. Skillful operation, frequent probe conditioning and calibration are necessary to ensure constant quality of the measurements.

4.1.3 Impurity concentration measurements by SIMS Secondary Ion Mass Spectroscopy (SIMS) was applied to characterize oxygen, carbon and boron concentrations in epilayers. During SIMS, material is sputtered from the sample surface and subsequently analyzed by mass spectrometry. Only about 1% of the sputtered atoms are ionized (secondary ions) and can be detected by the mass spectrometer. For a specific element the yield of secondary ions depends on the energy of the primary ions but also on the type of ions used for sputtering. Electronegative ions are used if electropositive elements are to be detected and vice-versa [65]. The chemical surrounding i.e. the composition or type of the sputtered material represents another factor influencing the yield of secondary ions. For quantitative measurements, calibrated element standards of known composition have to be used. The strength of SIMS lies in its capability to detect any kind of element with detection limits as low as 1x1014 cm-3 for some elements. The lateral resolution depends on the dimension of the ion beam and is typically in the range of 100 µm. For depth profiling the sputter crater is measured and correlated to the sputter time by linear interpolation. SIMS measurements were done by RTG Microanalyse (Berlin, Germany) using a Cameca ims4f + + system. For boron and carbon/oxygen profiles an O2 beam with 8 keV energy and a Cs beam with 14.5 keV energy has been applied respectively. 42 4 Process Optimization for RTCVD100

4.1.4 Defects The most frequent defect type in epilayers are stacking faults, spikes and dislocations [63]. Stacking faults and spikes can be identified by microscopic analysis of the surface of the epilayer. Dislocations can be revealed by chemical etching, where small etch pits develop on the site of dislocation. The etch pit density is generally used as a measure to quantify the crystallographic quality of silicon material. Dislocation densities in epilayers were determined by Secco9 etching of polished sample surfaces and automated counting of the etch pit density. This method does not make account of stacking faults and spikes, only point defects and line defects intersecting the surface are used for measurement.

4.1.5 Lifetime measurement by MW-PCD Microwave Photo-Current-Decay (MW-PCD) is a powerful tool for the characterization of minority carrier lifetimes in silicon bulk material. It makes use of the correlation of effective lifetime on the asymptotic decay characteristic of excess minority carriers generated by a pulsed excitation. A change in the number of excess minority carriers is associated with a change in reflectivity. The temporal change in reflectivity of a microwave signal is used as a measure for the decay of minority carriers in the sample [65]. The measured lifetimes are effective lifetimes which means that surface recombination effects are included. Surface recombination velocities can be reduced by passivating the surfaces with silicon dioxide or silicon nitride layers. At Fraunhofer ISE surface passivation is done by the deposition of

SiNx:H layers by PECVD resulting in surface recombination velocities below 10 cm/s [70]. The application of MW-PCD on epilayer systems is not straightforward because thickness, doping density and bulk lifetime in the epilayer and substrate as well as interface recombination velocity influence the measured minority carrier lifetime. Using a low resistivity substrate, such that the lifetime in the epilayer is considerably larger than the lifetime in the substrate, information on the epilayer bulk lifetime and the interface recombination velocity can be extracted from MW-PCD measurements [71]. In return, the measurement becomes more difficult due to the high reflectivity of the highly doped substrate. The generating laser pulse and the microwave antenna are located on opposite sides of the sample. Therefore generation is high if the epilayer faces the laser but at the same time the measurement signal is small because the substrate faces the microwave antenna. Turning the sample results in a weak generation but good detection characteristics. In this work, best results were obtained for the substrate surface facing the laser pulse.

4.2 Epitaxial deposition Within the approaches of crystalline silicon thin-film solar cells pursued at Fraunhofer ISE the active base layer of the cell is typically deposited onto recrystallized silicon layers or other silicon substrates by epitaxy. The requirements imposed on layer quality in terms of defect density and impurity content are stringent if high minority lifetimes are to be achieved. Optimization of the epitaxy process in the RTCVD100 was carried out with focus on thickness and doping uniformity as well as crystal quality.

9 Secco etch: Solution from K2Cr2O7 and HF. 4.2 Epitaxial deposition 43

According to the prevailing temperature distribution within the reactor, characterization and optimization procedure were reduced to sample positions in the middle of the top wafer row where the temperature distribution was found to be the most homogeneous (see section 3.4.2). State-of-the-art CVD processes are run at high temperatures of 950-1250°C where high quality layers can be grown at high deposition rates. For the RTCVD100 a deposition temperature of 1170°C was found to be adequate to produce epilayers of low defect density. Going to higher temperatures results in higher growth rates at the expense of an early process gas depletion. On the other hand lowering the temperature gives silicon layers with a larger defect density. With respect to these restrictions and based on first experimental results [40] the deposition temperature was fixed to 1170°C for the optimization.

4.2.1 Pre-epitaxial sample cleaning Sample preparation prior to epitaxy plays a crucial role concerning crystal quality of the epitaxial layer. Residual oxygen or other contaminants on the surface form nucleation centers for defect generation leading to highly defective epilayers. Standard cleaning procedures include an ex-situ cleaning before loading the samples into the reactor and an in situ cleaning during the CVD process. The ex-situ cleaning aims to remove organic and metallic contaminants from the sample surface. For in-situ cleaning a hydrogen prebake at elevated temperature (≥1000°C) is typically applied during which the native oxide (1.0-1.5 nm) which forms on every silicon surface is decomposed and evaporated [72]. An additional HCl in-situ etch is sometimes implemented directly before silicon deposition starts [73]. Within this work, sample pre-cleaning was usually done by an ex-situ RCA10 cleaning with the last HF-dip omitted to prevent any impurities or water molecules from adhesion on the hydrophobic hydrogen-terminated sample surface [74]. Polished wafers coming from the producers box were directly introduced into the reactor without additional ex-situ cleaning. Before deposition a hydrogen bake at growth temperature was applied for all sample types.

4.2.2 Thickness uniformity A uniform distribution of the process gas across the entire deposition area is essential if excellent thickness homogeneity is to be accomplished. Wafer geometry and gas inlet play a key role on that score. The entire setup of the RTCVD100 reactor can be compared to traditional horizontal reactors and some of the problems encountered there have also been found to arise in the RTCVD100. In [40] some basic characteristics of the RTCVD100 system concerning epitaxial depositions have already been evaluated. The effects of process temperature, gas composition and total gas flow on the longitudinal deposition profile of both wafer rows were investigated. As a result of these experiments a standard process was defined. The evaluation of the longitudinal growth rate profiles has been performed on the base of mean values calculated from the difference in mass before and after deposition leaving the real thickness distribution across the sample area in the dark.

10 RCA cleaning: Standard chemical cleaning procedure to remove metallic and organic impurities from silicon wafers. Step 1: solution of NH4OH:H2O2:H2O, Step 2: solution of HCl:H2O2:H2O. 44 4 Process Optimization for RTCVD100

Taking the parameter set defined in [40] as a starting point the effect of gas inlet geometry was investigated and further variations of total gas flow rates and composition were carried out. Saw- damage etched Cz-Si wafers with <100> crystal orientation were used for all experiments and the defect method was applied for thickness measurement. A mesh of 9x7 measurement points was applied on a 50x100 mm2 area, giving a resolution of 15 mm in longitudinal direction and 5 mm in lateral direction. Figure 4.8 shows the thickness distributions for two deposition runs differing only in gas inlet geometry. A simple gas tube with round cross section (Figure 4.8, top) and a nozzle (Figure 4.8, bottom) have been applied as gas inlet for the deposition processes. All values are relative to the maximum thickness measured for each run.

20 relative 10 thickness [%] 100

0 80 TCS = 12 g/min 60 H = 3 sl/min -10 40 2i 20 gas inlet: tube -20 0 -80 -60 -40 -20 20 40 60 80 Lateral position Lateral

rel. to center [mm] center to rel. Distance from the center of the lamp field [mm]

20 relative 10 thickness [%] 100 0 80 TCS = 12 g/min

60 H = 3 sl/min -10 40 2i 20 gas inlet: nozzle -20 0 -80 -60 -40 -20 20 40 60 80 Lateral position Lateral

rel. to center [mm] center to rel. Distance from the center of the lamp field [mm]

Figure 4.8: Thickness distribution for two runs with identical process parameters. Top: Application of a tube as gas inlet. Bottom: Application of a nozzle as gas inlet.

Both distribution maps in Figure 4.8 feature a decrease in lateral direction towards the edges of the deposition area. Assuming laminar flow the gas velocity distribution within the reaction volume follows a parabolic profile with zero velocity at the boundaries and maximum velocity in the center of the main gas stream. The concentration of chemical species is proportional to the velocity and therefore decreases towards the walls leaving the corners impoverished of process gas. A drop in growth rate from center to the corners of the carrier follows [45]. Application of the tube as gas inlet leads to a thickness distribution which is symmetric relative to the middle of the furnace reflecting the temperature distribution within the reactor. A so called “cold finger” effect is observed in gas flow direction (Figure 4.8, top). This characteristic is commonly explained as follows: heat is transferred from the reactor walls to the incoming cold process gas leading to a cooling of the sample surface and hence a drop in growth rate [34]. This drop in growth rate can be seen in Figure 4.8 (top) along the centerline of the deposition area. The presence of the cold finger depends on the properties of the process gas: a large thermal capacity or a high gas flow rate (which means large velocity) generally results in a more pronounced cold finger effect [75]. A maximum deposition rate of 6.3 µm/min was measured under the prevailing conditions. 4.2 Epitaxial deposition 45

In horizontal reactors gas diffusers like screens and shower heads were developed to accomplish a uniform gas distribution [76]. In our setup a simple nozzle is used to widen the incoming gas flow. The process gas is conducted towards the boundaries of the reaction volume making the parabolic velocity and mass concentration profile in the reaction volume more shallow. A more uniform distribution of all gas species across the entire reaction cross section and a more homogeneous heating up of the gas mixture is the consequence. The thickness distribution in Figure 4.8 (bottom) illustrates these effects. The cold finger has disappeared and the onset of the uniform region of the deposition zone has moved upstream towards the gas inlet as a result of the broader gas distribution. Compared to the process without nozzle a higher maximum growth rate of 8.4 µm/min was reached which corresponds to an increase by a factor 1.3. However, a drop in growth rate is observed in downstream direction. This effect is attributed to a depletion in precursor gas resulting from an improved distribution and heating of the incoming process gas and consequently an enhanced consumption of trichlorosilane at the inlet region. In traditional horizontal reactors and also barrel reactors a slight tilt of the sample tray counteracts the depletion. In the RTCVD100 reactor larger flow rates are employed to diminish depletion effects. To evaluate the limits in terms of thickness uniformity when using the nozzle for gas injection, further experiments were carried out with varying total gas flow rates and gas composition. Best results were achieved for maximum gas flow rates of precursor and carrier gas resulting in a thickness distribution as illustrated in Figure 4.9. The large flow rate of 20 g/min of trichlorosilane is needed to minimize the depletion effect which is still observed in Figure 4.8. On the other hand, a large amount of hydrogen is necessary to ensure an effective chemical conversion.

20 relative 10 thickness [%] 100

0 80

TCS = 20 g/min 60 H = 10 sl/min -10 40 2i 20 gas inlet: nozzle -20 0 -80 -60 -40 -20 20 40 60 80 Lateral position Lateral

rel. to center [mm] center to rel. Distance from the center of the lamp field [mm]

Figure 4.9: Thickness distribution map measured for a deposition process using a nozzle and maximum gas flow rates. A maximum growth rate of 10 µm/min was determined.

In conclusion, the optimized process gives a mean deviation in layer thickness of 13% across the deposition area of 40x100 mm2. Further improvement in thickness uniformity can be expected using a more sophisticated gas injection system e.g. a shower head. Two different growth processes giving similar thickness uniformity but featuring a large difference in growth rate were selected for a further characterization of epilayer quality. The deposition parameters of both processes A and B are listed in Table 4.1. The corresponding thickness distribution mappings have already been presented in Figure 4.8 (top) and Figure 4.9 for process A and B respectively. 46 4 Process Optimization for RTCVD100

AB T [°C] 1170 1170 TCS [g/min] 12 20

H2i [l/min] 3 10 Total gas flow rate [l/min] 5 13.3 Cl/H 0.75 0.43 Gas inlet Tube Nozzle Average growth rate [µm/min] 5.5 9 in uniform area

Table 4.1: Comparison of process parameters for two different epitaxy processes.

4.2.3 Doping of epilayers Two aspects of doping concentration in epitaxial layers were investigated: first, the functional dependence of doping density on dopant gas flow and second, the uniformity of the doping density across the deposition area. A detailed discussion of the characteristics of the epilayer doping profiles is presented in a separate chapter 5. The measurement range of the diborane mass flow controller limits the maximum dopant gas flow rate to 50 sccm. For flow rates below 1 sccm the accuracy of the controlling unit reduces the reproducibility of doping concentrations. Figure 4.10 shows the dependence of minority carrier density from the diborane gas flow rate for process A and B.

1019

] 18 -3 10

1017

1016 process A

Carrier density [cm density Carrier process B 1015 110 B H -flow [sccm/min] 2 6

Figure 4.10: Measured carrier density as a function of diborane gas flow rate for epitaxy process A and B on a double-logarithmic scale.

Increasing the diborane gas flow for fixed process conditions results in an increase in carrier density. On the other hand, the carrier concentration decreases when leaving the diborane gas flow fixed and using process A (low growth rate) instead of process B (high growth rate). For both cases the linear 4.2 Epitaxial deposition 47 relationship between carrier density and dopant gas flow rate is obvious. The observed functionality allows for a deposition of epilayers with defined carrier concentrations. The mechanism of boron incorporation and the dependency of process parameters on carrier density are discussed in detail in chapter 5. The deposition of silicon without addition of diborane results in p-type layers with specific resistivity in the range of 133 Ωcm, independent of substrate resistivity. The low doping density measured for these intrinsic layers verifies the purity of the used process gases and the cleanliness of the entire reactor and gas system. The growth of intrinsic layers and the corresponding doping profiles are studied in chapter 5. The doping uniformity along the deposition area was quantified for the maximum and minimum reproducible gas flow rates. Local SRP measurements of carrier densities were carried out along the centerline of the reactor and in a parallel line along the side walls, which represents the longitudinal edge of the deposition area. In Figure 4.11 the distribution of specific resistivity is graphed for both deposition processes A and B.

1 cm] Ω

Process A

2 sccm B H 2 6 , centerline (y=0mm) 50 sccm B H 0.1 2 6 , edge (y=20mm) Spec. resistivity [ resistivity Spec. -80 -40 0 40 80 Distance from the center of the lamp field [mm]

1 cm] Ω Process B 2 sccm B H 2 6 , centerline (y=0mm) 50 sccm B H 2 6 , edge (y=20mm) 0.1 Spec. resistivity [ resistivity Spec. -80 -40 0 40 80 Distance from the center of the lamp field [mm]

Figure 4.11: Distribution of dopant concentration across the deposition area for process A (top) and B (bottom). Measurements were carried out along the centerline and in a parallel line near the edge. 48 4 Process Optimization for RTCVD100

Comparing the two processes (Figure 4.11 top vs. bottom) again shows the difference in doping density for equal dopant gas flows but different process conditions: the measured specific resistivity is considerably larger for process B compared to process A. For both deposition processes, the resistivity values along the edges are slightly higher compared to the centerline and a slight rise is observed in downstream direction. The standard deviation in doping density across the entire deposition area is determined to 11% for both diborane gas flow rates and both epitaxy processes. In conclusion, the distribution of doping density across the deposition area shows a uniformity similar to the growth rate distribution. Dopant gas depletion along the direction of gas flow only plays a minor role. For silicon thin-film solar cells, comparatively large variations in doping densities can be tolerated without considerably reducing the performance. The uniformity in carrier concentration accomplished for both epitaxy processes is sufficient for solar cell application.

4.2.4 Crystal quality The crystal quality of epilayers depends on substrate material, pre-epitaxial cleaning and process conditions [77]. Epitaxial defects can be categorized according to their origin in substrate-related defects and defects related to process conditions. Grain boundaries or other crystal imperfections intersecting the substrate surface are continued in the epitaxial layer and are therefore accounted to the first category. Stacking faults and spikes are the most common epitaxial defect type. They are generally attributed to the presence of impurities (organic or metallic) on the substrate surface [78]. Contamination of the sample surface can be caused by an incomplete cleaning prior to epitaxy and unclean process conditions (wafer handling, laboratory cleanliness, purity of the process gases etc). Epitaxial layers are known to have larger defect densities compared to standard wafers but the oxygen concentration is typically lower compared to Cz-Si [79]. Epitaxial stacking faults have already been discussed in section 4.1.1. Characterization of epitaxial solar cells on <100> Cz-substrates by EBIC (Electron Beam Induced Current) shows low short circuit currents at the corners of the stacking faults, indicating that the dislocations present at these sites act as potential barrier for minority carriers [80]. In [64] it is proposed that the electrical recombination activity is not caused by the stacking fault itself but is related to its gettering effect on point defects and impurities. Spikes appear as polycrystalline protrusions of several µm in height on the epilayer surface and sometimes they are combined with stacking faults. Of all defect types they are reported to have the most detrimental effect on the electrical quality of epitaxial wafers [63]. Figure 4.12 shows SEM11-images of both defect types. The surfaces of epitaxial layers grown in the RTCVD100 on Cz-Si substrates were inspected by Nomarski microscopy. The density of stacking faults and spikes was found to depend on the substrate pre-cleaning procedure and morphology: epilayers on polished Cz-Si substrates taken directly from the producers box revealed only few stacking faults and no spikes indicating excellent layer growth. Application of an HF-dip prior to epitaxy enhanced the growth of both defect types. This effect is assumed to be related to the hydrophobic sample surface after HF-treatment and the associated enhanced attraction of particles from the surrounding. Growth of epilayers on CP-133 saw-damage

11 SEM: Secondary Electron Microscopy. 4.2 Epitaxial deposition 49 etched Cz-Si substrates of minor quality typically resulted in high densities of stacking faults and spikes within the epilayer.

Figure 4.12: Left: Epitaxial stacking fault on <100>-oriented silicon layer. Right: Spike protruding from epitaxial surface (microscope images).

The quality of the epitaxial layers grown by process A and B was quantified in terms of dislocation densities. High quality single-side polished <100> Cz-Si wafers with an off-orientation of 1° were used as substrate material. They were taken directly from the producers box and introduced into the reactor without additional ex-situ cleaning. For both epitaxy processes a mean value of 1x104 cm-2 was specified as defect density. Assuming a typical value of less than 100 cm-2 for silicon wafers [81] this corresponds to an increase by 2 orders of magnitudes. In commercial epitaxy reactors used for microelectronics defect densities below 1x103 cm-2 are typically reached. However, the measured defect density of 1x104 cm-2 is still in an acceptable range for an application of the epilayers in silicon solar cell preparation. High oxygen and carbon concentrations or a high density of self-interstitials within the epilayers might be the reason for the comparatively high defect density.

4.2.5 Lifetime measurements The effective minority carrier lifetime in epilayers was determined by MW-PCD. Samples were prepared by epitaxial deposition of a 2 µm thick BSF layer and a 30 µm thick silicon base layer on Cz- Si wafers (≤0.02 Ωcm). The doping concentration of the BSF was set to a high level comparable to substrate doping density, while the base layer doping was varied from 4x1016 cm-3 to 1x1017 cm-3. For comparison, epitaxial layers grown in a commercial system were also characterized. All samples were

RCA cleaned with SiNx:H layers deposited by PECVD on front and rear side for surface passivation. Figure 4.13 illustrates the dependence of the measured effective carrier lifetime from specific resistivity of the epilayers. The measured values for effective minority carrier lifetime range from 2.5 µs to 7.2 µs depending on the doping concentration of the epilayer. Increasing the specific resistivity results in an increase of the effective minority carrier lifetime due to a reduced Auger recombination. The measured effective carrier lifetime depends on the lifetime of the bulk epilayer and the surface recombination velocities. The front surface is well passivated by SiNx:H whereas the rear surface recombination is determined by the interface between substrate and epilayer. The contribution coming from minority carriers generated in the substrate material is considered to be negligible due to the high doping level. Assuming perfect surfaces with zero recombination velocities 50 4 Process Optimization for RTCVD100 the effective lifetime gives a lower limit for the actual bulk lifetime. At a doping level of 1x1017 cm-3 the measured carrier lifetime of 2.48 µs corresponds to a minority carrier diffusion length of 66 µm, which is about twice the epilayer thickness, satisfying the imposed requirement on epilayer quality.

8

7 RTCVD 100: process A RTCVD 100: process B 6 commercial reactor

5 [µs]

eff

4 τ 3

2

1 0.1 0.2 0.3 0.4 0.5 0.6 Specific resistivity [Ωcm]

Figure 4.13: Effective minority carrier lifetimes measured by MW-PCD for epitaxial layers with different specific resistivity.

4.2.6 Chemical analysis Oxygen and carbon are two of the most common impurities which are incorporated during silicon CVD film growth. The amount of incorporated atoms depends on process conditions and especially on gas purity. High concentration peaks of either impurity at the interface between substrate and epilayer generally result from incomplete preclean of the sample surface [82]. The concentration of both elements in the epilayer generally increases with decreasing deposition temperature [79]. For a characterization of the oxygen and carbon content in epilayer samples were prepared on RCA cleaned FZ-Si and Cz-Si substrates. The epilayers were either mechanically ground or wet-chemically etched to a final thickness of approximately 7 µm in order to reduce SIMS measurement time and to increase depth resolution. Using FZ-Si substrates, oxygen and carbon concentration below the detection limit of 1x1016 cm -3 were measured for epilayer and substrate verifying the high purity of the RTCVD100 system. Figure 4.14 shows carbon and oxygen concentration profiles for an epilayer grown on Cz-Si substrate. The depth of the interface was determined by SRP and verified by SIMS boron profiling. The oxygen concentration in the substrate is at the level of solid-state solubility and in a typical range for Cz-Si12. Within the epitaxial layer the concentration reduces to 1x1018 cm-3 at the surface. The carbon concentration behaves in just the opposite way: it increases slightly from substrate to epilayer surface. The carbon content in the substrate comes up to approximately 3x1017 cm-3 compared to 6x1017 cm-3 at the epilayer surface. At the interface between substrate and epitaxial layer no peaks in oxygen or carbon concentration are observed indicating that surface contamination does not present a problem.

12 In Cz-Si and FZ-Si typical oxygen concentrations are in the range of 1x1017 to 2x1018 cm-3 and 1x1015 to 1x1016 cm-3 respectively [May90], [Kar99]. 4.2 Epitaxial deposition 51

1019 oxygen 1019 carbon ] -3

epitaxy substrate 18 18 10 10

Concentration [cm 1017 1017 6420-2-4-6 Distance from interface [µm]

Figure 4.14: Oxygen and carbon concentration profile measured by SIMS for an epilayer on Cz-Si substrate.

The decrease of oxygen concentration with increasing distance from the interface is considered to be due to a solid-state out-diffusion of oxygen from the silicon substrate into the epilayer [83]. A simulation of the epitaxial growth process and oxygen diffusion was carried out to verify this statement. The applied simulation tool is based on a discretized growth process with Fick’s diffusion equations being solved after each growth step. Input parameters for the simulation are silicon deposition parameters and material properties. The CVD process is characterized by growth temperature, duration and thickness of the final epilayer. Additional high temperature steps following the growth process can be included. The concentration of the element under investigation – in this case oxygen – has to be assumed for substrate and epilayer region. The diffusion process strongly depends on the diffusion coefficient which is given by

E A D(T) = D0 exp(− ) (4.6) k BT where T is the diffusion temperature, kB is Boltzmann’s constant and D0 and EA denote diffusion constant and activation energy respectively [84]. For the diffusion of oxygen in silicon both values were taken from [85] for the simulation:

2 −1 E A = 2.53 eV, D0 = 0.13 cm s (4.7)

According to experimental values, the growth of a 25 µm epilayer at a deposition rate of 10 µm/min was simulated. Growth temperature and post-deposition anneal temperature were varied to evaluate their influence on the oxygen diffusion profile. An oxygen concentration of 1x1013 cm-3 and 4x1018 cm-3 were assumed for epilayer and substrate respectively. Because of the strong functional dependence of the diffusion coefficient on temperature, the growth temperature and the anneal temperature significantly effect the diffusion of oxygen. Figure 4.15 shows simulated oxygen diffusion profiles resulting from a variation of growth temperature. 52 4 Process Optimization for RTCVD100

18 ] 10 -3

1017 Growth temperature [°C] 1270 1170 1070 Concentration [cm Concentration 1016 anneal at 1200°C

6420-2-4-6 Distance from interface [µm]

Figure 4.15: Simulated oxygen concentration profiles across the interface between substrate and epilayer. The growth temperature has been varied.

In general, increasing the deposition or anneal temperature results in an enhanced diffusion of oxygen. The gradient of the corresponding concentration profile is consequently smaller and the profile more flat. The simulation verifies that the oxygen concentration in the epilayer can indeed be explained by a diffusion of oxygen from the substrate into the epilayer. However, in case of carbon the SIMS profile in Figure 4.14 shows an increase in concentration from substrate to epilayer. Taking into consideration that the carbon concentration in epilayers grown on FZ-Si substrates are below 1x1016 cm-3 a diffusion of carbon from epilayer to the substrate has to be excluded. At present the reason for the increase in carbon concentration in the epitaxial layer is not clear.

4.2.7 Surface morphology of multicrystalline layers Nomarski microscopy was used for a characterization of surface morphology. On <100>-oriented Cz- Si substrates the morphology of the epilayer was found to depend on the substrate surface. For epilayers on polished substrates the surface was equally smooth. An orange peel like morphology was observed for epilayers on saw-damage etched substrates, reflecting the substrate morphology. Epilayers grown on multicrystalline substrates show different surface morphologies from almost flat to inverted tripyramid-like textures according to the underlying grain orientation. Trenches at the site of most grain boundaries is a typical feature. A dependence of growth rate on crystal orientation has been observed. In Figure 4.16 all of these features are illustrated. Surface micrographs and corresponding topographic profiles for an epilayer on mc-Si substrate are presented for two different positions. Note: the measured height does not correspond to the epilayer thickness. The image on the left hand side in Figure 4.16 (top) shows two grains of similar or equal crystal orientation enclosing a small grain of different crystal orientation. The grain in the middle is characterized by a significantly larger thickness and a rougher surface structure compared to the outer grains. The typical base length of the isosceles triangles visible on the surface is in the range of 90 µm with an enclosed angle of ~64°. The structure resembles the shape of an inverted tripyramid with the apex located several microns below the actual surface of the epilayer. The grain boundaries between the adjacent crystal orientations are rather smooth without trenches. 4.2 Epitaxial deposition 53

On the right hand side in Figure 4.16 (top), two grains with very smooth surface morphology are adjoining. On the site of the grain boundary a trench has developed with a width of ~120 µm and a depth of ~9 µm. The difference in thickness between the two grains was determined to 5 µm.

26 26 24 24 22 22 20 20 18 18 16 16 14 14

Height [µm] 12 Height [µm] 12 10 10 8 8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 x-axis [mm] x-axis [mm]

Figure 4.16: Nomarski microscope images (top) and corresponding profiles (bottom) of epilayers grown on a multicrystalline substrate.

For LPE layers a difference in growth velocity for neighboring grains of different crystallographic orientation is reported to be a consequence of growth conditions. In the surface reaction limited regime this difference is large, leading to large steps between neighboring grains [86]. For mass transport limited growth the difference is smaller leading to a smoother transition between two grains of different orientation. Epitaxy in the RTCVD100 is limited by surface reaction kinetics and thus the growth rate is also a function of grain orientation which is clearly visible in Figure 4.16. The growth induced texture of multicrystalline epilayers is a typical feature for high temperature APCVD and is reported to be a consequence of the development of <111> facets [87]. The shape of the texture depends on the crystallographic orientation of the underlying grain. The trenches observed on sites of grain boundaries can be explained from an energetical point of view: the growth of most grain boundaries requires high energies and as a consequence the growth rate is reduced on these sites. The development of crystal facets between neighboring grains usually requires less energy and is therefore more favorable compared to the growth of the grain boundary [88]. The development of trenches can be interpreted as a compromise between these two mechanisms. Once the facets have established the silicon species impinging on the sample surface are more likely to be incorporated on these slightly protruding sites, thus further retarding the growth of the grain boundary 54 4 Process Optimization for RTCVD100

[89]. The width and depth of the trenches depends on the type of grain boundary between adjacent grains with low-energy grain boundaries usually being associated to small and shallow trenches.

4.3 Silicon deposition on foreign substrates In chapter 2 a silicon thin-film solar cell approach based on recrystallization of silicon layers on foreign substrates was presented. The realization of this concept requires the heterogeneous growth of a thin highly doped silicon layer on non-Si substrates. For this purpose CVD processes had to be developed and optimized. The substrate material to be used for this solar cell structure are low-cost ceramics encapsulated by a diffusion barrier layer. At Fraunhofer ISE, silicon dioxide (SiO2) and SiO2/SiNx/SiO2 (ONO – oxide/nitride/oxide) layer stacks are generally used as effective diffusion barrier. The CVD process for the deposition of silicon layers on substrates with SiO2 encapsulation was optimized for mc-Si substrates covered by a 2 µm PECVD SiO2 layer.

Compared to epitaxy, silicon growth on a SiO2 covered surface has to be performed at lower temperatures in order to prevent a decomposition of the silicon dioxide by hydrogen and therefore a damage of the dielectric layer. The process temperature was fixed to 950°C for the optimization procedure. Silicon deposition at low temperatures is determined by reaction kinetics and consequently growth rates are comparatively low and depletion can already be avoided by comparatively low precursor gas flows. In return, the maximum dopant partial pressure and therefore the maximum dopant concentration which can be achieved in the deposited layer is increased. This effect is beneficial for the later function of the layer as BSF within the solar cell. In principle, silicon deposition on foreign substrates can also be carried out at high temperatures provided that the substrate material remains mechanically and chemically stable. In this case, high dopant gas flow rates are necessary to achieve the required doping level.

4.3.1 Thickness uniformity The growth rate distribution across the deposition area was quantified by thickness measurements on cross sections according to the method described in section 4.1.1. Equivalent to the optimization procedure for epitaxial layers, the effect of gas inlet geometry, total gas flow and process gas composition was evaluated by systematic variation of these parameters. The application of the nozzle had a similar effect on thickness homogeneity as already seen for the epitaxy process: the lateral distribution was improved and the deposition zone shifted towards the gas inlet. Therefore the nozzle was used for further optimization. Figure 4.17 illustrates a deposition series with fixed partial pressures of the process gas components but different total gas flow, the latter increasing from top to bottom. For constant Cl/H-ratio the effect of total gas flow rate or equivalently trichlorosilane gas flow rate on the thickness distribution in gas flow direction is clearly visible. In the top graph of Figure 4.17 the process gas contained only 1 g/min of trichlorosilane, resulting in a depletion in gas flow direction and a distinct drop in growth rate from center to the edges. The graph in the middle shows the best thickness uniformity in this series. The precursor gas flow is large enough to prevent depletion and the total gas flow rate is sufficient to 4.3 Silicon deposition on foreign substrates 55 achieve a comparatively good lateral uniformity. In the bottom graph of Figure 4.17 a large total gas flow rate was applied and the associated large heat capacity led to a cooling of the substrate region near the gas inlet and a downstream shift of the center of the deposition zone.

20 relative 10 thickness [%] 100 0 80 TCS = 1.0 g/min 60 H = 1.5 l/min -10 40 2i 20 total = 1.7 l/min -20 0 -80 -60 -40 -20 20 40 60 80

Lateral position

rel. to center [mm] center to rel. Distance from the center of the lamp field [mm]

20 relative 10 thickness [%] 100 0 80

TCS = 2.0 g/min 60 H = 3.0 l/min -10 40 2i 20 total = 3.3 l/min -20 0 -80 -60 -40 -20 20 40 60 80

Lateral position

rel. to center [mm] center to rel. Distance from the center of the lamp field [mm]

20 relative 10 thickness [%] 100 0 80

TCS = 3.0 g/min 60 H = 4.5 l/min -10 40 2i 20 total = 5.0 l/min -20 0 -80 -60 -40 -20 20 40 60 80 Lateral position

rel. to center [mm] center to rel. Distance from the center of the lamp field [mm]

Figure 4.17: Maps of thickness distribution for silicon layers deposited at 950°C. The Cl/H ratio is fixed to 0.16 for all runs and the total gas flow rate increases from top to bottom. The maximum growth rates were all in a similar range of 1 µm/min.

T [°C] 950 TCS [g/min] 2

H2i [l/min] 3 Cl/H 0.16 Gas inlet Nozzle Average growth rate [µm/min] 1.1 in uniform area

Table 4.2: Deposition parameters for optimized silicon growth process at low temperatures. 56 4 Process Optimization for RTCVD100

The best thickness uniformity was determined for the set of parameters listed in Table 4.2. Under these conditions the mean standard deviation in layer thickness across an area of 40x90 mm² is 15%, similar to the epitaxial depositions. A mean growth rate of 1 µm/min was achieved. In the RTCVD100, closed layers with a minimum thickness of approximately 5 µm can be grown. Below this critical value the surface is covered with single crystallites.

4.3.2 Doping of seeding layers Silicon growth on amorphous substrates generally results in a fine-grained crystal structure with grain sizes in the 1 µm range. In this case neither 4-point-probe measurements nor SRP can be applied for a characterization of doping concentration. To enable a determination of the doping level in polycrystalline silicon films, these layers were recrystallized by ZMR. The resulting multicrystalline coarse grain structure enables the application of SRP on a single large grain. Figure 4.18 shows the carrier concentration profile measured for such a sample.

1020 19 SiO layer 10 2 18

] 10 -3 1017 1016 1015 1014 Base BSF Substrate 1013 1012 11 Carrier density [cm density Carrier 10 1010 0 1020304050 Depth[µm]

Figure 4.18: Carrier density profile of a recrystallized and epitaxially thickened silicon layer

deposited on mc-Si substrate with SiO2 barrier layer (SRP).

The base layer of 35 µm thickness is followed by the highly doped recrystallized seeding layer (BSF). The silicon dioxide intermediate layer can clearly be identified as a 2 µm thick region of high resistivity. At a depth of 43 µm the onset of the highly doped substrate region is visible. With respect to their function as BSF, the seeding layers were always deposited with the dopant gas flow adjusted to its maximum possible value. Under the process conditions optimized for thickness homogeneity a minimum specific resistivity of approximately 0.02 Ωcm was obtained.

4.4 Layer growth in RTCVD160 In this section, first results achieved for the deposition of polycrystalline silicon layers in the RTCVD160 reactor are presented. The insight already gained on the characteristics of the deposition 4.4 Layer growth in RTCVD160 57 process especially with respect to the geometry of the reactor could be transferred from the RTCVD100 to the up-scaled reactor model. First experiments were carried out using a quartz tube with round cross section for gas injection. The gas inlet is not located in the center of the sample carrier front plate but at a height of 30 mm making the setup asymmetric. The deposition temperature was set to 950°C. Figure 4.19 illustrates the presence of a cold finger extending from the gas inlet into the deposition area. The top area of the first two samples seems to be affected by a roll back cell which might be associated to the large total gas flow rate of 7.4 l/min. In general, the same correlation between process parameters and thickness distribution as discussed for the RTCVD100 were observed: using too little process gas leads to a depletion and adjusting the total gas flow to small values gives a more pronounced drop in growth rate from centerline to the edge. On the other hand, a cold finger can only be avoided if gas flow rates are not too high. The choice of process parameters is in fact a compromise between these effects.

relative 80 thickness [%] 60 100

80 TCS = 14.0 g/min 40 60 H = 5.1 l/min 40 2i 20 total = 7.4 l/min 20 Heigth [mm] 0 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Distance from the center of the lamp field [mm]

Figure 4.19: Map of relative thickness distribution on 3 wafers of 100x100 mm2 in size positioned in the middle of the RTCVD160 reactor. A maximum growth rate of 1.2 µm/min was measured.

At present, the best deposition process in terms of thickness uniformity results in a mean standard deviation of 34% in growth rate across a deposition area of 90x90 mm2. Considering a smaller area of 70x90mm² in the middle of the sample the standard deviation reduces to 14%. From the experience gained on characterizing deposition processes in the RTCVD100, it seems to be clear that a sufficient thickness uniformity across the deposition zone can only be achieved, if a more efficient gas distribution system is used. For this aim, perforated silicon masks were designed which can be inserted into the sample carrier acting as shower heads. The total area covered by holes was adapted to the cross section of the inlet tube to avoid any overpressure. Alternatively a nozzle can also be used for gas distribution. The benefits to be gained from these modified setups are currently subject of further optimization procedures. The suitability of the deposited silicon layers for zone melting recystallization has been successfully tested. Figure 4.20 shows the image of a recrystallized silicon layer on a 100x100 mm2 substrate. The width of the recrystallized area depends on the width of the melting zone as indicated in the figure. 58 4 Process Optimization for RTCVD100

Figure 4.20: Recrystallized silicon seeding layer on a 100x100 mm2 sample. The deposition of the silicon layer has been done in the RTCVD160 reactor.

4.5 Summary Characterization methods suitable for a complete analysis of silicon epitaxial layers and polysilicon layers were evaluated. A combination of thickness profiling and 4-point probe mapping is presented as an effective tool for a fast and efficient characterization of thickness and dopant homogeneity on large area samples. The epitaxy deposition process in the RTCVD100 was optimized in terms of thickness uniformity which could be quantified to 13% across a deposition area of 40x100 mm² for optimized process conditions. The dependence of doping concentration on dopant gas flow was determined over two orders of magnitude and a doping homogeneity of 11% across the deposition area could be defined, independent from dopant gas flow and deposition process. The possible doping range for epilayers extends from 5x1015 cm-3 to 1.5x1018 cm-3 with the maximum doping density being limited by the operation range of the diborane mass flow controller. Defect densities below 1x104 cm-2 and effective minority carrier lifetimes up to 7.5 µs for a 30 µm thick epilayer of 0.5 Ωcm resistivity indicate a high crystal quality of the epilayers indifferent of growth rate. Carbon and oxygen concentration below 1x1016 cm-3 were measured by SIMS in epilayers on high-resistivity FZ-Si substrates. The entire characterization procedure was carried out for two epitaxy processes, differing in growth rate by a factor 1.6. Using the fast growth mode, an average deposition rate of up to 9 µm/min can be achieved. Thickness and doping uniformity as well as defect density, impurity concentration and carrier lifetime are comparable for both process types. As a result of the extensive characterization and optimization procedure, high purity epilayers with well defined properties and mean growth rates up to 9 µm/min can now be deposited in the RTCVD100. For the deposition of silicon layers on foreign substrates at low temperatures the thickness homogeneity could be optimized to 15% across a deposition area of 40x100 mm². A minimum resistivity of 0.02 Ωcm was reached using maximum dopant gas flow. 4.5 Summary 59

First experiments were run in the RTCVD160 reactor and the CVD process for seeding layer deposition was characterized in terms of thickness homogeneity. The layers proved to be well suitable for zone melting recrystallization. For both reactor types the geometry of the gas inlet was identified to have a detrimental effect on growth rate homogeneity. An improved gas distribution and consequently thickness uniformity could be achieved by the application of a nozzle and masks similar to a showerhead.

5 Doping of epitaxial silicon layers

The application of epitaxially grown doped silicon layers for semiconductor devices originates in the integrated circuit technologies. Unlike conventional doping techniques like diffusion or ion implantation CVD allows the fabrication of silicon layers with well controlled doping concentration profiles and doping levels on any kind of silicon substrate without introducing any damage to the silicon crystal. With CVD the growth of lightly doped layers over heavily doped substrates is possible.

A short introduction on the theory of dopant incorporation is given in the first section and the functional dependence between doping level and process parameters is pointed out. Subsequently boron diffusion from the gas phase, autodoping and memory effect are described based on experimental results. Main emphasis is put on the discussion of different shapes of doping profiles which were obtained in dependence on process conditions in the RTCVD100. Finally, the effect of different doping profiles on the performance of epitaxial solar cells is evaluated by means of device simulation. The chapter closes with a discussion of the gas system of the RTCVD100 and a proposal for an improved design.

5.1 Dopant incorporation The request for growing epitaxial silicon layers with well defined doping concentrations and profiles makes an understanding of the dopant incorporation process necessary. Similar to silicon deposition the process of dopant incorporation can be described by the following steps: transport of dopant gas to the substrate surface, adsorption of the dopant molecules, chemical decomposition and incorporation, and finally desorption of byproducts [41], [90]. A detailed comprehension of the chemical reactions taking place on the substrate surface is still a topic of research. The amount of dopant incorporated during silicon deposition is known to depend on process parameters like temperature, growth rate and partial pressure of the process gases. In literature this dependence is often modeled by the following equation [91], [52], [79]:

p 0 dopant (5.1) Cdopant = K eff (T,v) 0 , 0 ≤ K eff ≤ 1 pSi

0 0 where Cdopant denotes the dopant concentration in the deposited silicon film, p Si and p dopant are the

partial pressures of silicon and dopant containing process gases and Keff is the effective segregation coefficient, which depends only on temperature and growth rate for low dopant concentrations [92].

Keff can be regarded as a measure for the effectiveness of dopant incorporation, assuming that the

incorporation efficiency for silicon is always equal to 1. In the limiting case Keff =1 all the dopant

atoms reaching the substrate surface are built into the growing film. For Keff <1 only a fraction of

61 62 5 Doping of epitaxial silicon layers atoms is incorporated, the rest being rejected from the surface. According to this model the carrier concentration in the growing film is linear with the partial pressure of the dopant gas. Depending on the type of dopant the incorporation efficiency shows different characteristics. In case of B2H6 the dopant concentration is known to increase with rising temperature whereas for PH3 or

AsH3 the dopant incorporation decreases [91], [93]. Figure 5.1 shows the phosphorus doping concentration in epitaxial silicon as a function of temperature, growth rate and dopant partial pressure for a PH3-SiH4 system [94], pointing out the complexity of the incorporation mechanism.

Figure 5.1: Doping concentration in epitaxial layers as a function of temperature for different PH3 partial pressures and silicon growth rates [94].

In [41] a model describing the mechanisms of boron incorporation is developed for a B2H6-SiHCl3-H2 system at atmospheric pressure. The model is based on a competitive incorporation of silicon and boron during the growth process and further assumes a negligible desorption rate of boron atoms from the silicon substrate surface due to the low concentration of diborane gas. The dopant concentration in the epitaxial silicon layer is defined as

N B CB = CSi , N B = 2ka [B2 H 6 ] (5.2) N B + N Si where CB and CSi denote the density of boron and silicon atoms in the grown silicon film, respectively.

NSi is the molecular deposition rate of the silicon crystal and correspondingly NB describes the boron deposition rate. [B2H6] denotes the molecular diborane concentration. ka is the overall rate constant of the boron incorporation process and is assumed to depend on the ratio of the silicon substrate surface occupied by chemisorbed SiCl2 molecules:

ka = (1− Θ)kv + Θko (5.3) 5.1 Dopant incorporation 63

kv and ko denote the rate constants for the chemical reaction of diborane molecules on vacant and occupied surface sites respectively. Θ represents the fraction surface states occupied by SiCl2. In contrast to diborane molecules, the TCS-molecules are assumed to react only on vacant surface sites leading to a competition for these states between both species. Thus the boron deposition rate does not only depend on the boron concentration but also on the SiHCl3 and H2 concentration.

In [48] a functional dependence between the silicon growth rate NSi, temperature and Cl/H ratio is given. Taking this into consideration, the effect of temperature and growth rate on dopant incorporation are clearly specified through eqn. (5.2), in contrast to the model described by eqn. (5.1). Based on experimental results Habuka reports a decrease in carrier concentration with increasing silicon deposition rate, for fixed diborane concentration [41]. Furthermore, similar to eqn. (5.1) a linear increase of carrier concentration was observed for an increasing concentration of diborane. Comparing experimental results with numerical calculations, the proposed model could be verified for low Cl/H-ratios and within a temperature range of 950-1050°C. For the numerical simulation of doping densities in epitaxial layers the transport phenomena in a horizontal cold-wall reactor were taken into account. To determine the dependence between process parameters and epilayer carrier concentration for the RTCVD100 reactor, experiments with varying diborane gas flow were carried out. The depositions were done using two different epitaxy processes (A and B) which have already been presented in chapter 4. The main difference between the two processes is the total gas flow and composition and therefore the growth rate. Process A and B yield growth rates of 5-6 µm/min and 9-10 µm/min respectively, corresponding to a difference by factor of 1.6. The diborane gas flow was varied within a range of 1 sccm to the maximum possible gas flow of 50 sccm. Diborane diluted to 2500 ppm in hydrogen was used for all experiments. The minority carrier concentration in the epilayers was analyzed by spreading resistance measurements, always assuming that the measured carrier concentration equals the concentration of incorporated boron atoms. Figure 5.2 shows carrier densities measured in epilayers as a function of boron concentration in the process gas for both epitaxy processes. All data points can be fitted by one single curve independent from the applied deposition process. A good fit is obtained for

2 log(CB ) ~ 16.54 +1.41× log([B2 H 6 ]) − 0.17 × log([B2 H 6 ] ) (5.4)

In a first order approximation the fit curve shows a superlinear dependence of the carrier density on the boron concentration at the inlet:

16 1.41 CB ~ 3.47 ×10 [B2 H 6 ] (5.5)

This interrelation shows that under the prevailing conditions the minority carrier concentration in the epilayer does not depend on the silicon growth rate. For an interpretation of these results with respect to the observations made in [41] the process conditions under which the experiments were carried out have to be compared and the assumptions made for the modeling have to be considered. The discussed model of boron incorporation presented by Habuka is based on a conventional CVD process, run in the reaction-limited regime. The TCS is highly diluted in hydrogen and large process gas flows are used. In [41] silicon depositions were carried out using process gas mixtures with TCS concentrations of 0.9-3.5% of H2 gas corresponding 64 5 Doping of epitaxial silicon layers to Cl/H-ratios in the range of 0.01-0.05 and mean molecular weights between 3.2x10-3-6.7x10-3 kg mol-1. The deposition temperature ranged from 950-1050°C with deposition rates between 1- 3 µm/min. For boron doping the diborane concentration at the inlet was varied between 1x10-4-1 ppm. Consequently a negligible interaction between TCS and diborane molecules was assumed and for both species the binary diffusion coefficient in hydrogen was used to describe the diffusion forced by the concentration gradient.

19 10 Process A Process B 16.54 1.41 ] Fit: y =10 *x -3 1018

17

10

1016 Carrier density Carrier[cm density 1015 0.1 1 10 B H concentration at the inlet [ppm] 2 6

Figure 5.2: Measured carrier densities for epilayers of process A and B graphed against the diborane concentration in the process gas. All data points can be fitted by one curve with superlinear characteristics.

Within this work, process gas compositions with Cl/H-ratio of 0.75 and 0.43 for process A and B respectively have been used with mean molecular weights of 5.5x10-2 kg mol-1 and 3.5x10-2 kg mol-1. In this case, TCS and hydrogen make up a similar mole fraction of the entire process gas. For process A and B the TCS concentration can be determined to 40% and 25% of the total gas respectively. The properties of the process gas mixture are no longer dominated by the properties of hydrogen but is significantly influenced by the TCS species. The depositions were carried out at a temperature of 1170°C with growth rates ranging from 5-6 µm/min for process A and 9-10 µm/min for process B. Diborane concentrations between 0.1-25 ppm have been applied. Compared to [41], silicon depositions in the RTCVD100 were carried out in a regime, where the growth rate is no longer limited by adsorption but by reaction kinetics. Cl/H-ratio, mean molecular weight of the gas composition and diborane concentration are by one order of magnitude larger for the depositions in the RTCVD100 compared to the commercial reactor used in [41]. In addition, a substantially higher process temperature has been applied. Altogether, gas flow dynamics and reaction kinetics can be expected to be different for both systems and deviations from the model for dopant incorporation presented in [41] can be expected. For the development of a theoretical model to describe the mechanism of dopant incorporation leading to the observed carrier concentrations, additional experiments e.g. with varying growth rate and temperature are necessary. 5.2 Doping profiles of epitaxial layers 65

5.2 Doping profiles of epitaxial layers The characteristics of a typical doping profile in epitaxial layers is determined by a transition zone between substrate and epilayer where the doping level of the substrate gradually approaches the doping level of the epitaxial layer. In microsystem technology sharp transitions and thin epilayers are required for an optimal performance of the devices [73], [95]. In crystalline silicon thin-film solar cell technology the demands on the width of the transition region are less critical. In general, a step-like change in dopant gas flow does not result in an equally abrupt change in carrier density in the growing film, because a finite amount of time is needed to establish a new steady-state of dopant concentration in the gas phase [96]. The region between the initial and final constant doping concentration reflects the gradual change in partial pressure of the dopant containing gas during the deposition process. This transient is commonly referred to as transition region. An ideal transition zone is only characterized by the time which is needed to establish a stable gas phase after changing the dopant partial pressure. Realistic transients are additionally affected by solid- state diffusion and autodoping [37], [52]. Solid-state diffusion occurs if e.g. the deposited epilayer features a doping density different from the underlying substrate. Assuming the deposition of a lightly doped layer on a heavily doped substrate, the substrate can in a first approximation be taken as an inexhaustible source for dopant atoms and the doping concentration by solid-state diffusion can therefore be described by a complementary error function depending on location x and diffusion time t: x C(x,t) = C0 erfc( ) (5.6) 2 Dt where C0 and D denote initial substrate concentration and diffusion coefficient of the dopant species. The traditional model for autodoping is based on the evaporation of dopant atoms from the surface of the wafers inside the reactor during the heating ramp and the high-temperature prebake and their introduction into the gas stream. Part of these atoms can be re-incorporated into the growing film, giving rise to an unintentional doping of the epilayer [97]. Other additional dopant sources are the back of the wafers and the surrounding reactor. For the growth of lightly doped layers on heavily doped substrates, the constant background doping coming from the deposition system is the limiting factor for the maximum resistivity to be reached (assuming pure process gases). Figure 5.3 shows schematics of intended (left) and actual (right) doping profiles for an intrinsic epilayer grown on a heavily doped substrate. The components of unintentional doping are highlighted. Common methods to decrease the effect of boron autodoping include e.g.

• Low bake temperature and time

• Reduced process pressure to decrease gas residence time

• Rapid thermal processing i.e. fast heating and cooling ramps • Low deposition temperature

• Backsealing of the samples. 66 5 Doping of epitaxial silicon layers

Intended doping profile Actual doping profile

Figure 5.3: Intended (left) and actual (right) doping profile in an intrinsic epitaxial film deposited on a heavily doped substrate. Sources of unintended doping: (1) Solid-state out diffusion, (2) Autodoping, (3) Background doping [96].

5.3 Experimental carrier concentration profiles The following paragraphs deal with the characteristics of doping profiles in epitaxial silicon layers grown under different epitaxy process conditions. The depositions were carried out in the RTCVD100 reactor using epitaxy process B (fast growth mode). All substrates were p-type boron doped with a <100> crystal orientation. Unless otherwise stated, the substrates were not polished and a damage etch has been applied before epitaxy.

5.3.1 Boron diffusion and evaporation

The first basic experiments on doping profiles focused on the intentional diffusion of boron from B2H6 into the silicon wafers at high temperatures. FZ-Si and Cz-Si substrates with a specific resistivity exceeding 10 Ωcm and below 0.02 Ωcm respectively have been used as test wafers. The applied diffusion process followed the standard deposition process in terms of purge time, heating and cooling ramps and gas stabilization. Diffusion temperature, time, diborane and hydrogen gas flow rate were set to 1170°C, 5 min, 50 sccm and 8 slm respectively. The diffusion processes were followed by a 1.5 min reactor-purge at 1170°C and a 1 min annealing step at 1200°C under hydrogen. Figure 5.4 shows the carrier concentration profiles measured by SRP after the diffusion process. Both carrier density profiles show a distinct increase in doping concentration towards the surface of the sample. The increasing slope is restricted to a surface-near region of about 1.5 µm with a peak concentration in the range of 6x1019 cm-3 for the high resistivity substrate and slightly below for the low resistivity sample. The profiles verify that a diffusion of boron from the gas phase has occurred during the high- temperature step. While the carrier concentration profile of the high resistivity sample shows a Gauss like characteristic, the profile is rather flat for the low resistivity sample. SIMS measurements are 5.3 Experimental carrier concentration profiles 67 necessary to verify whether this difference is caused by electrical inactivity of boron in case of the heavily doped substrate or is related to the diffusion mechanism of boron in silicon [98], [77].

1020

1019 ] -3 1018

1017

1016

Substrate [Ωcm] Carrier [cm Density 1015 > 10 < 0.02

1014 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Depth [µm]

Figure 5.4: Carrier concentration profiles measured after high-temperature boron diffusion from the

gas phase containing B2H6 and H2.

The diffusion of boron from the vapor-phase is only little discussed in literature. In [99] this method has been used for the preparation of shallow MOS base structures. Similar to the experiment described in this section the diffusion was carried out in an APCVD reactor using B2H6 as a dopant source at temperatures between 800-900°C. Under these conditions the carrier concentration was found to increase with increasing dopant gas flow rate and diffusion time. For carrier concentrations exceeding a value of about 1x1019 cm-3 the boron concentration exceeded the carrier concentration, i.e. part of the boron atoms was not activated. In [100] the diffusion of boron from B2H6 in a UHV-CVD apparatus with subsequent RTA (rapid thermal anneal) is presented as a novel technology for the preparation of ultra-shallow junctions for MOSFET devices. However, the boron diffusion mechanisms are not investigated in either publication. To gain more insight on the diffusion of boron from the vapor-phase additional experiments have to be carried out in the RTCVD100. The dependence of carrier concentration and boron diffusion profiles on the sample position in the reactor, diffusion time and temperature and diborane concentration in the gas phase have to be determined. In a second experiment, the inverse process – diffusion of boron atoms from the bulk of the sample to the surface and evaporation into the gas phase – was studied. The diffusion process has been tested using again a high resistivity FZ-Si and a low resistivity Cz-Si sample in separate runs. Prior to each experiment, the reactor and the dummy wafers were capped by a doped silicon layer in order to generate standard deposition process conditions. After heating up to 1170°C, the substrates were annealed for 5 min under pure hydrogen. Figure 5.5 shows the carrier concentration profiles of both sample types after anneal. 68 5 Doping of epitaxial silicon layers

Considering the low resistivity sample, the doping concentration decreases towards the surface. Based on the SRP data, the integrated boron dose loss was calculated to 1.4x1014 cm-2. This result verifies that during the high-temperature process step, boron atoms can in fact evaporate from the sample surface. For the high resistivity sample, the carrier density increases from 8x1014 cm-3 in the substrate to a peak concentration of 1x1016 cm-3 at the surface. In this case, a diffusion of boron into the substrate has occurred. Since no diborane has been injected, the diffused boron atoms must originate from the surrounding. During the heating- and cooling-ramp and the high-temperature bake, boron can evaporate from the surrounding dummy wafers and quartz carrier, which have been intentionally capped by a doped silicon layer. A subsequent adsorption of boron species on the surface of the lowly doped test wafer and diffusion of boron into the bulk results in the observed doping profile. The integrated dose across the diffused region of the high resistivity sample is by almost 4 magnitudes lower compared to the case of intentional diffusion of boron from B2H6.

1020

1019 ] -3 1018

17 Substrate [Ωcm] 10 > 10

< 0.02 1016

Carrier [cm Density 1015

1014 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Depth [µm]

Figure 5.5: Carrier concentration profiles measured after high-temperature anneal under hydrogen.

The experimental results show that depending on the specific resistivity of the substrates and the boron concentration in the surrounding atmosphere, a diffusion of boron can occur either from the gas phase into the bulk of the sample or vice versa if the sample is subjected to a high-temperature anneal. For a quantification of the influence of process conditions like bake temperature and time, hydrogen gas flow, doping concentration of the test sample and of the surrounding on the diffusion process of boron, additional experiments have to be carried out.

5.3.2 Background doping and memory effect To evaluate the contribution to epilayer carrier density coming from a constant background doping, intrinsic silicon layers have been grown on silicon substrates of different resistivity. To exclude any contamination from parasitic deposits on the quartz carrier or quartz tube these parts were wet chemically cleaned and baked in hydrogen before the depositions were carried out. Quartz carrier and dummy wafers which were used for the experiment were capped with an intrinsic silicon CVD layer. 5.3 Experimental carrier concentration profiles 69

The test wafers were used in the order of increasing doping level to exclude any memory effects from proceeding samples. Figure 5.6 shows the measured carrier concentration profiles for intrinsic epilayers grown on different silicon substrates. All curves in Figure 5.6 (left) show the same characteristic: the carrier concentration profiles consist of a steep drop until a concentration of approximately 3x1014 cm-3 is reached, followed by a more gradual decrease and a dip before the final constant doping level is approached. For each substrate type the minimum carrier density in the dip is located at 6-7x1012 cm-3 and the final epilayer doping concentration reaches a constant value of 1x1014 cm-3. The whole transition region from substrate until the constant part of the profile begins, expands over 7-8 µm for all depositions (Figure 5.6, right). The on-substrate steep decrease is not present for the substrate of 100 Ωcm resistivity.

1019 1017 transition region 18 ρ [Ωcm] 10 sub < 0.02 16

] 10 -3 17 1 zoom 10 > 10 substrate 100 15 1016 10

constant doping 15 10 1014 1014 13 13 10 ρ [Ωcm] 10 sub

Carrier Density [cm Carrier Density 1 1012 1012 25 30 35 40 45 50 32 34 36 38 40 42 44 46 Depth [µm] Depth [µm]

Figure 5.6: Carrier concentration profiles of intrinsic epilayers deposited on silicon substrates of different resistivity.

The independence of the measured profiles on the resistivity of the substrates indicates a negligible dopant contribution from the backside or edges of the samples. All epitaxial layers are p-type with a carrier concentration of 1x1014 cm-3, representing the background doping level. Interpolating the empirical function given in eqn. (5.5), a diborane concentration of 16 ppb is necessary to produce this doping concentration. A contamination through impurities present in the trichlorosilane can be excluded since the trichlorosilane which has been used, is of electronic grade purity with a specified boron content below 0.1 ppba. Other sources for boron contamination may be the quartz carrier, the surrounding quartz tube or the gas system. Compared to the schematic doping profile illustrated in Figure 5.3, the experimental curves show a distinct dip in carrier concentration within the transition region. The interpretation of this characteristic is not straightforward and will be discussed in the next section. To extract the influence of system memory effects on the carrier concentration of epilayers, two depositions with a different conditioning process of the surrounding carrier and dummy wafers were carried out. In the first case, an intrinsic pre-deposition was applied while in the second experiment the reaction chamber was conditioned by depositing a doped silicon layer. The resulting carrier concentration profiles are shown in Figure 5.7. 70 5 Doping of epitaxial silicon layers

The sample with intrinsic pre-deposition shows the same characteristics as in Figure 5.6 (right). The conditioning of the reaction chamber by a doped silicon layer (doped predep.) resulted in a carrier density profile with on-substrate peak. The peak doping density was determined to 6x1015 cm-3. The formation of the peak is assumed to result from a diffusion of adsorbed boron atoms from the surface into the bulk of the sample during the heating-ramp and the prebake (see section 5.3.1) i.e. before the deposition process begins. The adsorbed boron atoms are provided from boron evaporation of the doped surrounding. The final shape of the peak is determined by solid state diffusion of boron from the peak into the lower doped neighboring regions during the deposition process and the following high-temperature purge and annealing step.

1017 Reactor conditioning

16 intrinsic predep. ] 10 doped predep. -3

1015

1014

1013 Carrier Density [cm Carrier Density 1012 10 12 14 16 18 20 22 24 Depth [µm]

Figure 5.7: Influence of memory effect on the carrier concentration profiles of intrinsic epilayers.

To evaluate the impact of gas phase autodoping caused by the residence time of the dopant gas in the reactor system, a high-low doping deposition process was carried out where the growth of a low resistivity epilayer was directly followed by the deposition of an intrinsic layer. The resulting carrier concentration profile of the entire epilayer and the corresponding setting of the diborane gas flow rate are illustrated in Figure 5.8. The abrupt change in diborane gas flow results in an immediate drop in carrier density, followed by a steady decrease. Within the deposition time of 2 min, the final steady state featuring a constant doping concentration of 1x1014 cm-3 was not reached. The residence time of dopant gas in the reaction volume and in the gas lines determine the transition of the high-low junction. These parameters are intrinsic characteristics of each deposition system, depending on reactor geometry, gas inlet and gas system. The residence time of the process gas in the RTCVD100 reaction chamber is assumed to be comparatively short, due to the high total gas flow rates and the associated high gas velocities in the range of several 10 cm/s. The gradual decrease in carrier density is supposed to be mainly related to the design of the gas system (see section 5.3.4). After closing the diborane valve, the diborane gas line is still filled with dopant gas which slowly diffuses into the main gas line feeding the reactor. 5.3 Experimental carrier concentration profiles 71

10 8 6 [sccm] 6 4 H 2

B 2 0

1018 ] -3

1017

1016 Carrier Density [cm Density Carrier 1015 5 10152025 Depth [µm]

Figure 5.8: Diborane gas flow rate set for a high-low doping deposition process (top) and corresponding carrier density profile (bottom).

For the preparation of epitaxial silicon thin-film solar cells, epilayers with carrier concentrations in the range of 4x1016-1x1017 cm-3 are deposited onto highly doped substrates. Compared to these concentrations, the observed background and gas phase autodoping and memory effect are negligible.

5.3.3 Doping profile of intrinsic epilayers The main features of a typical carrier concentration profile for intrinsic epilayers have already been presented in the previous section. The most prominent and unexpected characteristic is the dip in carrier concentration within the transition region between substrate and epilayer. This section aims to discuss and explain possible mechanisms which can lead to the development of such a depression. In general, there are two possibilities to explain the lack in carrier concentration: first, it is due to a physical lack of boron atoms and second, the electrical activity of boron atoms in this region is eliminated or compensated. Both hypotheses are discussed in the following. SIMS measurements were carried out to determine the actual boron content in the epilayer. In Figure 5.9 SRP and corresponding SIMS profile are compared. The boron concentration in the substrate accounts to 2.6x1016 cm-3 and exceeds the corresponding SRP value. In contrast to the SRP measurement, no dip in dopant concentration is visible near the interface, whereas the mean value for boron in the epilayer is in good agreement with the measured carrier concentration. The deviation between boron and carrier concentration in the substrate might be caused by an electrical inactivity of part of the boron atoms or might be associated to the SIMS measurement principle. A careful interpretation of the SIMS profile measured in the transition region is necessary: the detection limit for SIMS is in the same range as the doping density in the epilayer and in addition, the depth resolution typically deteriorates with increasing depth of measurement. For these reasons it has to be taken into consideration that SIMS is probably not capable to detect the dip observed in SRP and no unambiguous information on the boron concentration in the dip region can be drawn. 72 5 Doping of epitaxial silicon layers

SRP ] 16 -3 10 SIMS

1015

1014

1013 Dopant concentration [cm Dopant concentration 76543210-1 Distance from interface [µm]

Figure 5.9: Comparison of boron concentration measured by SIMS and corresponding carrier concentration (SRP).

Physical lack of boron atoms In the absence of intentionally injected dopant gas, background and gas phase autodoping determine the dopant concentration in the epitaxial layers. To understand the formation of the dip, possible mechanisms have to be found which are capable to explain, why at the beginning of the epitaxial growth process, no or only little boron is incorporated into the growing layer. According to eqn. (5.5) the reduction in doping concentration from 1x1014 to 7x1012 cm-3 corresponds to a decrease in diborane concentration by a factor 6.6. If the incorporation of boron depends only on the boron-concentration in the gas phase, the formation of the dip can either be achieved by a short- term reduction of boron-containing species or by an increase in trichlorosilane gas flow, assuming the hydrogen gas flow to be fixed. From a technical point of view, the latter scenario is less likely and for the following considerations only the first possibility is regarded. In the following the issues of gas transport and chemical consumption of boron species are addressed to give possible explanations for a sudden drop in boron concentration. Transport After heating and prebake, the reaction volume is in a state where the boron concentration in the atmosphere is determined by the evaporation of boron from carrier and wafers (assuming a negligible contribution from gas system or other parts of the reactor). The introduction of the process gas represents a perturbation of the present atmosphere and some time is needed until a steady state is re- established. The diffusion of boron atoms to the sample surface may be disturbed or even inhibited during this period. Based on these assumptions, the formation of the sink could be explained as follows: immediately before the process gas enters the reactor, the system is in a quasi equilibrium with boron atoms being adsorbed and desorbed on the sample surface. With the injection of the process gas, part of the boron species present in the gas atmosphere may be driven out of the system by forced convection. On the other hand, boron which is adsorbed on the sample surface can be incorporated into the growing film. The on-substrate decreasing part of the dip reflects the consumption of the limited amount of boron by incorporation. The abrupt disturbance of the gas phase and the short “evacuation” of the atmosphere from boron species prevents a continuous supply of the 5.3 Experimental carrier concentration profiles 73 sample surface with boron. Assuming a growth rate of 9 µm/min, about 27 sec are needed to grow an epilayer thickness of 4 µm, i.e. after about 27 sec a constant boron concentration begins to establish in the gas stream. However, with respect to the large gas velocities in the reaction chamber in the range of several 10 cm/s even at room temperature (total gas flow rate of 10 sl/min), the establishment of a new steady gas phase is supposed to occur on a much smaller time scale in the order of few seconds. According to the presented assumption, a dip will develop every time the trichlorosilane is injected into the system. To verify this statement, an experiment has been carried out, where two intrinsic layers were deposited within one run, the deposition steps only being separated by a 2 min hydrogen bake. An analysis of the doping profile showed that between substrate and first epilayer the typical deep dip had developed whereas between first and second epilayer only a minor depression in carrier concentration is visible. This result is also in contradiction to the above presented transport theory. Chemical consumption of boron A mechanism known to consume boron or diborane is the chemical reaction of water vapor with reactive boron halides. The presence of water vapor and HCl in the reactor atmosphere has been reported to influence the boron concentration in epitaxial layers [101]. It was found that for a fixed partial pressure of diborane the boron concentration in the grown layer decreases with increasing water vapor concentration. A similar result has been obtained for the presence of HCl in the atmosphere. At thermal equilibrium and high temperatures, BH2 is the dominant boron species in a gas phase containing only hydrogen and boron. Chemical reactions of this halide with Cl, HCl or H2O lead to a consumption of this species [102], [101]. For a B-H and a B-H-O system in thermal equilibrium the gas phase composition was calculated using a simulation program [53]. According to experimental conditions, a temperature of 1170°C and a total pressure of 1 atm was assumed. Figure 5.10 shows the mole fractions of the dominant chemical species calculated for different concentrations of diborane and water vapor.

10-5 H 10-5 H

H O = 0 ppm B H = 1 ppm 2 2 6

BHO

-6 -6 BH 10 BH 10 2 2

BH BH 3 3 Mole fraction Mole fraction BHO 2

10-7 10-7 0.1 1 10 0.1 1 10 100 B H concentration [ppm] H O concentration [ppm] 2 6 2

Figure 5.10: Gas phase composition of a B-H-O-system in thermal equilibrium for a total pressure of 1 atm and a temperature of 1170°C. 74 5 Doping of epitaxial silicon layers

If the humidity in the gas phase is set to zero, BH2 and BH3 are the most abundant compounds (Figure 5.10, left) and the amount of both species increases with increasing initial diborane concentration. In

Figure 5.10 (right) the initial diborane concentration is fixed to 1 ppm and the H2O concentration is varied. For low concentrations of water vapor, BH2 and BH3 are still the dominating species. With increasing humidity, the mole fraction of oxygen containing boron halides rises rapidly on the expense of BH2 and BH3. For H2O concentrations exceeding the diborane concentration, boron hydride oxide (BHO) dominates the gas phase composition. If the amount of water vapor is further increased, the mole fractions of BH2 and BH3 become negligible and instead BHO and BHO2 (boric acid) are the most stable compounds. The same characteristics can be observed if the initial diborane concentration is increased. The simulation shows that in the presence of water vapor, diborane may in fact be used up by chemical reactions including hydrogen and oxygen. If the concentration of water vapor is greater than the diborane concentration, the reduction in boron halides becomes significant. Assuming that the resulting boric acids do not contribute to the incorporation of boron, the carrier concentration in a growing epilayer may be reduced. To explain the measured carrier density profiles according to this theory, it must be assumed that during the first stages of deposition, water vapor is introduced into the system e.g. through the trichlorosilane, or that oxygen containing species cover the surface of the samples and impede the adsorption of boron-containing molecules. To reduce the background doping density of 1014 cm-3 by one order of magnitude, the diborane concentration must also be reduced by approximately the same factor. With respect to the hypothesis presented in this section, this can be achieved if the partial pressure of water vapor in the reactor is greater than the partial pressure of diborane. Assuming a background diborane concentration of 16 ppm, the concentration of water vapor must exceed this value. From a technical point of view the presence of water vapor in the trichlorosilane or the corresponding gas lines is difficult to detect and could not be investigated within this work. During the heating-ramp and the high-temperature prebake, all oxygen should be removed from the reactor and the sample surface should be free from native oxide. Assuming an incomplete prebake, the residual oxygen on the sample surface might hinder the adsorption of boron species and/or might react with the boron halides according to the presented reaction path way. In any case, the boron concentration near the interface substrate/epilayer would be reduced. First tests on the influence of prebake time and temperature were carried out with the results indicating that these parameters in fact influence the doping profile. Further experiments on prebake conditions are needed to quantify their impact. Compensation or electrical inactivity Substitutional boron represents an acceptor state in the silicon crystal with the minority carrier concentration depending on the boron content. In the presence of donors the hole concentration may be reduced or even compensated thus lowering the p-type conductivity. Apart from group V impurity atoms, defects or thermal donors can act as donor states in the silicon crystal. Crystal defects disturb the normal lattice order and can therefore introduce electrically active states of either kind in the forbidden band gap. A prominent source for donor states are different oxygen complexes known as 5.3 Experimental carrier concentration profiles 75 thermal donors or new donors [103]. An accumulation of either kind in an otherwise boron doped region may lead to a locally reduced minority carrier concentration. The oxygen and carbon concentration in the epilayer and especially across the interface were analyzed by SIMS measurements. An accumulation of either impurity at the interface might lead to a highly defected area, capable of trapping carriers or in case of oxygen enhance the formation of donors and in consequence compensate the acceptor concentration at this site. Figure 5.11 shows SIMS profiles for both elements. Although carbon and oxygen are present in high concentrations no irregularities are visible at the interface. The dip in carrier concentration has been observed in epilayers on substrates with high oxygen and carbon concentrations but also on FZ-silicon substrates where the concentration of both elements is below 1x1016 cm-3. A dependence of the carrier concentration profile on the substrate concentration of these impurities can therefore be excluded.

19 oxygen

] 10

-3 carbon

epitaxy substrate 18

10

1017 Impurity concentration [cm Impurity 6 4 2 0 -2 -4 -6 Distance from interface [µm]

Figure 5.11: Oxygen and carbon concentration profile measured for epilayer and substrate (SIMS).

The epitaxial deposition of high resistivity layers on low resistivity substrates can result in an enhanced formation of crystal defects caused by the lattice mismatch between the differently doped regions. The crystal structure at the epilayer/substrate interface was investigated by defect etching of cross sections and in addition EBIC measurements were carried out on corresponding sample cross sections. Neither defect density nor recombination activity were found to be increased at the interface. In conclusion, the observed dip in carrier concentration cannot be clearly attributed to any of the proposed mechanisms. Under the prevailing deposition conditions the width of the dip-region corresponds to a deposition time of approximately 50 sec assuming a constant deposition rate of 9 µm/min. An investigation of the dependence of the local decrease in carrier concentration on process parameters (prebake conditions, growth rate, temperature) could give further insight on the mechanisms responsible for the formation of the dip. 76 5 Doping of epitaxial silicon layers

5.3.4 Standard epitaxy The standard process for epitaxial deposition of doped silicon layers in the RTCVD100 consists of heating the samples under hydrogen to the process temperature of 1170°C, prebaking for 1 min and subsequent layer growth. In chapter 4 two epitaxy process A and B were described and characterized. The outstanding difference between process A and B is the growth rate, which is 5-6 µm/min for process A and 9-10 µm/min for process B. Now the carrier concentration profiles measured for epilayers grown via both processes are discussed in more detail. Epitaxial layers of 30-40 µm thickness were deposited on highly-doped, polished Cz-Si substrates with varying diborane flow rate. Figure 5.12 shows the carrier concentration profiles measured by SRP for both epitaxy processes.

1019 1019 1018 1018

] 17 ] 17 -3 10 -3 10 1016 1016 1015 1015 Process A Process B 14 B H [sccm] 14 B H [sccm] 10 2 6 10 2 6 1.5 2.0 1013 2.0 1013 5.0 10.0 10.0 12 50.0 12 50.0

Carrier Density [cm 10 Carrier Density [cm 10 1011 1011 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Depth [µm] Depth [µm]

Figure 5.12: Carrier concentration profiles of epilayers deposited by epitaxy process A (left) and B (right) for different diborane gas flow rates.

All profiles show the same characteristics, independent from deposition process and dopant gas flow. The transition region can be separated into three regions: first, the carrier concentration decreases until a minimum is reached, then a steep increase follows and the final constant epilayer doping level is gradually approached. An exception to this characteristic is observed for a maximum diborane gas flow rate of 50 sccm. In this case, the substrate-near decrease in carrier concentration is missing and instead a slight increase in visible. With decreasing dopant flow rate the substrate-near dip gets wider and deeper. About 1 µm before reaching the sample surface the carrier concentration rises again to values in the range of 1x1018 cm-3.

Transition region The measured carrier concentration profiles in the transition region resemble the transients obtained for intrinsic epilayers (see section 5.3.3). However, while for all intrinsic layers the minimum was located at a constant carrier density of 7x1012 cm-3, the width of the dip and its depth now depend on the diborane gas flow rate and silicon growth velocity or more general on the diborane inlet concentration. The dip with the lowest carrier concentration featured a density below 1012 cm-3, one order of magnitude smaller compared to the intrinsic case. 5.3 Experimental carrier concentration profiles 77

In order to control the actual boron concentration in the grown silicon film, SIMS measurements were carried out. In Figure 5.13 a SIMS profile is compared to the corresponding SRP characteristics. The curves were adjusted to match the on-substrate slope. ] -3 1018 SRP SIMS 1017

1016

1015

1014

1013 Dopant concentration [cm 0246810121416 Depth [µm]

Figure 5.13: Comparison of boron and carrier concentration profiles measured by SIMS and SRP respectively for an epilayer grown on a highly doped substrate.

The boron concentrations measured for substrate and epilayer agree with the corresponding carrier concentration measured by SRP. The SIMS profile reveals a sink in boron concentration confirming the SRP measurement. However, in case of SIMS the dopant density in the dip is by about 1.5 magnitudes larger and expands over a smaller region compared to SRP. This deviation from SRP may be attributed to an artefact of the SIMS measurement, where depth and concentration resolution decrease with increasing depth of measurement. The deeper the sputter crater, the larger is the influence of additional signals coming from the borders of the crater. This effect is pronounced in cases where the boron concentration decreases with increasing depth. In Figure 5.13 the boron concentration measured in the dip may be influenced by the top layer where the boron content is much larger. In contrast to the intrinsic layers, the decrease in carrier density observed in SRP measurements can now be definitely related to a lack in boron concentration. The transition from the dip to the region of constant doping density can be separated in a steep increase followed by a more gradual rise in carrier concentration. Compared to this, the dip appeared to be more or less symmetric for the intrinsic case. Considering the carrier density profile under the aspect of dopant concentration in the gas phase, the steep rise reflects a sudden change in diborane concentration while the gradual slope marks a slow establishment of the final state of quasi- equilibrium. Figure 5.14 shows an extract of the gas system, in particular the course of diborane, trichlorosilane and hydrogen gas lines. Starting from the valve, the diborane gas line crosses the hydrogen line after a length of 85 mm. This gas mixture combines with the trichlorosilane gas line after another 190 mm length. The length of the TCS gas line from valve to nodal point comes up to only 25 mm. Since the hydrogen gas flow is typically by a factor 100 larger compared to the diborane gas flow, the velocity 78 5 Doping of epitaxial silicon layers of the diborane/hydrogen mixture is determined by the hydrogen gas flow. Assuming a simultaneous operation of diborane and TCS valve the time for the diborane to reach the nodal point can be calculated from the volume of the diborane gas line, which is approximately 1.1 cm3, and the diborane gas flow rate.

B2H6 B2H6 mixes with SiHCl3 (nodal point)

valve SiHCl3 85mm 25mm H2 reactor

190mm

Figure 5.14: Extract of the RTCVD100 gas system featuring the connection of the process gas lines.

In Table 5.1 the calculated delay times for different diborane gas flow rates are listed. The delay refers to the difference in time between the arrival of TCS and diborane at the nodal point. The larger the diborane gas flow the shorter is the delay. By the time the diborane reaches the reactor, the silicon deposition process has already started. With respect to the two epitaxy processes, the thickness of the epilayer which can grow until the diborane reaches the reactor is also calculated (dA, dB).

B2H6 tdelay dA dB [sccm/min] [sec] [µm] [µm] 1645.99.6 2322.94.8 5131.21.9 10 6 0.6 0.96 50 1 0.13 0.19

Table 5.1: Diborane delay times and corresponding layer thickness for different diborane flow rates. Growth rates of 5.5 µm and 9 µm have been assumed for process A and B respectively.

The epilayer between the substrate surface and the minimum of the dip corresponds to the intrinsic film which can grow during the delay time. The width of this region decreases linearly with increasing diborane concentration or increasing silicon growth rate (Figure 5.12). The calculated delay times and the corresponding layer thickness show the same characteristic and a correlation between both features is obvious. To verify the effect of the gas system on the carrier density profile in epilayers, experiments were carried out where the operation point of the diborane valve was adjusted to enable a simultaneous 5.3 Experimental carrier concentration profiles 79 arrival of trichlorosilane and diborane at the nodal point. This synchronization was achieved by an in time manual operation of the diborane gas valve. Figure 5.15 shows a comparison between carrier concentration profiles measured for standard epilayers (process B) with a delayed introduction of diborane gas and for epilayers where the delay was compensated by an in time operation of the diborane gas valve.

1019 1019 B H =2 sccm 18 2 6 18 10 B H delayed 10 2 6

] B H delay eliminated ] 17 2 6 17 -3 10 -3 10 1016 1016 1015 1015 1014 1014

13 13 B H =5 sccm 10 10 2 6 B H delayed 12 12 2 6 B H delay eliminated Carrier Density [cm 10 Carrier Density [cm 10 2 6 1011 1011 5 1015202530 5 1015202530 Depth [µm] Depth [µm]

Figure 5.15: Carrier concentration profiles for epilayers grown with (delayed) and without (delay eliminated) a delayed injection of diborane relative to trichlorosilane (SRP). Two different diborane concentrations are considered.

As a result of the earlier operation of the diborane gas valve, the steep slope from sink to constant epilayer doping level has disappeared, verifying the impact of the gas system on the doping profiles. The gradual rise of the carrier concentration remains almost unchanged indicating that an additional effect must be present. The experiments described in this section prove that the dip in carrier concentration can be partly traced back to a delayed injection of diborane relative to trichlorosilane in case of intentionally doped epilayers. For the construction of future CVD reactors, a change of the gas system is necessary to prevent delay times between different process gases. Similar to the intrinsic case, the transition region still features a depression in carrier concentration and a very gradual approach of the constant epilayer doping level, even if the delay time of diborane is compensated. A slow establishment of constant gas phase composition and deposition process, an incomplete prebake procedure or water vapor present in the atmosphere may be responsible for this phenomenon.

Surface-near peak In Figure 5.16 the surface-near carrier density profiles for process A are depicted for three different diborane gas flow rates. The characteristics show that the width and the height of the surface-near peak depends on the diborane gas flow rate: the larger the gas flow, the higher the maximum carrier density and the wider the peak. The same features are observed for process B. The presence of a peak in doping concentration at the epilayer surface is assumed to be a result of the delayed operation of the diborane valve, combined with a long residence time of the diborane in the 80 5 Doping of epitaxial silicon layers reaction volume or in the gas system. The moment the TCS valve is closed, diborane is still injected into the reactor at full flow rate while the TCS gas flow quickly diminishes. The prevailing high temperature and the following anneal at 1200°C facilitates a diffusion of residual boron into the grown epilayer.

1020

Process A 19 B H [sccm] 2 6

] 10

-3 2 5 10 1018

1017

1016 Carrier Density [cm Density Carrier

1015 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Depth [µm]

Figure 5.16: Surface-near carrier concentration profiles for different diborane gas flow rates.

5.3.5 Deposition with pre-epitaxial diffusion The standard epitaxy process (type B) was modified in terms of an additional vapor-phase diffusion of boron prior to the beginning of the growth process. For this aim, the diborane gas valve was manually opened 60 sec in advance of the TCS valve. While the diborane gas flow was fixed to 10 sccm for the growth of the epilayer, it was varied between 10-50 sccm for the pre-epitaxial diffusion step. The corresponding carrier concentration profiles are depicted in Figure 5.17.

19 10 Pre-diffusion B H [sccm] 2 6

] 10

-3 25 50 1018

1017 Carrier Density [cm Carrier Density epitaxy substrate

20 21 22 23 24 25 Depth [µm]

Figure 5.17: Carrier concentration profiles for epilayers with pre-epitaxial diffusion of boron (SRP). The pre-diffusion was carried out for 60 sec with variable diborane gas flow rate. 5.3 Experimental carrier concentration profiles 81

The implementation of a boron diffusion step resulted in the formation of a peak between the regions of constant doping level. The width and the height of the peak increases with increasing diborane gas flow. The transition from the peak to the substrate side of the profile features a slow decrease in carrier concentration while the transient from peak to epilayer is much steeper. The observed characteristic can be explained as follows: prior to the onset of the deposition, the reaction volume is flooded with diborane and according to section 5.3.1 a diffusion of boron atoms from the gas phase into the bulk of the sample can occur. The gradual rise from substrate to peak reflects this process. The width and the height of the peak depend on the diborane gas flow rate applied during the diffusion step: the greater the dopant gas flow the larger is the amount of boron species adsorbed on the sample surface and the more boron can diffuse into the bulk. The opening of the TCS valve and the simultaneous change in diborane gas flow determine the beginning of the deposition step and the abrupt decrease in carrier concentration reflects the associated change in gas composition. Solid-state out diffusion and the establishment of a steady state in the gas phase determine the transient from diffusion peak to constant epilayer doping. The transient is about 1.5 µm wide, indicating a fast generation of a steady state in the changed gas phase and a negligible autodoping effect. The situation discussed here is similar to the experiment carried out to determine the memory effect (section 5.3.2). The difference between the two experiments lies in the different boron sources and the different dopant concentrations in the gas atmosphere at the onset of the deposition process. For the autodoping-experiment the boron content in the vapor-phase resulted only from an evaporation of the surrounding system. Now, the atmosphere was intentionally over-saturated by the introduction of diborane. In both cases, a diffusion of boron into the bulk of the sample takes place.

5.3.6 High-low deposition In contrast to the standard deposition process a so-called high-low process consists of two subsequent growth steps differing in dopant gas flow rate. This deposition process is especially attractive if a p/p+- junction with low interface recombination velocity is to be accomplished. The direct deposition of a p- doped layer on a low resistivity substrate is known to enhance the formation of crystal defects due to the lattice mismatch between the two regions. With the application of a high-low process, the electrical interface can be separated from the crystallographic interface of epilayer and substrate and the recombination velocity at the junction may therefore be reduced. For epitaxial thin-film solar cells on highly doped substrates, low surface recombination velocities are essential and therefore high-low CVD processes are often used for the deposition of the base layer. Within the solar cell structure the heavily doped region acts as back surface field (BSF). This nomination will also be used in the following paragraph to denote the highly doped epilayer grown during the first deposition step. Experiments were carried out with the duration of the BSF deposition being varied between 5-20 sec and the diborane gas flow held constant at the maximum value of 50 sccm. According to the cell structure of epitaxial silicon thin-film solar cells, only highly-doped substrates have been used. The resulting carrier concentration profiles are presented in Figure 5.18. The characteristics in Figure 5.18 show, that an increase of the BSF deposition time from 5 to 20 sec results in the development of a separate on-substrate shoulder with its width and height increasing 82 5 Doping of epitaxial silicon layers with deposition time. The gradient of the on-substrate slope decreases with increasing BSF-time. For the 5 sec BSF the deposition time was too short for a full development of the shoulder. Instead, the transient between substrate and epilayer is smooth.

1019 BSF-time [sec] 5 10 ]

-3 20

1018

1017 Carrier [cm Density epitaxy substrate

18 19 20 21 22 23 24 Depth [µm]

Figure 5.18: Carrier concentration profiles measured for epilayers deposited by a high-low process (SRP). The diborane gas flow for BSF was fixed to 50 sccm.

The presence of a dip between substrate and peak indicates that a lowly doped epilayer must have been grown prior to the actual BSF-deposition. This cannot be explained by the retarded introduction of diborane, since the calculated delay time for a gas flow of 50 sccm comes up to 1 sec and assuming a growth rate of 9 µm/min this corresponds to an epilayer thickness of only 0.15 µm. Compared to this value, the distance between minimum carrier concentration and substrate/epilayer interface is determined to approximately 1 µm (~7 sec growth time) from experimental profiles. In previous sections, possible mechanisms for the generation of a thin, high resistivity epilayer at the interface between substrate and epilayer have already been discussed. These mechanisms also apply in this case. The maximum doping density of the BSF layer is determined by the limited diborane gas flow rate which can be applied. With the application of epitaxy process B the doping density is therefore restricted to values below 6x1017 cm-3. In future systems, an increase of the tunable dopant gas flow range is necessary to enable the deposition of silicon layers with doping concentrations exceeding 1019 cm-3. This feature would allow the controlled generation of high-low junctions at high deposition rates, with even larger doping gradients and improved BSF effect. In the RTCVD160 this demand is already realized and maximum diborane gas flow rates of 1000 sccm can be used.

5.4 Effect of doping profile on solar cell performance To evaluate the effect of different doping profiles on solar cell performance, device simulation was carried out using PC1D [126]. Two cases were compared: (1) Steep, step-like transition of doping density between substrate and epilayer (ideal case) and (2) Dip between substrate and epilayer. The minority carrier lifetime in the dip was assumed to be identical to the constant base region. The shape of the dip was modeled by a fixed total width of 4 µm, while the minimum doping density in the 5.4 Effect of doping profile on solar cell performance 83 dip was varied. In Figure 5.19 (top, left) the doping density profiles used for the simulations are given. Dip 1 represents a situation, where the depth of the sink is only about one order of magnitude below the constant base doping level. A significant decrease in doping density is assumed for dip 2. For comparison the ideal case of a sharp transition was added. The doping density in base layer and substrate were set to 5x1016 cm-3 and 4x1018 cm-3 respectively. The substrate was assumed to be 600 µm thick with a minority carrier diffusion length of 3 µm. The interface recombination velocity between substrate and epilayer was fixed to zero. These settings were adjusted to match experimental values. For a detailed description of the simulated solar cell model see section 6.2.8. Simulations were carried out with varying base lifetime and thickness. Considering a sharp transition in doping concentration, a strong electric field builds up at the interface between substrate and base which repels the minority carriers coming from the base (BSF-effect). The inverse effect occurs if a dip is located between substrate and base: due to the low doping level in the dip, minority carriers in the base are accelerated towards the dip region where they get “trapped”.

1019 Sharp transition 1.0 Efficiency [%] 1018

] 8.000

-3 8.0 - 9.0 9.000 17 0.5 9.0 - 10.0 10 10.00 10.0 - 11.0 11.00 16 11.0 - 12.0 10 12.00

) [µs] 0.0 12.0 - 13.0 13.00 13.0 - 14.0 15 base 14.00 10 τ

log( -0.5 1014 Sharp transition Doping density [cm Dip 1 Dip 2 13 10 -1.0 24 25 26 27 28 29 30 31 10 20 30 40 50 60 Depth [µm] Base thickness [µm]

Dip 1 Dip 2 1.0 1.0 Efficiency [%] 8.0 8.0 - 9.0 9.0 0.5 0.5 9.0 - 10.0 10.0 10.0 - 11.0 11.0 11.0 - 12.0 12.0

) [µs] ) [µs] 12.0 - 13.0 0.0 0.0 13.0 13.0 - 14.0 base base 14.0 τ τ

log( -0.5 log( -0.5

-1.0 -1.0 10 20 30 40 50 60 10 20 30 40 50 60 Base thickness [µm] Base thickness [µm]

Figure 5.19: Top, left: Doping concentration profiles for simulated solar cells with sharp transition and dip between substrate and epilayer. 3D-diagrams: Corresponding electrical efficiency as a function of base thickness and minority carrier lifetime for different doping concentration profiles.

Figure 5.19 (top, right) shows the efficiency diagram obtained for a step-like transient in doping density. For minority carrier lifetimes below 1 µs (corresponding to a minority carrier diffusion length 84 5 Doping of epitaxial silicon layers of 46 µm) the performance of the solar cell is almost independent on the base thickness. In this case, the efficiency is limited by the quality of the base layer. For larger carrier lifetimes, the efficiency increases with base thickness: carriers generated at the back of the cell can reach the pn-junction and contribute to the photocurrent. Comparing the efficiency diagram for the sharp transition and the shallow dip 1, the existence of the dip results only in minor changes in efficiency for minority carrier lifetimes below 1 µs independent from base thickness. For greater lifetimes the minimum thickness to reach a certain efficiency shifts towards larger values i.e. thicker layers are necessary to obtain similar efficiencies. Increasing the depth of the dip (dip 2) leads to a further shift of efficiency boundaries towards thicker base thickness and also toward greater lifetimes. The dependence of efficiency on base thickness for low carrier lifetimes indicates an increased effect of the electrical attraction imposed by the sink on generated minority carriers.

5.5 Improved gas system design Within the course of the experiments carried out on the issue of doping profiles in epitaxial layers, two shortcomings of the gas system as implemented in the RTCVD100 have been revealed:

• A simultaneous operation of diborane and TCS valve results in a temporal delayed injection of diborane and TCS into the reaction chamber.

• After closing the diborane valve, the corresponding gas line is still filled with dopant gas which slowly diffuses into the main gas stream. To avoid the associated effects on carrier density profiles (e.g. dip and surface peak) the gas system has to be changed. The schematic in Figure 5.20 shows an outline of a future gas system.

other B2H6 SiHCl3 H2i N2i

H2, N2 purge aa aM c b bb d reactor P valve three-way valve exhaust

Figure 5.20: Schematic of improved gas system design.

The length of the gas lines denoted by small letter a, b, c and d have to be as short as possible to reduce the dead storage capacity. Compared to the existing gas system, the improved design allows a common gas stabilization of the diborane (or any other dopant) and TCS mixture into the exhaust line. At the beginning of the deposition process the three-way valve M is operated and the homogeneous gas mixture is introduced 5.6 Summary 85 into the reactor. Similarly a closing of the three-way valve, entirely cuts off the reactor from the process gas supply. A delayed or supplementary injection of any process gas can therefore be avoided. A multilayer growth of epilayers of different doping types and sharp transitions can only be realized if a hydrogen purge of the process gas lines is included in between separate deposition steps. Considering e.g. the subsequent growth of a p- and n-type layer, where the gas line denoted by “other” in Figure 5.20 is fed by the dopant gas PH3: a subsequent closing and opening of the diborane and phosphine valve respectively results in a delayed injection of an unstabilized phosphine gas flow into the reactor. In addition, a supplementary diffusion of residual diborane occurs from the dead storage between diborane valve and main gas line into the process gas stream. Both effects counteract the growth of epilayers with sharp transients. A solution to this problem is the separate deposition of layers of different doping-types. After each deposition step, all process gas valves are closed, the three-way valve M is opened to the exhaust and the process gas line is purged by hydrogen. As soon as the gas lines are cleared from any residuals, the corresponding process gas valves are opened and the new process gas mixture is stabilized into the exhaust before it is injected into the reaction chamber. During the gas-line purge and the gas stabilization the reactor is purged with hydrogen. This hydrogen purge step can only be avoided if a more complex gas system is used, where each dopant gas can be mixed with TCS in a separate gas line.

5.6 Summary Under the prevailing conditions for epitaxial deposition in the RTCVD100, the incorporated carrier concentration of intentionally doped epilayers was observed to depend only on the diborane concentration in the initial gas mixture.

Intrinsic epilayers feature a p-type conductivity with a resistivity in the range of 100 Ωcm confirming a high level of purity of the entire system. Background doping and memory effect were found to be uncritical for the deposition of epilayers for thin-film solar cells. During high-temperature hydrogen anneal, a diffusion of boron from the gas phase into the bulk of silicon samples or vice-versa occurs, depending on the resistivity of the sample. The intentional injection of B2H6 during hydrogen anneal results in an enhanced diffusion of boron into the bulk of the samples. The design of the gas system in the RTCVD100 causes a delayed injection of diborane into the reactor, relative to trichlorosilane. As a consequence, the resulting carrier density profiles of intentionally doped layers feature a dip in doping concentration near the substrate/epilayer interface, with depth and width of the dip depending on silicon growth velocity and the diborane gas flow rate. The compensation of the diborane delay by an in time manual operation of the diborane gas valve results in carrier density profiles which still feature a shallow depression near the interface. A similar characteristic is observed for intrinsic layers. At present, the origin for the formation of a high resistivity silicon layer during the initial stages of layer growth is unclear. A variation of prebake conditions should be carried out, to exclude the possibility of an incomplete prebake process and the associated presence of residual oxide on the sample surface. Solar cell simulations have been carried out to evaluate the effect of a dip in doping concentration between substrate and epilayer, according to the experimental findings. The results show that a 86 5 Doping of epitaxial silicon layers decrease in carrier concentration between substrate and base is to be avoided if high efficiencies are to be attained. Consequently, either a high-low deposition process should be used or a deposition with pre-diffusion should be applied. Finally, an improved gas system design is outlined where all process gases can be homogeneously mixed before they are introduced into the reaction chamber. The delayed injection of any process gas is avoided and dead storage capacities are reduced. 6 Epitaxial thin-film solar cells

The term “epitaxial solar cell” refers to a solar cell structure where the active silicon base layer is deposited onto a silicon substrate by epitaxy. The characteristic feature of epitaxial silicon thin-film solar cells is the electrical inactivity of the substrate and the reduced thickness of the base layer which is typically below 50 µm. Using inexpensive substrates and silicon deposition techniques, this material represents a potential low-cost wafer equivalent which can be directly introduced into standard industrial solar cell production lines.

In this chapter the application of screen printing technologies on epitaxial material is investigated in detail using epilayers grown on low-resistivity Cz- Si wafers as ideal model system. Subsequently the industrial type solar cell process is transferred to epilayers on mc-Si and single-crystal reclaim substrate wafers. The chapter closes with a preview on future applications of RTCVD in the area of emitter and BSF formation.

6.1 Solar cell concept Compared to other silicon thin-film solar cell concepts the epitaxial solar cell plays an outstanding role because of its simplicity and the possibility to introduce it directly into industrial production. Figure 6.1 illustrates the typical design and solar cell process sequence of an epitaxial thin-film solar cell.

Silicon substrate PECVD SiNx deposition emitter contact grid

Saw damage removal / ARC Screen printing of contacts cleaning

Epitaxy of base layer Rapid thermal firing

Homogeneous emitter Edge isolation epitaxial base (p) n+ diffusion

p+ silicon substrate PSG removal

base contact

Figure 6.1: Left: Schematic of epitaxial thin-film solar cell structure. Right: Solar cell process sequence for epitaxial solar cells.

In general, the solar cell material consists of a low-cost silicon substrate and a thin base layer (<50 µm) epitaxially grown on top. The substrate wafers typically feature high doping levels or / and

87 88 6 Epitaxial thin-film solar cells high defect densities, making them electrically inactive. The possibility to use silicon as substrate is of great advantage compared to other silicon thin-film approaches: matching of thermal expansion coefficient and high-temperature stability do not present a problem and the expertise from already existing silicon technologies can be applied. Compared to conventional silicon wafers, the active device region is drastically reduced and lower quality material can be employed (see chapter 2). Using a highly doped silicon substrate, the solar cell performance benefits from the BSF effect of the high-low junction at the interface between active base layer and silicon substrate. On the other hand, the disadvantages of the reduced base layer thickness and the thick highly doped substrate are obvious: the generation of electron-hole pairs contributing to photocurrent is restricted to the thin active base layer since electron-hole pairs generated in the substrate recombine very fast and are therefore lost. The implementation of optical confinement features is essential to increase the short-circuit current. The solar cell process sequence in Figure 6.1 (right) points out that compared to conventional solar cell processing only one additional step is needed for the preparation of epitaxial solar cells: the epitaxy of the base layer. For a large scale production of epitaxial solar cells, the existing production lines can be directly addressed, making this concept a very attractive cost-saving alternative to conventional silicon wafer solar cells. For a successful industrial manufacturing of the epitaxial silicon thin-film solar cell concept the following criteria have to be accomplished: the processing of epitaxial material by conventional industrial techniques has to be proved to be straightforward and the aspect of cost-saving has to be fulfilled. The successful application of screen printing technologies on epitaxial material has already been demonstrated for epitaxial layers deposited in a commercial system on various kinds of substrates [104]. The issue of cost-saving is affected by the cost for the silicon substrate, the epitaxial deposition as well as the solar cell efficiency. These three aspects and their effect on solar cell structure or processing will be discussed in the following sections.

6.1.1 Silicon substrate materials Compared to conventional silicon wafer solar cells the concept of silicon thin-film solar cells can tolerate base layers of minor quality. The restrictions imposed on crystal perfection and contamination level in the base are less severe. This conclusion similarly holds for the substrate material making the application of low quality silicon as a starting material for silicon substrates possible. The cost for commercial silicon wafers is basically determined by the starting material, which is the silicon powder, and the manufacturing cost, especially the slicing step. The production of Cz-Si or FZ- Si rods requires the use of high purity silicon. During wafering a substantial part of the high-quality material is lost by kerf loss. Both aspects, high purity silicon powder and kerf loss contribute to the high cost for this type of silicon material. Consequently, the cost of either one or both steps has to be reduced for a competitive alternative material. The cost for silicon powder depends on the degree of contamination: the higher the impurity level in the powder, the lower the price. Metallurgical grade (MG) or upgraded metallurgical grade (UMG) silicon therefore represents a cost-saving option to electronic grade material at the expense of high contamination levels. UMG-Si is gained from MG-Si by a low-cost cleaning step. Common impurities in UMG-Si are C, O, Ti, Al, Ca and large amounts of Fe and B thus making the material unsuitable for 6.1 Solar cell concept 89 conventional solar cell production. Because of the large impurity concentration and / or defect density in MG and UMG silicon wafers, these substrates are in general electrically inactive. The expensive slicing of the wafers can be replaced either by new slicing techniques resulting in thinner wafers and less kerf loss or by ribbon technologies where thin silicon sheets are directly produced thus saving the slicing step. Edge Defined Film-Fed Growth (EFG) [105], String Ribbon [106], Dendritic Web [108], Ribbon Growth on Substrates (RGS) [109] and Silicon Sheets from Powder (SSP) [110] are the most prominent ribbon technologies to be mentioned. A large variety of different silicon materials has already been tested as substrate for epitaxial thin-film solar cells. In [111] epilayers were grown on highly doped RGS ribbons leading to a maximum efficiency of 10.4% for a 30 µm base layer. The solar cell process included tube furnace diffusion of the emitter, evaporated contacts, hydrogen passivation and the deposition of a double layer antireflection coating. For epitaxial solar cells on SSP a maximum efficiency of 8% has been achieved [112]. SSP is characterized by a low average grain size of 60 µm which basically limits the solar cell performance. In recent years, many R&D projects focused on the application of silicon substrates from cast MG or UMG multicrystalline ingots. Compared to ribbon technologies, this concept benefits from the expertise from industrial production. At the University of Konstanz epilayers were grown by LPE on UMG mc-Si substrates. Using screen printing technologies a maximum efficiency of 10% was obtained for a 30 µm thick epilayer [113]. CVD-epilayers grown on grooved MG mc-Si substrates were reported to reach efficiencies of up to 12% for a 100x100 mm² solar cell with screen printed contacts [104].

6.1.2 Efficiency The potential of crystalline silicon thin-film solar cell in terms of high efficiencies has already been discussed in chapter 2. The efficiency of epitaxial solar cells depends on various parameters. Material properties, thickness, doping level and minority carrier lifetime of the base, as well as interface recombination velocity and contributions coming from the substrate determine the solar cell parameters. Thickness and doping of the deposited base layer have to be tailored to the substrate material to maximize the solar cell efficiency. In section 6.2.8 the influence of these parameters on the overall solar cell performance is investigated by device simulation. Effective light trapping is a basic requirement for crystalline silicon thin-film solar cells to reach high short-circuit currents. For epitaxial thin-film cells the application of a reflective porous silicon intermediate layer represents a promising option to enhance the optical confinement [114]. An increase in photocurrent can also be obtained by texturing the front surface of the cell thus reducing the front-surface reflection and increasing the optical path length in the base. Surface texturing can be applied after the deposition of the epilayer e.g. by an isotropic etching of random pyramids or before epitaxy e.g. by mechanical V-grooving. The rough surface obtained by texturing imposes high challenges on solar cell processing technology. Because of the increased surface area excellent surface passivation is necessary and the emitter formation and front metallization must meet the demands imposed by the structured surface. 90 6 Epitaxial thin-film solar cells

6.1.3 Epitaxial deposition systems In microelectronic industry batch type or single-wafer CVD epi-reactors with low wafer size capacity are commonly used. These reactors typically operate with large gas flow rates but low chemical yield and therefore gas consumption makes up for a substantial part of the final high cost for silicon deposition. Assuming a solar cell production capacity of 50 MWp per year and an electric solar cell efficiency of 15%, a throughput of 28 m²/h is necessary (no losses in yield). The batch-type CVD reactors used for microelectronic applications are not capable to meet the required demands on cost- effectiveness and throughput imposed by solar cell production. Alternative solutions for silicon deposition have to be found and therefore, the development of high throughput epitaxy systems is a current issue in R&D of silicon thin-film solar cells. At the University of Konstanz an up-scaled batch-type LPE system with a potential wafer capacity of 0.54 m² per run is currently developed [115]. The LPE process makes use of a melt back step before silicon deposition thus supplying the melt with silicon material and in principle, no additional silicon has to be added. Assuming a process time of 8 h per run for a 30 µm thick layer, a maximum throughput of 0.07 m²/h can be reached. Industrial feasibility is expected to be achievable by a further enlargement and multiplication of the deposition system. In [39] an up-scaled batch-type LPCVD system is proposed for industrial-scale silicon deposition at low cost. The presented deposition reactor has a capacity of 20 wafers of 100x100 mm² and deposition rates between 0.1 and 0.5 µm/min are reported. Epitaxial layers grown in this reactor proved to be of excellent quality. An early development of an open-tube continuous silicon deposition reactor is described in [60], where 200 µm thick polycrystalline silicon films were grown and subsequently used as solar cell material. The deposition process was based on high-temperature CVD from trichlorosilane in a hot- wall reactor and the successful operation of this system demonstrated the technical feasibility of a continuous silicon deposition reactor. At Fraunhofer ISE a continuous APCVD system has recently been developed where samples of up to 200 mm in width can be processed (see section 3.4.4). Assuming a realistic epitaxial deposition rate of 5 µm/min a throughput of 1.4 m²/h can be reached for a 30 µm thick epilayer with the option of further up-scaling. This high throughput CVD apparatus represents a good basis for the development of a proto-type CVD reactor for industrial scale production.

6.1.4 Efficiency table for epitaxial thin-film solar cells In Table 6.1 the most important results achieved in the area of epitaxial thin-film solar cells are summarized. The solar cell approach has been tested on different silicon substrate materials using mainly CVD and LPE growth techniques. High-efficiency processes as well as industrial screen printing technologies have been applied for solar cell preparation. Solar cells prepared on epilayers on high-resistivity p-type substrates or with supplementary thinned substrates were not taken into consideration. In general, depositions denoted by APCVD were carried out in a commercial CVD system used for microelectronic production. In contrast, LPE and RTCVD100 (the reactor discussed herein) represent lab-type systems. One major goal of this work was to verify that epilayers grown in the lab-type RTCVD100 on different silicon substrates can be processed by industrial type technologies and yield 6.2 Solar cells on Cz-Si substrates 91 similar efficiencies than solar cells prepared on epilayers grown in a commercial system. Together with the possibility for an up-scaling of the reactor-principle (as already done by the RTCVD160 and the continuous APCVD - see chapter 3), the RTCVD100 might be regarded as an embryo for future silicon deposition systems in crystalline silicon thin-film solar cell production.

Substrate Deposition Epilayer Area Solar cell process Efficiency Ref. [µm] [cm²] [%] Single-crystal silicon substrates p+ sc-Si RTCVD100 37 4 High-efficiency 17.6 [40] p+ sc-Si LPE 32 4 Microgrooved, high- 16.4 [116] efficiency Multicrystalline silicon substrates p+ mc-Si APCVD 20 4 Evaporated Contacts 13.3 [117] Hydrogen passivation p+ mc-Si, APCVD 20 24 Screen printed contacts 13.2 [87] grooved p+ mc-Si LPE, melt-back cycles 25 4 Evaporated contacts 15.2 [89] UMG-Si substrates p+ UMG-Si APCVD 20 4 Evaporated contacts 12.8 [104] Hydrogen passivation p+ UMG-Si APCVD 20 100 Screen printed contacts 10.8 [104] p+ UMG-Si, APCVD 20 100 Screen printed contacts 12.0 [104] grooved UMG-Si LPE, Substrate melt-back 30 3 Screen printed emitter and 10.0 [113] contacts Ribbon silicon substrates p+ SSP RTCVD100 15 4 Evaporated Contacts 8.0 [112] p+ RGS APCVD 30 4 Evaporated Contacts 10.4 [111] Hydrogen passivation

Table 6.1: Thin-film epitaxial solar cells on different highly doped silicon substrates.

6.2 Solar cells on Cz-Si substrates In this work, epitaxial silicon thin-film solar cells were prepared on Cz-Si substrates to test the application of industrial screen printing technologies on epitaxial material and to verify the quality of epilayers grown in the RTCVD100. Epitaxy was carried out in the RTCVD100, where two process types featuring different growth rates were used. For solar cell processing, conventional cleanroom and industrial techniques for emitter and contact formation were applied in various combinations. Therefore, possible interactions between the epitaxial material and different solar cell process steps could be separated. 92 6 Epitaxial thin-film solar cells

6.2.1 Solar cell processing Highly doped <100>-oriented Cz-Si wafers with a nominal specific resistivity ≤ 0.02 Ωcm were used as substrate material. Prior to epitaxy the samples were wet-chemically treated by a CP-133 damage- etch and a subsequent RCA cleaning with the last HF-dip omitted. The epitaxial depositions were carried out in the RTCVD100 using two different CVD-deposition processes, A and B. In the following, process A determines a process with medium growth rates of 5-6 µm/min, whereas process B is defined by large growth rates of 9-10 µm/min. The almost doubled growth rate for process B compared to process A represents an attractive option for industrial production, where high throughput is requested. Both processes were already discussed in detail in chapter 4. Epitaxial layers of 30 µm thickness and with a doping density of 5x1016 cm-3 were deposited. The thickness of the layers was determined by weighing the samples before and after deposition, and calculating the average thickness. Before solar cell preparation the highly doped surface layer, which is a consequence of the deposition process in the RTCVD100, was removed thus reducing the effective base layer thickness to approximately 26 µm. In Figure 6.2 the standard process sequence used for the preparation of epitaxial material is summed up.

Removal of ~5 µm Solar cell CP-133 damage etch RCA cleaning Epitaxy from the surface process

Figure 6.2: Standard process sequence for the preparation of epitaxial solar cells.

Apart from the epi-samples two different types of reference material were included in the solar cell batches. First, Cz-Si or FZ-Si wafers were used to enable a control of the solar cell process. Second, epilayers on highly doped, polished Cz-Si substrates deposited in a commercial system were added as an ideal epi-reference. In contrast to the samples grown in the RTCVD100, these epilayers were 40 µm thick with a doping level of 4x1016 cm-3, as measured by SRP. The specific resistivity of the substrate was determined to 0.015 Ωcm. Before solar cell processing, both reference types were subjected to the same cleaning procedure as the epi-samples. Five different solar cell processing routes were tested. In Table 6.2 an overview is given on the realized solar cell structures. Process 1 represents the standard cleanroom process typically used at

Fraunhofer ISE for silicon solar cells. The emitter is homogeneously diffused from a POCl3 source in a conventional tube furnace with a final sheet resistance of 80 Ω/sq. Photolithography was employed for the definition of the front contact grid and metallization was done by evaporation of TiPdAg and additional electro-plating. For base contact formation, aluminum was evaporated on the backside of the cell. Finally a double layer antireflection coating (DLARC) of TiO2/MgF2 was deposited onto the front surface of the solar cell. In contrast to this cleanroom process only screen printing techniques were employed in process 5. The standard screen printing process at Fraunhofer ISE consists of the following steps [118]: screen printing of phosphorus dopant and in-line diffusion of the emitter in a conveyor belt furnace with a final sheet resistance of 40 Ω/sq, deposition of an antireflection passivating PECVD-SiNx layer, rear and front contact formation by screen printing using aluminum and silver paste respectively and Rapid

Thermal Firing (RTF) of the contacts through the SiNx-layer. 6.2 Solar cells on Cz-Si substrates 93

Emitter Metallization

POCl3-source Screen printed dopant Lithography Screen printing

Process no. Tube furnace In-line diffusion Evaporation RTF through SiNx 1 80 Ω/sq X 2 40 Ω/sq X

3 40 Ω/sq a: with SiNx

b: without SiNx 4 40 Ω/sq X

5 40 Ω/sq a: with SiNx

b: without SiNx

Table 6.2: Different combinations of cleanroom and industrial screen printing technologies realized on epitaxial material in five solar cell batches.

The remaining solar cell process routes 2, 3 and 4 represent different combinations of emitter formation technique and metallization from cleanroom and screen printing technologies. Comparing process 2 and 3 information can be obtained about the impact of contact formation by screen printing and evaporation respectively on samples with POCl3 diffused emitters. A similar comparison can also be done for process 4 and 5 where both metallization techniques are applied to a standard screen printed and in-line diffused emitter. On the other hand, the effect of emitter formation technique on the solar cell characteristics of samples with evaporated contacts can be studied using the results from process 2 and 4. Combining process 3 and 5 a similar investigation can be carried out with respect to a screen printed metallization. In addition, the influence of firing through SiNx can be evaluated comparing solar cells processed via route 3 and 5 with and without silicon nitride deposition. Process 3 and 5 represent industrially relevant processing routes and are therefore of major interest while process 1 was included to allow for a monitoring of the epilayer quality. Summing up, the extensive experimental setup allows the detection of any effect on solar cell performance induced by screen printing technologies.

6.2.2 RTCVD-process A vs. B In this section the influence of epilayer deposition process on solar cell performance is investigated. Comparing the solar cell parameters for both epilayer types A and B within one process route can give information about possible differences in epilayer quality. Instead of analyzing all process routes only process 1 is considered exemplarily. In Table 6.3 the calculated mean values for the illuminated I/V characteristics of 4 solar cells per process type are summarized. The results show that process A yields an overall better solar cell performance. For both epitaxy process types, the relative standard deviations differ only on a small scale indicating a comparable reproducibility. While the mean values for the open-circuit voltage are similar for both CVD processes, solar cells on epilayers of type B feature a slightly lower short-circuit current density and fill factor. However, in both cases the differences are still within the range of standard deviation. The reduced fill factor for 94 6 Epitaxial thin-film solar cells process B may be explained by additional defects which might be introduced during the deposition as a result of the fast growth mode. In Figure 6.3 the internal quantum efficiency of two solar cells prepared by CVD-process A and B are compared. Apart from a small difference in the long wavelength range the characteristics are identical. The solar cell with type B epilayer shows a slightly reduced red response indicating a thinner base region.

Process VOC JSC FF Efficiency [mV] [mA/cm²] [%] [%] RTCVD100 (A) 627 ± 6 28.6 ± 0.4 78.5 ± 1.1 14.0 ± 0.2 RTCVD100 (B) 626 ± 5 28.2 ± 0.2 75.9 ± 2.4 13.4 ± 0.5

Table 6.3: Comparison of epitaxy process A and B in terms of illuminated I/V parameters for solar cell process 1.

1.0

0.8

0.6

IQE 0.4 Epitaxy process 0.2 A B

0.0 400 600 800 1000 1200 λ [nm]

Figure 6.3: Comparison of internal quantum efficiency for solar cells with type A and B epilayer.

In conclusion, it can be stated that solar cells prepared on epilayers of type A show a slightly better solar cell performance compared to epilayers of type B. The large growth velocity of 10 µm/min is thought to introduce additional defects leading to an increase in saturation current density and the formation of shunts, thus reducing the fill factor. For solar cell process 2 to 5 a similar behavior is observed, verifying that the differences are indeed related to material properties. Using process B the throughput of the silicon deposition system can be almost doubled with a loss in solar cell efficiency below 1% absolute, compared to process A. This characteristic makes the fast growth mode an interesting choice for large scale production. Unless otherwise stated the following investigations were carried out for solar cells with type A epilayers. 6.2 Solar cells on Cz-Si substrates 95

6.2.3 Epilayer quality The electrical quality of epilayers deposited by process A is evaluated comparing solar cell parameters and spectral response to the results gained for FZ-Si and commercial epitaxial reference cells. Again, only solar cells prepared by the standard cleanroom process 1 are considered. In Table 6.4 the calculated mean values for the illuminated characteristics are given. Comparing the solar cell parameters with respect to the epitaxy process, similar values for open-circuit voltage and fill factor are observed. The main difference lies in the short-circuit current density, which is 1.9 mA/cm² larger in case of commercial epilayers, possibly due to the greater thickness of the base layer.

The solar cells on FZ-Si wafers resulted in slightly larger VOC and substantially greater JSC compared to the epi-cells, the latter reflecting the increased thickness of the active device region. The mean values for the fill factor are in the same range.

Process dbase VOC JSC FF Efficiency [µm] [mV] [mA/cm²] [%] [%] FZ-Si Ref. 633 ± 2 35.3 ± 1.0 78.4 ± 0.2 17.5 ± 0.6 Commercial epitaxy 35 625 ± 1 30.5 ± 0.2 78.0 ± 0.6 14.9 ± 0.2 RTCVD100 (A) 26 627 ± 6 28.6 ± 0.4 78.5 ± 1.1 14.0 ± 0.2

Table 6.4: Calculated mean values and standard deviations for illuminated I/V parameters of FZ-Si references and epi-cells. The epilayers were deposited in a commercial reactor and in the RTCVD100 using process A.

1.0

0.8

0.6

IQE 0.4 FZ-Si reference 0.2 Epitaxial reference Epitaxial cell (ISE)

0.0 400 600 800 1000 1200 λ [nm]

Figure 6.4: Comparison of internal quantum efficiency for solar cells prepared on FZ-Si and on epilayers deposited in a commercial reactor and in the RTCVD100.

The internal quantum efficiency characteristics measured for the three solar cell types are compared in Figure 6.4. In the short-wavelength range the curve for the epitaxial reference differs from the others due to a slight difference in emitter properties, related to the solar cell process. Otherwise, all three 96 6 Epitaxial thin-film solar cells curves show an almost identical characteristic up to a wavelength of 700 nm. In the long-wavelength range the decrease in spectral response is mainly correlated to the thickness and minority carrier diffusion length of the active base region. In case of the FZ-Si reference cell, the hump observed near a wavelength of 1100 nm results from internal rear surface reflection. Because of the large substrate thickness and the high doping level this hump lacks in case of the epitaxial cells. Summing up, the results show that epilayers grown in the RTCVD100 are of sufficient quality to yield high solar cell efficiencies. The implementation of an adequate optical confinement could further increase the photocurrent.

6.2.4 Comparison of solar cell technologies In the proceeding sections the high quality of the epilayers grown in the RTCVD100 has been demonstrated. Now the focus is put on a correlation between solar cell preparation technique and epitaxial solar cell performance. The influence of emitter formation and metallization technique on the epitaxial material and the associated solar cell parameters are discussed. Before comparing the process technologies in terms of solar cell characteristics, the process steps for both emitter and contact formation techniques are described in more detail to enable an understanding of possible effects.

Emitter formation

- TF emitter (Tube Furnace): emitter diffusion from a POCl3 source takes place in a closed tube

furnace under an atmosphere containing nitrogen, POCl3 and oxygen. A chemical reaction of oxygen and the phosphorus containing compounds on the heated sample surface leads to the formation of phosphorus silicate glass (PSG), serving as source for the phosphorus diffusion. The diffusion of highly doped emitters was carried out at temperatures around 875°C for 20 min. - CBF emitter (Conveyor Belt Furnace): the phosphorus containing paste “Soltech P101” was homogeneously screen printed on the front side of the wafer. After drying, in-line diffusion was carried out in an infrared heated RTC conveyor belt furnace at 925°C under oxygen atmosphere. The total process time for this step was 15 min. Both emitter formation techniques finish with a PSG-etch using hydrofluoric acid (HF).

Contact formation - EC (Evaporated Contacts): the standard cleanroom process at Fraunhofer ISE employs contact formation by photolithography and subsequent evaporation of the contact metal. For the emitter front contacts a combination of Ti/Pd/Ag and in addition electroplating is used whereas aluminum is evaporated on the rear surface. The photolithographic emitter contact grid used for these solar cells is optimized for an 80 Ω/sq emitter. The fingers and bus bar are tapered with a contact width of 10 and 20 µm in case of the fingers and 60 and 120 µm for the bus bar. After electroplating the finger width was determined to approximately 100 µm with a final height of 20 µm. The entire process ends with a sinter step at 400°C for 35 min. - SPC (Screen Printed Contacts) : the standard screen printing process starts with the deposition of

an antireflection PECVD-SiNx at 346°C for 10 min resulting in a layer thickness in the range of 55 nm. The front and rear contacts are screen printed using Ag-paste and Al-pase respectively. 6.2 Solar cells on Cz-Si substrates 97

After drying, rapid thermal firing is employed for contact formation. The RTF process includes a burn out of the organics which remained in the paste and a subsequent firing step at 780°C for few seconds. The final width and height of the front contacts were measured to 100 µm and 8 µm respectively.

85 640 80 620 75

70 [mV] 600 OC 65 FF [%] V

580 60

29 14 28 13 27 12 26 [mA/cm²]

SC 25 11 J Efficiency [%]

123a45a 1 2 3a 4 5a

Figure 6.5: Mean values of illuminated I/V parameters calculated for all process types.

The mean values for the solar cell parameters determined from illuminated characteristics were calculated for all solar cell types. Figure 6.5 gives an overview on the results. For solar cells with screen printed contacts but without SiNx layer (3b and 5b) no statistical evaluation was carried out. As expected, the standard cleanroom process 1 shows the overall best solar cell performance with an electrical efficiency of 14.8% due to an optimized emitter and contact grid. Only slightly lower mean efficiencies were achieved for solar cells with CBF emitter and screen printed contacts (4) while the efficiencies of the remaining solar cell types are all in the range of 12%. Solar cells with screen printed contacts (3a and 5a) feature lower fill factors compared to solar cells with evaporated contacts. This is a typical characteristic associated to contact formation by screen printing which results in increased contact and series resistance. From fitted dark I/V characteristics the series resistance was determined to values well above 1 Ωcm² for solar cells with screen printed contacts. The application of evaporated contacts led to constant fill factors above 78%, comparable to those determined for process 1 and independent from emitter formation technique. Considering the open-circuit voltage, the combination of CBF emitter with SPC (5a) results in a mean value comparable to process 1. The lowest VOC is observed for solar cells with TF emitter and EC (2) with a loss of -16 mV compared to process 5a. Keeping the emitter formation technique fixed, it can be observed that the application of screen printing for contact formation instead of evaporation leads in general to larger open-circuit voltages (2 vs. 3a and 4 vs. 5a). For TF and CBF emitter an increase of 11 mV and 7 mV respectively is calculated for screen printing compared to evaporation. 98 6 Epitaxial thin-film solar cells

On the other hand, if the contact formation technique is fixed, an increased VOC is achieved if a CBF emitter is used instead of a TF emitter (2 vs. 4 and 3a vs. 5a). In this case, a rise of 9 mV and 6 mV is observed in VOC for evaporated contacts and screen printed contacts respectively, when replacing the TF emitter by a CBF emitter. Both features can be readily explained by the different contact and emitter formation techniques. The application of a SiNx layer in case of screen printed contacts leads to an effective passivation of the surface, emitter and bulk region thus reducing the recombination activity and therefore increasing VOC.

The results further show that the application of a CBF emitter is beneficial for VOC, indicating that a general difference exists between the characteristics of the two emitter types. A possible explanation for the low performance of the TF emitter might be that high phosphorus surface concentrations or a large density of phosphorus precipitates led to an enhanced recombination in the emitter and space charge region. The mean values in short-circuit current are equal for process 4 and process 1 while process 2, 3a and 5a feature considerably lower values, all in a similar range. Using screen printed contacts, the emitter formation technique has only little impact on JSC. CBF and TF emitter result in almost identical mean values (3a vs. 5a). On the other hand, a significant boost in JSC can be observed for evaporated contacts, if a CBF emitter is used instead of a TF emitter (4 vs. 2). Increased shadowing and series resistance loss determine the short-circuit current densities if contact formation is done by screen printing. This characteristic is clearly reflected when comparing process 4 and 5a, where a difference of almost 3 mA/cm² in JSC is observed in favor of the solar cells with evaporated contacts. A similar difference is expected for process 2 and 3, where both emitters are formed by POCl3 diffusion but different contact formation techniques are applied. Instead, both processes result in similar short-circuit current densities. To explain this discrepancy the following assumption concerning TF and CBF emitter is made: compared to the CBF emitter the POCl3 diffused emitter features an increased surface concentration and is less deep. In addition the sheet resistance might be slightly different for both emitters, with the CBF emitter probably featuring a lower value.

Considering process 2 and 4 the detrimental decrease in JSC for the TF emitter can then be attributed to an enhanced recombination velocity in the emitter region. The internal quantum efficiency measurements graphed in Figure 6.6 confirm this statement. The solar cell with CBF emitter shows an overall better internal quantum efficiency compared to the solar cell with TF emitter. While the increase in red response is comparatively low and might be either a consequence of the CBF diffusion or a slight deviation in base layer thickness, the difference in the short-wavelength range is apparent. Up to a wavelength of 600 nm the solar cell with CBF emitter shows a substantially higher IQE than the solar cell with TF emitter, possibly due to different emitter characteristics. In Figure 6.7 the IQE characteristics for solar cells prepared by process 3a and 5a are compared. Again, the CBF emitter shows an overall better spectral response. However, compared to Figure 6.6 the difference between both emitter types is less pronounced and in the mid-wavelength range they even show almost identical values. 6.2 Solar cells on Cz-Si substrates 99

1.0

0.8

0.6

IQE 0.4

EC with 0.2 TF emitter (2) CBF emitter (4)

0.0 400 600 800 1000 1200 λ [nm]

Figure 6.6: Internal quantum efficiency measured for epitaxial solar cells with different emitter diffusion techniques. In both cases, contact formation was done by evaporation.

1.0

0.8

0.6

IQE 0.4 SPC with RTF through SiN x 0.2 TF emitter (3a) CBF emitter (5a)

0.0 400 600 800 1000 1200 λ [nm]

Figure 6.7: IQE for solar cells with screen printed metallization and different emitter types.

To evaluate the effect of the passivating SiNx layer on spectral response, IQE measurements were also carried out on solar cells of process 3b and 5b. The resulting curves are depicted in Figure 6.8 and compared to the IQE characteristics obtained for corresponding solar cells with SiNx (type a).

The application of a SiNx layer on a TF emitter leads only to a minor improvement in IQE for short wavelengths (Figure 6.8, left). In contrast, a substantial rise in blue response is obtained for the CBF emitter, if a passivating silicon nitride layer is deposited on the solar cell surface (Figure 6.8, right). In both cases, a slight increase in red response is observed if a SiNx layer is applied, indicating a bulk passivation of the base layer region. Similar to the improvement in the short-wavelength range the effect is more pronounced for the CBF emitter. 100 6 Epitaxial thin-film solar cells

1.0 1.0

0.8 0.8

0.6 0.6

IQE 0.4 IQE 0.4

TF emitter CBF emitter RTF through SiN (3a) RTF through SiN (5a) 0.2 x 0.2 x RTF without SiN (3b) RTF without SiN (5b) x x 0.0 0.0 400 600 800 1000 1200 400 600 800 1000 1200 λ [nm] λ [nm]

Figure 6.8: Effect of RTF through SiNx on internal quantum efficiency studied for two different emitter formation techniques. Left: TF emitter with screen printed contacts. Right: CBF emitter with screen printed contacts.

Considering the solar cell parameters for TF emitter, contact formation with RTF through SiNx yields an increase in VOC by 29 mV and an increase in JSC by 7.3 mA/cm² compared to contact formation by evaporation. For the CBF emitter the improvement is even more drastic with a rise in VOC by 35 mV and in JSC by 8.2 mA/cm². The results from IQE and illuminated I/V characteristics show that the CBF emitter can be better passivated by the SiNx layer, indicating a lower surface concentration compared to the TF emitter and thus further confirming the assumption made on the shape of the emitter profiles. In Figure 6.9 the impact of contact formation on spectral response can separately be studied for both emitter types. Concerning the TF emitter the internal quantum efficiency characteristics suggests that the mere process of contact formation by screen printing (without RTF through SiNx) considerably improves the emitter and bulk region of the solar cell. For the CBF emitter almost the inverse effect is observed: the process of screen printing deteriorates the emitter but not the bulk.

1.0 1.0

0.8 0.8

0.6 0.6

IQE 0.4 IQE 0.4

TF emitter CBF emitter 0.2 EC (2) 0.2 EC (4) SPC without SiN (3b) SPC without SiN (5b) x x 0.0 0.0 400 600 800 1000 1200 400 600 800 1000 1200 λ [nm] λ [nm]

Figure 6.9: Internal quantum efficiency for solar cells with TF emitter (left) and CBF emitter (right) and evaporated as well as screen printed contacts. 6.2 Solar cells on Cz-Si substrates 101

A conclusions which can be drawn from these results is that the process of screen printing seems to influence the solar cells with TF emitter in terms of an improved minority carrier lifetime in emitter and bulk. Temperature and duration of the firing step are very short compared to the emitter diffusion from POCl3 source and therefore a change of the emitter properties as a consequence of the firing process seems to be unlikely. At present, the mechanism leading to the observed improvement is not clear. To quantify the CBF and TF emitter profiles, SIMS and Stripping Hall measurements were ordered but not completed at the end of this work.

6.2.5 Overview on solar cell efficiencies In Table 6.5 the best solar cell efficiencies achieved for each solar cell process for all three different material types are listed. The illuminated I/V parameters for samples marked with an asterisk are confirmed measurements by the Fraunhofer ISE Calibration Laboratory. Solar cells with epilayers deposited at Fraunhofer ISE are denoted Epi (ISE) while those with epilayers grown in a commercial CVD system are denoted Epi-Ref.

Process Area Sample VOC JSC FF Efficiency [cm²] [mV] [mA/cm²] [%] [%] 1 21.2 Epi (ISE)* 635 28.9 80.8 14.8 Epi-Ref. 631 30.7 78.9 15.3 FZ-Si Ref.* 633 34.2 81.1 17.6 2 21.6 Epi (ISE)* 613 26.8 78.4 12.9 Epi-Ref. 612 27.5 79.9 13.4 FZ-Si Ref. 620 33.6 79.8 16.6 3a 23.0 Epi (ISE)* 621 25.5 77.1 12.2 Epi-Ref.* 625 26.5 78.7 13.1 FZ-Si Ref. 621 30.7 76.7 14.6 4 21.2 Epi (ISE)* 626 29.0 80.5 14.6 Epi-Ref. 622 29.4 80.4 14.7 Cz-Si Ref. 549 33.6 75.9 14.0 5a 23.0 Epi (ISE)* 628 25.9 74.0 12.0 Epi-Ref.* 628 26.5 72.8 12.1 Cz-Si 589 31.5 68.2 12.6 * Confirmed measurement by ISE Calibration Laboratory

Table 6.5: Summary of the best solar cell results achieved for all process routes. The parameters for the epitaxial cells, the epitaxial references (Epi-Ref.) and the FZ- and Cz-Si references are listed for comparison. 102 6 Epitaxial thin-film solar cells

The list is aimed to give an overview on the best results gained for each solar cell process type. The basic differences between each material type and each solar cell process route have already been discussed in previous sections and therefore only some outstanding features will be highlighted here. In general, the silicon wafer references feature the best solar cell performance for each process type.

Exceptions are process 4a and 5a, where the Cz-Si reference cells suffer from low VOC and low fill factor compared to the epitaxial cells. This property seems to be related to the applied emitter formation technique by in-line diffusion from a screen printed source. Typically, process 5a yields efficiencies of 14.3% with open-circuit voltages and fill factors well above 600 mV and 77% respectively for Cz-Si wafers [119]. The deviation from this standard result must be caused by a difference in the emitter diffusion process. Surprisingly, the epitaxial cells are not affected, possibly because of different material properties. The general differences in short-circuit current reflect the deviations in base layer thickness, which is largest for the silicon wafer material and lowest for the ISE epi-cells. For the epitaxial thin-film solar cells with epitaxy done at Fraunhofer ISE a maximum efficiency of 14.8% is obtained for the standard cleanroom process 1. The solar cell parameters determined for this solar cell clearly show the potential of the epitaxial thin-film concept: the measured open-circuit voltage is slightly larger than for the epitaxial reference and especially larger than for the FZ-Si wafer reference. On the other hand, the lowest short-circuit current is observed for epi (ISE) as a consequence of the small thickness of the active base layer and a reduced minority carrier lifetime in the base (see section 6.2.8). The fill factors for epi (ISE) and FZ-Si reference cell are in the same range. For the epitaxial solar cells, the application of an adequate optical confinement could substantially increase JSC thus leading to efficiencies comparable to silicon wafer material. A record efficiency of 13.1% was achieved for an epitaxial thin-film solar cell of 35 µm thickness prepared by industrial relevant screen printing technologies (3a). For epitaxial layers grown in the RTCVD100 reactor, a maximum efficiency of 12.2% could be reached for a 25 µm base layer using the same solar cell process.

6.2.6 Characterization by lock-in thermography Lock-in thermography [120] was applied to analyze the shunts affecting the solar cell performance of all solar cell types presented in the last sections. Local shunts may influence the I/V characteristics and can lead to a loss in fill factor and VOC [121]. Figure 6.10 shows lock-in thermograms (amplitude image) measured at 0.5 V forward bias for epitaxial solar cells prepared by solar cell process 3a, 4 and 5a. Solar cells on epilayers deposited in a commercial system and in the RTCVD100 are compared. Brighter contrasts correspond to higher local current densities. Edge shunts resulting from an incomplete separation of emitter and base are common to all solar cells and dominate the thermograms in Figure 6.10. Considering process 3a no significant difference can be observed between the thermograms of the solar cells with epilayer grown in different CVD systems. In addition, it can be stated that the screen printing process does not affect the formation of shunts for solar cells with TF emitter. CBF emitter and TF emitter feature similar homogeneity as the thermograms for solar cells of process 3a and 4 reveal. No negative interaction between material properties and CBF emitter is observed. 6.2 Solar cells on Cz-Si substrates 103

Point-like shunts within the area of the solar cell are visible in the thermogram in the lower left corner of Figure 6.10 which corresponds to a solar cell with epilayer grown in the RTCVD100, an emitter prepared by conveyor-belt furnace diffusion and screen printed contacts. The shunts were found to be mainly located underneath the emitter grid lines. The equivalent solar cell with commercial epilayer is not affected by such shunts. Taking into consideration all the information gained from lock-in thermography it is obvious that the formation of shunts for solar cells of process 5 must be associated to a combined interaction between epitaxial material, CBF emitter and screen printed contacts.

RTCVD100 Commercial reactor

Process 3a TF emitter Screen printed contacts

Process 4 CBF emitter No measurement Evaporated contacts

Process 5a CBF emitter Screen printed contacts

Figure 6.10: Thermograms (amplitude image) of epitaxial cells prepared by different epitaxy processes and solar cell technologies. The measurements were carried out at 0.5 V forward bias. 104 6 Epitaxial thin-film solar cells

The occurrence of shunts located underneath the emitter grid lines was already observed in earlier experiments where CBF emitter and screen printed metallization were applied to epitaxial material prepared under similar conditions as presented in the previous sections [122]. For state-of-the-art multicrystalline solar cells, an increased occurrence of shunts underneath emitter grid lines has also been reported in [123]. In [122], the formation of these shunts could be associated to an interaction between epitaxial defects and screen printed metallization. However, at this stage the influence of emitter formation technique could not be determined unambiguously. With the new experiments discussed herein, it is clear that an enhanced formation of shunts depends not only on the properties of the epitaxial material and the contact formation technique but also on the type of emitter diffusion. To understand possible interactions between these three counterparts a detailed knowledge of the individual characteristics of each component is essential. According to recent studies [124] the contact formation by screen printing can be described as follows: the silver paste which is used for screen printing contains glas frit, which etches into the antireflection coating and subsequently into the emitter upon heating. Silicon and silver are dissolved in the glas frit during the firing process and recrystallize upon cooling down thus forming Ag crystallites at the interface. The penetration of Ag crystallites into the silicon emitter region is assumed to contribute to leakage currents of the pn- junction. For epitaxial solar cells, the observed accumulation of shunts underneath the emitter grid lines could be explained by the following mechanism: screen printing of Ag-paste over defective regions (e.g. epitaxial spikes) or grain boundaries can result in an enhanced etching of silicon in these regions by the glas frit [125] thus affecting the space charge region or even leading to the formation of holes in the emitter structure. An increased penetration of interfacial Ag crystallites into the silicon emitter of defective regions might also explain the correlation between screen printed contacts, epitaxial defects and the formation of shunts. However, at present the influence of emitter formation technique on the development of shunts is not clear.

6.2.7 Summary An extensive study on the application of different emitter and contact formation techniques was carried out for epitaxial thin-film solar cells. Emitter structures were realized by diffusion from POCl3 source in a closed tube furnace and by conveyor-belt furnace diffusion from a screen printed phosphorus source. Evaporated and screen printed contacts with and without firing through SiNx were applied to both emitter types. Epitaxial solar cells were also prepared by a standard cleanroom process for material quality monitoring. The quality of epilayers grown in the RTCVD100 reactor at Fraunhofer ISE was evaluated with respect to epilayers grown in a commercial CVD system. In addition, the influence of very fast silicon growth velocities on solar cell performance was investigated. The results show, that solar cells processed on epilayers grown at a rate of 5 µm/min are only slightly superior to those grown at a doubled rate of 10 µm/min. The difference is assumed to be attributed to an increased defect density in case of the fast growing films leading to an enhanced saturation current. Epitaxial thin-film solar cells prepared in a cleanroom process on fast grown epilayers resulted in a maximum efficiency of 13.9%, with VOC=632 mV, ISC=28.0 mA/cm² and FF=78.8%. Summarizing all solar cell results it can be stated that epilayers deposited in the RTCVD100 are of sufficient quality to reach high solar cell efficiencies. 6.2 Solar cells on Cz-Si substrates 105

The analysis of solar cell parameters and IQE characteristics for epitaxial solar cells prepared by different process types led to the assumption that TF emitter and CBF emitter feature different doping profiles. A CBF emitter with lower surface concentration, larger junction depth and larger sheet resistance compared to the TF emitter could explain the observed characteristics. An analysis of both emitters is currently carried out by Stripping Hall and SIMS measurements to verify the assumptions made. IQE measurements showed that the application of a CBF emitter results in a slight increase in red response, indicating a gettering or anneal effect on the epitaxial base layer. Concerning contact formation by screen printing, both emitter types can be equally well applied. A significant passivation of the emitter region is obtained by firing through SiNx. Screen printing of emitter contacts combined with in-line emitter diffusion was found to result in enhanced shunt formation on sites of epitaxial defects. While a plausible explanation for a possible interaction between metallization and defects could be given, the influence of the emitter formation technique on the formation of shunts remains to be clarified. Using industrial relevant screen printing technologies a record efficiency of 13.1% was achieved for a 35 µm epitaxial thin-film solar cell. For epilayers grown in the non-commercial lab-type RTCVD100 reactor a remarkable efficiency of 12% could be reached for a 25 µm thick base layer using the same solar cell process.

6.2.8 Solar cell simulation According to the solar cell results presented in the previous section a simulation was carried out to evaluate the potential of the solar cell structure. The one dimensional simulation program PC1D [126] was used to calculate the solar cell performance for different material parameters. The solar cell model is based on the characteristics of an epitaxial thin-film solar cell corresponding to type 3a in previous sections with epilayer grown in the RTCVD100 and industrial type solar cell process technologies. The simulated solar cell structure is illustrated in Figure 6.11: it is divided into three regions corresponding to emitter, epitaxial base and substrate. The transition zone between substrate and base has been approximated by an ideal step function.

front contact grid ARC

Sfront emitter ] 20 -3 10 base 1019 Sinterface 1018

substrate 1017

1016 Carrier [cm density Sback Al rear contact emitter base substrate

Figure 6.11: Simulated solar cell structure and corresponding carrier density profile.

A correct simulation of any epitaxial solar cell requires knowledge of material parameters for the emitter, base and substrate region: 106 6 Epitaxial thin-film solar cells

• The emitter structure was simulated assuming a sheet resistance of 45 Ω/sq as measured by 4- point probe on a FZ-Si reference. The emitter doping profile was designed by a Gauss curve with a junction depth of 0.45 µm and a peak surface concentration of 1.2x1020 cm-3. The front surface recombination velocity was fixed to a value of 1x105 cm/s [127]. The simulated emitter

corresponds to a highly doped emitter diffused from a POCl3 source as used for solar cell process 2 and 3.

• Thickness, doping density and minority carrier lifetime are the most important input parameters for the base region. In addition, the rear surface recombination velocity of the base (the interface between substrate and epilayer) has to be accounted for in the simulation. The deposition of lowly doped epilayers on highly doped substrates induces strain at the substrate/epilayer interface due to the different lattice constants [128], [129]. The lattice mismatch can be relieved by the formation of dislocations building recombination centers. While thickness and doping density can be estimated from SRP measurements on comparable samples, neither minority carrier lifetime of the base layer nor interface recombination velocity can be separately measured. In our case, the epilayer thickness was determined to 25 ± 3 µm with a carrier density of 5x1016 ± 1x1016cm-3.

• Similar to the base region, thickness, doping density and minority carrier lifetime have also to be known for the substrate region. The aluminum rear surface of the substrate is simulated by a recombination velocity of 1x107 cm/s. The substrate thickness of 600 µm was taken from the producers information. The specific resistivity of 0.015 Ωcm (4x1018 cm-3) was measured by SRP and 4-point probe. Due to the large doping density the effect of band gap narrowing has to be accounted for [11]. The lifetime of the minority carriers in the substrate could not be experimentally determined. In Table 6.6 the relevant parameters of epitaxial layer and substrate material used for the simulation are summarized. Layer thickness, doping density and minority carrier diffusion constant are denoted by d, NA and De respectively. ∆Eg describes the apparent band gap narrowing, which has to be taken into account for doping densities exceeding 1x1017 cm-3.

-3 d [µm] NA [cm ]De [cm²/s] ∆Eg [meV]

Base 25 5x1016 20.98 0 Substrate 600 4x1018 6.07 46.9

Table 6.6: Material parameters used for the modeling of an epitaxial thin-film solar cell according to experimental values.

The difficulty in simulating the solar cell structure lies in the uncertainty concerning minority carrier lifetime in the base and in the substrate region as well as the unknown recombination velocity at the interface between substrate and epilayer. All these parameters have significant influence on the solar cell parameters but a separate measurement of these values is not trivial. 6.2 Solar cells on Cz-Si substrates 107

Interface recombination velocity, carrier lifetime in the substrate and base In our case a high-low epitaxy deposition process has been used, with the doping density of the highly doped layer being identical to the substrate doping level. Therefore, the lattice mismatch at the interface epilayer/substrate can in a first approximation be assumed as negligible and the simulation problem reduces to a determination of τepi and τsubstrate. The degraded lifetime of boron-doped Cz-Si material is limited by Shockley-Read-Hall recombination. In [130] an empirical model for the bulk lifetime in boron-doped Cz-Si material is given. Extrapolating the model to high doping densities allows a confinement of the bulk lifetime for the Cz-Si substrates used for the epitaxial solar cells under consideration. For a doping density of 4x1018 cm-3 bulk lifetimes of 6x10-4 µs and 4.5x10-2 µs are obtained for the degraded and annealed state respectively. To determine a range for the lifetime in the epilayer, effective minority carrier diffusion lengths were calculated from IQE measurements and analyzed according to [131]:

L d 1− eff tanh( ) D L L S = ⋅ (6.1) L L d eff − tanh( ) L L where S denotes the effective rear recombination velocity at the back side of the cell which is in our case the interface substrate/base. Leff is the effective minority carrier diffusion length, d, L and D denote thickness, minority carrier diffusion length and diffusion constant in the base. Thus a separation of diffusion length in the base and rear surface recombination velocity is possible. Assuming d/L<0.5 and solving for L, eqn. (6.1) can be approximated by

dL L = eff S (6.2) 1+ (d − L ) D eff

This yields a lower limit for the bulk diffusion length Lmin and an upper limit for the back side recombination velocity Smax of the base layer according to

Lmin = dLeff for S = 0 cm / s (6.3)

D S max = (6.4) Leff − d

In Table 6.7 the experimentally determined value for Leff and the calculated values for Lmin, Smax and

Lmin/d are listed for an epitaxial thin-film solar cell prepared by process 3.

The value for Lmin/d is below 0.5, verifying the validity of the approximation made in eqn. (6.2). For the diffusion length in the base and the rear side recombination velocity, a minimum of 39 µm and a maximum of 5670 cm/s respectively were obtained. The diffusion length of 39 µm corresponds to a 108 6 Epitaxial thin-film solar cells minority carrier lifetime of 0.73 µs and represents a lower boundary for the lifetime in the epitaxial base layer. Taking into consideration these results, a simulated IQE curve fits well to the experimental data for

τepi=2 µs and τsub=0.016 µs.

Leff [µm] Lmin [µm] Smax [cm/s] Lmin/d d/Lmin 75 ± 13 43 ± 4 4500 ± 1170 0.34 ± 0.06 3.0 ± 0.54

Table 6.7: Effective minority carrier diffusion length as determined from IQE measurements for

epitaxial thin-film cells prepared by solar cell process 3. Lmin, Smax and Lmin/d were

derived from Leff.

For a two layer system, the influence of the underlying substrate on the minority carrier lifetime in the base can be approximated by an effective recombination velocity, if the minority carrier lifetime in the base layer is greater than the lifetime in the substrate. According to [132] this effective recombination velocity Seff represents an upper limit for the interface recombination velocity and is given by: S L d sub sub + tanh( sub ) D 1 D L S = sub ⋅ ⋅ sub sub (6.5) eff L Φ S L d sub 1+ sub sub ⋅ tanh( sub ) Dsub Lsub

N A,sub with Φ = ⋅ exp(∆Eg,epi − ∆Eg,sub ) N A,epi

Where dsub, Dsub and Lsub denote thickness, minority carrier diffusion constant and diffusion length in the substrate. The rear surface recombination velocity at the back of the substrate is given by Ssub. The parameter Φ takes the band gap narrowing into account: NA,sub/epi and ∆Eg,sub/epi denote the acceptor density and the apparent band gap narrowing for substrate and epilayer. Equation (6.5) shows that apart from the epilayer doping, Seff depends only on substrate properties.

In Figure 6.12 the correlation between Seff and Lsub according to eqn. (6.5) is graphed. For the calculation, the material parameters were taken from Table 6.6 and the minority carrier diffusion length in the substrate was varied within the range of 0.1-19.4 µm (Auger-limit). For a maximum diffusion length of 19.4 µm an effective recombination velocity of 240 cm/s was calculated. LSRH,x denotes the minority carrier diffusion length for Cz-Si material limited by SRH recombination. The corresponding effective surface recombination velocity can be taken from the graph. Smax,Leff is the maximum rear surface recombination velocity as calculated from experimental Leff values (Table 6.7).

For the PC1D simulation Lsub was set to 3.1 µm, represented by the filled square. Using equation (6.5) it can be shown that the solar cell structure can equally well be modeled by only one region with an effective rear surface recombination velocity of 1248 cm/s. In this case, the contributions to photocurrent coming from the substrate region are negligible. 6.2 Solar cells on Cz-Si substrates 109

105

104

S max,Leff PC1D Simulation

[cm/s] 3

eff 10 S

2 L L L 10 SRH, degraded SRH, annealed sub,Auger

0.1 1 10 L [µm] sub

Figure 6.12: Calculated effective recombination velocity as a function of minority carrier diffusion length in the substrate according to eqn. (6.5).

To evaluate the effect of an interface recombination velocity unequal to zero, the solar cell was modeled in close relation to experimental conditions: instead of a sharp step-like change in doping concentration between substrate and epilayer a transition-zone was implemented where the slow change in doping density due to autodoping is taken into account. In accordance to experimental data gained from SRP measurements, the width of the transition zone was set to 4 µm. The diffusion length in this region was assumed to be slightly larger than the Auger limited diffusion length in the substrate. The surface recombination velocity at the interface between base and transition region was set to zero while the recombination velocity at the crystallographic interface between transition-zone and substrate was varied from 0 to 106 cm/s. Figure 6.13 shows the calculated loss in efficiency as a function of interface recombination velocity.

6

5

4

3

2

1 Relative loss in efficiency [%] Relative loss in efficiency 0 101 102 103 104 105 106 S [cm/s] interface

Figure 6.13: Relative loss in efficiency depending on the recombination velocity at the crystallographic interface between substrate and epilayer. 110 6 Epitaxial thin-film solar cells

For a maximum interface recombination velocity in the range of 104 cm/s as determined from eqn. (6.5) for a degraded Cz-Si substrate with a boron concentration of 4x1018 cm-3, the relative loss in efficiency comes up to 1.6% which is still in an acceptable range. For large interface recombination velocities of 106 cm/s the influence on solar cell performance becomes significant and cannot be tolerated if high efficiencies are to be achieved.

Optimization of epilayer properties For an optimization of solar cell efficiency, epilayer thickness and doping level were varied for the simulated solar cell structure. In Figure 6.14 the results are illustrated. Within the range of 1x1016cm-3 to 1x1017 cm-3 the base doping density has only little effect on solar cell efficiency for fixed base layer thickness. A further increase in doping concentration leads to a reduction in efficiency because of an increased Auger recombination. Greater base layer thicknesses are beneficial for the solar cell performance independent from base layer doping, due to the larger volume of the active device. Within a doping range of 2x1016 cm-3 to 1x1017 cm-3 the efficiency does not change significantly for a base thickness exceeding 35 µm. In this case, the solar cell performance is limited by the minority carrier lifetime in the base.

14 Efficiency [%] 9.5 9.5 - 10.0 10.0 12 10.0 - 10.5 10.5 ]

-3 10.5 - 11.0 10 11.0 11.0 - 11.5 11.5 cm 11.5 - 12.0 16 8 12.0 12.0 - 12.5 12.5

[10 12.5 - 13.0 6 13.0

A, base A, 4 N 2

10 20 30 40 50 60 Base Thickness [µm]

Figure 6.14: Solar cell efficiency as a function of base layer thickness and doping concentration.

The effect of surface texture on short-circuit current has been investigated by simulating an inverted pyramid texture with a depth of 7 µm. Figure 6.15 shows the influence of a textured front surface on short-circuit current density. Three different settings are compared: first, the surface is assumed to be plane with a corresponding experimental reflection curve used for the simulation (1). Second, the same reflection curve is applied, but a pyramidal texture is simulated on the front surface (2). Third, the front surface is modeled as textured and a reflection curve corresponding to a random texturing with a 7 µm deep pyramidal structure has been implemented (3). While simulation (2) only considers the enhancement in short- circuit current density by a greater optical path length, simulation no.3 also accounts for the reduced optical reflection associated to the pyramidal structure. The experimental reflection curves were measured on samples without antireflection coating. Comparing the characteristics in Figure 6.15 the benefit of a textured front surface on short-circuit current density is clearly visible. Considering a base layer thickness of 25 µm, a gain in short-circuit 6.3 Solar cells on mc-silicon substrates 111 current of 3% is calculated, if front texturing is applied and only the geometric effect by an enhanced optical path length is considered (2). The total reflection of an experimental random texturing was calculated to 12%, compared to 36% for a plane silicon surface. Taking into account the changed optical reflection (3), an increase by approximately 29% is obtained compared to (2). Last but not least, the reflection can be further reduced by the deposition of an antireflection coating. Combining an antireflection SiNx layer and a textured front surface a total reflectance of only 4% can be achieved.

30

28

26

24

[mA/cm²] 22 SC J 20 1 2 18 3

10 20 30 40 50 60 Base Thickness [µm]

Figure 6.15: Effect of optical confinement by surface texturing on short-circuit current density for simulated epitaxial thin-film solar cell.

Summing up, the simulations show that the efficiency of the epitaxial solar cell under consideration can be increased by slightly increasing the base layer thickness and/or the application of surface texturing for optical confinement.

6.3 Solar cells on mc-silicon substrates In the last section ideal single-crystal, electrically inactive Cz-Si wafers have been used as substrate material. The influence of different solar cell process steps as well as the quality of two different CVD-processes could be studied on these epitaxial cells. Compared to this ideal system the solar cell process technology is confronted with the challenge of an uneven surface morphology and grain boundaries when applied to multicrystalline wafers. In general, multicrystalline material is characterized by the presence of grain boundaries which can act as effective recombination centers and by the presence of other crystallographic defects which are often decorated by impurities [11]. An enhanced diffusion of impurities along grain boundaries can be expected.

Highly doped (0.01-0.02 Ωcm) Wacker-Silso multicrystalline-Si substrates cut from successive positions in the block were used as substrate material. The epitaxial samples were prepared according to the process sequence described in section 6.2.1. Epilayers of 35 µm thickness and 5x1016 cm-3 doping density were deposited using epitaxy process A. Two solar cell process routes were applied identical to process 1 and 3, described in the previous section. The process sequence is depicted in Figure 6.16. The cleanroom process 1 was used for monitoring while process 3 represents a typical industrial solar cell process with heavily doped emitter and screen printed contacts. Samples from 112 6 Epitaxial thin-film solar cells successive substrate wafers were introduced in both batches in alternating order to enable a direct comparison of both process types. Table 6.8 gives the mean values for the illuminated I/V parameters calculated for both process types. For comparison the results obtained for epi-cells on Cz-Si substrates are added.

Process 1 Process 3

TF-diffusion from POCl3 TF-diffusion from POCl3 source (80 Ω/sq) source (40 Ω/sq)

PECVD of antireflection SiNx

Definition of front contacts Screen printing of front and by photolithography rear contacts

Evaporation and electro- Rapid Thermal Firing (RTF)

plating of contacts through SiNx

Deposition of double layer antireflection coating

Figure 6.16: Process sequence of the two solar cell processes applied to epitaxial thin-film solar cells on multicrystalline silicon substrates.

Process Area Substrate VOC JSC FF Efficiency [cm²] [mV] [mA/cm²] [%] [%] 1 21.2 mc 591 ± 9 28.5 ± 0.1 69.9 ± 2.6 11.8 ± 0.6 Cz 627 ± 6 28.6 ± 0.4 78.5 ± 1.1 14.0 ± 0.2 3 23.0 mc 595 ± 10 24.4 ± 0.1 75.2 ± 1.5 10.9 ± 0.4 Cz 619 ± 1 25.9 ± 0.3 76.1 ± 0.3 12.2 ± 0.2

Table 6.8: Mean solar cell parameters calculated for epitaxial thin-film solar cells on mc-Si and Cz-Si substrates.

The largest fill factors are obtained for solar cells on Cz-Si substrates prepared by process 1. The reduction in fill factor for equivalent solar cells prepared by process 3 is a direct consequence of contact formation by screen printing. However, while solar cells on mc-Si substrates of process 3 feature a fill factor of 75% comparable to their monocrystalline counterpart, a significant reduction is observed for process 1, where only about 70% are reached for solar cells on mc-Si substrates compared to 78.5% for Cz-Si substrates. 6.3 Solar cells on mc-silicon substrates 113

The series resistance Rs,light was calculated from illuminated and dark current characteristics for both multicrystalline cell types [133]. Since no significant difference between Rs,light and the series resistance determined from fitted dark I/V-characteristics was observed, the reason for the lower fill factor in process 1 must be traced back to a lower parallel resistance and greater saturation current. This can be attributed to the absence of bulk passivation schemes for process 1 and the influence of crystallographic defects on the second diode. The large defect density in multicrystalline material makes an effective bulk passivation obligatory, if high efficiencies are to be reached. In process 3 this is realized by the deposition of a passivating SiNx layer. A reduction in open-circuit voltage can be observed for the mc-Si solar cells of both process types, compared to their corresponding Cz-Si counterpart. For process 1 and 3 the difference amounts to 38 mV and 24 mV respectively, in favor of the monocrystalline solar cells. Again, the deviations between both process types can be traced back to the passivation scheme applied for process 3. Considering the short-circuit current densities, process 3 in general results in lower values due to higher shadowing for screen printed contacts. Comparing the mean values for both monocrystalline cell types an increase of 2.7 mA/cm² can be observed for process 1. For their multicrystalline counterparts, an even larger increase of 4.1 mA/cm² is obtained. Assuming that both contact grid designs always result in the same shadowing loss, the difference in JSC for process 1 and process 3 should be equal or at least in the same range for different solar cell materials. The experimental values contradict this conclusion. The reason for this discrepancy was found to originate from a variation in emitter contact width for Cz- and mc-Si solar cells prepared by process 1. While screen printing results in nearly equal finger width for both material types, a deviation is observed for solar cells with evaporated contacts. In this case, the solar cells on multicrystalline substrate feature a very small contact width compared to the corresponding monocrystalline solar cells leading to a reduced loss in

JSC by shadowing. In process 1, the definition of contact width is done by photolithography, which can be affected by irregularities in surface morphology and reflectivity. The morphology of epitaxied multicrystalline substrates imposes high demands on the front contact formation technique. The typical characteristics of epilayers grown on multicrystalline silicon substrates have already been discussed in chapter 4. The most important features are the dependence of growth rate on crystal orientation and the resulting difference in epilayer thickness, the growth- induced texture of certain grain orientations and the trenches, which develop in most cases on sites of grain boundaries. Figure 6.17 shows the image of two epitaxial cells prepared by process 1 and 3 on successive mc-Si wafers. A position has been chosen where the finger grid crosses a grain boundary. Definition of the emitter grid by photolithography resulted in a straight line nearly undisturbed by the grain boundary. The underlying morphology is reproduced in the contact finger. Nonetheless, photolithography on this material is not straightforward: the presence of an uneven surface texture and different layer thickness of neighboring grains imposes high challenges on the spin-on of etch resist and on the definition of adequate exposure times. Concerning the screen printed grid a smearing out of the metallization paste is observed on sites of grain boundaries, where trenches are present or the neighboring grains differ in height. On more elevated grains the grid fingers are typically more narrow because of the reduced distance to the screen printing mask. Both features – smearing out and different width of contact fingers – are related to the application of screen printing on rough surfaces. Comparing the two images in Figure 6.17, the significant difference in contact width becomes apparent. 114 6 Epitaxial thin-film solar cells

Figure 6.17: Emitter contact crossing grain boundaries. Left: Contact definition by photolithography. Right: Screen printed contact.

The effect of different base layer thicknesses and surface morphology on short-circuit current density has been studied by SR-LBIC13 measurements. Figure 6.18 shows a mapping of effective minority carrier diffusion length determined from SR-LBIC and corresponding reflection measurements for an epitaxial solar cell prepared by the standard cleanroom process 1. The grain boundaries are clearly visible as regions of low minority carrier diffusion lengths. Crystal imperfections already present in the substrate continue in the epitaxial layer and are visible in the map as spots or lines (scratches) with locally reduced diffusion length. Deviations in Leff for different grains were found to correlate to different epilayer thicknesses and to the presence of growth-induced texturing. The greatest diffusion lengths were measured for grains with thick, textured epilayers.

Leff [µm]

65

10

46 mm

Figure 6.18: Mapping of effective minority carrier diffusion length for an epitaxial thin-film solar cell on multicrystalline silicon substrate.

13 SR-LBIC: Spectrally Resolved Light Beam Induced Current. 6.3 Solar cells on mc-silicon substrates 115

Lock-in thermography was applied to analyze the shunts effecting the solar cell performance. In Figure 6.19 the lock-in thermograms (amplitude image) measured at 0.5 V forward bias for multicrystalline and monocrystalline epitaxial solar cells prepared by process 1 and 3 are depicted. Independent on solar cell process technology the thermograms for monocrystalline solar cells are dominated by edge shunts. This is a feature commonly observed in solar cell thermograms and is related to technological instead of material imperfections [134]. Point-like shunts located within the cell area and edge shunts are visible in the thermograms of the corresponding multicrystalline solar cells. In fact, such shunts clearly dominate the thermogram of the multicrystalline solar cell prepared by process 1. The formation of point-like shunts for multicrystalline solar cells can be attributed to the imperfect crystal structure of the material. The thermograms in Figure 6.19 show that the occurrence of leakage currents is also affected by the solar cell process. The passivation of emitter and bulk by the SiNx layer is assumed to be responsible for the reduction in shunt formation for the mc-Si solar cell with screen printed contacts. However, the measurements do not allow an unambiguous determination of the main factor responsible for the increased formation of shunts in case of process 1.

Epitaxial solar cells on Epitaxial solar cells on mc-Si Cz-Si

Process 1

TF emitter (80 Ω/sq) Evaporated contacts

Process 3 TF emitter (40 Ω/sq) Screen printed contacts

Figure 6.19: Thermograms measured for epitaxial thin-film solar cells on mc-Si (left) and Cz-Si (right) substrates (amplitude image, 0.5 forward bias). Solar cell process 1 and 3 are compared.

In conclusion, it has been demonstrated that industrial screen printing processes could be successfully transferred to epitaxial cells on multicrystalline substrates. The surface morphology of epitaxied mc-Si 116 6 Epitaxial thin-film solar cells substrates was found to impose high challenges on both contact formation techniques, photolithography and screen printing. The multicrystalline structure of the material requires the application of suitable passivation schemes e.g. hydrogen passivation or the deposition of a passivating SiNx layer, as done for the formation of screen printed contacts. For epitaxial thin-film solar cells on heavily doped multicrystalline Silso material the best solar cell prepared by screen printing technologies featured a VOC=610 mV, JSC=25.0 mA/cm² and a FF=76.8% resulting in an efficiency of 11.7%, confirmed by Fraunhofer ISE Calibration Laboratory.

6.4 Solar cells on reclaimed silicon wafers In microelectronic production lines, reclaimed silicon wafers are often used for process monitoring out of cost-saving reasons. To make a re-utilization possible, the reclaim process must accomplish a complete removal of all layers (dielectric, metallic or other) deposited on the original silicon wafer and ensure a contamination-free surface. Furthermore, the recycling process aims to remove only little material from the wafer to make a multiple re-use possible. Reclaimed wafers from microelectronic industry represent an interesting option as potential low-cost substrate material for epitaxial silicon thin-film solar cells. The preparation of a thin-film solar cell on a reclaimed silicon wafer is less sensible to substrate properties compared to microelectronic devices. A less sophisticated reclaim procedure might be sufficient thus further contributing to the aspect of cost-saving. Single-crystal silicon reclaim wafers from microelectronics industry were supplied by the company AstroPower (Delaware, USA) for a re-use as substrates in epitaxial thin-film solar cells. The reclaim procedure included a mechanical removal of all devices by sand-blasting and a wet-chemical surface cleaning in a NaOH solution. The specific resistivity and the thickness of the electronic grade wafers was determined to 0.01 Ωcm and 600 µm respectively. Prior to further processing, the 6” wafers were cut into 50x50 mm² samples by laser scribing. The wafers were treated by different cleaning methods, resulting in different surface morphologies: a. No additional treatment. Mean roughness: 3.7 µm. b. Removal of 100 µm from the surface by wet-chemical CP133-damage etch. Mean roughness: 1.6 µm. The strong etching led to an increased fragility of the edges and a significant reduction in wafer area. The latter aspect presented a severe problem to the formation of the front contact grid which is defined to a specific area. c. Mechanical grinding of one surface with a final wafer thickness of 400 µm. The surface damage introduced by the grinding was removed by KOH etching. Mean roughness: 0.6 µm. The epitaxial layer is grown on the ground surface. d. Mechanical grinding of both surfaces with a final wafer thickness of 400 µm. Further treatment and mean roughness are identical to c. The main characteristic for pre-treatment b to d is that a large amount of material is removed from the surface prior to epitaxy. All samples were RCA-cleaned prior to epitaxy. Solar cells were prepared using process 3 with industrial screen printing technology and for reference, a selection of samples was introduced into the standard cleanroom process 1. 6.4 Solar cells on reclaimed silicon wafers 117

For an evaluation of the pre-treatment methods, solar cells from process 3 were analyzed. Within each pre-treatment group, samples with similar or equal epilayer thickness were used for the calculation of the mean values which are depicted in Table 6.9. For an interpretation of the different pre-treatment methods the difference in epilayer thickness between each group has to be accounted for. Best efficiencies were obtained for epitaxial thin-film solar cells on ground reclaim substrates. Solar cells of type c and d feature similar characteristics, indicating that the condition of the rear surface does not affect the solar cell performance. The difference in short-circuit current density can be attributed to the different epilayer thickness. The high reproducibility of the grinding and the epitaxy process respectively are reflected in the comparatively low standard deviations.

Comparing solar cells of type b and d a decrease in VOC, JSC and FF can be observed for the wet- chemically treated samples. The mean epilayer thickness is larger for type b and therefore the decrease in short-circuit current cannot be traced back to a thinner base layer. The same feature can be found for solar cells with type a pre-treatment. This characteristic (reduced JSC and VOC with increasing epilayer thickness) can be explained if low minority carrier lifetimes in the base are assumed. The comparatively low fill factor for solar cells with pre-treatment b is attributed to technological problems in contact formation and edge isolation due to the fragility of the samples.

Pre-Treatment dbase VOC JSC FF Efficiency [µm] [mV] [mA/cm²] [%] [%] a none 37 597 ± 5 22.3 ± 0.4 77.5 ± 0.6 10.3 ± 0.4 b CP-133 35 610 ± 3 23.0 ± 0.2 74.6 ± 3.8 10.5 ± 0.5 c 1 side ground 33 614 ± 1 24.4 ± 0.1 77.1 ± 0.1 11.6 ± 0.1 d 2 sides ground 30 613 ± 2 23.6 ± 0.4 78.1 ± 0.1 11.3 ± 0.2

Table 6.9: Mean values for epitaxial solar cells on reclaimed Cz-Si wafers prepared by solar cell process 3. The different substrate pre-treatments are compared.

Figure 6.20 shows internal quantum efficiency characteristics measured for solar cells of type a, b and d. The epilayer thickness of 25 µm is the same for all cells. For comparison, the IQE curve for a solar cell on epitaxial reference material (30 µm epilayer grown on highly doped Cz-Si in a commercial system) prepared in the same solar cell process is included. For the entire spectral range, the solar cell without additional pre-treatment (type a) reveals the lowest response. The characteristics for type b and d are similar with type d being slightly superior. The spectral response is clearly correlated to the pre-treatment of the samples. Wet-chemical CP-133 damage-etch and a grinding of the surface result in a comparable epilayer quality. The mechanical removal of the devices by sand-blasting and the subsequent NaOH treatment possibly results in a highly defected wafer surface, inadequate for high-quality epitaxy. Another explanation for the low response of type a solar cells might be that surface near regions are still contaminated by impurities after the reclaim procedure. During high-temperature CVD these impurities could easily diffuse into the epilayer leading to reduced carrier lifetime. Future work on reclaim material will have to deal with a characterization of impurities in the substrate material and in the epilayers e.g. by means of GDMS (Glow-Discharge Mass Spectrometry). 118 6 Epitaxial thin-film solar cells

Compared to the internal quantum efficiency measured for the epitaxial reference cell, the CP-etched or ground samples show a similar blue response and are only slightly inferior in the mid-wavelength range. The superiority of the epitaxial reference cell in red response is attributed to a combination of better minority carrier diffusion length, thicker base layer and probably a reduced interface recombination velocity. The best efficiencies were reached on ground substrates for both solar cell process types. In Table 6.10 the illuminated I/V solar cell parameters of the best solar cells are summed up.

1.0

0.8

0.6

IQE 0.4

Epitaxial Ref. 0.2 a - as received b - CP133 d - ground on both sides 0.0 400 600 800 1000 1200 λ [nm]

Figure 6.20: Internal quantum efficiency for epitaxial thin-film solar cells on highly doped reclaim wafers with different epitaxial pre-treatment.

Process Area Sample dbase VOC JSC FF Efficiency [cm²] [µm] [mV] [mA/cm²] [%] [%] 1 21.2 Reclaim (d)* 22 630 28.6 74.5 13.4 FZ-Si Ref. 634 35.9 78.5 17.8 3 23.0 Reclaim (d) 35 615 23.9 78.3 11.5 FZ-Si Ref. 621 30.7 76.7 14.6 * Confirmed measurement by ISE Calibration Laboratory

Table 6.10: Solar cell parameters of best solar cells achieved on epilayers grown on ground, highly doped reclaim wafers.

Comparing the solar cell results of the epitaxial cells to the FZ-Si reference cells shows the potential of the realized concept. Apart from small reductions in open-circuit voltage, the main loss for the epitaxial cells can be observed in short-circuit current. Future activities will focus on the optimization of the reclaim procedure for an application of reclaim wafers as substrate material for epitaxial thin-film solar cells. 6.5 Front surface texturing for epitaxial cells 119

6.5 Front surface texturing for epitaxial cells For epitaxial thin-film solar cells the short circuit current and thus the efficiency can be increased by texturing the front surface. Conventional lab-type solar cell processing of single-crystal wafers employs anisotropic random texturing to reduce the optical front side reflectance. Because of the anisotropy this technique is less effective on mc-Si wafers. In this case, mechanical V-grooving or Reactive Ion Etching (RIE) can be alternatively used for texturing. Considering epitaxial cells these techniques can similarly be utilized. Random pyramids are most effective if the depth extends to several microns. Application of such a texture on an epitaxied sample means that part of the epitaxy has to be removed or in fact wasted. V-grooving of the substrate results in a structure with a typical scale length of 50 to 100 µm and epitaxial films are typically grown on already V-grooved substrates. However, the front metallization on these deep grooves still represents a challenge to solar cell processing [135]. Following the concept of an epitaxial thin-film solar cell on a low-cost single-crystal silicon substrate a texturization method which allows for good optical properties, no or low consumption of the epilayer and industrial feasibility is the most attractive. Instead of applying an anisotropic etching step after epitaxy Cz-Si substrates were textured before the epitaxial growth of the base. The etch rate of the applied KOH solution strongly depends on the doping density and silicon wafers with boron concentrations exceeding ~1x1019 cm-3 act as an etch stop [136]. For <100>-oriented Cz-Si wafers with doping level of 4x1018 cm-3 the texturization process could be successfully optimized to yield low reflecting surfaces. Texturing was done using a KOH/IPA14 solution at elevated temperature. Subsequently epitaxial layers of 30 µm thickness were grown on these textured substrates. In Figure 6.21 measured reflection curves and corresponding SEM images of a textured substrate with and without epitaxial layer are shown.

70 Substrate 60 plane textured textured with 30 µm epilayer 50

40

30 Reflection [%] Reflection 20

10 400 600 800 1000 1200 λ [nm]

Figure 6.21: SEM image (left) and reflectivity measurement (right) of a KOH textured substrate with and without epitaxy.

14 IPA: Isopropanol. 120 6 Epitaxial thin-film solar cells

The SEM image in Figure 6.21 (left) show that the texturing resulted in random pyramids with a mean base length of 8 to 10 µm. The corresponding reflection curve proves the effectiveness of the texturing in terms of a significantly reduced overall reflectivity of 12%. After epitaxy, the surfaces of the samples were nearly planar and the optical properties were only slightly improved compared to the plane substrate. The smoothing of the textured surface is a typical characteristic of high temperature CVD at atmospheric pressure [24]. The experiment verifies that structures on a significantly larger scale than the epilayer thickness are necessary if the texture is to be transferred from substrate to epitaxial layer.

6.6 Innovative solar cell technology by CVD This section aims to give a preview on possible alternative applications of high-temperature APCVD depositions and reactors. The basic ideas of three different innovative CVD processes are outlined. While preliminary experiments and considerations have already been carried out, the verification of technological and economical feasibility has still to be accomplished in future work.

6.6.1 Emitter epitaxy Up to now, only little research has been done on the application of n-type epitaxial layers for solar cells. In [137] n-epitaxy has been performed by LPE and a multilayer junction thin-film solar cell has been prepared on a stack of six layers with alternating doping type grown on a highly doped p-type substrate. Another example is given in [24], where a n-type APCVD epilayer serves as base layer for crystalline silicon thin-film solar cells prepared by the PSI-process.

Conventional emitter formation is done by diffusion from a POCl3 source in a tube furnace and subsequent PSG etching. The entire process step is time consuming and wet chemicals have to be used. The epitaxial deposition of n-type phosphorus doped layers by CVD represents an interesting alternative to conventional emitter formation. Epitaxial layers can be grown at high rates up to 10 µm/min, the layers can be doped in situ by adding the appropriate dopant gas, doping profiles can be adjusted and no additional wet-chemical treatment is necessary. In [138] the technical and economical feasibility of epitaxial emitters was investigated. Solar cell simulations assuming a standard high-efficiency solar cell process showed that epitaxial emitters can indeed compete with conventional diffusion. Assuming a high throughput reactor as presented in section 3.4.4 the cost-effectiveness of the entire process was demonstrated.

6.6.2 Boron BSF epitaxy and diffusion The effectiveness of a back surface field depends on the surface concentration, on the profile of the p+ layer and on the recombination activity of the interface at the high-low junction [10]. The p/p+ junction is typically prepared by diffusion or alloying, using aluminum or boron as dopants. In industrial processing, the back surface field is formed by screen printing of Al on the rear side of the cell and a subsequent anneal above the eutectic temperature. The gettering effect or BSF effect of the Al back surface or a combination of both are assumed to be responsible for the improvement in solar cell performance [139]. Compared to Al greater surface concentrations can be achieved if boron is used as dopant thus making boron a more attractive choice for BSF formation. The diffusion coefficient of boron in silicon is 6.7 Summary 121 much smaller compared to aluminum making larger temperatures (>1000°C) and increased process times necessary for the diffusion step. As an alternative, boron BSF layers can also be formed by ion- implantation. However, neither technology is suitable for industrial scale production. CVD offers the possibility to deposit heavily boron-doped silicon layers on any kind of substrate thus creating large doping gradients beneficial for an effective BSF. A surface doping concentration exceeding 1x1019 cm-3 can easily be achieved and high deposition rates above 5 µm/min enable a fast processing. For the epitaxial deposition the wafers have to be exposed to high temperatures above 1100°C. The applicability of an epitaxial boron-BSF to conventional Cz-Si wafers depends on the impact of such a high-temperature treatment on the electrical properties of high-quality material. In section 5.3.1 a diffusion of boron from the gas phase has been observed leading to high surface peak concentrations of 6x1019 cm-3 and a junction depth in the micron range. A diffusion time of 5 min was sufficient to generate this profile. The diffusion has been carried out in the RTCVD100 reactor using high temperatures above 1100°C and B2H6 diluted in hydrogen as dopant source. Using this diffusion method, the diffused boron profiles are assumed to be tunable by variation of dopant gas flow, diffusion temperature and diffusion time. In [99] the application of this diffusion technique for the preparation of ultra-thin-base Si bipolar transistors has been reported. Compared to the epitaxial deposition of a highly-doped boron layer, lower junction depth can be more easily achieved, lower process temperatures can be used and no trichlorosilane is consumed. For the preparation of low junction depth the vapor phase diffusion of boron from B2H6 is therefore superior to the epitaxy of low resistivity silicon layers.

6.6.3 In-situ HCl texturing In-situ HCl texturization represents an interesting alternative to wet-chemical texturing of epilayers. Traditionally HCl in-situ etching is an additional step within the epitaxy process of silicon wafers. A thin surface layer is removed from the substrate preparing it for silicon epitaxy. For this application the HCl in-situ etch step is optimized to result in a smooth substrate surface. Under different process conditions a texturing or roughening of the substrate surface can also be achieved [57]. This effect could be utilized for a front surface texturing of epitaxial layers. Considering a continuous CVD reactor, the HCl texturing step could be implemented in an in-line CVD process by adding an additional reaction chamber to the reactor.

6.7 Summary The successful application of industrial screen printing technologies on epitaxial silicon thin-film material was highlighted in this chapter. Highly doped Cz-Si substrates were used to characterize the quality of epilayers grown in the lab-type RTCVD100 reactor and to evaluate the effect of different solar cell process technologies on the epitaxial material. Subsequently, industrial solar cell process technologies were applied to epilayers on highly-doped mc-Si wafers and on potential low-cost reclaimed wafers. Epitaxy and solar cell processing were successfully accomplished on all substrate types and the results show that the quality of epitaxial films deposited in the RTCVD100 reactor at Fraunhofer ISE is sufficient to reach high solar cell efficiencies. It was demonstrated that epitaxial thin-film solar cells can equally well be processed by screen printing technologies and standard cleanroom techniques irrespective of substrate material making a direct introduction of epitaxial wafer equivalents into standard industrial production lines possible. 122 6 Epitaxial thin-film solar cells

Doubling of the silicon deposition growth rate from 5 to 10 µm/min results only in minor losses in efficiency but a substantial increase in throughput, making the fast growth mode an attractive choice for high throughput manufacturing. A record efficiency of 13.1% was obtained for a 35 µm epitaxial base layer on highly doped Cz-Si substrate prepared by screen printing technologies. For the first time reclaimed single-crystal wafers were used as substrate material. The best solar cell on this substrate type reached an efficiency of

11.5% with VOC=615 mV, JSC=23.9 mA/cm² and FF=78.3% using screen printing techniques. Solar cell results and device simulation demonstrated that optical confinement schemes are essential for epitaxial thin-film cells. A significant increase in short-circuit current can be expected if e.g. front side texturing is applied. Finally, innovative future applications for epitaxial CVD layers were suggested e.g. epitaxy of emitter layers and formation of boron BSF by epitaxy or vapor-phase diffusion. 7 Silicon thin-film solar cells on insulating substrates

Silicon thin-film solar cells on low-cost substrates can significantly reduce cost for photovoltaics due to their potential for high efficiencies comparable to wafer silicon solar cells. The application of insulating substrates enables an integrated series connection of solar cells simultaneously processed on one large substrate, thus eliminating the necessity for e.g. cell connectors.

The principle layer structure and solar cell process technologies for thin- film solar cells on insulating substrates are described with respect to the high-temperature approach. Within this work various ceramic materials have been investigated as potential low-cost substrates. Multicrystalline silicon thin-films were prepared on these materials and characterized in terms of crystallographic, chemical and electrical properties. Based on these findings and on solar cell results the suitability of the examined ceramic substrates is discussed.

7.1 Solar Cell principle and technology The concept of crystalline silicon thin-film solar cells on insulating substrates is based on the preparation of a thin, active silicon base layer on a low-cost, electrically insulating substrate. Typical features of a thin-film solar cell on insulating substrate are the implementation of diffusion barriers or highly reflective intermediate layers between substrate and silicon film, the application of recrystallization steps to enlarge the grain size of polycrystalline silicon layers grown on the non- silicon substrate, bulk and surface passivation schemes, effective optical confinement features and a contact scheme, where emitter and base contacts are both located on the front side of the cell. Compared to epitaxial thin-film solar cells this cell structure is much more complex but in return it enables a series interconnection of several cells processed on the same substrate. Other advantages are the possibility to realize effective optical confinement features e.g. by using highly reflective substrates, and the independence from the use of silicon as substrate material. At Fraunhofer ISE the high-temperature approach is pursued for the preparation of silicon thin-film solar cells. This approach allows the application of APCVD for a fast deposition of silicon films, liquid-phase recrystallization of silicon layers by zone-melting and the use of conventional solar cell processing technologies.

7.1.1 Layer system Within the high-temperature approach stringent requirements are imposed on the physical properties of potential substrate materials: high-temperature stability, thermo-shock resistivity, homogeneous thermal conductivity and matching of thermal expansion coefficient (TEC) to silicon are the most important demands to be fulfilled. Combined with the request for low production cost the choice of

123 124 7.1 Solar Cell principle and technology substrate materials is limited to silicon wafers or ribbons from metallurgical grade silicon powders and different types of low-cost ceramics. The production cost for ceramic materials can be substantially reduced if inexpensive manufacturing technologies and low-cost starting powders are used. With respect to process technology the tape casting technique represents an attractive option to produce large area ceramic sheets at comparatively low expenses. The cost for ceramic powders is determined by their purity and low-cost is therefore correlated to large, mostly metallic, impurity concentrations. In silicon solar cell materials, impurities like oxygen and carbon can be tolerated in the base layer at high concentrations and are typically present up to their solubility level in commercial Cz-Si wafers15. In contrast, transition metals like e.g. vanadium or titanium are detrimental for minority carrier lifetime and cannot be accepted even in concentrations below 1 ppba [140]. Using substrates with high impurity concentrations, the active silicon layer is endangered to be contaminated during high- temperature processing by impurities diffusing out of the substrate. Such a contamination can be reduced or entirely avoided if adequate diffusion barriers are implemented. Similar to the substrate material, the barrier layers must be chemically and mechanically stable during the entire sample preparation and solar cell process. In addition the deposition of these layers must be industrially feasible and inexpensive. A combination of silicon dioxide and silicon nitride layers effectively prevents the diffusion of many harmful transition metals and is known to resist high temperatures [141]. Using APCVD these layers can be deposited at comparatively low cost. PECVD

SiO2 or SiO2/SiNx layer stacks are used as standard barrier layers at Fraunhofer ISE. The direct deposition of a silicon layer onto a foreign substrate by CVD results in polycrystalline films featuring small grain sizes in the range of 1 µm. Solar cells prepared on such low-quality layers are typically limited in performance by large saturation currents and shunts. Most thin-film concepts therefore apply a recrystallization step, where the polycrystalline silicon is transformed into a layer with coarse grained crystal structure. Recrystallization can be done e.g. by laser or optical systems, with the latter technique being used within the frame of this work. A detailed description of the ZMR apparatus constructed and used at Fraunhofer ISE can be found in [142]. The recrystallized layer is usually heavily doped and represents the back surface field and the base contact of the cell. Finally, the active base layer with thickness below 50 µm is epitaxially grown onto the recrystallized multicrystalline layer. Excellent efficiencies of 16% have been reported by Mitsubishi Electric Corporation for a large area 100x100 mm2 silicon thin-film solar cell on a SOI16 structure prepared by ZMR demonstrating the potential of this technique [143].

7.1.2 Cell technology For solar cell processing samples based on contaminated substrate materials have to be encapsulated to prevent an out-diffusion of harmful impurities. Using porous substrates, the encapsulation at the same time serves as a shield against penetration of chemicals and filling of the open pores during wet

15 18 -3 17 -3 Impurity concentrations in Cz: C(O2) ≤ 2x10 cm , C(C) ≤ 5x10 cm [103]. 16 SOI: Silicon On Insulator. 7 Silicon thin-film solar cells on insulating substrates 125 chemical processing. Alternatively, a completely dry solar cell process can be applied, where no additional encapsulation is necessary. In [144] the successful dry processing of a silicon thin-film solar cell on graphite substrate was reported. The application of insulating substrates requires a contact scheme where both, emitter and base contacts, are located on the front side of the solar cell. Alternatively, electrical contact to the base can also be provided by a highly conductive layer at the back of the base. In [145] an interdigitated grid design has been applied to thin-film solar cells prepared by the SIMOX17 technology leading to high efficiencies of up to 19.2%. In [146] the concept of interdigitated grid has been transferred to industrial relevant processing techniques. Within this study different technological realizations of an interdigitated grid were investigated and in conclusion best results were achieved using the BBC-concept (Buried Base Contacts). This concept employs homogeneous emitter diffusion, screen printing of an etch resist pattern for the definition of the base region, local etching of the emitter by RIE, stripping of the etch resist, surface cleaning by oxygen plasma and screen printing of both contact grids. Using this technique efficiencies of up to 11.5% could be achieved on Cz-Si wafers [119]. Typical thin-film systems based on recrystallized and epitaxially thickened silicon layers feature an increased surface roughness which imposes high demands on the technology of contact formation. Recent results on the application of the BBC-concept to silicon thin-film structures showed that surface roughness in fact represents a severe problem for contact formation and that large shading losses due to the two front contact grids limit the cell efficiency [147].

7.2 Silicon thin-film solar cells on ceramic substrates During the last decade, a large variety of different potential low-cost ceramics including graphite 18 [148], SiSiC [149], Mullite [150], SiAlON [151], Al2O3 [152], SiN [141] and ZrSiO4 [153] has been tested as substrate material. Table 7.1 gives an overview on the best efficiencies achieved so far for silicon thin-film solar cells on ceramic substrates. Zone-melting recrystallization has been applied for the preparation of all solar cells. For comparison, the best result obtained for a thin-film solar cell with recrystallized layer on a SiO2 encapsulated single-crystal silicon substrate is added. The work presented in this chapter has been accomplished within the frame of the European SUBARO19 project. One of the major objectives of this project is to evaluate the application of different ceramics as substrate materials for a cost-effective preparation of silicon thin-film solar cells.

17 SIMOX: Separation by Implanted Oxygen.

18 Mullite: Stable phase in the SiO2-Al2O3 system. 19 SUBARO: Substrate and barrier layer optimization for CVD-grown thin-film crystalline Si solar cells. 126 7.2 Silicon thin-film solar cells on ceramic substrates

Substrate Barrier layer Base Area Solar cell process Efficiency Ref. [µm] [cm²] [%]

Single crystal Si Thermal SiO2 50-60 4 Conventional contacts by via-holes 16.45 [20] Texture, hydrogen passivation Graphite LPCVD-SiC 30 1 Conventional contact scheme 11.0 [144] (conductive) RPHP20 Mullite ONO 49 1 Hydrogen passivation 8.2 [150]

ZrSiO4 ONO 30 1 Texture, RPHP 8.3 [153]

Si3N4 ONO 30 1 Texture, RPHP 9.4 [141] SiSiC ONO/µc-Si/ONO 30-90 1 Dry solar cell process 9.3 [149]

Table 7.1: Efficiency table for crystalline silicon thin-film solar cells on ceramic substrates.

7.2.1 Material and solar cell preparation

Within this work, tape cast SiAlON and Si3N4 ceramics, hot-pressed Si3N4 and reaction-bonded silicon-infiltrated SiC (SiSiC) ceramics have been investigated as substrate material. All of these ceramics feature a thermal expansion coefficient close to silicon and are known to resist high temperatures. The suitability of the materials in terms of cost-effectiveness is evaluated within the SUBARO project. All samples were treated by the same process steps and were characterized by the same methods to allow for a direct comparison of sample properties. In Figure 7.1 the sample structure (left) and process sequence for sample preparation (right) are illustrated.

PECVD of SiO capping layer Epitaxial base Wet chemical cleaning 2 25 µm Zone-melting High-temperature anneal Recrystallized silicon layer (BSF) recrystallization (ZMR) 10 µm 1 µm SiO 2 O Removal of capping layer and Wet chemical cleaning 100 nm SiNx N pre-epitaxial cleaning 1 µm SiO2 O

PECVD of ONO barrier layer CVD of epitaxial base layer

CVD of silicon seeding layer Solar Cell Process Ceramic substrate

Characterization

Figure 7.1: Schematic of realized sample structure (left) and process sequence for the preparation of silicon thin-films on ceramic substrates (right).

20 RPHP: Remote Plasma Hydrogen Passivation. 7 Silicon thin-film solar cells on insulating substrates 127

After a wet chemical cleaning all ceramic substrates were treated by a high-temperature annealing step at 1200°C under nitrogen atmosphere. A second cleaning step was included to remove any impurities which might have formed on the sample surface during thermal anneal. Subsequently the ceramic substrates were encapsulated by an oxide-nitride-oxide (ONO) barrier layer system of 1 µm SiO2,

100 nm SiNx and 1 µm SiO2 deposited by PECVD. The application of an ONO system as intermediate layer is based on results presented in [154], where its effectiveness as diffusion barrier for different transition metals is reported. For part of the samples a 2 µm PECVD SiO2 layer has been used instead of the ONO stack for comparison. On top of the intermediate layer a thin (10-15 µm), highly doped silicon film was grown by APCVD at 950°C (seeding layer). Because of the high doping level above 1x1018 cm-3 this layer serves as back surface field in the final solar cell structure. Prior to ZMR the silicon film was covered by a 2 µm thick SiO2 capping layer deposited by PECVD to prevent balling- up of the liquid silicon during recrystallization. After ZMR the capping layer was removed by hydrofluoric acid and a short CP-133 etch was applied for pre-epitaxial cleaning of the silicon surface. Finally, the active base layer was grown epitaxially onto the recrystallized silicon film by APCVD. After seeding layer deposition and epitaxy the samples were characterized by optical Nomarski- interference microscopy and SEM on cross sections and surfaces. Doping and impurity concentration were measured across the entire layer system using SRP and Glow-Discharge Mass Spectrometry (GDMS). During ZMR two CCD cameras enabled an in situ observation of the zone-melting process. The shape of the solidification front, the width and the shape of the molten zone gave additional information on the crystal quality of the recrystallized layers but also on thermal properties of the substrate or the entire sample.

Separation of base and Alkaline texturing emitter contact grid emitter by RIE base contact DLARC Emitter formation by POCl3- Photolithographic definition diffusion of base contacts

Photolithographic definition Evaporation of Al for base of emitter contact grid frame contact

Evaporation and electro p-type base n+ p+ RPHP plating of emitter contacts ceramic substrate Photolithographic definition Deposition of DLARC of solar cell area barrier layers

Figure 7.2: Solar cell scheme and processing sequence for one-side contacted solar cells on insulating substrates prepared within this work.

Solar cells were prepared on samples based on Si3N4 and SiSiC ceramic substrates using a cleanroom process with photolithographic process steps. Figure 7.2 shows the mesa-like solar cell structure realized on all samples. The solar cell formation included alkaline etching of the silicon base layer for light trapping, homogeneous emitter diffusion in a closed tube furnace from POCl3 source (100 Ω/sq), photolithographic definition of emitter contact grid, evaporation of TiPdAg and electro plating of emitter contacts, photolithographic definition of solar cell area and separation of emitter and base by RIE, photolithographic definition of base frame contact, evaporation of Al for base contact, Remote 128 7.2 Silicon thin-film solar cells on ceramic substrates

Plasma Hydrogen Passivation (RPHP) and deposition of a double layer antireflection coating 2 (DLARC) of TiO2/MgF2. Solar cells with an area of 1 cm were prepared. Using this solar cell process an efficiency of 13.5% has already been reached for a recrystallized silicon film on SiO2-encapsulated mc-Si substrate [69]. The rough surface induced by the alkaline texture made the application of photolithographic steps difficult. Local accumulation of etch resist, inhomogeneous thickness of the masking oxide layer and non-optimized exposure times lead to an incomplete exposure, leaving locally undeveloped areas. As a consequence the emitter grid lines were partly interrupted, very thin or sometimes even separated from the bus bar. Neither hydrogen passivation nor antireflection coating were optimized for this solar cell structure. Altogether there is still room for improvement from the viewpoint of solar cell processing technology. The resulting solar cells were analyzed by illuminated and dark I/V-characteristics, spectral response and SR-LBIC measurements. Combined with the results obtained from sample material characterization, an evaluation of the different ceramic materials for an application in thin-film silicon solar cells was accomplished.

7.2.2 Silicon thin-films on silicon-infiltrated silicon carbide ceramics (SiSiC) Reaction bonded silicon-infiltrated silicon carbide (SiSiC) substrates were provided by the company H.C. Starck Ceramics (Selb, Germany). According to the manufacturer the SiSiC contained 0.34 wt% of boron making the ceramic electrically conductive. The 900 µm thick samples were single-side polished and featured an open porosity below 1%. In general, SiSiC is resistant to temperatures up to the melting point of silicon, it is very hard and its thermal expansion coefficient is close to that of silicon21. The silicon-infiltrated silicon carbide consists of a SiC matrix with silicon filling up the pores thus giving a low bulk porosity.

Sample preparation and characterization

Silicon layers deposited on ONO and SiO2-encapsulated SiSiC ceramic substrates featured a homogeneous surface morphology. A microscopic characterization of cross sections revealed smooth substrate surfaces covered by undamaged and equally smooth intermediate layers (Figure 7.3), indicating that substrate, barrier and silicon layer fit together in terms of thermal, mechanical and chemical stability for process temperatures up to 950°C. Recrystallization of the silicon seeding layers was successful and partly dendritic and cellular growth fronts dominated the recrystallization process. The dendritic growth mode could be associated to a supercooling in the silicon melt caused e.g. by high impurity concentrations in the melt [156]. A cellular (or facetted) growth front generally indicates an oriented growth of high-quality crystallites. Although the dendritic growth mode is less favorable than the cellular one, large grains could be obtained.

21 TEC of silicon: 2.616-4.5x10-6 K-1 (300-1400K) [155]. 7 Silicon thin-film solar cells on insulating substrates 129

p+-Si ONO

SiSiC ceramic

10 µm

Figure 7.3: Cross section micrograph of SiSiC ceramic substrate with ONO barrier layer and silicon seeding layer (p+-Si).

Chemical and electrical analysis

To evaluate the efficiency of the applied barrier layers (SiO2 and ONO) the chemical composition of the entire layer stack from epitaxial base to substrate was characterized by GDMS. Figure 7.4 (left) shows the impurity concentration profile measured for a silicon film on SiSiC ceramic substrate encapsulated by a 2 µm SiO2 barrier layer. The highly doped recrystallized silicon seeding layer is denoted by p+-Si (BSF) while the epitaxial layer corresponds to the p-Si region. The location of the BSF can be easily identified by an increase of the boron signal. The onset of the substrate is visible as a rise in the characteristic impurity concentration of the corresponding substrate material, which is carbon for SiSiC. Because of the measurement principle the depth resolution is limited and the location of the interface between different regions can only be approximated. Hollow symbols denote measurement signals below the detection limit.

20 6 10 10 B11 5 p-Si p+-Si SiO C12 10 2 N14

4 P31 ] 19 10 -3 10 Ti48 103 V51 Cr52 2 10 Mn55 18

10 1 Fe56 10 Substrate Ni58 Cu63 100 Base BSF 17 10-1 10

Concentration [ppma] -2

10 Carrier[cm Density -3 10 1016 012345678910 5 1015202530 Sputter time [A.U.] Depth [µm]

Figure 7.4: Left: GDMS impurity profile of a silicon film prepared on a SiO2 encapsulated SiSiC ceramic substrate. Right: Corresponding carrier density profile.

The GDMS measurement reveals a large contamination of the ceramic substrate by boron, phosphorus and various transition metals. Concentrations of 103 ppma and 20 ppma were determined for boron and iron respectively with the boron corresponding to the suppliers specification of 0.34wt%. 130 7.2 Silicon thin-film solar cells on ceramic substrates

Noticeable amounts of phosphorus and the transition metals titanium, vanadium, chromium, manganese and nickel in the order of 0.1-2 ppma were detected in the SiSiC substrate. Within the barrier and BSF layer the concentration of all impurity elements decreases substantially and in the base layer only iron and nickel are still detected in concentrations in the range of 0.01 ppma. This corresponds to a reduction by three and two orders of magnitude respectively, compared to the substrate concentration. With the application of an ONO intermediate layer, the signal for the transition metals similarly decreases in the p+-region and is below the detection limit within the epilayer. An exception to this general feature is iron: while no iron can be detected in the bulk of the base, a concentration in the range of 4 ppba is measured in the surface-near region. This result indicates that a transfer of impurities has occurred from substrate to silicon layer system in spite of the ONO barrier. Assuming a damage of the ONO layer such a transfer can either occur by diffusion or by a mixing of liquid silicon coming from the substrate and the seeding layer during ZMR. Since no damage was observed by optical microscopy, the scale length of the perforation must be in a range below the resolution limit of the microscope. The accumulation of iron near the sample surface might be caused by segregation. In Figure 7.4 (right) the carrier concentration profile measured for a silicon film on SiSiC with ONO barrier layer is shown. The measured data correspond to the concentrations determined by GDMS. The carrier density in the BSF layer exceeds 1019 cm-3 although the seeding layer deposition process typically results in concentrations in the range of several 1018 cm-3. The increased doping density confirms that a diffusion of impurities must have occurred from substrate to silicon layer system.

Solar cells on SiSiC ceramic substrates A maximum efficiency of 10.7% was achieved for a 25 µm silicon base layer on SiSiC ceramic substrate with ONO barrier layer. This solar cell was measured at the Fraunhofer ISE Calibration

Laboratory and featured a VOC of 554 mV, JSC=28.9 mA/cm² and FF=66.8%. This represents an excellent result for a thin-film solar cell on ceramic substrate (compare Table 7.1). Because of the dendritic growth mode affecting the recrystallization process and the resulting regions of minor crystal quality, the obtained efficiencies varied over a wide range from 3.4 to 10.7%. The low quality of part of the silicon layers gave rise to high saturation currents of the space charge region and low parallel resistance leading to fill factors below 50%. In the following the characteristics of the best solar cell is discussed in more detail. In Figure 7.5 the dark I/V characteristic (left) and internal quantum efficiency curve (right) are illustrated for the best solar cell. The dark current characteristics shows that the solar cell performance is mainly affected by a large saturation current of the space charge region, thus reducing the fill factor. The series resistance is comparatively low, indicating a sufficient thickness and doping level of the back surface field which also serves as back side contact. In the short-wavelength range, the internal quantum efficiency (Figure 7.5, right) reaches high values above 90%. The drop in spectral response around a wavelength of 600 nm is determined by the low minority carrier lifetime in the base. In the range of 900-1000 nm an increase in IQE is obtained due to the optical confinement induced by the ONO intermediate layer. Light reflected by the ONO layer is absorbed in the base layer and contributes to short-circuit current. 7 Silicon thin-film solar cells on insulating substrates 131

100

10-1

-2 1.0 10

10-3 0.8

-4 10 0.6

10-5

IQE 0.4 10-6 Current density [A/cm²] Current density 0.2 10-7 0.0 0.0 0.2 0.4 0.6 400 600 800 1000 1200 Voltage [V] λ [nm]

Figure 7.5: Dark current characteristic (left) and internal quantum efficiency (right) for the best silicon thin-film solar cell on SiSiC ceramic substrate.

Figure 7.6 shows a map of effective minority carrier diffusion length calculated from SR-LBIC and reflection measurements (left) and the corresponding histogram (right). The topography of Leff verifies that regions which were affected by dendritic growth (“branches” covering the bottom and part of the right side of the cell) result in low minority carrier diffusion lengths. The average effective minority carrier diffusion length of 24 µm calculated from the histogram is in the range of the base layer thickness, in accordance to the comparatively large efficiency obtained for this cell.

10000 Leff [µm]

>50 8000

6000 average L = 24µm 4000 eff Counts 2000

0 0 0 10203040506070 0246810 L [µm] mm eff

Figure 7.6: Topography of effective minority carrier diffusion length as calculated from SR-LBIC and reflection measurements (left) and corresponding histogram (right).

To examine the assumption of a damaged barrier layer, an aluminum back contact was evaporated on part of the solar cells to enable conventional 2-side contacting. Independent from contact scheme the same illuminated I/V-characteristics were measured, proving the permeability of the intermediate layer. 132 7.2 Silicon thin-film solar cells on ceramic substrates

Summary Sample preparation and solar cell processing were successfully accomplished on SiSiC ceramic substrates. Chemical analysis of the substrate material revealed a high contamination level of transition metals, phosphorus and boron. An improved barrier effect against these impurities was demonstrated for the ONO intermediate layer compared to SiO2. However, the detection of an increased boron concentration in the recrystallized silicon layer, contamination of surface-near regions of the epilayer by iron and finally the possibility to use a conventional 2-side solar cell contact scheme showed that the ONO layer was not completely stable to all process steps. During recrystallization the silicon layers were mainly affected by a dendritic growth mode, probably induced by inhomogeneous thermal properties of the substrate or a contamination of the silicon seeding layer by iron. Areas affected by dendritic growth featured low local short-circuit current densities. A confirmed efficiency of 10.7% was obtained for the best solar cell. This efficiency exceeds the record value which has been published up to now for a similar solar cell structure [149] by 1.4% absolute.

7.2.3 Silicon thin-films on hot-pressed silicon nitride ceramics

High density, non-conductive hot-pressed Si3N4 ceramic substrates were provided by H.C. Starck Ceramics (Selb, Germany). The 530 µm thick samples were polished on one side to give optimal surface conditions and an open porosity below 1% was specified. Silicon nitride ceramics in general are known for their excellent mechanical stability even at high temperatures and their resistance to thermal shock. The thermal expansion coefficient of silicon nitride lies between 2.9x10-6-3.6x10-6 K-1 for a temperature range of 273-1473K, which is slightly lower compared to silicon. The manufacturing of Si3N4 by hot pressing allows the preparation of very dense materials.

Sample preparation and characterization

The deposition of silicon seeding layers on encapsulated hot-pressed Si3N4 ceramic substrates resulted in homogeneous films. The cross section image in Figure 7.7 shows a planar substrate surface with closed ONO layer.

p+-Si ONO

Hot-pressed Si3N4 ceramic

10 µm

Figure 7.7: Nomarski microscope image of a sample cross section after silicon seeding layer deposition (Secco etched). 7 Silicon thin-film solar cells on insulating substrates 133

The samples were found to respond well to the recrystallization process: cellular or planar growth fronts indicating an oriented crystal growth with low defect density, were the dominating features. The width of the molten zone remained constant and stable during most recrystallization processes which means that the thermal properties of the entire sample and especially the substrate are homogeneous. Large grains up to several millimeters in width and several centimeters in length were obtained by ZMR. After epitaxy, cracks were found to penetrate the entire silicon film from barrier layer to epilayer surface (Figure 7.8). The development of these cracks could be a consequence of a difference in thermal expansion coefficient between substrate and silicon films. Stress, which might have built up during the cooling period of the epitaxy process could result in the formation of cracks. An analysis of sample cross sections revealed a damage of both barrier layer types - SiO2 and ONO - after epitaxy.

p-Si Crack p+-Si

ONO

Hot-pressed Si3N4 ceramic

10 µm

Figure 7.8: After epitaxy, cracks penetrate the entire silicon film. Left: SEM image of sample surface. Right: Optical micrograph of sample cross section (Secco etched).

Chemical analysis The chemical analysis of silicon layer system and substrate by GDMS (Figure 7.9) revealed comparatively low impurity concentrations in the ceramic substrate: phosphorus and iron are detected with concentrations of 0.1 ppma, while other metallic transition elements like e.g. titanium, chromium, vanadium and nickel occur in concentrations below 0.1 ppma. Except for iron no other transition element was detected in the silicon film, independent from the applied barrier layer. With a concentration in the range of 1 ppba, the iron content in the silicon is comparatively low but can still be harmful to minority carrier lifetime. The detection of iron in the silicon film is consistent with the observed perforation of both barrier layer types which enables a diffusion of impurity atoms from the substrate into the silicon layer during high-temperature processing. 134 7.2 Silicon thin-film solar cells on ceramic substrates

5 10 B11 4 p-Si p+-Si SiO C12 10 2 N14 3 P31 10 Ti48

2 V51 10 Cr52

1 Mn55

10 Fe56

Substrate Ni58 0 10 Cu63 10-1

-2 Concentration [ppma] Concentration 10

10-3 01234567891011 Sputter time [A.U.]

Figure 7.9: GDMS measurement for a silicon thin-film prepared on hot-pressed silicon nitride

ceramic substrate with SiO2 barrier layer.

Solar cells on hot-pressed Si3N4 ceramic substrates

Solar cells prepared on silicon films on hot-pressed Si3N4 ceramic substrates showed only little photovoltaic activity, if any at all. The best solar cell reached an efficiency of 2% with VOC=398 mV, 2 JSC=15.9 mA/cm and FF=32%. The characteristics of this cell are discussed in the following. Considering the dark current characteristics graphed in Figure 7.10 (left) it is evident, that the solar cell under consideration suffers from extremely low parallel resistance and an increased series resistance. In addition, large saturation currents affect the solar cell performance. Parallel and series 2 2 resistance were determined to RP=32 Ωcm and RS=2.4 Ωcm by fitting the dark I/V curve The internal quantum efficiency measurement (Figure 7.10, right) reveals a low response across the entire spectral range, confirming the measured low short-circuit current density. In the long- wavelength range the optical confinement by the ONO barrier layer is visible as a slight increase around a wavelength of 1000 nm. In Figure 7.11 (left) a topography of effective minority carrier diffusion lengths and a corresponding microscope image of sample surface and cross section (Figure 7.11, right) are depicted. The Leff mapping shows that distinct regions of the solar cell suffer from low effective minority carrier diffusion lengths. The right-angled network visible in the map was identified as cracks in the silicon film. Similar observations were already reported in [141]. The penetration of the cracks from epilayer surface to isolating barrier layer results in a splitting up of the entire solar cell area in single regions, which are electrically isolated from each other. As a consequence, the emitter contacts are partly interrupted, a complete electro plating of evaporated contacts becomes impossible and the solar cell suffers from large series resistance. Areas which are completely isolated are characterized by a zero effective diffusion length. These regions cannot contribute to photocurrent. 7 Silicon thin-film solar cells on insulating substrates 135

100

-1 1.0 10

0.8

10-2 0.6

IQE 0.4 10-3 Current [A/cm²] density 0.2

10-4 0.0 0.0 0.2 0.4 0.6 400 600 800 1000 1200 Voltage [V] λ [nm]

Figure 7.10: Left: Dark current characteristics for thin-film solar cell on hot-pressed Si3N4 ceramic with ONO barrier layer. Right: Corresponding internal quantum efficiency curve.

L [µm] eff Crack

>30 Contact finger

100 µm

Contact finger

0 Si-film Crack

0246810 mm 10 µm

Figure 7.11: Left: Topography of effective minority carrier diffusion length as calculated from SR-

LBIC measurements. The straight lines with increased values of Leff correspond to cracks, visible in the micrograph of the solar cell surface (right, top) and cross section (right, bottom).

An increased effective diffusion length is observed on sites of cracks. This phenomenon can probably be explained by the formation of vertical pn-junctions during emitter diffusion. For carriers generated near the crack, lower diffusion lengths are necessary to reach the vertical pn-channel instead of the homogeneous emitter on the front surface, thus increasing the collection efficiency in these areas. In 136 7.2 Silicon thin-film solar cells on ceramic substrates

Figure 7.11 (right, bottom) a filling of the gaps by contact metal is visible. If the emitter does not cover the flanks of the cracks, this would give rise to a short circuit of emitter and base.

Summary

Silicon seeding layer deposition and recrystallization process worked well for hot-pressed Si3N4 ceramic substrates. During epitaxy, cracks developed in the silicon layer system, possibly due to a difference in thermal expansion coefficient between substrate and silicon. In addition, a perforation of the barrier layers was observed after epitaxy. Iron was found to contaminate the base layer independent from barrier layer system. A concentration in the range of 1 ppb was detected, indicating a diffusion of iron from the ceramic substrate into the silicon film. The performance of the processed solar cells is limited by the presence of electrically isolated regions generated by the cracks.

7.2.4 Silicon thin-films on tape cast silicon nitride ceramics

Tape cast Si3N4 ceramic substrates were supplied by the Netherlands Energy Research foundation ECN (Petten, The Netherlands). After sintering, the tape cast samples featured a thickness of only

240 µm. Compared to the preparation of Si3N4 by hot pressing, the tape casting method represents an industrially relevant technique for the manufacturing of large-area ceramic sheets at low cost.

Sample preparation and characterization Figure 7.12 shows an optical microscope image of a sample cross section after silicon seeding layer deposition. The substrate surface is comparatively rough, but barrier layer and silicon film follow the given surface topology. The ONO intermediate layer is damaged, with the gaps being filled up with silicon, indicating that they probably developed during the heating up phase of the silicon deposition process. Chemical reactions or mechanical stress between substrate and intermediate layer might have caused this damage. After seeding layer deposition the samples were slightly bowed. This bending deteriorated with every additional high-temperature step during the entire process sequence. A difference in TEC between ceramic substrate and silicon layer is assumed to result in a tensile stress in the silicon layer which subsequently causes the thin sample to bend.

p+-Si ONO Crack

Tape cast Si3N4 ceramic

10 µm

Figure 7.12: Cross section of tape cast Si3N4 ceramic substrate with ONO barrier and silicon seeding layer (Nomarski microscope image). 7 Silicon thin-film solar cells on insulating substrates 137

An inhomogeneous width of the molten zone dominated the recrystallization process. In some areas the molten zone even reached the back of the sample i.e. the whole substrate was molten through. Due to the resulting low temperature gradient, the crystal structure of the recrystallized silicon film was characterized by small grains in these regions. A facetted growth front was observed on part of the samples, indicating oriented crystal growth. In this case, large grains of several mm in width and several cm in length developed. In general, an inhomogeneous width of the molten zone reflects inhomogeneous thermal properties of the substrate, assuming uniform properties of the silicon film and barrier layer. Incomplete mixing of the starting powders or non-uniform sintering conditions may cause such inhomogeneities when tape cast Si3N4 is used as substrate material. Because of the severe bending of the samples, the sample back side was only in local contact to the carrier quartz plate during ZMR, thus generating “hot spots” where a melting through was facilitated. To prevent such hot spots a quartz plate with cut-out in the center was used such that the samples were only supported at the edges by the quartz plate. The image in Figure 7.13 (left) shows the cross section of a sample after epitaxial deposition of the base. On elevated sites of the substrate surface the seeding layer is no longer present and a polycrystalline silicon layer has grown on the exposed barrier layer during epitaxy. The holes in the seeding layer are assumed to develop during ZMR and subsequent etching. During ZMR liquid silicon can accumulate in the lower seated parts of the substrate surface, thus reducing the film thickness on elevated sites. In the following pre-epitaxial cleaning step a thin layer is removed from the surface leading to the formation of holes on these sites. For substrates featuring a very large surface roughness holes can also form during the recrystallization step already, if the deposited silicon seeding layer is very thin. As a general rule, the seeding layer thickness should exceed the surface roughness of the substrate.

Figure 7.13: Left: Cross section of recrystallized and epitaxied silicon film on tape-cast Si3N4 (Secco etched, microscope image). Right: Image of a sample surface after epitaxy. The white contour marks an area which was molten through during ZMR.

Figure 7.13 (right) shows the surface of a recrystallized and epitaxied silicon film on tape cast Si3N4. The white contour encloses a region, which has been molten through during ZMR. Small grains and large defect densities characterize this area, while large grains were obtained for the remaining silicon film. In some areas, the epitaxial layer is affected by whisker growth, probably induced by a contaminated surface of the recrystallized layer. 138 7.2 Silicon thin-film solar cells on ceramic substrates

Chemical and electrical analysis

In Figure 7.14 (left) the GDMS impurity profile for a silicon film prepared on tape cast Si3N4 is depicted. The boron concentration remains on a more or less constant level throughout the entire profile, which means that either no BSF is present or the sputter depth was too low. The corresponding SRP measurement (Figure 7.14, right) shows, that the back surface field features a doping level of 2x1018 cm-3, compared to a carrier density of 8x1016 cm-3 in the base layer. Both regions can be clearly identified in the SRP profile, thus verifying that only the epilayer was characterized by the GDMS measurement. With increasing depth the impurity concentration of nitrogen, iron and chromium in the silicon base layer increases by one to three orders of magnitude. For the transition metals iron and chromium maximum concentration of 1.4 ppma (6x1016 cm-3) and 0.1 ppma (5x1015 cm-3) were measured respectively. These values are in the range of their solubility limit in silicon given in literature22. The presence of these impurities in the silicon film can be traced back to the perforation of the ONO barrier layer, which was already observed after seeding layer deposition. During high-temperature processes like epitaxy and especially ZMR fast diffusing elements like iron and chromium can easily overcome the barrier layer and contaminate the silicon film.

5 19 10 B11 10 4 C12 Base BSF 10 N14

3 P31 ] 10 Ti48 -3 18 2 V51 10 10 Cr52

1 Mn55

10 Fe56 Ni58 0 10 Cu63 1017 10-1

-2 Concentration [ppma]

10 Carrier[cm Density

10-3 1016 1234567 5 10152025303540 Sputter time [A.U.] Depth [µm]

Figure 7.14: GDMS (left) and SRP (right) measurement carried out for a silicon film based on tape

cast Si3N4 ceramic substrate.

Solar cells on tape cast Si3N4 ceramic substrates A batch of solar cells containing 15 samples has been prepared on silicon thin-films on tape cast silicon nitride ceramics. The severe bending of the samples made the entire processing and especially the photolithographic steps difficult. The batch turned out to be very inhomogeneous with efficiencies ranging from 3 to 8.1%. Low fill factors of 36 to 61% and short-circuit current densities of 18.4 to 25.9 mA/cm² determine the solar cell performance, with the fill factor being mostly the limiting factor. The best solar cell featured an efficiency of 8.1%, with VOC=530 mV, JSC=24.9 mA/cm² and FF=61.2%.

22 16 -3 15 -3 CFe(1300°C) = 5x10 cm , CCr(1280°C) = 2.5x10 cm , according to [77]. 7 Silicon thin-film solar cells on insulating substrates 139

An analysis of dark I/V-curves showed that the prepared solar cells suffer from low parallel resistance, increased values for I02 and high series resistance, resulting in the observed low fill factors. Fitted I/V- 2 2 parameters yield values for RP and RS below 1000 Ωcm and above 3 Ωcm respectively. Low parallel resistance and high saturation currents are attributed to a minor crystal quality of the recrystallized and epitaxially thickened silicon layers. The large series resistance might be caused by an increased contact resistance as a result of defective photolithography processes associated to the bending of the samples. Apart from that, the low doping density and thickness of the BSF layer might cause an increase in series resistance. The graph in Figure 7.15 visualizes the inhomogeneity of the entire batch in terms of solar cell efficiency and demonstrates the effect of hydrogen passivation and double layer antireflection coating. The application of hydrogen passivation resulted in an average increase in efficiency by 5% relative. The samples show a large scatter in their response to the passivation step. Typically the improvement in open-circuit voltage and fill factor by hydrogen passivation increases with decreasing crystal quality for silicon films prepared by ZMR [69] i.e. a larger boost in efficiency can be expected for solar cells based on low quality films. This characteristic does not apply in this case. The open-circuit voltage of all solar cells benefits from the passivation step leading to an increase between 9 and 37 mV. Similarly larger short-circuit currents are measured for most cells after passivation. However, significant improvements in fill factor are observed only for a few cells. The defective emitter contact grid might be the reason for this result.

14 13 After ARC 12 After RPHP 11 Before RPHP 10 9 8 7 6 5 4 Efficiency [%] Efficiency 3 2 1 0 Solar cells on tape cast Si N 3 4 FZ-Ref.

Figure 7.15: Impact of hydrogen passivation and antireflection coating on solar cell efficiency.

A gain of 11% relative in short-circuit current density was obtained by the deposition of a double layer antireflection coating. A larger boost in short-circuit current is observed for the FZ-Si reference solar cell because no texturing has been applied in this case. The internal quantum efficiency was calculated from spectral response and reflection measurements for the best solar cell prepared within this batch. The characteristic in Figure 7.16 reveals an effective blue response exceeding 90%. The curve features a decrease in IQE at a comparatively low wavelength of 500-600 nm due to a low minority carrier lifetime in the base. At a wavelength of 140 7.2 Silicon thin-film solar cells on ceramic substrates

1000 nm an enhanced response is obtained as a result from optical confinement introduced by the ONO barrier layer.

1.0

0.8

0.6

IQE 0.4

0.2

0.0 400 600 800 1000 1200 λ [nm]

Figure 7.16: Internal quantum efficiency for silicon thin-film solar cell on tape cast Si3N4 ceramic substrate.

In addition, the SR-LBIC technique was applied to create a mapping of effective minority carrier diffusion lengths, calculated from local short-circuit currents and corresponding reflectivity. In Figure 7.17 the mapping and the corresponding histogram are given. A fairly homogeneous distribution in minority carrier diffusion length across the entire cell area is obtained. On the left-hand side of the cell a region with increased diffusion length is observed indicating a better crystal quality of the corresponding grain compared to the remaining area. The histogram shows that only a small fraction of diffusion lengths exceeds the thickness of the base layer. An average value of 11 µm was calculated from the histogram.

16000 Leff [µm] 14000 >24 12000 average L = 11µm 10000 eff 8000 6000 Counts 4000 2000 0 0 0 5 10 15 20 25 30 35 40 0246810 L [µm] mm eff

Figure 7.17: Mapping of effective minority carrier diffusion length (left) and corresponding histogram (right) of the solar cell with best efficiency.

The large concentration of the transition metals chromium and especially iron within the silicon film is assumed to cause a severe reduction in minority carrier diffusion length, thus being the limiting factor for solar cells with complete and undamaged contact grids. 7 Silicon thin-film solar cells on insulating substrates 141

Summary

The preparation of silicon thin-films on tape cast Si3N4 ceramic substrates was affected by a perforation of the ONO barrier layer after seeding layer deposition, inhomogeneous recrystallization behavior and melting through of the samples. The silicon layers were found to be contaminated by metallic impurities (mainly iron) which diffused from the substrate into the silicon layer during high- temperature processing. A severe bending of the samples was observed, which might be attributed to a mismatch in thermal expansion coefficient between substrate and silicon film.

For the first time, silicon thin-film solar cells have been prepared on tape cast Si3N4 ceramic substrates. A maximum efficiency of 8.1% was achieved, which represents a remarkable result considering that neither substrate properties nor solar cell processing were optimized. The optimization of the tape cast Si3N4 ceramic material in terms of thermal and chemical properties represents a major challenge for future activities in this area.

7.2.5 Silicon thin-films on SiAlON ceramics Tape cast SiAlON ceramic substrates were provided by the Netherlands Energy Research foundation

ECN (Petten, The Netherlands). The non conductive sheets were made from commercial Si3N4, AlN and Al2O3 powders. After sintering, open and bulk porosity were determined to values below 1% and 10% respectively. The substrate thickness was specified to 460±30 µm and according to suppliers information the TEC ranged between 4 to 5x10-6 K-1.

Seeding layer deposition and zone-melting recrystallization Silicon CVD on ONO encapsulated SiAlON substrates was non-ideal and resulted in inhomogeneous silicon layer thickness. Severe whisker growth affected the quality of the deposited silicon films. After seeding layer deposition the layer system was analyzed by microscopy on cross sections and sample surfaces. The SEM cross section image in Figure 7.18 reveals a severe damage of the ONO barrier layer. At intervals of few microns, the intermediate layer is interrupted by cracks.

p+-Si

SiO2

SiNx

SiO2 Crack

SiAlON substrate

Figure 7.18: Cross section image of a silicon seeding layer grown on SiAlON substrate with ONO barrier layer (Secco etched, SEM image).

The development of fissures may be explained by thermal stress which builds up between the substrate and the layer system during the heating or the cooling phase of the silicon deposition process. Second, 142 7.2 Silicon thin-film solar cells on ceramic substrates some kind of chemical reaction could have take place between the substrate components and the intermediate layer during the CVD process, where the samples are heated to 950°C. The observed growth of whiskers might be caused by the diffusion of impurities from the substrate to the sample surface, where they act as nucleation centers for a defective growth mode [157]. The recrystallization process was characterized by an inhomogeneous width of the molten zone, balling up of the liquid silicon, infiltration-like features and in general little oriented crystal growth. The bone-shaped, inhomogeneous width of the molten zone might be caused by inhomogeneous thermal properties across the substrate area. The already damaged barrier layer and the large bulk porosity may in fact lead to an infiltration of the liquid silicon into the substrate material. The silicon seeding layers were only partly recrystallized and in most cases a peeling off of the silicon layer occurred. In conclusion, the entire layer system proved to be unstable during ZMR. The removal of the capping layer by hydrofluoric acid activated a chemical reaction between substrate and acid making the samples very brittle. This observation is in correlation with the perforated barrier layer and the bulk porosity, which enables any fluid to penetrate the substrate material.

Epitaxy of the base layer Optical microscopy and SEM were applied to analyze the crystallographic properties of the samples after epitaxy of the base layer. Figure 7.19 illustrates typical properties of the recrystallized and epitaxially thickened silicon films on SiAlON ceramics. Cracks were found to penetrate the silicon film down to the barrier layer (Figure 7.19, left). The perforation of the intermediate layer is also clearly visible. The surfaces of the epitaxial layers were typically covered with whiskers as the SEM image in Figure 7.19 (right) shows.

p-Si Crack

p+-Si

SiO2 SiAlON substrate

Figure 7.19: Left: Cross section of recrystallized and epitaxially thickened silicon layer on SiO2 encapsulated SiAlON substrate. A crack penetrates the entire silicon layer system. Right: Surface of the same sample featuring severe whisker growth (SEM images).

The occurrence of cracks in the silicon layer may be attributed to a mismatch in TEC for SiAlON substrate and silicon film. The extension of the cracks from base layer to intermediate layer indicates that they developed during the cool-down phase of the epitaxy process. 7 Silicon thin-film solar cells on insulating substrates 143

An incomplete surface cleaning or the diffusion of impurities from the bulk to the silicon surface during the heating-up phase of the epitaxy process are possibly responsible for the enhanced growth of whiskers. Because of the large density of whiskers the samples on SiAlON ceramic substrates were not further processed.

7.3 Summary The evaluation of different potential low-cost ceramic material for an application as substrates in silicon thin-film solar cells was subject of this chapter. For this purpose, silicon thin-films were prepared on silicon-infiltrated SiC, hot-pressed Si3N4, tape cast Si3N4 and tape cast SiAlON ceramic substrates with dielectric ONO barrier layer. An extensive characterization of sample and solar cell properties was carried out to allow for an assessment of the suitability of the ceramic materials. The best result in terms of efficiency was obtained for a crystalline silicon thin-film solar cell on SiSiC ceramic substrate. A maximum efficiency of 10.7% was reached, exceeding the best efficiency published so far for a similar solar cell structure using SiSiC as substrate material.

A remarkable efficiency of 8.1% was achieved on tape cast Si3N4 ceramic substrates. These are the very first solar cells prepared on this type of material and further improvement can be expected if substrate material properties and solar cell process are optimized.

Silicon-film and solar cell preparation on hot-pressed Si3N4 and tape cast SiAlON ceramic substrates were not successful. Thermal and chemical properties of these substrates hindered an effective sample preparation making them unsuitable as potential substrate for silicon thin-film solar cells. The matching of thermal, chemical and mechanical properties of the substrate material with the remaining layer system was found to be crucial for a success of the presented solar cell concept. All of the investigated combinations of ceramic substrate and dielectric intermediate layer were affected by more or less harmful interactions between different components of the layer stack during sample processing. Nonetheless, the results obtained for SiSiC and tape cast Si3N4 ceramics show, that these materials have the potential for a successful application as substrates for thin-film solar cells, if their material properties can be further tailored to the requirements imposed by sample and solar cell preparation. Solar cell processing of silicon thin-films on insulating substrates is a very complex issue because of the necessity for a one-side contacting scheme. Recent publications show [147] that the realization of a solar cell process on insulating substrates using industrial relevant technologies is a great challenge which is still to be solved.

8 Summary

The aim of this work was to push the concept of crystalline silicon thin-film solar cells closer towards large-scale production. Two major aspects were considered: fast silicon deposition and preparation of epitaxial thin-film solar cells by industrial-type technologies. Research activities in the field of silicon thin-film solar cells are motivated by the demand for lower cost per Wp and reduced silicon consumption. A discussion of existing silicon thin-film solar cell approaches showed that most low-temperature routes suffer from low efficiencies or degradation. Considering the transfer techniques, the questions of wafer recycling, layer detachment and high- throughput silicon deposition are not yet solved. Within the high-temperature route, silicon thin-film solar cells on low-cost silicon substrates or foreign substrates are promising concepts to achieve efficiencies similar to conventional bulk solar cells but at lower cost and reduced silicon usage. A crucial issue for the success of this approach is the availability of high throughput silicon deposition reactors. In the past, a large variety of silicon deposition techniques has been developed according to the need imposed by microelectronic industry. Low-temperature deposition techniques suffer from low deposition rates at high technological effort while high-temperature CVD at atmospheric pressure is a suitable tool for the growth of high-quality layers at high rates. APCVD reactors used in microelectronic production are optimized to yield high-quality layers, irrespective of throughput and therefore the design of new deposition systems is inevitable. The RTCVD100 reactor, developed and built at Fraunhofer ISE, is based on a reactor and deposition concept which is expected to meet the requirements on high throughput and layer quality. Characteristic features of the RTCVD100 are the usage of trichlorosilane as silicon precursor gas, the optical heating system and the wafer setup which allows for a large chemical yield. While the RTCVD100 is a laboratory type reactor, an up-scaled version (RTCVD160) with larger wafer size capacity and improved process flexibility has recently been set up at Fraunhofer ISE. Finally, a continuous CVD (ConCVD) was presented, which is a deposition system on the cusp of industrial scale production. Within this work the reactor concept was evaluated using the RTCVD100 reactor. A thorough characterization and optimization of epilayers and seeding layers grown on foreign substrates in the RTCVD100 was one major issue within this work. Suitable characterization tools were defined and silicon layer properties were analyzed with respect to thickness and doping homogeneity, carrier concentration, impurity concentration, electrical and crystallographic quality. With increasing wafer size and throughput, new large-area characterization tools especially for an evaluation of thickness and doping distribution are necessary. Automatic surface profiling and high speed, large-area sheet resistance mapping were tested and to the author’s opinion both techniques have the potential for a successful application in large-area silicon film characterization. For silicon deposition, the design of the gas inlet was found to substantially effect the gas flow behavior in the deposition chamber and consequently the deposition rate and thickness uniformity. The implementation of gas diffusers or more generally a gas inlet which enables an efficient distribution of the incoming gas across the entire deposition cross section is essential for the growth of homogeneous

145 146 8 Summary films. This requirement becomes even more stringent for the up-scaled RTCVD160 reactor. Within this work, the gas distribution and thickness homogeneity could be improved by the application of a nozzle. Further improvement is expected, if more sophisticated injection systems like showerheads or masks are used. Two optimized epitaxy processes and one seeding layer deposition process were finally defined which served as a base for the following investigations. The deposited layers were of high purity, with thickness and doping homogeneity and minority carrier lifetime sufficient for an application in thin-film solar cells. For the RTCVD160 a standard seeding layer deposition process has similarly been set up. Future work in this area will concentrate on the development of deposition processes for the RTCVD160 and especially for the continuous CVD system. During epilayer analysis, Spreading Resistance Profiling has proved to be a powerful tool for the measurement of carrier density profiles. Based on this characterization method, carrier concentrations and profiles were characterized for epilayers grown under different deposition conditions. The analysis by SRP allowed an insight on the mechanisms of boron incorporation and the impact of the gas system on doping profiles. A change of the gas system was proposed to prevent the observed unwanted effects of delayed diborane injection and large dead capacities on doping density profiles. The carrier concentration was found to depend only on the initial diborane concentration in the gas phase. In literature, a dependence on growth rate and diborane concentration is widely reported. The different deposition conditions used in the RTCVD100 compared to commercial APCVD reactors is assumed to be responsible for this deviation. For a deeper understanding of the doping incorporation process additional experiments are desirable. The same holds for the observed boron diffusion from a diborane containing gas phase, an effect which is only little discussed in literature. The epitaxial silicon thin-film solar cell represents an attractive thin-film concept because it can in principle be processed by common industrial solar cell technologies. An extensive investigation was carried out with respect to an application of industrial relevant solar cell processing techniques to epitaxial thin-film solar cells. For this aim, epilayers were grown on different electrically inactive silicon substrates and thin-film solar cells were prepared by cleanroom and screen printing techniques.

The effects of emitter formation by POCl3 and in-line diffusion, and the impact of contact formation by evaporation and screen printing with and without firing through silicon nitride were investigated and compared. It was demonstrated that epitaxial thin-film solar cells can equally well be processed by either technology irrespective of substrate material, making a direct introduction of epitaxial wafer equivalents into standard industrial production lines possible. Using screen printing techniques, efficiencies of up to 12.2% and 11.7% were obtained for epitaxial thin-film solar cells on Cz-Si and mc-Si substrates respectively. For the first time single-crystal reclaimed wafers have been used as substrate material. The best solar cell reached an efficiency of 11.5% using screen printing techniques. It was demonstrated, that a doubling of the growth rate from 5 to 10 µm/min results only in minor efficiency losses and for high throughput production the fast growth mode represents an interesting option. The implementation of surface texture was found to be indispensable for epitaxial thin-film solar cells to increase photocurrent and efficiency. The development of efficient light trapping schemes, implementation of adequate bulk and surface passivation schemes and the evaluation of other potential low-cost silicon substrate materials (e.g. metallurgical grade silicon substrates) are amongst the most important issues to be solved in the future. The second solar cell structure under investigation followed the concept of silicon thin-films on foreign insulating substrates. Four high-temperature ceramics were tested as substrate material: hot- pressed silicon nitride and silicon infiltrated silicon carbide (“ideal” substrates) and tape cast silicon 8 Summary 147 nitride and SiAlON (“realistic” substrates). Solar cells were prepared according to the following sequence: deposition of diffusion barrier layer, silicon seeding layer deposition, zone-melting recrystallization, epitaxy of the base and solar cell processing with one-side contact scheme. During processing the ONO barrier layer got more or less damaged for all sample types, with the tape cast substrates being affected the most. The perforated intermediate layer allowed for a diffusion of metallic impurities from the substrates into the silicon film i.e. the silicon base layers were all contaminated by harmful impurities, thereby reducing minority carrier lifetime. Silicon film and solar cell preparation were not successful for hot-pressed silicon nitride and SiAlON ceramics due to a mismatch in thermal and chemical properties. Efficiencies of up to 8.1% were achieved for first thin- film solar cells on tape cast silicon nitride ceramics. This is a remarkable result, considering that the ceramic material properties were not optimized for this application. Using SiSiC ceramic substrates, an efficiency of 10.7% has been reached, exceeding the best efficiency published so far for a similar solar cell structure based on SiSiC substrate. At present the concept of silicon thin-film solar cells on insulating substrates suffers from the lack of suitable substrate/barrier layer systems. Moreover, the necessity for a one-side contact scheme represents a great challenge to industrial solar cell processing technologies. A challenge, which is still to be solved. A solution to the latter aspect is given by the use of electrically conductive substrate/barrier layer systems. These thin-film structures could be processed by conventional techniques. At Fraunhofer ISE, current research activities in this area focus on the development and use of conductive silicon carbide intermediate layers.

Deutsche Zusammenfassung 149

Deutsche Zusammenfassung

Die vorliegende Arbeit beschäftigt sich mit dem Ansatz der kristallinen Silizium- Dünnschichtsolarzelle. Dieses Konzept ermöglicht eine wesentliche Einsparung an Silizium-Material und trägt damit zur Reduktion der Modulkosten und zur Vermeidung oder Verzögerung eines drohenden Silizium-Engpasses in der PV-Industrie bei. Das Solarzellenkonzept basiert auf der Verwendung dünner Siliziumschichten, die auf ein geeignetes kostengünstiges Trägersubstrat abgeschieden werden. Gegenüber herkömmlichen Wafer-Solarzellen ist die aktive Siliziumschicht typischerweise auf etwa 1/10 reduziert. Gleichzeitig kann der teure Sägeschritt, der zur Herstellung der Silizium-Wafer notwendig ist und bei dem etwa die Hälfte des Ausgangsmaterials durch Sägeverschnitt verloren geht, umgangen werden und damit weiteres Material und Kosten gespart werden. Traditionell werden die Konzepte für die Herstellung von kristallinen Silizium-Dünnschichtsolarzellen in Hochtemperatur- und Niedertemperatur-Ansätze unterschieden, abhängig von der Maximaltemperatur, die für das Substrat noch tolerierbar ist. Die verschiedenen Ansätze zur Realisierung dieser Solarzellenstrukturen werden in der vorliegenden Arbeit vorgestellt und verglichen. Am Fraunhofer ISE wird an verschiedenen Hochtemperatur-Ansätze geforscht, da diese Konzepte eine Anwendung schneller Silizium-Abscheidetechniken bei hohen Temperaturen ermöglichen. Weiterhin können auf Fremdsubstrate abgeschiedene feinkristalline Siliziumschichten durch einen Kristallisationsprozess über die flüssige Phase in Schichten mit großkörniger Kristallstruktur überführt werden. Die elektrische Qualität der Schichten wird dadurch verbessert und höhere Wirkungsgrade können erreicht werden. Im wesentlichen werden zwei Konzepte verfolgt: epitaktische Dünnschichtsolarzellen auf kostengünstigen Silizium-Substraten und Dünnschichtsolarzellen auf Fremdsubstraten. Ein Erfolg dieser Konzepte hinsichtlich industrieller Fertigung ist unter anderem abhängig von der Entwicklung geeigneter Silizium-Abscheideanlagen mit hohem Durchsatz. Im Rahmen dieser Arbeit wurden zwei Schwerpunkte behandelt: die Weiterentwicklung von Hochleistungs-Silizium-Abscheidereaktoren und die Prozessierung epitaktischer Silizium Dünnschichtsolarzellen mit industriell relevanten Fertigungstechnologien. Zunächst werden gängige Methoden zur Abscheidung von Silizium beschrieben und diskutiert. Die Abscheidung aus der Gasphase unter Atmosphärendruck (APCVD23) ist für schnelle Abscheidungen bei hohen Temperaturen bestens geeignet. Konventionelle APCVD Abscheidereaktoren, wie sie in der Mikroelektronik zur Herstellung elektronischer Bauteile verwendet werden, arbeiten in der Regel im Batch-Betrieb bei hohen Gasflüssen, relativ geringen Wachstumsraten, hohem Gasverbrauch und damit hohen Kosten. Siliziumschichten mit exzellenter Schicht- und Dotierungshomogenität und von sehr guter Kristallqualität werden damit hergestellt. Für eine Anwendung in der Photovoltaik sind die Anforderungen an die Schichteigenschaften weniger strikt, dafür ist hoher Durchsatz und kosteneffektiver Betrieb der Anlage umso wichtiger. Am Fraunhofer ISE wird verstärkt an der

23 APCVD: Atmospheric Pressure Chemical Vapor Deposition. 150 Deutsche Zusammenfassung

Entwicklung von geeigneten APCVD-Reaktoren gearbeitet. Die erste Anlage, die in diesem Zusammenhang vor etwa 8 Jahren entwickelt wurde ist die RTCVD10024, die in dieser Arbeit gewissermaßen als Zugpferd verwendet wurde. Die Anlage arbeitet unter Atmosphärendruck und ist mit einem optischen Heizsystem ausgestattet. Die Abscheidung erfolgt aus der Gasphase, wobei Trichlorsilan und Wasserstoff als Prozessgase und Diboran zur Abscheidung Bor-dotierter Schichten eingesetzt werden. Ein weiteres charakteristisches Element ist der Substrathalter, auf den die Proben zur Beschichtung aufgelegt werden: zwei horizontale parallele Wafer-Reihen bilden zusammen mit dem Quarzträger ein abgeschlossenes Volumen. Durch eine Öffnung in der Frontplatte des Trägers wird das Prozessgas eingeführt und gleichermaßen durch eine Öffnung in der Endplatte wieder abgeführt. Das Prozessgas kommt somit nur mit den Waferflächen und mit den Bestandteilen des Quarzträgers in Berührung. Parasitäre Abscheidungen auf dem umgebenden Reaktor-Quarzrohr werden damit vermieden und die chemische Effizienz der Abscheidung verbessert. Die RTCVD100 ist eine Laboranlage, an der das Reaktorkonzept erprobt wurde. Das Nachfolgemodell RTCVD160 basiert auf den gleichen Prinzipien wie die RTCVD100, erlaubt aber die Bearbeitung größerer Proben und entsprechend höherem Durchsatz. Die kontinuierliche Silizium CVD-Anlage, die am Fraunhofer ISE innerhalb eines Forschungsprojektes entwickelt und dort Ende 2002 aufgebaut worden ist, stellt einen weiteren wichtigen Schritt in Richtung industrieller Fertigung dar. Alle drei Anlagen werden beschrieben, wobei der Schwerpunkt auf eine Ausführung der technischen Details der RTCVD100 gelegt wurde. Die Charakterisierung und Optimierung von Silizium-Abscheideprozessen für die RTCVD100 ist wesentlicher Bestandteil dieser Arbeit. Geeignete Charakterisierungsmethoden wurden evaluiert und epitaktische Siliziumschichten wurden hinsichtlich Schicht- und Dotierungshomogenität, elektrischer, kristallographischer und chemischer Eigenschaften analysiert. Verfahren zur Charakterisierung von Siliziumschichten auf großen Flächen wurden vorgeschlagen und getestet. Zwei Epitaxie-Prozesse und ein Prozess zur Abscheidung von Siliziumschichten auf Fremdsubstraten wurden optimiert und standardisiert. Die abgeschiedenen Schichten waren in all ihren Eigenschaften gut geeignet für eine Anwendung in Dünnschichtsolarzellen. Das erfolgversprechende Prinzip der RTCVD100 konnte damit bestätigt werden. Zukünftige Arbeiten in diesem Bereich werden sich auf die Optimierung von CVD-Prozessen in der RTCVD160 und vor allem in der Durchlaufanlage konzentrieren. Weiterer Punkt dieser Arbeit ist eine detaillierte Analyse von Dotierprofilen in Siliziumschichten, die unter verschiedenen Prozessbedingungen hergestellt worden waren. Die Mechanismen des Einbaus von Bor in die wachsende Siliziumschicht während der Epitaxie und die Diffusion von Bor aus der Gasphase wurde studiert. Unter anderem wurden dabei wichtige Einblicke in die Zusammenhänge zwischen Gassystem und Dotierprofil gewonnen. Basierend auf diesen Untersuchungen wird eine Modifikation des vorhandenen Gassystems vorgeschlagen. Epitaktische Silizium-Dünnschichtsolarzellen können auf direktem Wege in bereits bestehenden Fertigungslinien verarbeitet werden. Zusammen mit dem Kostensparpotenzial des Ansatzes ist dieses Zellkonzept besonders attraktiv. Die Anwendung industrienaher Solarzellentechnologien auf epitaktisches Material wird in dieser Arbeit intensiv diskutiert. Zu diesem Zweck wurden in der RTCVD100 dünne (ca. 20-30 µm) Siliziumschichten auf elektrisch inaktive Silizium-Substrate abgeschieden. Die Einflüsse von Emitterbildung durch POCl3 und Durchlaufdiffusion, und von

24 RTCVD: Rapid Thermal CVD (schnelle thermische Abscheidung aus der Gasphase). Deutsche Zusammenfassung 151

Kontaktbildung durch Aufdampfen und Siebdruck mit und ohne Feuern durch Siliziumnitrid wurden separat verglichen und beurteilt. Im Zuge dessen konnte gezeigt werden, dass sich epitaktische Zellen sowohl mit Reinraum- als auch mit Siebdruck-Prozessen gleich gut prozessieren lassen. Unter Verwendung von Siebdrucktechniken wurden Wirkungsgrade von 12.2% und 11.7% auf inaktiven Cz- Si und mc-Si Substraten erreicht. Zum erstenmal wurden einkristalline Reclaim-Wafer als Substratmaterial verwendet. Bei diesem Material handelt es sich um wiederverwertete Wafer aus der Mikroelektronik, bei denen alle Bauelemente entfernt wurden. Wirkungsgrade bis zu 11.5% konnten hiermit erzielt werden (Siebdrucktechnik). Weiterhin konnte gezeigt werden, dass eine Erhöhung der Abscheiderate von 5 auf 10 µm/min nur einen geringen Verlust der Solarzelleneffizienz nach sich zieht und damit für eine industrielle Fertigung interessant wird. Die Entwicklung von Strukturen für eine effiziente Lichteinkopplung, effektive Passivierungstechniken von Oberflächen und Bulk und die Untersuchung weiterer potenzieller kostengünstiger Silizium-Materialien wie z.B. Substrate aus metallurgischem Silizium, stellen zukünftige Forschungsschwerpunkte auf dem Gebiet der epitaktischen Dünnschichtsolarzelle dar. In einem letzten Arbeitspunkt wurden kristalline Dünnschichtsolarzellen auf isolierenden Fremdsubstraten hergestellt. Dazu wurden vier Keramiken als Substrat-Material verwendet: heiß gepresstes Siliziumnitrid und Silizium-infiltriertes Siliziumcarbid mit polierten Oberflächen („ideale“ Materialien), und foliengezogenes Siliziumnitrid sowie foliengezogenes SiAlON („realistische“ kostengünstige Materialien). Die Solarzellen wurden nach folgendem Prozess hergestellt: Abscheidung einer Barriereschicht, Abscheidung einer hochdotierten Siliziumschicht, Rekristallisation der Siliziumschicht durch Zonenschmelzen, Epitaxie der aktiven Basis und Solarzellenprozessierung mit einseitiger Kontaktierung. Die Barriereschichten wurden bei allen Schichtsystemen durch die Prozessierung teilweise beschädigt. Heiß gepresste Siliziumnitrid und foliengezogene SiAlON Substrate erwiesen sich aufgrund ihrer thermischen, mechanischen und chemischen Eigenschaften als ungeeignet für eine Anwendung als Substrat. Erste Dünnschichtsolarzellen auf foliengezogenen Siliziumnitrid Substraten erreichten Wirkungsgrade bis zu 8.1%. Weitere Steigerungen sind zu erwarten, wenn das Substrat auf die Anforderungen optimiert wird. Die beste Solarzelle auf Siliziumcarbid Substrat zeigte einen Wirkungsgrad von 10.7%, der sogar den bisher veröffentlichten höchsten Wirkungsgrad auf diesem Substrat um 1.4% absolut übersteigt. Die Entwicklung geeigneter Substrat/Barriereschicht-Kombinationen und die Einseitenkontaktierung auf Ebene der industriellen Fertigung stellen zwei herausragende Herausforderungen an das Konzept der kristallinen Dünnschichtsolarzelle auf isolierenden Fremdsubstraten dar. Letzteres Problem kann durch die Entwicklung elektrisch leitfähiger Substrat/Zwischenschicht-Systeme umgangen werden, wodurch eine konventionelle Prozessierung ermöglicht würde. Am Fraunhofer ISE wird daher derzeit verstärkt an der Entwicklung leitfähiger Siliziumcarbidschichten gearbeitet.

Appendix A Abbreviations 153

Appendix A Abbreviations

APCVD Atmospheric Pressure Chemical Vapor Deposition ARC Antireflection Coating BBC Buried Base Contacts BSF Back Surface Field CMOS Complementary Metal-Oxide Semiconductor CVD Chemical Vapor Deposition Cz-Si Czochralski silicon DLARC Double Layer Antireflection Coating EBIC Electron Beam Induced Current EFG Edge-defined Film-fed Growth EQE External Quantum Efficiency FF Fill Factor FTIR Fourier Transform Infrared Reflectrometry FZ-Si Float-Zone silicon GDMS Glow-Discharge Mass Spectrometry HWCVD Hot-Wire Chemical Vapor Deposition IAD Ion-Assisted Deposition IQE Internal Quantum Efficiency LPCVD Low-Pressure Chemical Vapor Deposition LPE Liquid-Phase Epitaxy MBE Molecular Beam Epitaxy MG Metallurgical-Grade MOS Metal-Oxide Semiconductor MOSFET Metal-Oxide Semiconductor Field-Effect Transistor MW-PCD Microwave Photo-Current-Decay PECVD Plasma-Enhanced Chemical Vapor Deposition PSG Phosphorus Silicate Glass PSI Porous Silicon PVD Physical Vapor Deposition RGS Ribbon Growth on Substrate 154 Appendix A Abbreviations

RIE Reactive Ion Etching RPCVD Reduced Pressure Chemical Vapor Deposition RPHP Remote Plasma Hydrogen Passivation RTA Rapid Thermal Anneal RTF Rapid Thermal Firing RTCVD Rapid Thermal Chemical Vapor Deposition RTP Rapid Thermal Processing SEM Secondary Electron Microscopy SIMOX Separation by Implanted Oxygen SIMS Secondary Ion Mass Spectroscopy SOI Silicon On Insulator SR-LBIC Spectrally Resolved Light Beam Induced Current SRP Spreading Resistance Profiling SSP Silicon Sheets from Powder

TCS Trichlorosilane, SiHCl3 TEC Thermal Expansion Coefficient TFT Thin-Film Transistor UHV-CVD Ultrahigh-Vacuum Chemical Vapor Deposition UMG Upgraded Metallurgical Grade QMS Quasi-Monocrystalline Silicon VHF-PECVD Very High Frequency Plasma-Enhanced Chemical Vapor Deposition VLSI Very-Large-Scale Integration ZMR Zone-Melting Recrystallization Appendix B Solar cell fundamentals 155

Appendix B Solar cell fundamentals

Solar cell devices incorporate a large area pn junction in a semiconductor with emitter and base being contacted by metal electrodes. Incident photons, when absorbed in the semiconductor, can generate electron hole pairs (photoeffect). Provided a sufficient lifetime, the generated minority carriers can diffuse to the pn-junction, where charge separation occurs by the incorporated electric field. The carriers are subsequently collected by the contacts, leading to a current flow in an external circuit. Treating the solar cell as an ideal infinite diode, its current-voltage characteristics can be described by the ideal diode model:

qV / kT I(V ) = I 0 (e −1) − I PC (B.1) where I0, q, V, k, T and IPC denote the saturation current of emitter and base, elementary charge, voltage, Boltzmann’s constant, device temperature and generated photocurrent. The thermal photovoltage is given by VT=kT/q. From eqn. (B.1) the short-circuit current density ISC and open- circuit voltage VOC can be deduced: (B.2) I SC = −I PC , VOC = VT ln(I PC / I 0 +1)

The maximum output power of the cell depends on open-circuit voltage, short-circuit current and fill factor (FF): (B.3) Pmax = Vmpp I mpp = VOC I SC FF

Where Vmpp and Impp denote the voltage and current at the maximum power point. The fill factor FF denotes the ratio of maximum output power to the product of VOC and ISC. The efficiency of a solar cell is given by the ratio of maximum output power to the solar radiation power provided by the incident sunlight. Eqn. (B.2) shows that low saturation currents are needed for large open-circuit voltages and subsequently large output power. The saturation current density of the base is given by

2 qni Dn I 0b (V ) = GF (B.4) N A Ln where ni, Dn, NA, Ln, and GF are intrinsic carrier concentration, minority carrier (electrons for a p-type base) diffusion constant, acceptor density, minority carrier diffusion length and the so-called geometry factor. The latter depends on the recombination velocity at the surfaces S, base thickness W and

“recombination velocity” in the crystal S∞=Dn/Ln:

cosh(W / Ln ) + (S∞ / S)sinh(W / Ln ) GF = (B.5) (S∞ / S)cosh(W / Ln ) + sinh(W / Ln )

For a reduction of the saturation current, large diffusion lengths, large acceptor concentrations and low geometry factors are beneficial. The increase in acceptor concentration is limited by the associated 156 Appendix B Solar cell fundamentals increase in Auger recombination and enhanced band gap narrowing. Figure B.1 illustrates the dependence of the geometry factor on the ratio of W/Ln for different values of S/S∞.

For base thickness larger than the minority carrier diffusion length (W≥3Ln) the geometry factor is equal to one, independent on surface and volume recombination velocity. If the surface recombination velocity exceeds the recombination velocity in the volume (S/S∞>1) the geometry factor is larger than one and increases with rising ratio of S/S∞. A reduction in open-circuit voltage is the consequence. The opposite effect results, if the surface recombination velocity is reduced such that S/S∞<1. To achieve high open-circuit voltages, minority carrier diffusion lengths exceeding the base thickness and well passivated surfaces are necessary.

In the limit of W<

2 qniW Ln I 0b (V ) = with τ n = (B.6) N Aτ n Dn where τn denotes the minority carrier lifetime in the base. This relation demonstrates that a reduction of base thickness W lowers the saturation current, if the minority carrier lifetime is held constant.

102 ∞

20 101 5

2 100 1 1/2 1/5

-1 Geometry factor 10 1/20

S/S∞= 0

10-2 0.1 1 10 W/L n

Figure B.1: Geometry factor as a function of W/Ln for different ratios of S/S∞.

In a real solar cell device, recombination losses have to be accounted for, leading to the two-diode model: V − IR (V −IRs) / n1VT (V −IRs) / n2VT S I(V ) = I 01 (e −1) + I 02 (e −1) + − I PC (B.7) RP

I01 is the saturation current of emitter and base and corresponds to I0 in eqn. (B.1). I02 denotes the saturation current of the space charge region and is induced by the presence of trap levels. In both cases, an increase in saturation current results in a decrease of open-circuit voltage.

The series resistance RS combines the resistance of the semiconductor material, emitter and base metal contacts and the contact resistance between metal electrode and semiconductor. The shunt resistance Appendix B Solar cell fundamentals 157

RP is caused by leakage currents. Both parasitic resistances reduce the fill factor and large series resistances can also lower the short-circuit current of the device. n1 and n2 are ideality factors which are equal to 1 and 2 respectively for ideal cell behavior but may differ from their theoretical values for real solar cells.

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Publications 171

Publications

S. Bau, T. Kieliba, D. Oßwald, A. Hurrle, Chemical Vapour Deposition of Silicon on Ceramic Substrates for Crystalline Silicon Thin-Film Solar Cells, 17th European Photovoltaic Solar Energy Conference (2001) 1575-1577.

S. Reber, J. Dicker, D.M. Huljić, S. Bau, Epitaxy of Emitters for Crystalline Silicon Solar Cells, 17th European Photovoltaic Solar Energy Conference (2001) 1612-1615.

S. Bau, D.M. Huljić, J. Isenberg, J. Rentsch, Shunt-Analysis of Epitaxial Silicon Thin-Film Solar Cells by Lock-In Thermography, 29th IEEE Photovoltaic Specialists Conference (2002) 1335-1338.

T. Kieliba, S. Bau, R. Schober, D. Oßwald, S. Reber, A. Eyer, G. Willeke, Crystalline silicon thin-film solar cells on ZrSiO4 ceramic substrates, Solar Energy Materials & Solar Cells 74 (2002) 261-266.

S. Bau, J. Rentsch, D.M. Huljić, S. Reber, A. Hurrle, G. Willeke, Application of Screen Printing Processes for Epitaxial Silicon Thin-Film Solar Cells, 3rd World Conference on Photovoltaic Energy Conversion (2003).

S. Bau, S. Janz, T. Kieliba, S. Reber, C. Schetter, F. Lutz, Application of PECVD-SiC as Intermediate Layer in Crystalline Silicon Thin-Film Solar Cells, 3rd World Conference on Photovoltaic Energy Conversion (2003).

S. Reber, C. Haase, N. Schillinger, S. Bau, A. Hurrle, The RTCVD160 – A new lab-type silicon CVD processor for silicon deposition on large area substrates, 3rd World Conference on Photovoltaic Energy Conversion (2003).

A. Slaoui, A. Focsa, S. Bau, S. Reber, T. Kieliba, A. Gutjahr, R. Bilyalov, J. Poortmans, Silicon Films on Ceramic Substrates (SOCS): Growth and Solar Cells, 3rd World Conference on Photovoltaic Energy Conversion (2003).

J. Rentsch, S. Bau, D.M. Huljić, Screen printed epitaxial thin-film solar cells with 13.1% efficiency, Progress in Photovoltaics, to be published.

Acknowledgements 173

Acknowledgements

At the end of this work, I would like to express my gratitude to all the people who supported me in my studies during the past four years. My colleges, friends and family encouraged this work in manifold ways and contributed to its success. I thank you all. ______

Mein Dank gilt zuallererst Herrn PD. Dr. Willeke für die Vergabe dieser spannenden Arbeit. Stefan Reber möchte ich ganz besonders danken für seine unermüdliche Unterstützung während der letzten Jahre, sein Vertrauen in diese Arbeit, sein Engagement und seine mitreißende Begeisterung nicht nur für die kristalline Silizium-Dünnschichtsolarzelle. Sein oft ungetrübter Enthusiasmus und Einsatz bleibt der Dünnschicht-Gruppe hoffentlich noch lange erhalten. Dank auch an Albert Hurrle für etliche Erklärungen zum Thema Gasphasen-Abscheidung. Sein Versuch, alles möglichst objektiv zu sehen und zu beurteilen und seine wunderbar logische Herangehensweise an Probleme – egal ob physikalischer, technischer oder politischer Art – waren mir immer ein Vorbild. Norbert Schillinger möchte ich danken für die Einweisung in das Innenleben unserer schnellen CVD- Anlagen und für unzählige Reparatur-, Flaschenwechsel- und Quarzarbeiten. Die gemeinsame Arbeit hat mir großen Spaß gemacht und hat mich gelehrt, auch scheinbar Selbstverständliches zu hinterfragen und Vor- und Nachteile aller Dinge ganz genau abzuwägen. Für die vielen Arbeiten im Chemielabor sei Frau Mira Kwiatkowska gedankt. Ihre Bereitschaft, besonders dringende Dinge auch sofort zu erledigen, haben die weitere Bearbeitung vieler Proben oft wesentlich vorangetrieben. Meinem Promotions-Kollegen Thomas Kieliba verdanke ich viele gute Stunden gemeinsamer Diskussion zum Thema Dünnschicht, viele wertvolle Tipps bei diversen EDV-Problemen, überaus angenehme Kaffee- und Schoko-Pausen und eine tolle Büro-Zeit. Über unsere ausgeglichene, zuverlässige und gut funktionierende Zusammenarbeit habe ich mich sehr gefreut. Auch den Kollegen Jochen Rentsch, Dominik Huljić, Jörg Isenberg und Stefan Janz sei für ihre Unterstützung und Zusammenarbeit im Dünnschichtbereich gedankt. Dem Einsatz des gesamten Tech-II Teams habe ich es zu verdanken, dass viele meiner Dünnschicht- Solarzellen den Weg ans Licht gefunden haben. Dieser Dank gilt allen voran Harald Lautenschlager und Christian Schetter für ihre Mühen bei der Solarzellenprozessierung und diversen Spezial- Anfertigungen. Die prompten Erledigungen sämtlicher Hell-/Dunkel-, SR- und SR-LBIC-Messungen, vor allem in den letzten Monaten, haben mir in meiner Arbeit sehr geholfen. Hierfür und für ihre vielen anderen Hilfen möchte ich mich bei Elisabeth Schäffer sehr herzlich bedanken. Die sonnige Atmosphäre im Messlabor war mir oft ein Grund, dort zu einer kleinen Pause vorbei zu schauen. 174 Acknowledgements

Für wegweisende und konstruktive Diskussionen zur Theorie und Analyse der Dünnschichtzelle danke ich Stefan Glunz und Wilhelm Warta. Vielen Dank auch an Daniel Spinner für seine überaus unkomplizierte, schnelle und zuverlässige Hilfe bei kleinen und großen Soft- und Hardware-Problemen. Jörn Denter gebührt ein herzliches Dankeschön für die tolle Zusammenarbeit im CVD-Labor und die unvergessenen Reisen und Unternehmungen mit Meier-Tours. Meiner Lebenspartnerin Anna danke ich für all die kleinen und großen Aufregungen, die unseren Alltag ausmachen, für ihre Offenheit, gemeinsam Neues auszuprobieren und für ihre unendlich große Geduld und Unterstützung nicht nur während der letzten Monate. Schließlich möchte ich meinen Eltern danken, die mich in all meinen Entscheidungen und Lebensweisen stets unterstützt haben und mir die Freiheit gaben, meine eigenen Wege zu suchen und zu gehen.