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Analytical Methods for Mixed Signal Processing Systems

DISSERTATION

Presented in Partial Fulfillment of the Requirements for

the Degree Doctor of Philosophy in the

Graduate School of The Ohio State University

By

Hung-Chuan Pai, B.S.E.E., M.S.E.E.

*****

The Ohio State University

1998

Dissertation Committee: Approved by

Professor Steven Bibyk, Adviser Professor Mohammed Ismail Adviser / Professor Joanne DeGroat Department of Electrical Engineering UMI Number: 9822355

UMI Microform 9822355 Copyright 1998, by UMI Company. All rights reserved.

This microform edition is protected against unauthorized copying under Title 17, United States Code.

UMI 300 North Zeeb Road Ann Arbor, MI 48103 (c) Copyright by

Hung-Chuan Pai

1998 ABSTRACT

With the emergence of computers, engineers found applications of powerfiil signal processing, signal transmission, as well as information storage methods using digital systems. When applying data to digital systems, the transfer of signals from analog to digital is the first step. Conventionally, this operation was dealt with using a variety of high precision components, such as flash converters. Other approaches, like

DPCM and Delta Modulation, increase system accuracy by reducing the variation of the signal processed. However, these approaches are inefficient because precision in the quantizer and D /A converter is still required; they do not take advantage of modem VLSI technology.

As VLSI technology progresses, very high speed clocking rates and instruction processing have become available and should now be applied to simplify traditional systems. In this dissertation, we apply oversampling and Sigma-Delta modulation

(SAM) approaches to propose an implementation structure for a general purpose, programmable, and multipherless DSP chip. The preceding anti-aliasing filter will become less important as a result of oversampling. Diverse SA modulators, including one first order lowpass SAM, several second order cascade-structure lowpass SAM’s, one second order MASH-stracture lowpass SAM, and one second order bandpass

SAM, will be discussed using additive quantization noise to model an one-bit quan­ tizer. A second order lowpass SA modulator is especially suitable for VLSI technology

11 because of its tolerance of component mismatch as well as nonideal circuit behavior.

Therefore, a second order EAM structure will be used throughout the discussion of a complete SAM system. To maintain the simplicity of DAC linearity, an one-bit quantizer will be chosen.

A wide input range SA modulator structure is proposed. This structure can extend the input range by at least threefold when compared with its competitive traditional SA modulators. Advanced (quasilinear) models for the one-bit quantizer with respect to a DC input and a sinusoidal input to a SA modulator are analyzed.

Stability issues are discussed using this advanced model for second and higher order

SA modulators. A highly important contribution of knowing the theoretical quan­ tization noise shape is to confidently design the required decimation stages/filters in lieu of trial and error approaches as well as overstrained conditions. Sinusoidal signals will be applied to explain and test the theoretical/realistic system because, by the

Fourier analysis (Fourier Series), all signals can be approximately decomposed as the summation of sinusoidal components. The exploration of the linearized SAM model with respect to different sinusoidal magnitude inputs will be crucial for the advanced inspection and design of the optimized SAM system. Diverse decimation-stage design strategies are going to be discussed. The feasibility of a multiplierless SAM system is also of interest. Because of the reduction of multipliers, the proposed SAM system structure will not only be simplified but also possess high data throughput and ex­ cellent resolution. A few high performance and multiplierless decimation-stages are presented.

m To my parents and my wife

IV ACKNOWLEDGMENTS

I wish to acknowledge my adviser, Dr. Steven Bibyk, for his direction, guidance, advice, and support throughout my research. I also wish to thank Dr. Mohammed

Ismail and Dr. Joanne DeGroat for their guidance, dedication, and encouragement for my research. Many thanks go to Dr. George Majda for being in my committee and reading my dissertation.

I extend heartfelt appreciation to my family, especially my parents and my wife,

Yun-I Patricia Liu, for their encourgement and support. I am also indebted to my friends, Hung-Chih Chiang, Tsung-Yuan Chang, and John Fisher, for their valued discussion. Many thanks go to Micrys Inc. for providing assistance and support. VITA

February 7, 1966 ...... Bom—Tainan, Taiwan, R.O.C.

June 1989 ...... B.S. Electrical Engineering, National Cheng-Kung University Tainan, Taiwan, R.O.C.

1989 - 1991 ...... Military second lieutenant Taipei, Taiwan, R.O.C.

1991 - 1992 ...... Research engineer Lieu Ming Company Tainan, Taiwan, R.O.C.

1992 - 1994 ...... M.S. Electrical Engineering, The Ohio State University Columbus, Ohio, U.S.A.

1994 - present ...... Graduate Research Associate The Ohio State University Columbus, Ohio, U.S.A.

VI PUBLICATIONS

Research Publications

Hung-Chuan Pai and Steven B. Bibyk “High Dynamic Range Design for SAM with Wide Input Ranges”. 1st Analog VLSI Workshop Proceedings, May, 1997.

Hung-Chuan Pai and Steven B. Bibyk “High Dynamic Range Design for SAM with Wide Input Ranges”. Submitted to the Special Issue of the Intematinal Journal of Analog Integrated Circuits and Signal Froccesing, 1998.

FIELDS OF STUDY

Major Field: Electrical Engineering

Studies in: Topic 1 Signal Processing Topic 2 System Circuit Design

vu TABLE OF CONTENTS

P age

A bstract...... ii

Dedication...... iv

Acknowledgments ...... v

V i t a ...... vi

List of Tables...... x

List of Figures ...... xi

Chapters:

1. Introduction ...... 1

2. Relationship of DPCM, AM, and EAM ...... 7

2.1 Differential Pulse Code Modulation (DPCM) ...... 7 2.2 Delta Modulation (A M )...... 8 2.3 Sigma-Delta (EA) M odulation ...... 10 2.4 Example for Oversampling and First-Order EA Modulation .... 11

3. Modeling and Analyzing EAM ...... 15

3.1 Modeling EA Modulators ...... 15 3.2 Second Order Lowpass EA Modulators ...... 23 3.3 Second Order Bandpass EA Modulator...... 27

viu 4. Advanced Model for EAM and Noise Shaping ...... 30

4.1 The Advanced EAM Model as DC Input...... 32 4.2 The Advanced EAM Model as Sinusoidal Input...... 38 4.3 Affect of Quantization Noise Signal Component Gain Gx in Stability 43 4.4 Affect of Quantization Noise Random Component Gain G„ in Noise S h a p in g ...... 46

5. Wide Input Range EAM ...... 49

5.1 Introduction and Problem Description ...... 49 5.2 Improved EA ADC Architecture and Design Algorithm ...... 52 5.3 Modified Digital Error Self-Calibration ...... 56 5.4 Investigation of Performance Improvement ...... 57

6. Decimation S ta g e ...... 63

6.1 Single-Stage Multiplierless Decimation Filter ...... 64 6.2 Multi-Stage Decimation Filter ...... 67 6.2.1 Comb F ilter ...... 67 6.2.2 Compensation FIR ...... 72

7. Programmable Multiplierless Decimation Filters ...... 77

7.1 Signed Power-of-Two FIR Compensation F ilter ...... 79 7.2 Investigation of Comb Filter Tap Numbers and Decimation Ratios 85 7.3 Flexibility of Comb Filter Tap Numbers and Decimation Ratios. . 88 7.4 Programmability ...... 97 7.5 Simulation Results...... 98

8. Conclusion ...... 106

8.1 Work Summary ...... 107 8.2 Future Works ...... 108

Bibliography ...... 110

IX LIST OF TABLES

T able P age

7.1 Theoretical and Simulated Frequency Spectra of Diverse Decimation A p p ro a ch es...... 105 LIST OF FIGURES

Figure Page

1.1 System Block Diagram ...... 2

2.1 (One-Tap) Differential Pulse Code Modulation...... 8

2.2 (1st Order) A Modulation System ...... 9

2.3 (1st -Order) EA Modulation System ...... 10

2.4 A / EA De/Modulation with a Sampling Frequency of 0.4 M H z . . . 12

2.5 A / EA De/Modulation with a Sampling Frequency of 12.8 M H z . . 12

2.6 Frequency Spectrum of x with an Oversampling Rate of 8 ...... 13

2.7 Frequency Spectrum of x with an Oversampling Rate of 256 ...... 13

3.1 (1st Order) EA Modulator (with Additive Quantization Error Model) 17

3.2 One-Bit Quantizer Characteristic...... 18

3.3 Dynamic Range of EA Modulation ...... 21

3.4 Cascade of Two 1st Order EAMs (MASH Architecture)...... 22

3.5 Conventional 2nd Order EA Modulator ...... 23

3.6 Boser’s 2nd Order EA Modulator ...... 24

3.7 Shenoi’s 2nd Order EA M odulator ...... 25

XI 3.8 Frequency Spectrum of x with an Oversampling Rate of 6 4 ...... 27

3.9 (2nd Order) Bandpass EA Modulator ...... 28

3.10 Frequency Spectrum of a 2nd Order Bandpass EA Modulator .... 29

4.1 Block Diagram of a EA Modulator ...... 30

4.2 Advanced Model of a EA M odulator ...... 31

4.3 EAM Model with Separate Sources: x{k) and n{k) ...... 32

4.4 Relationship of and as a DC Input to a EA Modulator...... 36

4.5 Relationship of ttIi , and as a DC Input to a EA Modulator . . 37

4.6 Relationship of rrix, me, and as a DC Input to a EA Modulator . 37

4.7 Relationship of cr^ and ^ as a Sinusoidal Input to a EA Modulator . 41

4.8 Relationship of a*, and Gn as a Sinusoidal Input to a EA Modulator 42

4.9 Relationship of Ox, and as a Sinusoidal Input to a EA Modulator 43

4.10 Pole Root Locus of a 2nd Order EA Modulator (ai = 0.5 and « 2 = 1) 44

4.11 Pole Root Locus of a 3rd Order EA Modulator ...... 45

4.12 Noise Shaping of a 2nd Order EAM (ai = 0.5 and 0 :2 = 1) with Diverse G„’s ...... 48

5.1 Performance for Boser’s and Shenoi’s M ethods ...... 50

5.2 Architecture of Wide Input Range EA A D C ...... 52

5.3 Reference Decision Architecture ...... 54

5.4 Performance of the Wide Input Range EA ADC ...... 55

5.5 Modified Digital Error Self-Calibration Architecture ...... 56

XU 5.6 Relationship of Sinusoidal Magnitude and Quantization Noise Ran­ dom Component ...... 58

5.7 Relationship of Sinusoidal Magnitude Ox and Quantization Noise Signal Component ...... 58

5.8 Probability Density for a 2nd Order EAM Using Proposed Architecture When the Sinusoidal Input Magnitude = -15.5 d B ...... 61

5.9 Probability Density for a 2nd Order SAM Using Boser’s Architecture When the Sinusoidal Input Magnitude = -15.5 d B ...... 61

5.10 Frequency Spectrum for a 2nd Order EAM Using Proposed Architec­ ture When the Sinusoidal Input Magnitude = -15.5 d B ...... 62

5.11 Frequency Spectrum for a 2nd Order EAM Using Boser’s Architecture When the Sinusoidal Input Magnitude = -15.5 d B ...... 62

6.1 Architecture of a Multiplierless FIR F ilter ...... 66

6.2 Block Diagram of a K-Stage Comb Filter ...... 68

6.3 Noise Shaping for Boser’s 2nd Order EAM ...... 69

6.4 Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter ...... 70

6.5 Noise Shaping after a 3-Stage 64-Tap Comb-Filter for Boser’s 2nd Or­ der EAM ...... 70

6.6 Noise Shaping after a 3-Stage 64-Tap Comb-Filter & Decimation by 64 for Boser’s 2nd Order EAM ...... 71

6.7 Baseband Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter . . . 73

6.8 Frequency Spectrum of a 256-Tap FIR Compensation F ilter 74

6.9 Baseband Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter Cas­ caded by a 256-Tap FIR Compensation F ilte r ...... 75

6.10 Noise Shaping after a 256-Tap FIR Compensation Filter & Decimation by 4 for Boser’s 2nd Order E A M ...... 76

xm 7.1 (Positive Side) 2b/16b Signed Power-of-Two Space ...... 80

7.2 Frequency Spectrum of a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation F ilter ...... 82

7.3 Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter Cascaded by a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter .... 83

7.4 Noise Shaping after a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter & Decimation by 4 for Boser’s 2nd Order EAM . . . 84

7.5 Relationship of Attenuated Signal to Spurious Noise ...... 86

7.6 Frequency Spectrum of a 2nd Order EAM (o-i = 0.5, = 0.5, and G-a = 0.2530) Shaped Noise and a 3-Stage 64-Tap Comb-Filter .... 87

7.7 Frequency Spectrum of a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter for a 3-Stage 64-Tap Comb-Filter whose output data will be decimated by 1 2 8 ...... 89

7.8 Baseband Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter Cas­ caded by a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation F ilter...... 90

7.9 Noise Shaping after a 3-Stage 64-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order E A M ...... 91

7.10 Noise Shaping after a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter & Decimation by 2 for Boser’s 2nd Order EAM . . . 91

7.11 Frequency Spectrum of a 2nd Order EAM ( 0 :1 = 0.5, 0=2 = 0.5, and Gji = 0.2530) Shaped Noise and a 3-Stage 128-Tap Comb-Filter . . . 92

7.12 Frequency Spectrum of a 3-Stage 128-Tap Comb-Filter ...... 93

7.13 Noise Shaping after a 3-Stage 128-Tap Comb-Filter for Boser’s 2nd Order E A M ...... 93

7.14 Noise Shaping after a 3-Stage 128-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order E A M ...... 94

XIV 7.15 Frequency Spectrum of a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter for a 3-Stage 128-Tap Comb-Filter ...... 95

7.16 Frequency Spectrum of a 3-Stage 128-Tap Comb-Filter Cascaded by a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter .... 96

7.17 Noise Shaping after a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter & Decimation by 2 for Boser’s 2nd Order SAM . . . 97

7.18 Frequency Spectrum of the Pulse Density Stream for Boser’s 2nd Order EAM ...... 99

7.19 Frequency Spectrum after a 3-Stage 64-Tap Comb-Filter & Decimation by 64 for Boser’s 2nd Order EAM ...... 100

7.20 Frequency Spectrum after a 256-Tap FIR Compensation Filter & Dec­ imation by 4 for Boser’s 2nd Order EAM ...... 100

7.21 Frequency Spectrum after a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter & Decimation by 4 for Boser’s 2nd Order EAM 101

7.22 Frequency Spectrum after a 3-Stage 64-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order S A M ...... 102

7.23 Frequency Spectrum after a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter & Decimation by 2 for Boser’s 2nd Order EAM 102

7.24 Frequency Spectrum after a 3-Stage 128-Tap Comb-Filter & Decima­ tion by 128 for Boser’s 2nd Order EAM ...... 104

7.25 Frequency Spectrum after a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter & Decimation by 2 for Boser’s 2nd Order EAM 104

XV CHAPTER 1

INTRODUCTION

At present, VLSI technology brings great convenience and huge improvement to

life because of its powerful signal processing efficiency. Conventionally, VLSI technol­ ogy is approximately divided into analog and digital branches. General speaking, all signals, even the digital ones and zeros signals, (if we acquire their timing,) can be considered as analog. However, direct analog signal processing is extremely tedious.

One complication is that noise exists wherever a signal is applied. Using an analog circuit, eg. an analog filter, to extract the desired signal components from noised ones is still a difficult issue for the complexity of an analog system’s implementation.

In contrast, digital systems offer many advantages, like smaller size, better reliabil­ ity, higher resolution, programmability, insensibility to noise, and much lower cost.

Therefore, if high performance analog-to-digital (A/D) and digital-to-analog (D/A) interfaces are available inexpensively, digital signal processors provide an excellent alternative for implementing an analog or even mixed (analog and digital) system.

In present day, digital signal processing systems are widely applied in daily life.

For instance, compact disc players, digital tapes, phone systems, and high defini­ tion television systems all apply digital signal processing. A future requirement of the whole system is the monolithic integration of both analog interfaces, A/D and

1 D/A, and the digital signal processor into a single chip, so that the noise is reduced

and therefore the system reliability as a whole is significantly improved. The block

diagram of the desired system is shown in Figure 1.1.

Discrete-Time x(t) Decimation y(t) System Rlter h[n],H(eT) Sampling D/A Modulator A/D

Figure 1.1: System Block Diagram

V^Tiile the VLSI technology is continuously improving, high speed performance is one of its main advantages. The conventional A/D converters designed at the

Nyquist sampling rate do not make good use of this characteristic. The oversampling technique, on the other hand, attracts wide attention in the implementation of VLSI analog and digital interfaces. Essentially, this technique trades temporal resolution with amplitude resolution [1]. As the very high sampling rate technique in VLSI gets more mature and less expensive, the goal of a cheap and high performance chip will become possible by the architectures of oversampling as well as VLSI technology.

The fundamental relation of Difierential Pulse Code Modulation (DPCM), Delta

Modulation (AM) and first order Sigma-Delta Modulation (EAM) will be reviewed in Chapter 2 as background. We can check the intuitive characteristics of a EA modulator and how it works. A first order EA modulator example will be used to explore the advantages of the oversampling technique ([2]). This example can also help us to describe the features of EA modulators.

Having described how first order EA modulators perform, we will exploit the various architectures of EA modulators in Chapter 3. The one-bit quantizer, a non­ linear component, is modeled as an additive quantization noise source in this chapter such that the analyzed EAM system becomes a linear system. The Z-domain transfer functions of different second order lowpass EA modulators, which attract the most attention among all EA modulation varieties, will be explored. How the modulators are affected by their transfer functions (and, of course, pole and zero locations) will also be discussed. While low pass EA modulators successfully convert baseband analog messages into one-bit streams, the applications of EA technology to bandpass signal has received more attention recently. One of the most important advantages of bandpass EAM is that no analog-mixer is required. The A/D conversion can be processed directly in the intermediate-frequency (IF) stage of a communication or radio system. Basic structure and performance of a fundamental second order bandpass EA modulator will be included in this chapter.

The model of an one-bit quantizer as an additive quantization noise source works fine for simple analysis and specific input. Nevertheless, for further analysis, (includ­ ing the higher order EAM systems, the stability issue, and the variation relationship between noise shape and input signal,) the previous simple model cannot well ex­ plain some situations. For example, the quantization noise is obviously input signal related. If the input of the EA modulator is a DC value with its magnitude equal to the modulator feedback reference value. A, then the pulse density stream of the one-bit quantizer output should be all digital ones and the power of the quantization noise is reduced to zero instead of which comes &om the assumption that the

quantization noise is equally distributed between quantization levels. An advanced

model for a EA modulator is exploited in Chapter 4. The situations of DC inputs

and sinusoidal inputs to a SA modulator are analyzed in this chapter. The stability

issue for a second order and a higher order SA modulators are also discussed in this

chapter.

In Chapter 5, a wide input range SAM system is proposed. A traditional SAM

system can only have its best performance over a specific range. A second order SAM

system is used as an explanatory example. In the proposed wide input range SAM

system, the high performance input range is extended at least threefold compared

with a traditional one. The calibration technique is applied such that no trimmed

components are necessary in the proposed system. This system includes the advan­

tages of an one-bit quantizer to maintain a linear D/A feedback. This proposed strategy can be applied to diverse SAM systems, including high order and MASH

architectures. The issue of why the proposed system possesses a better SNR than

its competitive conventional one is also discussed using the theoretical architecture

presented in Chapter 4.

The output rate of a SA modulator is much higher than the Nyquist rate because of oversampling. A decimation stage is required to filter out quantization noise as well as reduce output date rate to Nyquist rate. The decimation stage is discussed in

Chapter 6. If an one-bit quantizer is applied to a SA modulator, the output data is a pulse density stream. Because each pulse can only be digital one or zero, a signal- stage multiplierless decimation filter is presented in this chapter. An FIR strategy is interested here in order to maintain the property of linear phase. Because a single- stage FIR decimation filter requires an extremely high tap number of filter coefficients, the memory size and operation speed will be a serious issue in implementation. Two- stage ([3, 4]) decimation filters attract great attention because the number of filter taps can be significantly decreased. A multi-stage comb filter is usually applied as the first step of the decimation stage because the coefficients of a comb filter are all ones.

Another compensation filter is required for the second step of the decimation stage to compensate for the roll-off from the previous comb filter, to filter out the leftover quantization noise, and to decimate the final data rate to the Nyquist frequency.

Some feasible approaches for the second step of the decimation stage are discussed in Chapter 7. Depending on diverse applications, engineers should decide their de­ sired properties, including phase linearity ([5]), memory size([4, 6]), multiplication operations ([7, 8, 9]), baseband disturbance ([10]), coefficient representation ([II,

12]), and filter design algorithms ([13, 14, 15, 16]). In Chapter 7, a coefficients rep­ resentation approach called power-of-two space is applied to accomplish the second step of the decimation stage with no multiplication needed. Therefore, the complete

SAM system contains no multipliers and the hardware size can be kept most efficient.

One very important contribution for the advanced quantizer model in Chapter 4 is that the theoretical quantization noise shape can be closely estimated given a SA modulator. With the theoretical noise shape, we can confidently decide the neces­ sary compensation filter requirements, without relying on a trial and error approach, for the given specifications. A few combinations of comb filter length, decimation rate, and compensation filter are presented in this chapter to demonstrate the system programmability and design trade-oflfe. Chapter 8 concludes the contributions in this dissertation and future works.

In this dissertation, examples are mainly offered using sinusoidal inputs, because,

according to the Fourier Analysis (Fourier series), all signal can be approximately

decomposed as the summation of sinusoidal components ([17, 18, 19]). To explore

the system of interest using sinusoidal signals will not only be fundamental but also

be critical to realize the system. All simulations in this dissertation are executed by

MATLAB and SIMULINK; the data analyses are presented from the viewpoint of power/variance in DFT domain. CHAPTER 2

RELATIONSHIP OF DPCM, AM, AND 2AM

To apply signals to a discrete-time system, the use of an analog to digital (A/D) converter is the first step. Pulse Code Modulation (PCM) has been the direct ap­ proach for this kind of amplitude coding [20]. In order to increase amplitude res­ olution, the difference of the SEimpled signals, but not the sampled signal itself, is encoded, which is the Differential Pulse Code Modulation (DPCM). In this chapter, we will start from the DPCM structure to derive the Delta Modulation (AM) and then the first order Sigma-Delta Modulation (EAM) structure. By this sequence, the operating principle of a SAM becomes clear, which wiU be helpful to the compre­ hension and the modification of designs of various SAM structures. The principle of oversampling technique is also discussed. One example will be demonstrated to explain the function of oversampling on the SAM structure.

2.1 Differential Pulse Code Modulation (DPCM)

Figure 2.1 demonstrates the (one-tap) Differential Pulse Code Modulation (DPCM).

If x{t) is an analog signal to be evaluated and x{kT) is its sample, then we define prediction error d{kT) as d{kT) = x{kT)-x{kT)

= x{kT)-ax{kT -T ), (2.1)

7 X(t) x(kT) x(kT)

(DAO Sbtfler Piredicuir Regtiler (DAO

Figure 2.1: (One-Tap) Differential Pulse Code Modulation

where x{kT) = ax{kT — T) is the one-tap prediction of x{kT). Then we have the mean-square error as

E[(f(A;T)] = E{[x[kT)-aÆ{kT-T)f}

= E[j^{kT)]-2aE[x{kT)x{kT -T)\^a^E[x^{kT -T)]. (2.2)

If x{kT —T) is an unbiased estimate of x{kT — T), Equation 2.2 becomes

%(0) = R^{0)-2aR^{l)+a^R^{0)

= R,{0)[l-2aC:,{l)+a% (2.3) where Rd{0) and /2x(0) are the power of prediction error and signal respectively, i2*(l) is the autocorrelation function (Rx{m)) evaluated at successive x(t) samples (m = 1), and Ci(n) = is the normalized autocorrelation function.

2.2 Delta Modulation (AM)

Based on Equation 2.3, to minimize the power of prediction error, we have to set

dRi{0) = i2^(0)[-2C^(l)+2a] = 0 (2.4) da and the goal is attained as

a = (7 i(l). (2.5)

8 Substituting Equation 2.5 back to Equation 2.3, we have

&(0) = Æ.(0)[1 - C |(l)l = %(0)[1 - a \ (2.6)

Equation 2.6 explains if

o. = Cx(l) = ^ |q | ~ 1 -^(1) ^ ^ (0)> (2.7)

then the power of prediction error is minimized and the prediction gain (defined as

^ ^ ) can be large [20]. Meanwhile, Equation 2.7 can be satisfied if the sam pling rate

is much higher than the Nyquist rate of x{t), because the successive samples have

high correlations; therefore we can claim i2x(l) ^ Rx(0) and apply a weighting term

of a = 1. The fundamental idea of the over-sampling approach is to increase to the

(cor) relationship of successive samples [21].

Applying an one bit quantizer to a DPCM system and setting a = 1 yields another

system called a Delta Modulation (AM or DM) system as shown in Figure 2.2. In

1 d(kT) Level -1 x (lc l) Shifter I )— z LPF 'X Predictor One-Bit Qinnlizcr Level Generator Register x(k-n^T‘ (DAC)

E’tedictor Register Level Generator (DAQ

Figure 2.2: (1st Order) A Modulation System

this architecture, depending on the sign of d{kT), the digital signal d{kT) can only be a digital 0 or 1 and correspondingly, d{kT) is —A or A where A is a constant step size set in the level generator block in Figure 2.2. The predicted signal x{kT) can be

9 expressed as x{kT) = x{kT) + d{kT) = x{kT - T) + A - sign{d{kT)}, (2.8) where f (-) is a one-delay version of x(-). The Low Pass Filter (LPF block) at the end of the AM system is to reject the out of band components [21].

2.3 Sigma-Delta (EA) Modulation

Essentially, there are two kinds of tracking errors in AM system - slope overload and granular noise [20, 21, 22]. Slope overload distortion can be reduced by increasing the step size As, but this will aggravate granular noise distortion, and vice versa.

Applying an integrator in the front of AM system to reduce signal’s variation is a solution to the above two problems. Of course, a differentiator is necessary at the end of the AM system such that the recovered signal yields the input signal, not the integrated input signal. The appending differentiator can cancel out the decoder’s integrator (predictive loop); the preceding integrator is considered merging the encoder’s integrator (predictive loop) and relocated behind the adder to simplify the system’s structure as shown in Figure 2.3. This structure is a first order Sigma-

Delta Modulation (EAM or SDM) system.

x(t) d(t) fs ^ (CLKshii dOcT)' ^SDM Sbifter Predictor Register One-Bit Level Generator Quantizer (DAQ

x(kT) Level Shifter

Level Generator (DAQ

Figure 2.3: (1st -Order) EA Modulation System

1 0 2.4 Example for Oversampling and First-Order EA Modula­ tion

In this section, a speech range input testing signal, % = 3* c o s ( 27t * 9.375Ül' *t) * cos{2ir * 3.125ür *t) = 1.5 * cos(2ir * 12.5ür * t) 4-1.5 * c o s (2 7 * t 6.25AT * t) is applied to investigate the relationship between a EA Modulation/Demodulation system and oversampling. Figure 2.4 and Figure 2.5 show the performance of testing signal through A and EA modulators with sampling frequencies 0.4 Mffz and 12.8 Mffz respectively. If the bandwidth of interest is assumed to be 0 ~ 25 KHz, the Nyquist frequency is 2*25K = 50 KH z and the corresponding oversampling rates are = 8 and = 256.

The original testing signal x is superimposed upon x in Figure 2.4 and Figure 2.5 such that the relative coding variation message is more clear. The step size in AM is set at 1 for a sampling rate of 0.4 MHz and ^ for a 12.8 MHz sampling rate; the level generator in EAM is set to 3 for both sampling rates; the LPFs in both demodulators are generated using a Hamming window with a cut-off frequency of

25 KHz and of the order of 255 (coeflScient length 256). While xsdm has only two possible values (logical high and low), the xqm has several different values depending on the step size in the AM. The level generator in AM should be able to generate many accurate reference levels which is costly in VLSI technology. Moreover, as mentioned in Section 2.2, slope overload and granular noise are still problematic [20,

21, 22]. In contrast, EAM’s demodulator is much simpler than AM’s; EAM has only two codes, which are specially suitable for logic as well as mixed circuit design.

Therefore EAM attracts great attention at present. We will pay attention to only

EAM systems from now on.

1 1 60

lAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA/V 50 MjMJiatt

40 nJM

OOM

OJZ 0.4 0.6 0.8 1.2 Time (msec)

Figure 2.4: A / SA De/Modulation with a Sampling Frequency of 0.4 MHz

60

50

40

OJZ 0.4 0.6 0.8 1.2 Time (msec)

Figure 2.5: A / SA De/Modulation with a Sampling Frequency of 12.8 MHz

1 2 To appreciate the function of oversampling, we should check the frequency do­ main of Xsdm with different oversampling rates. Figure 2.6 and Figure 2.7 are the frequency domain spectra of Xsdm hi its full sampling frequency range and its Nyquist frequency range.

09

09

0.7 07

0.6

JOS

rOA 0.4

OJ 03

0 .1 oi

150 2 0 0 250 900 960 400 KKZ KHz (a). Full Frequency Domain (b). Nyquist Frequency Domain

Figure 2.6: Frequency Spectrum of x with an Oversampling Rate of 8

1

09

09

07

0.6

r0.4

I S10 1S 20 25 90 96 40 4SSO KHz (a). Full Frequency Domain (b). Nyquist Frequency Domain

Figure 2.7: Frequency Spectrum of x with an Oversampling Rate of 256

13 Comparing Figure 2.6 and Figure 2.7, the increment in sampling rate obviously has

two features - reducing the magnitude of the quantization noise as well as separating

signal and quantization noise components. The signal’s two frequency components

(pulses) are located at 6.25 KHz and 12.5 KHz only. These two signal components

in Figure 2.7 (oversampling rate of 256) clearly separate the quantizing noise (high

frequency components) further than those in Figure 2.6 (oversampling rate of 8.)

Consequently, the filter which is to extract the input signal components in Figure 2.7

(oversampling rate of 256), will be easier to design than the filter extracting corre­ sponding components from Figure 2.6 (oversampling rate of 8). Moreover, Figure 2.7 also explains why a loose anti-aliasing filter is enough for the situation with high over- sampling rate. Furthermore, because x is simply the level-shifted and scaled version of the quantized (digital) signal d{kT), (referred to Figure 2.3,) we can imagine the spectrum of d{kT) is sim ilar to the spectrum of x(kT) except for the scale factor and

DC component.

14 C H A PT E R 3

MODELING AND ANALYZING SAM

In this chapter, we will model diverse EA modulators as linear systems and check their Z-domain transfer functions to approximately explain and anticipate their per­ formance. Notice that the linear model discussed in this chapter is not 100% correct but it is simple and easy to understand; its analysis closely agrees with simulated (or experimental) results in many applications; therefore, it is popularly applied in the discussion of SAM [5, 23, 24]. (more sophisticated model will be presented in Chap­ ter 4.) Three second order lowpass and one fundamental second order bandpass SA modulators will be discussed and analyzed to check their (approximate) theoretical performance with their simulated results.

3.1 Modeling EA Modulators

Figure 2.3 shows the first order lowpass SA modulator/demodulator system block diagram. We are much interested in the modulator portion. The behavior of the One-

Bit Quantizer is d(kT\ = / ^Sital 1; when d{kT) > 0 . . ^ ^ { digital 0; when d(kT) < 0 ^ ^ The quantization error, e(kT), can be defined as

e{kT)=x{kT)-d{kT), (3.2)

15 then, &om Equation 3.2,

x{kT) = rf(fcT)+e(fcT)

= d{kT - T ) + d{kT - T) + e(fcT)

= x{kT - T ) - x{kT - T) + d{kT - T) + e{kT)

= x{kT - T ) + e(fcT) - e{kT - T) (3.3)

Equation 3.3 approximates the main function of the first order SA modulator. The estimated signal, x{kT), contains signal component as well as noise components. The signal component, x{kT — T), at the system output is just an one-sample delay. The first order difference of the quantization error, but not the quantization error itself, appears at the EA modulator output. We expect, the quantization error difference should be much smaller than quantization error because oversampling technology results in the successive samples being quite close to each other. The quantization error difference works like reducing the noise in the low frequency range [5, 25].

Some assumptions are generally applied for further processing of the quantizer.

The quantization error e{kT) is assumed white, uncorrelated with the input (d{kT) or indirectly x{kT)), uniformly distributed between quantization levels, and no over­ load condition occurred. These assumptions are obviously not perfect. However, analyses with these conditions closely match both the simulation and application re­ sults; therefore, these assumptions are widely used [23, 26, 24]. To simply the EAM structure shown in Figure 2.3, the level generator (ADC) is merged with the one-bit quantizer and widehatx{kT) is denoted as y(kT) for clearness; the first order EA modulator can then be modeled as Figure 3.1.

16 x(kT)

Figure 3.1: (1st Order) EA Modulator (with Additive Quantization Error Model)

Based on Figure 3.1, the STF (Signal Tiransfer Function) S{Z) of the first order

EA modulator can be derived:

[X(Z) - Y{Z)\ * = YiZ), Z — 1

X (Z ) y ( z ) *z, Z — 1 Zf — 1 i 1 S{Z) = (3.4) %(Z) z the NTF (Noise Transfer Function) N{Z) can also be derived:

-Y {Z )*^ ^ + E{Z)=Y{Z),

E(Z) = . Z,

(3.5)

Observe that Equation 3.4 and 3.5 are consistent with Equation 3.3. To investigate the NTF’s frequency spectrum, Z is substituted by ^ Equation 3.5 to get

I N(e;^) I = I 1 - I = I _ e-jv/T) |

= 2sm(7r/T). (3.6)

17 Equation 3.5 and Equation 3.6 explain that the noise shaping action of the first order

EA modulator is fundamentally a high pass function. The signal components, because of oversampling, will be located in the low firequency range. Therefore, we can extract signal components easily since the noise is mainly shifted to the high frequency range

(noise shaping). This statement also explains the characteristics of Figure 2.6 and

Figure 2.7.

If the quantization noise is assumed to be equally distributed between quantization level, the one-bit quantizer characteristic can be demonstrated by Figure 3.2 and the

Output

£■ Overload

-A Input Overload

Figure 3.2: One-Bit Quantizer Characteristic

quantization noise power is

(3.7) 3

18 Based on Equation 3.5 and Equation 3.6, if the NTF of a Lth order EA modulator is expressed as

iVt(Z) = (1 - (3.8) the frequency spectrum of the quantization noise (after shaping) ,5iv(/), can be de­ noted as

S^if) = [| N[,{Z) - [fs\ noise shaping noise power density

= [2sin(7r/T)]“ • ^ fs « (27rf)2^-^ (for T=land^,Cl) (3.9) fs fs fs fs where /, is the sampling frequency. Observe that Equation 3.9 explains the situation of the larger sampling frequency resulting in the smaller quantization error spectrum as shown in Figure 2.6 and Figure 2.7. To get the quantization noise power within baseband range, Sb , Equation 3.9 is integrated between [—^ , ^ ] (/v representing the Nyquist frequency of baseband):

Sb = I ^ S M ) d f

^ • f ‘'■f

where M = is defined as the oversampling rate. Equation 3.10 shows that the quantization error power is attenuated by the (2L4-l)st fold of the oversampling ratio

19 [5]. The dynamic range, DR, of an A/D converter with sinusoidal inputs is defined as the ratio of the output power at the firequency of the input sinusoid for a full scale input to the output signal power for a small input for which the SNR is unity (0 dB)

[5, 1]. The power of a full scale sinusoidal input is the power of an SNR=OdB signal equals the power of its noise, which is ^ (firom Equation 3.10 and Equation 3.7). Therefore, for an ideal EA modulator with a full scale input range of ±A, the dynamic range is:

o r _i_ 1 = 1.76 +10 • log - -H (2L + 1) • 10 • logM (dB). (3.11)

On the other hand, the dynamic range of a Nyquist rate uniform PCM (with b-bit) quantizer is

= 1.76 + 6.026 (dB). (3.12)

From Equation 3.11 and Equation 3.12, we can calculate the reachable (or equivalent) bit resolution for a given Lth order EA modulator with oversampling rate M. The relationship is shown in Figure 3.3.

Hence, if, for instance, 16 bit resolution (or equivalently 98.09 dB) is the system requirement. Mut order > 2418, Mgnd order > 153, and Mzrd order > 49 are neces­ sary for the oversampling rate of diverse EA modulators. For a Nyquist firequency of 50 KHz, the corresponding sampling firequencies are > 120.9 MHz, fsind order ^ 7.65 MHz, Bud > 2.45 MHz. The 1st order EA modulator is still not very suitable for high-resolution requirement now. Moreover, the quantiza­ tion noise of a 1st order EA modulator is considered highly correlated [27, 5].

2 0 35

ardqrtfer -!— 2nd order

25 rrr.'ist.c^er

S20

S 15 - 92.071»

- 31.96 dB-

Oversampling Ratio M in Octaves

Figure 3.3: Dynamic Range of EA Modulation

Meanwhile, for the 3rd order EA modulator, because there are three poles in its

NTF, the stability problem complicates its design [1]. One approach to achieve high order as well as stability is to cascade several first or second order modulators ([28,

29, 30, 31]), which is call the Multi stAge noise SHage (MASH) architecture. One fundamental MASH architecture is shown in Figure 3.4.

In Z-domain, the output of this architecture is

ffi Z~^ X Z~^ -E l Hi • Z~^ • E l Eg V = 1-HHi -Z-i H-Hi Z-: Ha (I4-H2 E-i) H3 • (1 + Ha • Z-^) Hi • Z-2 . X ^ (Ha - Hi) • Z-i • Ei Ea (if Hi = Ha) 1 + Hi-Z-i Ha-(H-Hi-Z-i) Ha • (1 + Hi • Z'^) Hi • Z-2 . X Ea (if Hi = Ha) l-fHi-Z-i Hi-(H-Hi.Z-i) = Z-2 . X - (1 - Z~^)2. Ea (Hi = iz^=r). (3.13)

2 1 x(kT) y(kT)

Quantizer

+"

Quantizer

Figure 3.4: Cascade of Two 1st Order 2 AMs (MASH Architecture)

The advantages of the MASH architecture are both stability and freedom from pattern noise in the output if the cascading stages are large enough. However, the MASH structure asks for high precision gain matching between the individual first order sections [Hi = H2 = Hz ’va Equation 3.13), which violates the intention of insensitivity to parameter tolerances and component mismatch [5]. Furthermore, if a switched capacitor implementation is applied to match the integrator transfer function of the

MASH structure, the required opamp gain must be very high [1].

A multi-bit quantizer [30, 32, 33, 34] in the feedback loop is another approach to increase the resolution of a given order EA modulator. If a b-bit quantizer is applied, the system’s dynamic range becomes

Ai Ai DR = 2 2 JLÜ- . ('i')2L+l . 1 . / A \2 jdL . . 1 . f4')2 2 L + 1 vAf/ 3 1 2^ / 2 L + 1 VAf/ 3

2 2 = — 226 7T2L or _ i_ 1 = 1.76 + 6.026 4-10 • log— ^ — h (2L 4-1) • 10 • logM (dB) (3.14)

Comparing Equation 3.11 and Equation 3.14, because the rms noise is proportional to the quantization step size, this structure can result in a 6.02 dB improvement for every bit added to the quantizer. However, the previous advantage is at the expense of component accuracy (DAC) and design complexity [35, 36].

In contrast, the second order EA architecture with one bit quantizer is insensitive to circuit nonidealities and parameter variations; its stability is also guaranteed over the full analog input range. It should then be the reasonable choice for a general purpose application.

3.2 Second Order Lowpass EA Modulators

Figure 3.5 shows a conventional second order EA modulator with one-bit quantizer modeled as additive noise.

e(kT)

y(kT)

One-Bit Quantizer

Figure 3.5: Conventional 2nd Order EA Modulator

23 Its signal and noise transfer functions are

STF: s{z) = ^ = (3.15)

Pole: Z = 0 No Zero

NTF: (3.16) ff(Z) = Z2 = (1 - z-^ f Poles: Z = 0, Q Zeros: Z = 1, 1

Observe that the NTF is the ideal format: (1 — Z~^)^ with L = 2. However, this ideal format is difficult to reach because the signal range required at the outputs of the two integrators of this conventional structure is several times the full-scale analog input range, ±A [5]. This situation will result in a saturation problem in the two integrators unless the input signal’s dynamic range is constrained.

Bernhard Ernst Boser proposed another structure, as shown in Figure 3.6, to improve this problem [5]. Boser’s approach has been successfully applied to digital- audio signal acquisition [23].

One*Bit Quanü«f

Figure 3.6: Boser’s 2nd Order EA Modulator

Its system functions are

STF: S(Z) = (3.17) 4Z2 -6Z-H3 3 ± jV3 Poles: Z = = 0.866e*Jt No Zero

24 N T F : = (3.18)

Poles: Z = —— ■■ = = 0.866e^^= Zero: 2T = I, 1

This confignration is different from the conventional one in two aspects. First, a forward path delay in applied in the two integrators, which will greatly simplify the implementation of the modulator with straightforward sampled-data analog circuits.

Second, each integrator is preceded by an attenuation of |. By the attenuation, the in­ tegrator circuit saturation problem is greatly reduced and the modulator performance becomes much better than the conventional one. EYom Equation 3.17, because the

DC gain (as Z = 1) is unity, we can anticipate that the signal’s gain in Boser’s struc­ ture will be close to 1, whenever the sampling rate is high enough and the input is within a reasonable dynamic range.

In contrast, Kishan Shenoi proposes another second order architecture, as shown in Figure 3.7 [25], to improve the conventional structure’s signal gain.

eflcT)

x(kT)

One-Bit Quantizer

Figure 3.7: Shenoi’s 2nd Order EA Modulator

Its system functions are

STF: 5(Z ) (3.19) 2Z2 - 2Z +1

25 Poles: Z = = 0.707é^^* No Zero

NTF: N(Z) =

Poles: Z = = 0.707e^^^ Zeros: Z = l, I

Check that Shenoi’s signal DC gain is 2. Moreover, Equation 3.16, Equation 3.18 and

Equation 3.20 all present no noise gain in DC, which is expected since the oversampled signal will be relatively close to DC.

One sinusoid input signal: 2 * cos(2ir * 9.375K * t) * cos {2-k * 3.125ÜT * t) =

œs{2ir*12.5K*t)+œs{2Tr*6.25K*t) was used to check the performance of first order,

conventional second order, Boser’s second order, and Shenoi’s second order EA mod­

ulators. The sampling firequency was 3.2 MHz; signal bandwidth was 0 ~ 25 KHz;

Nyquist rate was 50 KHz, and therefore the oversampling rate M = = 64.

Figure 3.8 demonstrates their performances (x) in firequency domain. (Here power supply ±A, (±5 volts), is assumed and the integrator outputs are constrained as

1.7 * ±5 volts, which is under Boser’s best performance condition.)

From Figure 3.8, as anticipated, the second order EA modulators separate quan­ tization noise further and have smaller quantization noise than the first order EA modulator does. Figure 3.8 is also consistent with our analyses that the Boser’s

EAM generates the smallest quantization noise and Shenoi’s EAM has signal gain 2 while the others have signal gain only 1.

26 (a). First Order EAM (b). Conventional Second Order EAM

Boser’s Second Order EAM (d). Shenoi’s Second Order EAM

Figure 3.8: Frequency Spectrum of x with an Oversampling Rate of 64

3.3 Second Order Bandpass EA Modulator

As lowpass EA modulators successfully process baseband signal A /D conversions, applying the same technology in passband also attracts more and more attention [37,

38, 39]. In this section, a fundamental second order EA modulator is demonstrated and analyzed.

Based on Figure 3.1, if the integrator is replaced by a resonator with transfer function: H{Z) = — , as shown in Figure 3.9.

27 -2 -2 I + Z x(kT)

Figure 3.9: (2nd Order) Bandpass SA Modulator

The system functions become:

STF: S{Z) = -z~^ (3.21)

Poles: Z = 0, 0 No Zero

NTF: (3.22) Z2 Poles:Z = 0, 0 Zeros: Z = ±j =

We observe that the signal component (s) will pass through the system with only two discrete time delays and an inverse sign which are not considered distortions.

On the other hand, quantization noise has zeros located at ± |, which represent one forth of sampling frequency. Therefore, if a signal (carrier) frequency is exactly one

forth of the sampling frequency, signal component(s) can be extracted by a followed bandpass filter. One input signal 4 * cos(27t * 6.25K *t) * cos{2tt* 3.2M * t ) with sampling frequency 12.8 MHz is applied to examine the system performance. The frequency spectrum is shown in Figure 3.10.

28 (a). Pull Frequency Domain (b). Zoomed Frequency Domain

Figure 3.10: Frequency Spectrum of a 2nd Order Bandpass EA Modulator

We can check that the signal components actually do locate around 3.2 MHz (= carrier frequency = t of sampling frequency.)

29 C H A PTER 4

ADVANCED MODEL FOR SAM AND NOISE SHAPING

In Chapter 3, modeling the one-bit quantizer as an additive White noise is simple and clear for a stable EAM; however, to discuss stability issues and higher order (> 3)

EAM systems, the additive White noise model for the quantizer is not enough. For example, a gain stage between the integrator and the quantizer of a EAM is suppos­ edly no different from the EAM without the gain stage because of the nonlinearity characteristic of the quantizer. The additive White noise model for the quantizer fails in modeling these situations [40].

An advanced model for general EAM systems is to include the statistical concept for the quantizer [41, 42, 43]. The sophisticated model for the EAM and noise shaping will be analyzed in this chapter. To exploit the statistical model for EAM system, without loss of generality, a EA Modulator can be modeled as shown in Figure 4.1

([41]).

One-Bit Quantizer x(k) e(k) B(Z)A(Z) Q(e)

Figure 4.1: Block Diagram of a EA Modulator

30 The one-bit quantizer is the only nonlinear part in this system. For advanced modeling, the input to the quantizer is modeled as two additive components, one from input signal x{k) and associated with the linearized quantization noise signal component gain, Gx, while the other one from the additive quantization noise, n(&), and associated with the linearized quantization noise random component gain, G„, as shown in Figure 4.2. Because different inputs x(Ar)'s will result in different statistical

1-bit Quantizer n(k)

Gn x(k) e(k) y(k) A(Z) B(Z) Gx

Figure 4.2: Advanced Model of a SA Modulator

properties of the SAM outputs, two most critical kind of inputs, DC and sinusoid, will be discussed in this chapter. The reasons to apply these two testing signals are that some stationary signals (like temperature and humidity) are close to DC while other signals (like speech and music) vary from time to time. By the Fourier

Analysis (Fourier Series), varying signals can be approximately decomposed as the summation of several sinusoidal components. Because the EAM is also modeled as a linear system, theoretically, all varying signals can be analyzed using the model coming from the assumption of a sinusoidal input.

31 4.1 The Advanced EAM Model as DC Input

For a DC input to the EAM system, if the quantizer input e(k) can also be denoted as an additive mean value me and a zero mean random component en(k),

Figure 4.2 can be represented as Figure 4.3. Note that n(k) is an additive White noise as applied in Chapter 3.

x(k) GxB(Z)

(a). Equivalent Linearized EAM Model for Signal Components

n(k)

B(Z)

(b). Equivalent Linearized EAM Model for Random Components

Figure 4.3: EAM Model with Separate Sources: x(k) and n(k)

The goal of modeling a EA Modulator as Figure 4.2 or Figure 4.3 is to determine

Gx and Gn such that the mean square error between the nonlinear quantizer and the linearized gains is minimized [41]. The error is defined as the quantization error n(k).

Therefore,

n{k)=y{k)-Gx'‘me-Gjt-en{k), (4.1) then the mean square error (variance) is

= E{n^k)}

= E{[y{k) -G x-m e-G n- e«(&)]^}

32 = E{y^{k)} + Glml + - 2Gxm^E{y{k))

-2GnE{y{k)e^{k)} + 2G^Grjn^E{en{k)}

= W ( t ) } + Glml + - 2G,m,E{y{k)} - 2Gr,E{y{k)e^{k)}, (4.2) assuming that E{enijk)} = 0. Taking the partial derivatives with respect to Gx and

G„ and setting them to zeros, we have

= 2Gxml - 2meE{y{k )} = 0 (4.3) and ^ = 2GnO^ - 2E{y{k)en{k)} = 0 (4.4)

Although no assumptions are made on the probability density distribution of the noise n{k), the signal, en{k), into the nonlinearity (one-bit quantizer) due to the noise is a double- or higher-order integrated version of the noise n(k) for a second- or higher-order one-bit quantizer SAM. The integration of a random variable tend to approach its distribution to a Gaussian distribution. Therefore, en(k) can be assumed to be a zero-mean Gaussian distribution variable ([41]). From Equation 4.3,

Gx = m .

33 where Q( ) is the one-bit quantizer function, is the outputs of the one-bit quan­ tizer,

erf{s) = / ezp(-f) dt, v'tt Jo and for zero-mean en{k),

^ = ^{4} = 4-6») -rrie]^} = E{[e{k) - mg]^} = o f.

Meanwhile, &om Equation 4.4,

G . = (4.6)

1 r®® 1 6^ = -T / ^ + G») • -= — exp{—^ ) de» J-oo v27rae„ 2(7^ 1 1 6^ = ~ 2 e»-Q(mg 4- e») • -y= — exp{—^ ) de» 0-| J-oo v27TO-e„ 2 ct|

" ; f X o o ^ = ^ CT C l A t=zzz^ _A -ea;p(£)|t=J^ 4- /— ezp(£)C°^2 \/^ (T e °° V^CT,

V^CTg 2o-2

Meanwhile, because

^{n(fc)e»(A;)} = .E{[y(fc) - G^me - G„e»(A;)]e»(A:)}

= E{y(fc)e»(fc)} - GxmeE{en{k)} - G»afCn

= 0 (from Equation 4.6 and E{e»(A;)} = 0) (4.8) the quantization noise n{k) is uncorrelated with e»(fc).

34 Prom Figure 4.3 (a),

— <« where, nix is the mean value of EAM input x{k) which is located at very low frequency portion compared with the sampling frequency; therefore, the frequency of interest corresponds to Z « 1. Meanwhile, A(Z w 1) w 1 and B{Z « 1) —> oo if an integrator is applied to the EAM. From Equation 4.5 and Equation 4.9, we get

= T -

From Figure 4.2, the pulse density stream output y{k) can be expressed as

y(fc) = GxTTie + G„en(fc) + n(fc); (4.11) therefore,

E{y^{k)} = A^ = Glml + Glal^ + = Glm\ + Gla^ + o^. (4.12)

By Equation 4.7, Equation 4.9, Equation 4.10, and Equation 4.12,

al = - ml - ^ea;p(-2[er/"^(^)]2). (4.13)

Equation 4.13 demonstrates that the additive quantization noise vEiriance depends only on the input mean value (m*), is independent of the loop gain, and is not always

^ which is from the assumption that the quantization noise is equally distributed between the one-bit quantizer outputs of ±A. When m* —^ A, > 0. The rela­ tionship of al and DC input magnitude mx is demonstrated in Figure 4.4.

To be specific, if a second order EAM has memory on its integrator feed forward path with integrator gain factors, ai and Ofa, preceding the first and second integrator

35 FWeioiieh^ e< m, and ^ as DC Input

0 3 6

0 3

0 0 6

ai 02 0 3 0 4 0 5 0 6 DC Input MagnOwdK t \ (wkA)

Figure 4.4; Relationship of and as a DC Input to a SA Modulator respectively, then from Figure 4.3 (b), the variance becomes

^ r \ B{exp{-jw)) dw " 27r7-x'l+G„B(exp(-jjw)) noise shaping

_ Z ^ r I______-otx<^2exp{—j 2w) - 0 2 ( 1 - exp{—jw)]exp{-jw) ______2

27t 7-ir [1 — exp{—jw)Y + o:2 Gn[l — exp(—jw) + aiexp{—jw)]exp{—jw) (4.14) where the additive quantization noise, n(k), is assumed to be White. Meanwhile, from Equation 4.7, 2 , A (4.15)

From Equation 4.10, Equation 4.14 and Equation 4.15, given ai and 0C2, the relation­ ship of rrii, cTg, and G„, will be available. Figure 4.5 demonstrates the relationship as ai = 0.5 and 0 2 = 1.

Note that the line marked ’o’ is the real relation position while the lines marked ’x’ are the projections to the individual surfaces. Known Ce and nix, from Equation 4.10, me is available. Then, Gx can be obtained from Equation 4.5. Figure 4.6 explains their relationship.

36 ■r* «"'« #/* 0-* 0 8

OC p C la p 'll

. RelatioasW o f TrVïi ç'iguie 4.5

.s.»-"— " '”'’' #*»OCW^*®

•»>

08 800

400 08 ry*"* « *'J* «■ 0.»

pû^îAoduiator OC t o a pC tn>e> çigttte 4.6-. 3 Î Figure 4.5 and Figure 4.6 demonstrate that Gn and Gx decrease as the input sinusoidal magnitude (rrix) increases. Meanwhile, Because of saturation, and me increase and then decrease as rrix close to reference value A.

4.2 The Advanced SAM Model as Sinusoidal Input

In this section, we will exploit the effect of the advanced model (Figure 4.2 and

Figure 4.3) with a sinusoidal input. The me shown in Figure 4.2 and Figure 4.3 should be modified to be ex{k) because the information at this node is a function of time in this case. Let the quantization error n(k) be defined as

n{k) = y{k) — Gx • ei(fc) — Gn • en{k), (4.16) then the mean square error (variance) becomes

al = E{n^{k)}

= E{[y{k)-Gx’ex(k)-Gn-en(k)f}

= W (t)} + G:(TL4-G^o^

—2GxE{y{k)ex{k)} — 2GnE{y{k)en{k)} 4- 2GxGnE{ex{k)en{k)}

= E{y^{k)} + Gla^^+Glal^

-2GnE{yik)enik)} - 2GnE{y(k)en{k)} (4.17)

with the assumption that the ex(k) and en{k) are uncorrelated and E{en{k)} = 0 .

Taking the partial derivatives with respect to Gx and Gn respectively and setting them to be zeros, we can get

M = 2G,ai - 2E{y(k)e.(h)} = 0 (4.18)

^ = 2G.<7j, - 2E(,(t)e.(t)} = 0 (4.19)

38 Therefore,

^ _ E{y{k)e^{k)} * ------< 1 yoo foo = - 3- / / ^ * Q(6% + e„)9(ex)p(en) de^ dSn (4.20) J—00 J—00

^ _ ■®{y(^)en(A:)} “ < 1 roo roo = - 9 - / / ■ Q (6% + en)ç(ei)p(e„) rfe„ 4 (.2 1 ) J—00 J—00

where

?(e*) = i(4-e2)-i (4.22)

is the probability density function (pdf) of the sinusoidal signal with amplitude a^,

and

is the pdf of the Gaussian input e„(fe) ([41]).

Thesolutions of Equation 4.20 and Equation 4.21 are solved by Derek P. Atherton

([44])with the assumption that the one-bit quantizer is an ideal relay ([41]). The results are

Gx = i /^ ( — )^(% , 2, -p^) (4.24) V 7T O^n ^

G . = V 7T CTg z 1. V) (4.25) where

p = —^ (4.26) ^en and the function M{pc,0,'y) is the confluent hypergeometric function ([45]):

M{a, P, 7 ) = p-/o- ^ exp( 7 t)t“"^(l - dt. (4.27) r(/3 - o:)r(o:) 7o

39 Prom Figure 4.3 (a),

g.(Z ) _ A(Z)B(Z) _ 1 X(Z) 1 + G.B(Z) G,

if an integrator is applied to the SAM and oversampling technology is utilized. It

follows that

because cr^ = ^ for a sinusoidal signal.

From Figure 4.2, the pulse density stream output y(k) can be denoted as

i/(k) = GxCxCk) + GnSnik) 4- n{k) , (4.30)

and

g{y^(*)} = A= = GK+Gj

From Equation 4.24 emd Equation 4.29,

=► 2, -p^) = (by Equation 4.26) '2 ’ ’ 4A2 => % = ^ = zAVM::(i2,-/) (4.32)

From Equation 4.31, Equation 4.32, and Equation 4.25 , it follows

cr^ = A^[l — -p^M ^(-, 2, —p^) — —M^(-, 1, —p^)\ (4.33)

Note that A f(|, 1 , —p^) = exp (^ )/o(^ ), where /o(-) is the modified Bessel function of the first kind with order 0 , and M (j, 2, —p^) should be solved directly from Equa­ tion 4.27. The relationship between a* and p can be obtained from Equation 4.32

40 and then the relationship of quantization noise power and p (and a^) can follow from Equation 4.33. Figure 4.7 demonstrates their relationship and explains that the assumption, is quite acceptable as sinusoidal inputs.

01 and p* ■■ SkMGidil ImM B a ZSM 1 ‘X ' —1 -- 1 — 'I ------T------1— ■ -r- • ...... ^

* I ...... -...... ^......

...... < .... I ......

: ...... a.-B.-'-l*- , Shwoidrt M aanftlT ^ (unit A)

Figure 4.7: Relationship of and as a Sinusoidal Input to a EA Modulator

Again, to be specific, if a second order EAM has memory on its integrator feed forward path with integrator gain factors, ai and 0 =2 , preceding the first and second integrator respectively, then from Figure 4.3 (b), the variance cr^ is

B(exp{-jw)) 2 • ' - - ’« O t + GnB{exp{-jw)) noise shaping

—aia 2exp{—j 2w) — 0 :2 [ 1 — exp{—jw)]exp{—jw) = ^ r I-— ’ dw, 27t j- k ' [11 —- exp(—jw)]'^ + 0 !2 Gn[l — exp{—jw) + aiexp{—jw)]exp{—jw) (4.34)

41 where the additive quantization noise, n(fc), is assumed to be White. Meanwhile,

from Equation 4.25,

1, -P^) (4.35)

Prom Equation 4.34 and Equation 4.35, given ai and 0 :2 , the relationship of Gn and p

(and Ox) will be available. Thereafter, from Equation 4.35, we can get the relationship

of and p (and Ox). Figure 4.8 demonstrates the relationship as ai = 0.5 and

0=2 = 1 . Note that the line marked ’o’ is the real relation position while the lines

marked ’x’ are the projections to the individual surfaces.

RaladonsNp Of and M a SInuMédBl Input to a Sacond Onter £dM wHh a^vOS md <^*1

1 .6 1.4-

06 06 04

0 2 -

06 06

Sinusoidtl MagnttudK ^ (unit: A)

Figure 4.8: Relationship of a*, a^, and as a Sinusoidal Input to a SA Modulator

Using Equation 4.24 and then Equation 4.29, the relationship of Gx, and ax is available as shown in Figure 4.9. Figure 4.8 and 4.9 explain that Gn and G* decrease while the variance and increase as long as the input sinusoidal magnitude (a*)

42 Millonsritp of 1^ and 6 ^ w ft Shunidal Input to ft Sacond Ordtr ^ twMh 0 ,- 0 5 and

12

ir­ as 04

02 0 4 0 6

SinuMidal MagnttudK ^ (unttzA)

Figure 4.9: Relationship of a^, a^, and Gx as a. Sinusoidal Input to a EA Modulator

aggrandizes. The aflEect of the reduced gain factors (G„ and Gx) will be exploited later.

4.3 Affect of Quantization Noise Signal Component Gain Gx in Stability

From Figure 4.6 and Figure 4.9, we realize that the Gx decreases while the input magnitude increases no matter the input is a DC or a sinusoidal signal. The variation of Gx will affect the stability. Figure 4.10 is the pole root locus as Gx changes for a second order SAM with memory on the integrator feed forward path and first integrator gain a\ = 0.5 and second integrator gain « 2 = 1-

In Figure 4.10, as the G* = 0, all poles start from (IJO) in the complex Z- plane. As the Gx keeps increasing, the locus reach the real axis and separate to the opposite directions upon the real axis. The pole paths are within the unit circle except

43 Root Locus of the Pales as o,aO^. Ojb I. and Q^aO - 3

■1 - 0 5 0 1 Real Ajds

Figure 4.10: Pole Root Locus of a 2nd Order EA Modulator (ai = 0.5 and 0 2 = 1)

Gx > G'x„iS~ 2 here). In this situation, one root goes outside the unit circle on the negative real axis. This means that if for any reason Gx > (jx„io ^he system will become (temporarily) unstable even though this is just a second order EAM.

Fortunately, as soon as one pole goes outside the unit circle, signal levels within the modulator increase; the input to the quantizer increases, the gain will decline, and the pole moves back inside the unit circle, maintaining the modulator in stable operation

[42]. Note that the model appUed in Chapter 3 is the case that Gx is assumed to be fixed on 1 .

The importance of Gx to the stability of a EAM will become significant as the order of the EAM increases. Figure 4.11 shows the cases for a third order EAM, which has memory in the integrator feed forward path and three integrator gains 0 :1 , tt2 , and 0=3 respectively.

44 Root Locus of liw Paies a s a ,> 0 5 . o^aO ^. c^ bI . and 6^>0 - 3

1.33 03

1 0 0 3 1 Real Axis

(a). Pole Root Locus as o-i = 0.5, « 2 = 0.5, and 0 :3 = 1

Root Locus of the Poles es a , >035. c^>03S. o ^ a l. and G^aO - 3

G =0.41

I I

1 0 1 Real Axis

(b). Pole Root Locus as o:i = 0.25, 0 -2 = 0.25, and 0 :3 = 1

Figure 4.11: Pole Root Locus of a 3rd Order EA Modulator

45 Similarly, the pole loci start from (1 jO) in Z-plane as Gx increases &om 0. Two pole loci go outside the unit circle while the third locus heads for the negative real axis as the Gx increasing starting from 0. The outside-unit-circle complex conjugate poles (while Gx < Gx„n) does not lead to a stable limit cycle operation because signal levels within the modulator become too large and drive the pair of complex roots outside the unit circle. Signal levels in the modulator will grow larger such that the Gx decreases, and the complex conjugate roots will move further outside the unit circle instead of back inside ([42]). The complex conjugate pole pair will go back inside the unit circle if G* > Gxcrit while the pole locus on the negative real axis may go outside the unit circle while Gx > G'xcru this negative real pole does not affect the modulator stability by the same argument already given in second order case. In addition, from Figure 4.11, the smaller ori and a 2 have a smaller Gx„u- However, lower integrator gain will sacrifice the system Signal to Noise Ratio (SNR). A few higher order (> 3) SAMs’ design algorithms and stability discussion are documented in [40, 42, 46]; the instability issue resulted from integrator saturation is solved by resetting the integrator whenever the integrator saturation situation is detected. In summary, keeping high Gx (> Gx„u) is critical to the system stability; moreover, from Figure 4.9, we realize that lower variance (a^) will allow for higher Gx-

4.4 Affect of Quantization Noise Random Component Gain Gn in Noise Shaping

Figure 4.5 and Figure 4.8 demonstrate that the Gn will decrease as long as the input magnitude increases no matter whether the input is a DC or a sinusoidal signal.

From Figure 4.3 (b), for a second order SAM with memory on the integrator feed

46 forward path and integrator gains, a i and «2 , the shaped noise Vn(Z) is

Vn(^) = iV(^) • ( 1 _ 2 - 1 ) 2 + a2Gn[(l ~

We have assumed that the quantization noise iV’(Z) is White, therefore,

= (4.37) J s where /, is the sampling frequency. Hence, the noise spectrum becomes

s A f )

, (1 - \(4.38) f s (1 _ e-;2^^)2 + a2Gn[{l -

Figure 4.12 demonstrates the importance of diverse G^’s to the noise shaping, Sn-

(The Gn = 0.1265 is corresponding to a* « A while the Gn = 1.2131 is relative to ttx « 0. The noise shaping of G„ = ° i2G5f i . 2 i3 i _ 0.6698 is also plotted for reference.)

Note that the x-axis is the normalized frequency and the unit in y-axis ignores the factor of ^ which is a constant by the previous assumption.

Figure 4.12 demonstrates that the lower G„ is, the larger that the quantization noise is into the baseband frequency range which is of interest. To have a better signal to noise ratio, G„ should be kept high. We also notice that, from Figure 4.8, lower variance cr^ allows for higher Gn-

Note that in this chapter, all of the last-stage integrator gains are assumed to be

I’s. Actually, if the last-stage integrator gain is reduced by a factor, the Gx and Gn will correspondingly increase exactly the same factor and thus results in the entire system properties have no change at all.

47 T)wRelat>aiBNpa(G^andNaisaSliaplhg«iWirnpactloa toaSscanlORtar£&Mwima,>a5arKla2«

j I

0.4 0.6 1.4 1.6 Frequenqr(untt;x)

Figure 4.12: Noise Shaping of a 2nd Order SAM (ai = 0.5 and 0 -2 = 1) with Diverse Gn’s

48 C H A PT E R 5

WIDE INPUT RANGE EAM

A new design algorithm is introduced to improve the input ranges of a Sigma-

Delta Modulation (SAM). Digital error correction techniques [35, 33] are modified to carry out the wide range DAC of a EA modulator. This design algorithm includes the advantages from both single-bit EAM and multi-bit EAM. This chapter utilizes a second order lowpass EA modulator as an explanatory example to demonstrate the design process as well as the performance improvement. This algorithm can also be applied to different order EAM’s with lowpass, bandpass and MASH architectures.

Applying the advanced model mentioned in Chapter 4, the reason of improvement is also discussed in this chapter.

5.1 Introduction and Problem Description

The performance of a EA modulator is described by Dynamic Range {DR) in

Equation 3.14:

o r _L 1 DR = 1.76 -h 6.02iV +10 • log 4- {2L 4-1) • 10 • logM (dB) where N is for N-bit DAC feedback, L is the system order, and M is the oversam­ pling rate. For instance, if 16 bit resolution (or equivalently 98.09 dB) is required for

49 a single-bit EAM system, M ist order > 2418, M ind order> 153, and M srd order> 49 are necessary for the oversampling rate of diverse EA modulators. For a Nyquist fre­ quency of 50 KHz, the corresponding sampling frequencies are > 120.9 MHz,

îsind order ^ ^.65 MHz, fs^ri > 2.45 MHz. The sampling frequency needed for using the first order EA modulator in high resolution requirement is still considered too high now, and the third order EA modulator’s stability issue complicates the design [ 1 ]; therefore, the second order EA modulator attracts more attention than the other architectures. The performance for Boser’s EAM (Figure 3.6) and Shenoi’s

EAM (Figure 3.7) is demonstrated in Figure 5.1.

110 X Shenoi Mejthod 100 X Boser Method X

:c-x X 70

oc z CO X X 40

30

;-l2IB

■Z7UB -3dB - 9 0-80 -70 -5 0 -40 -30 -2 0 -10 Normalized Input Level (dB)

Figure 5.1: Performance for Boser’s and Shenoi’s Methods

50 Figure 5.1 shows the performance (as M = 256 and N = 1) of the previous two second order single-bit SA modulators, where SNDR stands for signal to noise and harmonic distortion ratio. Their claims are demonstrated by Figure 5.1; essentially,

Shenoi’s method has a little bit higher best performance while Boser’s method allows higher input signal magnitude.

On the other hand, to obtain Equation 3.14, non-correlated and uniformly dis­ tributed quantization noise is assumed. A typical SA modulator utilizes a single-bit

ADC as well as a single-bit DAC. One advantage for using the one-bit output stream is that the comparator and decimation filter are easy to implement. However, a multi-bit SA ADC has attractive features including lower quantization noise, higher resolution (as referred to Equation 3.14), relaxed opamps requirement ([47, 32, 34]).

The advantages for a single-bit SA ADC are the disadvantages of a multi-bit SA

ADC, and vice versa. We consider utilizing the advantages firom both ADC struc­ tures and avoiding their drawbacks.

Based on Figure 5.1, we consider that the DC gain 2 is not a major issue for performance and we will utilize Boser’s structure to develop our improved design algorithm from this point forward. Meanwhile, for Boser’s method, we observe that the best performance point of the system is when the input maximum magnitude about 3 dB below the feedback reference voltage. If the applied input signal has high magnitude only occasionally but low magnitude for most other times, the high resolution characteristic will not be true all the time.

One way to keep the input magnitude constantly high is to apply an analog auto gain control (AGC) in the front of the EA ADC input such that the input to the EA

ADC always keep its maximum magnitude, say, 3 dB below the reference voltage.

51 Nevertheless, there exists distortion in the AGC stage; moreover, the gain factor, which should be quantized and sent to decimation filter block, may cause another

ADC problem.

A possible improved EA ADC architecture and its design algorithm for high dy­ namic range with wide input ranges is proposed in next section. An explanatory example and its simulation result will demonstrate the EA ADC performance im­ provement. Modified digital error correction techniques are then proposed in Sec­ tion 5.3 to support the improved architecture.

5.2 Improved EA ADC Architecture and Design Algorithm

The main idea of our algorithm is to auto-detect and auto-modify the feedback reference voltage of a EA ADC system regarding the diverse period input magnitudes.

If oversampling rate M is used, there essentially needs to be an M-bit sequence stream to recover a Nyquist (decimated) rate output point. The reference voltage can be changed at the next Nyquist rate output period if the new reference voltage information is sent to modify decimation filter output. This idea will be proved shortly. Figure 5.2 demonstrates the proposed EA ADC architecture.

P Dedmatioa Fdler LPF K b it One- One-Bit bit • fP Quantizer + v re f p On^it

Reference Decision K-bit

Figure 5.2: Architecture of Wide Input Range EA ADC

52 As compared with Figure 5.1, Figure 5.2 utilizes a second order lowpass SA ADC as a demonstration to explain this idea, where A is an attenuation factor for reducing overload probability, P is an attenuation factor of the feedback reference voltage, E is the quantization noise without attenuation, and K is the ADC output bit number.

Observe that P is not necessary being a number with a power of 2 but if so, there is no multiplier needed in decimation filter.

With this model, we can express output Y being Equation 5.1,

A ^ P Z -^ X (P - A + A2)Z-2 + (A - 2P)Z-i + P

(P - A + A2)Z-2 + (A - 2P)Z-i + P'

If the oversampling rate M is high enough, we can approximate Z fa 1 within base­ band. Equation 5.1 becomes

Y = PZ-^X 4 - ^ ( 1 - Z-'^fE. (5.2)

Observe that at this stage, the signal component is amplified by a factor P while quantization noise is remained the same as compared with the case without quanti­ zation noise attenuation (P = 1). Therefore, if the decimated valued is divided by

P after lowpass filter (LPF) operation, the Nyquist rate output wül be the Nyquist rate sampled input signal with attenuated quantization noise. The input range can be greatly improved depending on the attenuation range. Figure 5.3 demonstrates one feasible detection diagram to auto-control P, where m = Zopg(M).

To explain our design algorithm, some exemplary conditions will be sequentially assumed. Checking Figure 5.1, if the region of input below reference voltage, say,

3 dB is not expected, the first step of the design algorithm is to set a gain factor so that reference voltage, Xref, is larger than the maximum magnitude of X (during

53 +vref

vref

» + - ^ Mux — 4

vref

Detector To Oecmiation DeCodei d x K Filter ( 4 X k ) CLK m-Bit > Memory K-bit Coantei

Figure 5.3: Reference Decision Architecture

previous M clock periods) by 3 dB (in the signal domain), which is the function of the detector. Furthermore, if a 90 dB output SNDR is desired, we check Figure 5.1 and observe that it occurs at the maximum input below the reference voltage about 15 dB.

The second step of the design algorithm is to decide on a new comparator threshold, which, under previous assumptions, is 4 (15 dB — 3 dB = 12 dB — 20 • log{A)).

The third step of the design algorithm is to choose how many reference voltages can offer the desired efficiency or how much of the input range should have to support the output SNDR higher than same specified value, 90 dB. We assume that three extra reference voltages can be selected and therefore reference voltages are able to be ±vref, or (P = 1, 4, 16, or 64 respectively). Each extra reference voltage offers 12 dB input range improvement and now we anticipate that the input range is extended by 36 dB.

54 Under the previous exemplar assumptions, by comparing with several threshold voltages, the EA modulator feedback voltage will be either ±vref,

or which is dependent on the input X at different periods. Note that if the components are accurate enough (up to K bits), then P will be 1, 4, 16, or 64 correspondingly and no multipliers are needed in decimation stage. However, if an extra digital multiplier is utilized in decimation stage, the component accuracy is not critical and P can be designed as a value other than a power of 2. Meanwhile, in this explanatory example, the detector in Figure 5.3 is designed to set a reference voltage

(Xref) to eliminate saturation circumstances and we expect that Boser’s SNDR per­ formance on the input range on -3 dB ~ -15 dB in Figure 5.1 will be extended to the range -3 dB ~ -51 dB for the improved EAM architecture. Figure 5.4 demonstrates the simulation results. Now, we are able to claim that the input range is improved by at least 3 * 1 2 = 36 dB for this second order lowpass EA ADC example under the previous design assumptions.

110 Improved Method 100 • S Im b I Method — — Bc^er Method

60

70 ffl QC 60 to 50

40

30

20 •12 B -

-9 0-6 0 -70 -6 0 —40 —30 -2 0 -1 0 NomwHzed Input Level (dB)

Figure 5.4: Performance of the Wide Input Range EA ADC

55 5.3 Modified Digital Error Self-Calibration

Several multi-bit EA ADC methods use error correction and offer a variety of approaches to attain self-calibration [32, 34, 48]. For the proposed improved EAM architecture (in section 5.2), digital error caUbration ([33, 35]), which is usually used in multi-bit EAM, is modified to accomplish our goal of self-calibration. The modified digital error self-calibration architecture is demonstrated in Figure 5.5.

+vtef -v ref vref

da» in

cue

V

vref

Mux

Figure 5.5: Modified Digital Error Self-Calibration Architecture

Here, one part of the Mux (multiplex) output, 6 i 6 o, is generated by a 2-bit counter such that all possible reference voltages, (4-%.g/, and -^-^), are sequen­ tially calibrated. Essentially, the error self-calibration process is to reconfigure the converter (Figure 5.2 and Figure 5.3) as a single-bit (corresponding to reference volt­ age ±vref) EA ADC. During the calibration process, because the input voltage are

56 DC values for all possible P’s), its bandwidth is considered zero, and there­ fore the in-band quantization noise turns out zero. Hence, the reference voltage can possibly be made arbitrary precise and they are recoded in the d x K K here) memory. The calibration process can be executed at the oversampling clock rate; the calibration period will be only about 4x2^ clock cycles plus the time needed for system settling up. This calibration period can also be executed automatically and it is even much shorter than the time (2^ x 2^, where N is for iV-bit DAC) needed in conventional digital error self-calibration [35]. The calibrated results will be used in the decimation stage.

5.4 Investigation of Performance Improvement

In this section, the theorem &om Chapter 4 will be applied to explain the reasons why the proposed EAM architecture possesses better performance than traditional

(or Boser’s) structure.

For the example given in this chapter, the auto feedback control adjusts the refer­ ence voltage such that the sinusoidal magnitude between —3 ~ —51dB to the (fixed) reference voltage is actually located between —3 ~ —l5dB to the modified reference voltage. Figure 5.6 and Figure 5.7 re-plot the relationship of sinusoidal magnitude Ux, quantization noise random component a^, and quantization noise signal component

(T^ using logarithmic scales (referencing Figure 4.8 and Figure 4.9).

57 10

10® I • -tW39t

-60-70 -50 -40 -30 -2 0 - 1 0 Sinusofdal MagnHuds: (dB)

Figure 5.6: Relationship of Sinusoidal Magnitude Ox and Quantization Noise Random Component

Ratatfonshlp Of and

0.0113

-7 0 -60 -40 -30 - 2 0 - 1 0 Sinusoidal Magnitudo: i^A (dB)

Figure 5.7: Relationship of Sinusoidal Magnitude and Quantization Noise Signal Component

58 If the input sinusoidal magnitude is slightly less than —IhdB of the reference volt­ age (±vref = ±A ), according to Boser’s architecture, the quantization noise random component is about 0.4392A^, and the quantization noise signal component is around O.OllSA^. In contrast, according to the proposed architecture, which would automatically apply (or — 1 2 dB of the original reference voltage) as the modified reference voltage in this case, the quantization noise random component cr^ becomes 0.6676( = 0.0417A^, and the quantization noise signal component changes to 0.3420( = 0.0214A^, (because in the proposed architecture, the in­ put sinusoidal magnitude is located at —ZdB of the modified reference voltage.) We realize that the variance of the quantization noise signal component, does not change much while the variance of the quantization noise random component, cr^, is significantly decreased by the proposed EAM architecture.

Therafter, the quantization noise random component gain, G„, is also correspond­ ingly increased (reference Figure 4.8) and results in quantization noise being shifted to a high frequency region and allowing improved SNR in baseband. Meanwhile, we can anticipate that the (total) output variance of the integrator directly before the quantizer will be considerably reduced, and the performance will be increased because, for the proposed architecture, the signal level inside the circuit has much less chance to exceed the saturation threshold when compared with the conventional

EAM structures. Moreover, because the smaller reference voltage is applied, the quantization noise power {^vrep) will be decreased and the system performance is significantly improved.

59 Figure 5.8 and Figure 5.9 demonstrate the probability density distribution when

the sinusoidal input magnitude is equal to —15.5dB and is applied to a second or­

der SAM using the proposed architecture and using Boser’s architecture respectively.

The proposed architecture does possess narrower probability density distribution than

Boser’s architecture. Meanwhile, Figure 5.10 and Figure 5.11 are the frequency spec­ trum when the sinusoidal input magnitude is equal to —15.5dB and is applied to a second order SAM using the proposed architecture and using Boser’s architec­ ture individually. Clearly, from the high frequency range in Figure 5.10(a) and Fig­ ure 5.11(a), we are able to find that the proposed architecture has less noise magnitude than Boser’s architecture. Moreover, we can also carefully observe the low frequency range in Figure 5.10 and Figure 5.11 and find that the proposed architecture does have wider low noise range in low frequency range compared with Boser’s architec­ ture. (Circles are marked at the low frequency range in Figure 5.10 and Figure 5.11 for explanatory purpose.)

60 linn I

•I <4IJ -Of -04 -02 0 &2 04 O# O# t -I -Of -Of -04 -02 0 02 04 Of Of t Mi9 Mar.f OuW»WW#/4 (a), pdf of Integrator.! Output (b). pdf of Integrator.2 Output

Figure 5.8: Probability Density for a 2nd Order EAM Using Proposed Architecture When the Sinusoidal Input Magnitude = -15.5 dB

m^finnm»»mm###

1 -t -Of -02 0 02 04 Of Of I Wi y n or.t 0 * # f Ui9 «uri*/A MifnlDr_20i#if MignM*/A (a), pdf of Integrator-! Output (b). pdf of Integrator.2 Output

Figure 5.9: Probability Density for a 2nd Order SAM Using Boser’s Architecture When the Sinusoidal Input Magnitude = -15.5 dB

61 (a). Frequency Spectrum (b). Zoomed Frequency Spectrum

Figure 5.10: Frequency Spectrum for a 2nd Order EAM Using Proposed Architecture When the Sinusoidal Input Magnitude = -15.5 dB

F«qMnqrSMiBa(aMoi*rUUwÉ9aBwtAMeaMMli^StaaoiMlkgnftid^-tSSdB

-60

-#0

-too

•140

•160

0 05 15 2 S IS 45 S (a). Frequency Spectrum (b). Zoomed Frequency Spectrum

Figure 5.11: Frequency Spectrum for a 2 nd Order EAM Using Boser’s Architecture When the Sinusoidal Input Magnitude = -15.5 dB

62 CH APTER 6

DECIMATION STAGE

The last stage of an oversampling ADC (analog to digital conversion) system

is a (set of) decimation filter(s) to filter the out-of-band noise, extract the desired

bandwidth, and decimate the sampled signal to its Nyquist rate. Multipliers, which

are expensive in VLSI technology, are expected to be avoided for the decimation stage. We will attempt to look for a decimation filter structure without multipliers.

Several methods are noticed for implementing multiplierless decimation filters. Fur­

thermore, because there exists flexibility among data resolution, desired bandwidth, output data rate, gain factor, designing period, system complexity, and product cost, the programmability is considered critical for user orientation. A serial interface ca­ pability will be necessary for the chip to allow for modification of the decimation filter operations [49]. The feasibility of multiplierless operation will be verified; one possible single-stage multiplierless FIR filter using a pulse density (one-bit) stream is exploited in this chapter. The other decimation filter implementation applies multi­ stage filters, including comb filters, to save coefficient tap numbers and decrease filter operation speed but at the expense of sacrificing one-bit stream. One approach called the signed power-of-two coefficient expression will be exploited in Chapter 7 as an alternative to keeping the ADC system multiplierless property.

63 6.1 Single-Stage Multiplierless Decimation Filter

The last stage of a EAM system is a decimation filter. A two-stage decimation filter is generally used [1, 5, 26], so that the first stage does not need to be of extremely high order. Actually, multistage designs significantly reduce both computation and storage requirements when compared with single stage designs. The reductions are due to the wide transitions of filters in the early stages [3j. Nevertheless, multistage designs sacrifice the characteristic of EA encoders’ pulse density (one-bit) stream.

To explain the feasibility of a single-stage multiplierless decimation filter, we will demonstrate the fundamental processes using one possible architecture. In Figure 2.3, the FIR’s input is denoted as x{kT) and its output is xsdm - If the order of the FIR filter is P and its coeflScients are hi's (i = 0 ~ P), then xsdm can be expressed as the difierence equation;

— x{kT — PT)hp -{- x{kT — PT -f- T')hp—\ 4- x(fcT — PT -t- 2,T')hp—2 4"

• • • 4" x(JkT — 2 T’)/i2 4- x{kT — T')h\ 4- x{kT')hQ p = Yl^{kT-i-T)hi. (6.1) 1 = 0 Moreover, x{kT) is the DAC version of d{kT) which has only two digital signal pos­ sibilities, zero or one. The Level Generator processes their relationship as

x{kT) = A * (2 * d(A;T) - 1 )

= A *d'{kT) (6.2) where 2 * d{kT) — 1 = d'{kT) which can only possibly be —1 or 1.

Substituting Equation 6 . 2 into Equation 6 . 1 , we have p xsDAfikT) = ^ A * d’ikT -i-T )* fn. (6.3) 1=0 64 Because d’ can only possibly be — 1 or 1 , we can group Equation 6.3 as

p p xsDMikT) = A * hj - hi) (6.4) J=o[?(ifer-j-T)=i] f=o[?(tr-(T)=-i]

For one-bit outputs, if the operation speed in digital part is high enough, no

multiplier is needed to get the decimated results. For example, using an oversampling

rate of 256 as given in Section 3.2 and an FIR tap number of 256, we can construct

a multiplierless system as shown in Figure 6.1.

However, in some situations, the FIR tap number of 256 is not enough to offer flat

baseband, short transition band, and high attenuation stopband. An FIR filter with

a higher tap number is required to reach the previous conditions at the same time.

A more sophisticated (single-stage multipUerless) structure which can be applied in

the situations of oversampling rate lower than the filter order is introduced in [50].

Note that A in Equation 6.4 is just a scaling factor in the system; the gain shown in

Figure 3.6 and Figure 3.7 can be accurately controlled by adjusting the capacitors’

ratio with low cost in VLSI, if a technology called Switch-Capacitor ([51, 52, 53]) is

applied to construct the integrators. Therefore, the complete EAM (including both

encoder and decoder) system contains no multipliers.

In reality, there exists a dilemma for implementing either a filter with a signal stage, many registers are needed but no multipliers are necessary, or a filter with less

registers (for filter coeflScients) where multipliers are needed (Section 6.2). These filter

coefficients are programmable for diverse specifications. We will avoid the use of the

HR structure because of the higher degree of difficulty in controlling its stability than

an FIR. For general purpose and programmability consideration, the FIR structure

is a better candidate than the HR to implement a decimation filter.

65 Clock — (I2.8MegHz) Counter ( 8 bits)

Control Coefficient Memory (256 X 16 bits)

Sign Bit Ctemger (12.8MegHz) g

Switch Switch

Registei — Registei

Output Register

V Output (16bits, 50kHz)

Figure 6.1: Architecture of a Multiplierless FIR Filter

6 6 6.2 Multi-Stage Decimation Filter

A multi-stage decimation filter is an alternative to reduce the FIR order ([3]). For

the preliminary stages of a multi-stage decimation filter, the comb filter structure

is frequently applied because the coefficients of a comb filter are all ones ([5, 49,

54]). Nevertheless, the comb filter itself does not offer enough quantization noise attenuation. The other lowpass and compensation filter(s) will be needed following the comb filter. Either the HR or the FIR can be applied for this purpose. The HR filter needs less coefficients than the FIR filter but the later possesses better stability than the former. Because we are concerned with a general purpose application, the stability issue is considered more significant than coefficient saving. The FIR structure wiU be applied for the lowpass and compensation stages.

6.2.1 Comb Filter

If y(n) (Y(Z)) and x(n) (X(Z)) are the output and input of a comb filter in spatial

(frequency) domain, then the relationship of the output and the input of an N-tap comb filter is:

y{n) = ^ {x{n ) -I- x{n — 1) + x(n — 2 ) -I H x{n — N + 1 )), (6.5) where ^ is for unit gain purpose, and the transfer function, Hi(Z), is:

_ m _ 1,1-1:", (6.6)

67 Equation 6 . 6 can be expressed as two separate processes: integration followed by

diflferentiation as shown in Equation 6.7 ([27, 55]):

Y(Z) = ^(:^-^)(l-Z-^)X (Z). (6.7)

Therefore, the equation and block diagram for a K-stage cascaded comb filter are

shown in Equation 6 . 8 and Figure 6.2 respectively. (Note that is just a scale factor

which is not shown in Figure 6.2 for convenience.)

y ( z ) = (6 .s)

(— Cascaded of Klntegtatois ( l - z ‘) Cascaded of KDifferendalcis A______Dedmation / \

input sample me

Figure 6.2: Block Diagram of a K-Stage Comb Filter

The inband attenuation of the K-stage comb filter can be estimated firom Equa­ tion 6 . 8 on the unit circle in the Z-plane ([27]):

- phase magnitude James C. Candy suggests that the comb filter techniques are useful for decimation down to about four times the Nyquist rate [56]. Continuing with the example given in previous chapters, we have oversampling rate M = 256. Hence, if iV = ^ = 64 is applied here, then at the comer of the signal band (/ = ^ ) , the attenuation is

0 7 * 7 7 T T ^ 0 7 7 7 2 L 20 • « K • 2 Q lo g - ^ = -K • 0.2244 (dB) (6.10)

68 This roll-off in the baseband needs to be compensated in the second part of the decimation stage (which will be discussed in next section.)

To have a clear configuration for signals to this stage, the noise shaping shown in Figure 4.12 is reprinted in Figure 6.3 corresponding to the conditions given in

Chapter 4. Note that because we use Boser’s structure to explain the complete SAM system, the integrator gains are ai = 0.5, and ag = 0.5. Therefore, the Gn's applied in Figure 6.3 are exactly twice the G„’s shown in Figure 4.12. The reason for this has been explained in Chapter 4. Here the reference voltage magnitude. A, is assumed to be 1 and the quantization noise variance = jA = j.

The N o te Shaping with m p a c t to a Second Ordor£AM(a^aO^ and

-to

-2 0

-30

% -40

-60

-70

-80

-80

-1 0 0

Frequency (Hz)

Figure 6.3: Noise Shaping for Boser’s 2nd Order EAM

Figure 6.4 demonstrates the frequency spectrum of a 3-stage comb filter. Figure 6.5 demonstrates the noise shape after the 3-stage comb filter with respect to a second order EAM and a sinusoidal input.

69 Ffequenqr spectrum tora 3-Stage-Comb-Faier

-2 0

-4 0

-60

-8 0 I

-1 0 0

-1 2 0

-140' 6 8 Frequency (Hz)

Figure 6.4: Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter

Noisa Shaping (after 3-Stage 64-Tap-Comb-F8tef) wft a 2nd Order £4M (c^«Oj & o^aO ^ -40

-60

-80

-100

- 1 2 0

-140

-160

-160 12 Frequency (Hz)

Figure 6.5: Noise Shaping after a 3-Stage 64-Tap Comb-Filter for Boser’s 2nd Order SAM

70 Note that the complete shape (the one with ripples) is shown for Gn = 0.2530 and

the others are plotted only regarding to their individual ripple peaks for clearity. The

frequency spectrum relationship between before and after decimation is ([57])

(6 .11)

where, $ and denote the frequency spectrum before and after decimation (by M)

respectively. Figure 6 . 6 is the noise shaping after 3-stage comb filter and decimation

by a factor of 64.

NoiM Shmphg (aterS -S iagt 64-tap-Cofnb-Rt»r& Dm by 64) wit a 2nd Order (a^m0.5&a^#0j)

-2 0

-40

-60

jT -80

-1 0 0

>120

-140 >1

0.4 0.6 OJ 1.4 1.6 frequency (Hz)

Figure 6 .6 : Noise Shaping after a 3-Stage 64-Tap Comb-Filter & Decimation by 64 for Boser’s 2nd Order EAM

71 6.2.2 Compensation FIR

EVom Figure 6.5, the noise spectrum is below —80 dB in the pass-band (0 ~

25kHz) for the worst case as a sinusoidal input to the Boser’s second order SAM.

From Figure 6 .6 , the noise spectrum floor after decimation by a factor of 64 is be­ low —lOOdB. Note that using a comb filter to decimate an oversampled signal down to four times of the Nyquist rate is recommended by James C. Candy ([56]); he mentions that attempting to use a comb filter to generate lower frequencies results in significant spectral distortion in baseband and poor rejection of spurious noise. There­ fore another lowpass filter stage is needed for further noise attenuation. Meanwhile,

Equation 6.10 explains there exists roll-off at the edge of baseband if a multi-stage comb filter is applied. Therefore, the compensation lowpass filter should offer not only enough attenuation to reject the out of band noise below the required resolution consideration but also enough compensation to the roll-off at baseband.

To guarantee 16-bit resolution, the compensation filter may need as much as

—96dB attenuation in stop-band. Meanwhile, the ripples or variation in the pass- band should also be constrained under a certain range. The MATLAB command

“/ i r2 ” can be applied to design an FIR filter that satisfies the previous conditions.

Figure 6.7 shows the baseband frequency spectrum of a 3-stage comb filter with length of each stage being 64.

72 Zoomed Fmqwncy spectrum for e3-Stag»-Conib-fihar

CX5

- 1

Figure 6.7: Baseband Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter

Figure 6 . 8 demonstrates a compensation 256-tap FIR filter, designed by the fir2

MATLAB command and a Kaiser window, for the 3-stage comb filter. To check the total filtering characteristics, Figure 6.9 is the spectrum of the cascaded 3-stage comb filter and the compensation FIR filter. We realize that the out of baseband range has attenuation more than lOOdR and the baseband variation range is less than 0.006dB.

(Note that the baseband bound is represented by a dashed line throughout this and the remaining chapters in this dissertation.)

73 Compwiefcxi FIW (256-lip RR) Frequency Spectnim

(a). Compensation Filter

Zbomad Compensalion Filler (Z56-(ap RR) Fraquancy Specnun

- t

-2 Frequency (Hz) xiO (b). Zoomed Compensation Filter

Figure 6 .8 : Frequency Spectrum of a 256-Tap FIR Compensation Filter

74 FfBquwcy spectrum ol 3-Slsge Comb-Faw Cescsded by » Compwsibon F»er (256-tsp FIR)

-2 0

-40

-60

-1 0 0

-120

-140

-160

-180 xIO (a). Full Range Frequency Spectrum

aot

10 I to* (b). Zoomed Cmb + Cmp Filter (c). Cmb + Cmp Filter in Baseband

Figure 6.9: Baseband Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter Cascaded by a 256-Tap FIR Compensation Filter

75 Figure 6 . 1 0 demonstrates the typical noise shaping including the following steps: a sinusoidal signal oversampled by 256 passing through a Boser’s second order SAM,

3-stage comb filter, decimation by 64, 256-tap compensation lowpass FIR filter, and decimation by a factor of 4. We find that almost all noise spectra are below —\2QdB.

Noise Shaping (after 25S-tap Compensation Lowpass FiR & Dm liy 4) wrt a 2nd Order EAM (a,=OS & oy4)j) -8 0

-1 0 0

-120

-1 4 0

S -1 6 0

-180

-200

-220 1.5 2JS 3.5 4.5 Frequency (Hz) xIO*

Figure 6.10: Noise Shaping after a 256-Tap FIR Compensation Filter & Decimation by 4 for Boser’s 2 nd Order SAM

76 CH APTER 7

PROGRAMMABLE MULTIPLIERLESS DECIMATION FILTERS

The design shown in Section 6.2.2 with an FIR tap number of 256 needs many

multiplication operations as well as very long word memory to reach the desired

accuracy. For real-time applications, a simple hardware configuration should also be

a critical consideration in decision-making for the compensation filter architecture.

There exist diverse alternatives for the implementation of the final stage lowpass

compensation filter. The HR (Infinite Impulse Response) filter, a possible choice for

the compensation filter, typically needs higher internal word length for state variables

to avoid undesired affect of limit cycles. An HR filter applies only a few taps but the

phase of the HR filter is generally not linear. The HR decimation filter is suitable for

the voiceband telephony applications, in which the linear phase is not necessary [58].

In some applications, like high quality digital audio, the linear phase character­

istics is critical; an FIR (Finite Impulse Response) filter should be applied. To save coefficients, a method called Half Band Filter vs used in some SAM ADC systems ([4,

59]). The impulse response sequence of the half-band filter has every odd numbered sample equal to zero. In addition, this method is based on a symmetrical FIR design; therefore, the number of multiplications in implementing such a filter is one-fourth of

77 that needed for general FIR filter designs. However, the half-band symmetric filter has a natural decimation rate of only 2 ; a series of such half-band filters should be cascaded to achieve higher decimation filter work.

Meanwhile, because multipliers occupy large area in VLSI and their operations take time to do, the system would be more compact and efficient if the multiplication operations can be eliminated. The technology which uses table look-ups and residue arithmetic ([6 ]) is an alternative. Only squaring operations and additions are needed in this algorithm. However, if the arithmetic is n bits wide, each ROM table (for the look-up operations) is of the size 2^" x n bits. The table size and the table searching work may be the consideration for this algorithm in reality.

One possible multiplierless FIR filter is mentioned in Section 6.1. The one-bit pulse density stream is well utilized in Figure 6.1; nevertheless, the price paid for applying

Figure 6.1 is the high tap number necessary for the single-stage FIR decimation filter to attain good filtering (flat baseband, short transition band, and high attenuation stopband) .

Some other possible linear phase FIR filter designs are the windowing techniques

([60, 61]), the Chebyshev function based techniques ([62]), and the MAXFLAT tech­ niques ([63]). In [8 ], an implementation of multiplierless maximally flat interpolator is introduced; the specifications of sharp cutoff and large attenuation in stopband are accomplished by the nesting of many maximally flat building blocks. A high quality FIR design with sharp cutoff, narrowband, linear phase, and no multipliers are attainable. However, the complexity of the implementation grows exponentially with the number of nesting levels. This design trades addition and shifying for de­ lay. Actually, some of the criteria used in Chapter 6 are overstrained; the reasonable

78 constraint relaxation will be discussed in this chapter. In addition, a coefficient ex­ pression alternative called the signed power-of-two expression is also exploited; its usage in multiplierless EA system is attempted. Both theoretical as well as simula­ tion results will be presented in this chapter for comparison purpose.

7.1 Signed Power-of-Two FIR Compensation Filter

The previously mentioned decimation filter designs do not well utilize the advan­ tages of oversampling and multi-stage comb filtering. Observing Figure 6 .6 , all noise spectra from quantization are below — lOOdB. Therefore, in some high-speed chip ap­ plications, if the sharp cut-off edge is not critical, then only a few taps is enough for the final FIR decimation filter. A low-tap number FIR decimation filter can reduce the computation load and therefore result in simple hardware configurations.

In addition, if there is no spurious noise or this problem has been lessened by certain approaches, like dithering ([64, 65]) or chaos ([ 6 6 ]) configuration, then the accuracy of the FIR filter coefficients is not significant. An alternative called the

Signed Power-of-Two coefficients ([12, 67, 6 8 , 69, 70]) can be applied to increase the operation speed because not only are no multipliers needed but also simple hardware is qualified for the compensation lowpass FIR filter.

The signed power-of-two (p2) space. Cm, can be expressed as

m—1 C m = 'E s* 2 ’’S (7.1) i= 0 where m is the word length; s,- 6 {—1,0,1}, and r,- denotes the bit position. Figure 7.1 shows the positive side of the signed power-of-two space with two non-zero bits within

16 bits (2b/16b) and the most significant bit representing 1 (2 °).

79 2b/l 6b Signed Rower>-of—TWo Space

^ ,1 I I ' I V I I I 1,1 V

0 . 5 1 .5 Magnitude

Figure 7.1: (Positive Side) 2b/16b Signed Power-of-Two Space

By Equation 7.1, we realize that we need only a few bits of memory for the signed

power-of-two FIR filter coefficients because only two (or a few) bits out of sixteen

bits are non-zero. Moreover, because each non-zero bit position has only two allowed

values, 1 and —1 , the operation for the filtering is just shift and addition/subtraction.

The hardware implementation is surprisingly simple.

Hence, from the view point of the economy, we are especially interested in the per­

formance of applying the signed power-of-two technique to a low tap number lowpass decimation filter. Because the signed power-of-two FIR hardware implementation is simple nad sacrifices little accuracy, by the realization of theoretical shaped noise spectrum analysis, we are able to justify that designed signed power-of-two FIR sat­ isfies the requirements for a EAM system. Figure 7.2 is the filter frequency spectrum designed from the MATLAB command fir2 (with a Kaiser window) using only 32 taps

80 and mapping the coefficients to the closest 2b/16b signed power-of-two space. The attenuation in stopband is around —37 dB. Figure 7.3 shows the frequency spectrum of the 3-stage comb filter cascaded by the 32 taps 2b/16b signed power-of-two FIR filter. Notice that, given the tap number for the FIR filter, the roll-off in baseband can be traded for transition band range. For example, in Figure 7.3 (b), the roll-off at the edge of the baseband is designed to be around —MB. The roll-off in baseband can be made smaller but at the cost of extending the transition bandwidth.

81 <>*i»«is«k*i fiUr (32-«p2bn66 signed Poww-of-Tiio FIR) Riquency Specmsn

-1 0

-2 0

-40

-SO

-70

-SO Frequency (Hz) no (a). Compensation Filter

Zoomed CompeneeOon Filler (32-lap 20/16b Signed Power-of-Tm FIR) Frequency Spectrum

Frequency (Hz) (b). Zoomed Compensation Filter

Figure 7.2: Frequency Spectrum of a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter

82 Fisq, spectrum d a 3-SHgi Comb-fiBerCascidid by a CompwiBiton fiBsr(32-ttp 2hrt6b signed P2 FIR)

-1 0

-30

-40

-50

-60

-70

%10 (a). Cmb + Cmp Filter

Zoomed FfB(|.Sptmd a 3-Stag8Camb-FKer Cascaded by a Compansalian Flter02-lap2dl6b Signed P2 FIR)

06

0 -

-4

(b). Zoomed Cmb 4- Cmp Filter

Figure 7.3: Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter Cascaded by a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter

83 Figure 7.4 is final noise shaping after the 32-tap 2b/16b signed power-of-two FIR filter and decimation by a factor of 4 (back to the PCM Nyquist rate.) Figure 7.4 demonstrates that all of the noise levels are still below —12QdB. Comparing Figure 7.4 to Figure 6.10, we realize that the small tap number FIR filter with signed power-of- two coefficients is able to implement a .similar lowpass and final decimation as the full

FIR design (256-tap FIR with large impulse response dynamic range as discussed in

Section 6.2.2.) Note that the shape notch around 8K H z comes fiom the compensation

FIR notch around 42K H z in Figure 7.2 as well as aliasing.

Noise Shaping (after 32-tap 2bAI6b Signed P2 Comp FIR & Dm by 4) wtt a 2nd Order £AM (a^=0.5 & Og=0j) -8 0

-100

-1 2 0

-1 4 0

2 - 1 6 0 '

-1 8 0

-200

-220 0.5 1.52.5 3.5 4.5 Frequency (Hz) xIO *

Figure 7.4: Noise Shaping after a 32-Tap 2b/16b Signed Power-of-Two FIR Compen­ sation Filter & Decimation by 4 for Boser’s 2nd Order SAM

84 7.2 Investigation of Comb Filter Tap Numbers and Decima­ tion Ratios

In Chapter 6 , James C. Candy’s statement ([56]) is applied and the Comb filter is

applied to attenuate the quantization noise and decimate data to about four times of

the Nyquist rate. The resource of the factor, four, in [56] will be exploited. In fact,

the factor, four, is too strict for the technique with oversampling and noise shaping;

the reason for this will be explained.

From Equation 6.9, the magnitude response of the K-stage cascaded comb filter is

- M N - 1 ) K J T I n \^ N -sim rfT ^ ^ - phase magnitude

Candy ([56]) considers that that comb filter Equation 7.2 attenuates the signal most at the frequency /„ and provides least attenuation for the noise at the frequency

^ — fo, where /„ is of interest (or baseband) bandwidth. The ratio of the filter’s attenuation at these two frequencies is a figure of merit for the filter. The comb filter gain ratio (= $) of signal to noise at these two frequencies is

f 1 sin vNfoT\K sin icNfoT / i e T ‘\ — I sinicfoT / I — U sinnfoT xjCi _ ^(j\r Jo^)\K (y o\ L 1 5in ir/y(4-/o)r,y l sin{ir-^NfoT) ) I I s i m r f o T N sin ir(^-/o)r ' where fs = ^ is the sampling frequency. Figure 7.5 demonstrates the relationship between attenuated signal and spurious noise. In [56], Candy uses the criterion that when the decimating filter is the sole protection against this out-of-band noise, the

85 RaiadonsiUp of AtUnuatad Signal to AtunuaMd Spurious Noise 80

mSO

C 4 0 34 dB

C 3 0

Dedmadon Fraquancy: 1/(2Nf^T)

Figure 7.5: Relationship of Attenuated Signal to Spurious Noise

specification of total network codecs can be interpreted as requiring that $ exceed 3^

dB. From Figure 7.5, for K = 2, the previous criterion can be met around N > 4 and

1 > 4 2NfoT fs =*■ 77^4 (7.4)

Equation 7.4 explains why Candy claims that the (Comb filter) techniques are useful for decimation down to about four times the Nyquist rate [56].

From above, we understand that Candy considers only the efiect of the comb

filter and the effect of SAM noise shaping is ignored. In reality, this is not the

case for the 2AM technique. The complete 2AM system should involve both effects

of 2AM noise shaping and decimation stage (including comb filter and/or lowpass

compensation filter). For example, for Boser’s second order 2AM, from Figure 6.3,

86 we realize that the shaped noise spectra are generally below —30 dB. Superimposing

the basebands of Figure 6.3 and Figure 6.4 yields Figure 7.6, which is a low frequency

band zoomed version. Notice that only the worst (smallest) case is plotted for

K = 3 and IV = 64 in Figure 7.6.

Fq, Spun, of a 2nd OrdirSAM (a ,-0 5 o^-O^ and 6^-02530) Shiptd No Im «Id a 3-Slag» 64-Cip-Conib-Fater

-2 0

-4 0

-6 0

-8 0

-1 0 0

-120

-1 4 0 zs

Figure 7.6: Frequency Spectrum of a 2nd Order EAM (ai = 0.5, « 2 = 0.5, and Gn = 0.2530) Shaped Noise and a 3-Stage 64-Tap Comb-Filter

From Figure 7.6, we can check that the shaped noise at frequency ^ — /o is about

—58dB. From Figure 7.5, we realize that the margin of 58dB, which comes from a second order EAM noise shaping, allows for comb filters to be applied to lower deci­

mation rates than four. Norsworthy and Crochiere consider that a two stage design

for the decimation stage is best under the consideration of circuit implementation

complexity. Moreover, they also note that for most cases, the choice of 2:1 for the

last stage is both the theoretically best option as well as the most practical one [58].

87 7.3 Flexibility of Comb Filter Tap Numbers and Decimation Ratios In this section, the feasibility of 2-stage decimation with the second decimation

rate being 2:1 will be exploited. To be consistent with the previous explanatory exam­

ple, the same discussion conditions (/, = VlJ&MHz, fo = 25KHz, and oversampling

rate M = 256) will be used to examine the theoretical performance. The Boser’s

second order EAM is used for noise shaping. Two situations will be discussed; the

first one applies the 64-tap comb-filter followed with a decimation by a factor of 128,

while the second situation utilizes the 128-tap comb-filter and then a decimation by

a factor of 128. (In both cases, the last decimation rate is 2.)

Because a low tap number comb-filter offers smaller (better) roll-off at the edge

of baseband than a high tap number comb-filter does, the advantages of applying a

low tap number comb-filter include easier design of a compensation filter and better

baseband performance when compared with a high order tap number comb-filter case

if the low tap number comb-filter offers enough high frequency quantization noise

attenuation. Checking Figure 6.3, and Figure 6.4, we wonder if a comb filter tap

number of 64 is good enough for attenuating high frequency quantization noise.

An explanatory example (with a 3-stage 64-tap comb-filter and a first decimation

rate of 128) is offered to demonstrate the previous statement. Figure 7.7 is the de­ signed 32-tap 2b/16b power-of-two FIR for a 3-stage 64-tap comb-filter whose output data will be decimated by a factor of 128. Figure 7.8 is the baseband frequency spectrum of the 3-stage 64-tap comb-filter and the compensation filter. Figure 7.9 is

the noise shape after 3-stage 64-tap comb-filter and decimation by a factor of 128.

Observe that the high frequency quantization noise is aliased into baseband region.

Figure 7.10 is the noise shape after compensation filter and final decimation by a

88 factor of 2 (back to Nyquist rate). Although the final noise spectra are below —100

dB, this approach may not offer enough SNR for 16-bit resolution. (A simulation

result will be offered to explain the performance in Section 7.5.)

Cotnpn—gonWlw^((Wft>3-5ag>64 f p Comb n tof) 32-

-1 0

-30

-40

-70

-ao 10

(a). Compensation Filter

Zoomed Componoetfon F8lar ({wrt * O-Stago 64 lap Comb fUm) 32-tap 2 tn 6b S^nod P2 Comp RR) Froq Spoetrum

13

03 23 Fraquoncy (Hi ) * 10* (b). Zoomed Compensation Filter

Figure 7.7: Frequency Spectrum of a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter for a 3-Stage 64-Tap Comb-Filter whose output data will be deci­ mated by 128

89 Fre». Sp*»isn of s 3-Süge 64-lip-Coinb-Ftor Ciscadsd by s Compmsaflon fltor (32-lip 2brt 6b signed P2 Rfl)

•to

-SO

-70

06 KlO (a). Cmb + Cmp Filter

ZoomedFiteq.Spanotea-SlBQ>64 imp Comb fiierCMcededbyeCoiiyeM«eonFiHr(3a-tip2fan6bSianedP2RR)

05

25 3 6 Frequency (Hz) KlO* (b). Zoomed Cmb + Cmp Filter

Figure 7.8: Baseband Frequency Spectrum of a 3-Stage 64-Tap Comb-Filter Cascaded by a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter

90 NoiM Shtping («ftar3-Stag« 64-tip-Cofnb>Rtar&Dm by 128) wit«2nd Ofdir£AM (a^aOS&<^aaS) Oi------1------r -r 6^-0.2530 -2 0 G^«1.3396 G.-2.4262 -40

-60

-60

-1 2 0

-t4rf

-160

-180

-2 0 0 4 5 6 9 10 Fmquency(Hz) KlO*

Figure 7.9: Noise Shaping after a 3-Stage 64-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order EAM

Noise Shaping (aftar2-tip2ta/16b S*gnedP2CompFiR&Dmby2)Mta2nd(WsrZaM(a,W15&agma5) -40

-60

-60

-100

-1 2 0

-140i

-160

-180 KlO

Figure 7.10: Noise Shaping after a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter & Decimation by 2 for Boser’s 2nd Order EAM

91 On the other hand, for the case of applying 3-stage 128-tap comb-filter and then decimating a factor of 128, Figure 7.11 shows the (zoomed) frequency spectra when

Boser’s EAM noise shaping under the worst case = 0.2530 and a 3-Stage 128- tap-Comb-Filter (K — 3 and N = 128) are superposed. Utilizing the similar analysis approach as mentioned in the previous section. Figure 7.12 is the frequency spectrum of a 3-stage 128-tap comb-filter; Figure 7.13 shows the noise shaping after 3-Stage

128-tap comb filter for Boser’s EAM; Figure 7.14 demonstrates the noise shaping after 3-stage 128-tap comb-filter and decimating by a factor of 128 for Boser’s 2nd order EAM.

Fq. Spun. Of • 2nd Ofdtr£AM (0,-05 o^-O^ and Q^«O2530) Shaptd NoiM and • 3-Stao« laS-ttp-Comb-fltor

-2 0

-40

-80

-1 0 0

-120

-140. 2JS

Figure 7.11: Frequency Spectrum of a 2nd Order EAM (ai = 0.5, « 2 = 0.5, and Gn = 0.2530) Shaped Noise and a 3-Stage 128-Tap Comb-Filter

92 Frvquanqr Spectiun tor a 3»Stao9128-iap-Comb->FSl0r

-2 0

-40

-1 0 0

-1 2 0

-140 Frequanqr(Hz)

Figure 7.12: Frequency Spectrum of a 3-Stage 128-Tap Comb-Fiiter

Notoa ShaptoQ (aAar3-8taga 128-top-Comb-F9toO %wt a 2nd Ofdar EAM (@^«0.5 &

G >0.2530 G «1.3396 G_«2.4262

-140

6 B Frequency (Hz) KlO

Figure 7.13: Noise Shaping after a 3-Stage 128-Tap Comb-Filter for Boser’s 2nd Order SAM

93 Noin stuping (WUf3-Stmg# 12B-Up-Comb-Hter& D«cm_128) tant «2nd Oidtr SAM («,#05 & c^>05)

-2 0

% -80

-1 0 0

-1 2 0

-140

-160

-200

KlO*

Figure 7.14: Noise Shaping after a 3-Stage 128-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order EAM

Thereafter, Figure 7.15 is the compensation lowpass filter applying the similar

FIR design command and mapping it to the signed power-of-two space as mentioned in Section 7.1. Notice that, in Figure 7.11, the noise at the frequency of ^ — fo is about —72 dB, a larger margin than the case were N = 64. The price for the better margin is that a larger compensation is required for the compensation lowpass filter

(Figure 7.15(b) vs. Figure 6 .8 (b) or Figure 7.2(b) ). Figure 7.16 is the combined frequency spectrum of a 3-stage 128-tap comb filter cascaded by a compensation lowpass filter (32-tap 2b/16b signed power-of-two lowpass FIR filter). Figure 7.17 demonstrates the noise shaping after the signed power-of-two compensation lowpass filter and decimation by a faxtor of 2 for Boser’s 2nd Order EAM. Comparing Fig­ ure 7.17 and Figure 7.4 or Figure 6.10, we explain and show why comb filter can be applied to decimate data to as low as two times the Nyquist frequency.

94 Ccmpensibon fltor ((wit a 3-SHige 12B-Hp-Comb-F«er) 32-tap 2bneb signed re FIfl) Frequency Spectnsn

- 1 0

-2 0

-30

-SO

-70

-60 xIO (a). Compensation Filter

Zoomed Compenatfon FItor (Curt e 3-SttQe t28-4ip-Conib-faw) 32-Hp 2fan6b Signed P2 FIR) Frequrnqr Spw&um

OS

- 1

05 35 45 KlO* (b). Zoomed Compensation Filter

Figure 7.15: Frequency Spectrum of a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter for a 3-Stage 128-Tap Comb-Filter

95 Fm». Spsctum o< a 3-Slig» t2B-ep-Conti-F»ir Ciscsd*! by a Coniwisafcn Few (32-tip 2hn 6b signed P2 RR)

- 1 0

-60

-70

-80, 05 as * 10* (a). Cmb + Cmp Filter

Zoomed Fraq. Spira of a 3-Stige 128-tip-Corab-Faer Cascadsd by a Compweelbn Ftier p2-tip 2b/lflb Siywd P2 FIA)

S. OS

05 as 4^

(b). Zoomed Cmb 4- Cmp Filter

Figure 7.16: Frequency Spectrum of a 3-Stage 128-Tap Comb-Filter Cascaded by a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter

96 Mois» Stnpino (iflv 2 < ^ 2b^6b SigMd P2 Cofnp fir & Dm by 2) wit «and Ordor £dM (a,«05&a^>05) -8 0

-1 0 0

-1 2 0

-140

-1 8 0

-2 0 0

-2 2 0 06 2 6 Frequency (Hz)

Figure 7.17: Noise Shaping after a 32-Tap 2b/16b Signed Power-of-Two FIR Com­ pensation Filter & Decimation by 2 for Boser’s 2nd Order EAM

7.4 Programmability

Observing Figure 6.10, Figure 7.4, Figure 7.10, and Figure 7.17, we realize that

all of the previously introduced decimation combinations offer plenty of quantization

noise attenuation. The trade-offs among these choices can be checked from Fig­

ure 6.9(b), Figure 7.3(b), Figure 7.8(b) and Figure 7.16(b); those demonstrate the

baseband distortion. Higher performance requires more memory for FIR coeflScients

and arithmetical operations. Multiplication operations may be needed for the best performance; however, if small amonts of distortion in the baseband are toleraable, a multiplierless decimation stage is feasible. Depending on the diverse applications, the design freedom of the most suitable algorithms and organization is left to engineers.

97 Therefore, from the decimation stage combination given in Chapter 6 and this

chapter, for a robust EAM system, the programmable variables should include, sam­

pling frequency (/,), baseband bandwidth (2/o), oversampling rate (M ), comb-filter

tap number (N), decimation rate after the comb filter, compensation FIR filter tap

number, compensation FIR filter coefficient representation accuracy, baseband band­

width, and decimation rate of the compensation FIR filter.

7.5 Simulation Results

To demonstrate the robustness of the previous theoretical analysis to realistic

implementation, a few simulation results are presented in this section.

To be consistent with the previous theoretical analysis, the system is assumed

to be the Boser’s second order EAM (integrator gains: «i = 0.5 and 0 :2 = 0.5).

Observing Figure 5.1, in order to check the system’s dynamic range, a sinusoidal signal is appUed with magnitude —lOdB below reference value, which offers the best

performance for Boser’s EAM. The baseband bandwidth is assumed to be 25 KHz and

the sinusoidal frequency is located inside the baseband at 6.25 KHz. System sampling frequency 12.8 MHz is applied such that the oversampling rate is ~ 256.

The frequency spectrum of the pulse density stream is shown in Figure 7.18, where the signal magnitude, whole-band SNR and in-band SNR are demonstrated. We will trace the variation of these three values in further processes. Notice that the sinusoidal signal becomes two components within the whole sampling frequency range with each component being one half (—6.02dB) of the original magnitude. Moreover, note that

Figure 7.18 is the simulated realization of its theoretical analysis previously shown in

Figure 6.3.

98 Fmqumcy Specbum ef A *e Oeiwty Smeii (M bipiit^lO dB to Fefcmnce Value) (ifter Boeei» 2nd Ofderttiil)

Whola-aandSNOft -127861 dB -2 0 In-BendBNDRr : ••9&aB23«:

-40

-60

-100 -1201

-140

-160

-180

-2 0 0 * 1(f

Figure 7.18: Frequency Spectrum of the Pulse Density Stream for Boser’s 2nd Order EAM

Figure 7.19 is the frequency spectrum of data after the 3-stage 64-tap comb-filter and then a decimation by a factor of 64. Figure 7.19 corresponds to the theoretical performance given in Figure 6 .6 . Notice that the signal components are slightly distorted because of the roll-off of the 3-stage 64-tap comb-filter (reference Figure 6.7.)

We also realize that the comb-filter helps to significantly reduce the quantization noise.

Figure 7.20, corresponding to Figure 6.10, is the frequency spectrum after the compensation lowpass FIR filter (given in Figure 6 .8 ) and decimation by a factor of

4 to the Nyquist range. We find that not only a 16-bit resolution (SNR > 96 dB)

EAM system is accomplished, but also the signal components are compensated.

99 0 8 1 1 ^ FrMutnqr(Hz)

Figure 7.19: Frequency Spectrum after a 3-Stage 64-Tap Comb-Filter &: Decimation by 64 for Boser’s 2nd Order EAM

RMT 4 C9m br 4) • M OMV fcwrt ZAM r — 1 >100237dB >16.0237

SNOR* 96.52308

Figure 7.20: Frequency Spectrum after a 256-Tap FIR Compensation Filter & Deci­ mation by 4 for Boser’s 2nd Order EAM

1 0 0 Meanwhile, if a 32-tap signed power-of-two FIR filter (Figure 7.2) is applied in­ stead of the previously specified, high accuracy 256-tap FIR compensation filter, the frequency spectrum is demonstrated in Figure 7.21. We are aware that the signal component is slightly distorted (reference Figure 7.3) but the SNR (= 93.8754 dB)

(or dynamic range) is still around the range of 16-bit resolution. Note that, in this simulation, the tap number is only 32, and there are only two non-zero bits within the 16-bit coeflBcient (2b/16b) for this signed power-of-two FIR compensation filter.

Figure 7.21 is related to the theoretical performance shown in Figure 7.4.

m W 0wgr

l8.4116dB

SN0R»93J754

2 Z5 3 Fr#qu#ncy(Hz)

Figure 7.21: Frequency Spectrum after a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter & Decimation by 4 for Boser’s 2nd Order EAM

Figure 7.22 is the frequency spectrum of applying a 3-stage 64-tap comb-filter and decimating by a factor of 128. Similarly, Figure 7.22 is a realization for the theoretical analysis as demonstrated in Figure 7.9. Figure 7.23, corresponding to Figure 7.10, is

1 0 1 « iBi rm ii r— 4ttiibria»»it»artCWyWti«

~i&062SdB 7&9803# 7SJ99dB

4 5 9 FnqMnqr(Hz)

Figure 7.22: Frequency Spectrum after a 3-Stage 64-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order SAM

.18.0730 dB

SNOR « 752322 dB

-1 0 0

-140

-200 ' » : 1 1 ... 1 ia 2 Z5 3 3j 4 45 5 FrtquMcy(Hz) Jtio*

Figure 7.23: Frequency Spectrum after a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter & Decimation by 2 for Boser’s 2nd Order EAM

1 0 2 the frequency spectrum when the previous data (Figure 7.22) is passed through the

32-tap (2b/16b) signed power-of-two compensation filter in Figure 7.7 and finally decimated by a factor of 2. We realize that this approach (3-stage 64-tap comb-filter and decimating by a factor of 128) is not suitable for 16-bit resolution as the in-band

SNR has been 75.899dB at this step (Figure 7.22). However, for the application requiring only 12-bit resolution, this approach is still useful. Moreover, because the roll-off affect of the comb-filter is not dramatic in this case, the signal components are very close to their original magnitudes.

Finally, Figure 7.24 shows the frequency spectrum of another approach using a

3-stage 128-tap comb-filter and decimating by a factor of 128 for the first step of the decimation stage. Figure 7.25 is the frequency spectrum comes from the previous data

(Figure 7.24) passing through the 32-tap 2b/16b signed power-of-two compensation filter given in Figure 7.15. Checking Figure 7.25, we realize that the compensation work for the 32-tap 2b/16b signed power-of-two FIR filter is not perfect (signal com­ ponent being —16.7535dJ3), but the system SNR reaches the range of 16-bit dynamic range. Note that Figure 7.24 and Figure 7.25 correspond to Figure 7.14 and Fig­ ure 7.17 respectively.

For clearance, the theoretical and simulated frequency spectra of diverse decima­ tion approaches are summarized in Table 7.1, where “P2” represents power-of-two,

“T” stands for theoretical result, “S” illustrates simulated performance, “decm_l” is for the first decimation rate (after comb-filter), and “decm_2 ” means the second decimation rate (after compensation FIR filter).

103 OnenimM$iiic(NoWmM#igf— t n q » C m t r— 4Dwbyt2DtfarfO

-1&1882dB -16.1882 dB Whoto-B«id 9 0 R ; 8& 470«« W mndSNDÂ 98.5593dB -40

-60 r -60

^-100

I -120

-140

-160

-180

-2 0 0 4 5 6 Fr»qmncy(Hz) KlO*

Figure 7.24: Frequency Spectrum after a 3-Stage 128-Tap Comb-Filter & Decimation by 128 for Boser’s 2nd Order EAM

WW|(:4**".T«pC*npmM«Qnu#pM«n w &0m6|r2)#m#2n4OM#8umm%tlW

SNOR« 93.154168

2 25 3 FrtqiMnqr(Hz)

Figure 7.25: Frequency Spectrum after a 32-Tap 2b/16b Signed Power-of-Two FIR Compensation Filter & Decimation by 2 for Boser’s 2nd Order SAM

104 64-tap Comb 64-tap Comb 64-tap Comb 128-tap Comb decm_l=64 decm_l=64 decm_l=128 decm_l=128 256-tap FIR 32-tap P2 FIR 32-tap P2 FIR 32-tap P2 FIR decm_2=4 decm ^=4 decm_2 = 2 decm_2 = 2 pulse density T Figure 6.3 Figure 6.3 Figure 6.3 Figure 6.3 stream spectrum S Figure 7.18 Figure 7.18 Figure 7.18 Figure 7.18 Comb Figure 6.4 Figure 6.4 Figure 6.4 Figure 7.12 spectrum after Comb T Figure 6.5 Figure 6.5 Figure 6.5 Figure 7.13

spectrum after T Figure 6 . 6 Figure 6 . 6 Figure 7.9 Figure 7.14 Comb & decmJ. S Figure 7.19 Figure 7.19 Figure 7.22 Figure 7.24

FIR Figure 6 . 8 Figure 7.2 Figure 7.7 Figure 7.15 Comb + FIR Figure 6.9 Figure 7.3 Figure 7.8 Figure 7.16 spectrum after T Figure 6.10 Figure 7.4 Figure 7.10 Figure 7.17 FIR & decm_2 S Figure 7.20 Figure 7.21 Figure 7.23 Figure 7.25

Table 7.1: Theoretical and Simulated Frequency Spectra of Diverse Decimation Ap­ proaches

105 C H A PT E R 8

CONCLUSION

Recently, by the rapid advances of VLSI technology, oversampling E A modulator

ADC have become more and more important in applications requiring data accuracy.

Meanwhile, the already highly developed digital circuitry can be well applied to re­ duce the complexity in conventional analog circuitry. Although, the digital portion becomes complicated, the analog circuitry has been considerably simplified and the complete system turns out to be robust with respect to nonideal circuit behaviors.

Consequently, high-precision SA modulators can be implemented using high-density

VLSI technology optimized for digital circuitry. Moreover, solving analog complexity by digital technology also allows integration of the ADC with additional DSP pro­ cessor (s). Therefore, the entire system encourages smaller dimensions, less expense, increased programmabifity, and more reliability when compared with the conventional

(pure) analog circuitry. The contributions of this dissertation and the future works will be summarized in this chapter.

106 8.1 Work Summary

Instead of directly mtroducingthe the functions of a Sigma-Delta Modulation

(SAM) system, the SAM structure is derived from a Differential Pulse Code Modu­ lation (DPCM) and a Delta Modulation (AM). The relationship among DPCM, AM, and SAM and an oversampling example are introduced in Chapter 2, which helps to realize the implicit principles of a SAM system using oversampling technology.

A simple and an advanced linearized model are derived to represent the non­ linear one-bit quantizer in Chapter 3 and Chapter 4 respectively. The simple model is enough to explain the behavior of a generalized stable SAM system while the ad­ vanced (sophisticated) model is needed to anticipating the noise spectrum confidently as well as estimate the stability issuesaccurately. The advanced model derived from the sinusoidal inputs is especially critical because, by the Fourier Analysis (Fourier series), all signals can be approximately decomposed as the summation of sinusoidal components. Therefore, the realization of the linearlized SAM model according to diverse input sinusoidal magnitudes allows for advanced design and implementation of a sophiscitated SAM system. With the linearized model, the performance of a

SAM system can be theoretically obtained no matter what kind of input signal are applied.

In Chapter 5, a wide input range lowpass SAM architecture is proposed; the input range is improved by threefold when compared with its corresponding conven­ tional competitors. The modified digital error self-calibration technique is reported to support the new architecture. The improvement of the proposed wide input range lowpass SAM system is also explained by employing the advanced model mentioned in Chapter 4.

107 The last step of an oversampling SAM ADC is a decimation stage. The single- stage and the multi-stage (comb filter + compensation FIR filter) decimation filters are discussed in Chapter 6 . The two-stage decimation filter turns out to be the most practical choice due to both the memory and performance consideration. In

Chapter 7, two-stage multipUerless decimation filters are exploited and our analyses show their feasibility. One of the most crucial contributions of analyzing the advanced model is to obtain the theoretical noise spectra, and therefore engineers are able to confidently design the necessary decimation stage without relying on a trial and error approach or overstrained conditions. The programmability issue is discussed. The simulation results in each step of an entire second order SAM system are presented, and they demonstrate consistency with the theoretical analyses.

8.2 Future Works

In this dissertation both the theoretical and the simulation results of diverse sec­ ond order, cascaded, lowpass, EAM systems, including the proposed modified archi­ tecture, are offered. The main focus of the discussion is upon the high-resolution programmable ADC. The similar analysis approaches can also be attempted in DAG

([71]), MASH ([29]), bandpass ([72]), and EAPLL ([73]).

The merits for the theoretical analyses using the advanced model including noise spectra (by Gn) and stability issue (by G*). The affect of G„ is well explored with respect to the requirements of the compensation filter from the viewpoint of SNR.

On the other hand, the affect of Gx can be further developed for high-order EAM design.

108 A comb-filter and the signed power-of-two coefficient FIR filter are used to im­ plement the decimation stage for the purpose of being multiplierless herein. The investigation of other approaches for high resolution as well as increased efficiency deserves advanced research.

Hardware requirements and implementations ([53, 74, 75, 76, 67]), which were not discussed in detail, are essential to realize the applications. Applying the theoretical analysis to the realistic hardware implementation allows the construction of an opti­ mized modulator system. Programmability is one of the charming properties for the designed EAM system. An efficient and sophisticated algorithm and control circuit are also good topics for helping engineers to decide the necessary resolution, band­ width, output data rate, gain, developing period, system complexity, and product cost.

109 BIBLIOGRAPHY

[1 ] B. Leung, “The Oversampling Technique for Analog to Digital Conversion: A Tutorial Overview,” Analog Integrated Circuits and Signal Processing, vol. 1, pp. 65-74, 1991.

[2] B. M. Gray, “Oversampled Sigma-Delta Modulation,” IEEE Transactions on Communications, vol. 35, pp. 481-489, May 1987.

[3] E. C. Iferchor and B. W. Jervis,Digital Signal Processing A Practical Approach. New York: Addision-Wesley Publishers Ltd., 1993.

[4] S. Park, “A Real-Time Implementation of Half-Band Filters to Obtain 18-20 bit Resolution &om the DSP56ADC16 Sigma-Delta A/D Converter,” ICASSP, vol. 3, no. 16, pp. 989-992, 1990.

[5] B. E. Boser, “Design and Implementation of Oversampled Analog-to-Digital Con­ verters,” Ph.D. Dissertation, Stanford University, 1989.

[6 ] A. Skavantzos, “Multiplierless Signal Processors Using Table Look-Ups and Residue Arthimetic,” ICASSP, pp. 349-352, 1992.

[7] J. W. Adams and J. A. N. Willson, “A New Approach to FIR Digital Filters with Fewer Multipliers and Reduced Sensitivity,” IEEE Transactions on Circuits and Systems, vol. 30, pp. 277-283, May 1983.

[8 ] P. P. Vaidyanathan, “Efficient and Multiplierless Design of FIR Filters with Very Sharp Cutoff via Maximally Flat Building Blocks,” IEEE Transactions on Circuits and Systems, vol. 32, no. 3, pp. 236-244, 1985.

[9] T. Saramaki and H. Tenhimen, “Efficient VLSI-Realizable Decimators for Sigma- Delta Analog-to-Digital Converters,” Proceedings International Symposium on Circuits and Systems, pp. 1525-1528, 1988.

[10] J. J. Nielsen, “Design of Linear-Phase Direct-Form FIR Digital Filters with Quantized Coefficients Using Error Spectrum Shaping Technique.^,” IEEE Trans­ actions on Acoustics, Speech, and Signal Processing, vol. 37, pp. 1020-1026, July 1989.

1 1 0 [1 1 ] M. R. Bateman and B. Liu, “An Approach to Programmable CTD Filters Using Coefficients 0, 4-1, and -1,” IEEE Transactions on Circuits and Systems, vol. 27, pp. 451-456, June 1980.

[12] S. R. Powell and P. M. Chau, “Efficient Narrowband FIR and IFIR Filter Filters Based on Power-of-Two Sigma-Delta Coefficient Thmcation,” IEEE Transac­ tions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 41, no. 8 , pp. 497-505, 1994.

[13] J. W. Adams and J. A. N. Willson, “Some Efficient Digital Prefilter Structures," IEEE Transactions on Circuits and Systems, vol. 31, pp. 260-265, Mar. 1984.

[14] M. 0. J. Hawksford and W. Wingerter, “Oversampling Filter Design in Noise- Shaping Digital-to-Analog Conversion," J. Audio Eng. Soc., vol. 38, pp. 845-856, Nov. 1990.

[15] I. Kale, R. C. S. Morling, A. Kurkowski, and D. Devine, “A High Fidelity Dec­ imation Filter For Sigma-Delta Converters," lEE Advanced A-D and D-A Con­ version Techniques and their Applications, July 1994.

[16] B. H. Leung, “Design Methodology of Decimation Filters for Oversampling ADC Based on Quadratic Programming," IEEE Transactions on Circuits and Systems, vol. 38, pp. 1121-1132, Oct. 1991.

[17] A. V. Oppenheim, A. S. Willsky, and I. T. Young, SIGNALS and SYSTEMS. Englewood Clifis, New Jersey: Prentice-Hall, 1983.

[18] J. G. Proakis and M. Salehi, COMMUNICATION SYSTEMS ENGINEERING. Englewood Cliffs, New Jersey: Prentice-Hall, 1994.

[19] F. G. Stremler, Introduction to Communication Systems. New York: Addison Wesley, third ed., 1990.

[20] B. Sklar, Digital Communications Fundamentals and Applications. Pretice Hall, Englewood Clife, New Jersey 07632: Prentice-Hall, Inc., 1988.

[21] J. G.Proakis and D. G. Manolakis,Digital Signal Processing Principles, Algo­ rithms, and Applications. Pretice HaU, Upper Saddle River, New Jersey 07458: Prentice-Hall, Inc., 1996.

[2 2 ] T. F. Darling and M. O. J. Hawksford, “Oversampled Analog-to-Digital Con­ verter for Digital Audio Systems,” the 85th Convention of the Audio Engineering Society, pp. 924-941, Nov. 1988.

I ll [23] B. P. Brandt, D. E. Wingard, and B. A. Wooley, “Second-Order Sigma-Delta Modulation for Digîtal-Audio Signal Acquisition,” IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, Apr. 1991.

[24] M. W. Hauser, “Principles of Oversamplinf A/D Conversion,”Journal of Audio Eng. Soc., vol. 39, pp. 3—26, Jan. 1991.

[25] K. Shenoi, Digital Signal Processing in Telecommunication. Pretice Hall, Upper Saddle River, New Jersey 07458: Prentice-Hall, Inc., 1995.

[26] D. Welland, B. P. D. Signore, and E. Swanson, “A Stereo 16-Bit Delta-Sigma A/D Converter for Digital Audio,” the 85th Convention of the Audio Engineering Society, pp. 476-486, Nov. 1989.

[27] B. E. Boser, “Quantization error spectrum of Sigma-Delta Modulators,” IEEE International Symposium on Circuits and Systems, pp. 2331-1323, June 1988.

[28] Y. Matsuya, K. Uchimura, A. Iwata, and etc., “A 16-bit Oversampling A-to-D Conversion Technology Using THple-Integration Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. 22, pp. 921-928, Dec. 1987.

[29] K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata, “Oversampling A-to-D and D-to-A Converters with Multistage Noise Shapng Modulators,” IEEE Transac­ tions on Acoustics Speech and Signal Processing, vol. 36, pp. 1899-1905, Dec. 1988.

[30] B. P. Brandt and B. A. Wooley, “A 50-MHz Multibit Sigma-Delta Modulator for 1 2 -b 2 -MHz A/D Conversion,” IEEE Journal of Solid-State Circuits, vol. 26, pp. 1746-1755, Dec. 1991.

[31] G. Yin, F. Stubbe, and W. Sansen, “A 16-b 320-kHz CMOS A/D Converter Using Two-Stage Third-Order EA Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 640-647, June 1993.

[32] F. Chen and B. H. Leung, “A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 453-460, Apr. 1995.

[33] T. Cataltepe, A. R. Kramer, L. E. Larson, G. C. Temes, and R. H. Walden, “Digitally Corrected Multi-Bit EA Data Converters,” IEEE ISCAS, pp. 647- 650, Dec. 1989.

[34] P. Ju, K. Suyama, P. F. Ferguson, and W. Lee, “A 22-kHz Multibit Switched- Capacitor Sigma-Delta D /A Converter with 92 dB Dynamic Range,” IEEE Jour­ nal of Solid-State Circuits, vol. 30, pp. 1316-1324, Dec. 1995.

1 1 2 [35] L. E. Larson, T. Cataltepe, and G. C. Temes, “MultiBit Oversampled EA A/D Convertor with Digital Error Correction ,” Electron Letters, vol. 24, pp. 1051- 1052, 1988.

[36] R. T. Baird and T. S. Fiez, “Linearity Enhancement of Multibit SA A/D and D/A Converters Using Data Weighted Averaging,” ŒEE Transactions on Cir­ cuits and Systems, vol. 42, pp. 753-762, Dec. 1995.

[37] F. W. Singor and W. M. Snelgrove, “Switched-Capacitor Bandpass Delta-Sigma A/D Modulation at 10.7MHz,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 184-192, Mar. 1995.

[38] T. H. Pearce, “Cascade Bandpass Sigma-Delta A-D Converters,”lEE Advanced A-D and D-A Conversion Techniques and their Applications, July 1994.

[39] D. Johns and K. Martin,Analog Integrated Circuit Design. John Wiley and Sons, Inc., 1997.

[40] R. W. Adams, J. P. F. Ferguson, A. Ganesan, S. Vincelette, A. Volpe, and R. Libert, “Theory and Practical Implemenntation of a Fifth-Order Sigma- Delta A /D Converter,” Journal Audio Engineering Society, vol. 39, pp. 515—528, July/August 1991.

[41] S. H. Ardalan and J. J. Paulos, “An Analysis of Nolinear Behavior in Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems, vol. 34, pp. 593-603, June 1987.

[42] R. T. Baird and T. S. Fiez, “Stability Analysis of High-Order Delta-Sigma Mod­ ulation for ADC’s,” IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 41, pp. 59-62, Jan. 1994.

[43] R. T. Baird and T. S. Fiez, “A Low Oversampling Ratio 14-b 500-kHz AS ADC with a Self-Calibrated Multibit DAC,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 312-319, Mar. 1996.

[44] D. P. Atherton, Nonlinear Control Engineering. London: Van Nostrand, 1975.

[45] M. Abramowitz and I. A. Stegun, Handbook of Mathematical Functions With Formulas, Graphs, and Mathematical Tables. U.S. Department of Commerce: National Bureau of Standards, Applied Mathematics Series 55, 1964.

[46] L. Risbo, “StabUity Predictions for High-Order S-A Modulators Based on Quasi- linear Modeling,” ISCAS, pp. 361-364,1994.

113 [47] M. Sarhang-Nejad and G. C. Temes, “A High-Resoultion Multibit SA ADC with Digital Correction and Relaxed Amplifier Requirements,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 648-660, June 1993.

[48] L. Carley, “A Noised-Shaping Coder Topology for 15+ Bit Converters,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 267—273, Apr. 1989.

[49] “TLC320AS55C Data Manual,”TEXAS INSTRUMENTS.

[50] R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits. Singapore; McGraw-Hill Publishing Company, 1990.

[51] P. J. Hurst, R. A. Levinson, and D. J. Block, “A Switched-Capacitor Delta- Sigma Modulator with Reduced Sensitivity to Op-Amp Gain,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 691-696, June 1993.

[52] R. Gregorian and G. C. Temes, ANALOG MGS INTEGRATED CIRCUITS FOR SIGNAL PROCESSING. New York: JOHN WHLEY & SONS, 1986.

[53] N. Paulino, J. E. Franca, and F. P. Martins, “Programmable CMOS Switched- Capacitor Biquad Using Quasi-Passive Algorithmic DAC’s,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 715-719, June 1995.

[54] K. et al., “United States Patent,”Patent Number 5,446,917, Aug. 1995.

[55] S. Chu 2ind C. S. Burrus, “Multirate Filter Designs Using Comb Filters,” IEEE Transactions on Circuits and Systems, vol. 31, pp. 913-924, Nov. 1984.

[56] J. C. Candy, “Decimation for Sigma Delta Modulation,”IEEE Transactions on Communications, vol. 34, pp. 72-76, Jan. 1986.

[57] A. V.Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Pretice Hall, Englewood Cliffs, New Jersey 07632: Prentice-Hall, Inc., 1989.

[58] S. R. Norsworthy, R. Scherier, and G. C. Temes, Delta-Sigma Data Converters, Theory, Design, and Simulation. New York: IEEE Circuits & Systems Society, Sponsor, 1997.

[59] Principles of Sigma-Delta Modulation for Analog-to-Digital Converters. Mo­ torola, Inc.

[60] J. F. Kaiser, “Nonrecursive Digital Filter Design Using the Jg-sinh Window Func­ tion,” IEEE Symp. Circuits and Systems, pp. 20—23, 1974.

[61] J. F. Kaiser,Design Subroutine (MXFLAT) for Symmetric FIR Lowpass Digital Filters with Maximally Flat Pass and Stop Bands in Programs for Digital Signal Processing. New York: IEEE Press, 1979.

114 [62] J. J. Hill, R. Linggard, and A. G. J. Holt, “An Analytical Approach to the Design of Nonrecursive Digital Filters,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 23, pp. 382-385,1975.

[63] 0 . Herrmann, “On the Approximation Problem in Nonrecursive Digital Filter Design,” IEEE Transactions on Circuits Theiry, vol. 18, pp. 411-413, 1971.

[64] I. Galton, “One-Bit Dithering in Delta-Sigma Modulator-Based D/A Conver­ sion,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1310- 1313, 1993.

[65] R. K. Poorfard and D. A. Johns, “Analysis of SA Modulators with Zero Mean Stochastic Inputs,” IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 42, pp. 164-174, Mar. 1995.

[6 6 ] L. Risbo, “On the Design of Tone-Free SA Modulators,” IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 42, pp. 52- 55, Jan. 1995.

[67] Y. C. Lim, J. B. Evans, and B. Liu, “Decomposition of Binary Integers into Signed Power-of-Two,” IEEE Transactions on Circuits and Systems, vol. 38, no. 6 , pp. 667-672, 1991.

[6 8 ] H. Samueli, “An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Power-of-Two CoeflBcients,” IEEE Transactions on Circuits and Systems, vol. 36, no. 7, pp. 1044-1047, 1989.

[69] Q. Zhao and Y. Tadokoro, “A Simple Design of FIR Filters with Power-of- Two CoeflBcients,” IEEE Transactions on Circuits and Systems, vol. 35, no. 5, pp. 566-570, 1988.

[70] Y. C. Lim and S. R. Parker, “FIR Filter Design Over a Discrete Power-of-Two CoeflBcient Space,” IEEE Transactions on Acoustics, Speech, and Signal Process­ ing, vol. 31, no. 3, pp. 583-591, 1983.

[71] J. C. Candy and A.-N. Huynh, “Double Interpolation for Digital-to-Analog Con­ version,” IEEE Transactions on Communications, vol. 34, pp. 77-81, Jan. 1986.

[72] B.-S. Song, “A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 1309- 1315, Dec. 1995.

[73] I. Galton, “Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation,” IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 42, pp. 621-630, Oct. 1995.

115 [74] N. Tan and S. Eriksson, “A Low-Voltage Switched-Current Delta-Sigma Modu­ lator,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 599-603, May 1995.

[75] J. Nedved, J. Vanneuville, D. Gevaert, and J. Sevenhans, “A Ttansistor-Ordy Switched Current Sigma-Delta A/D Converter for a CMOS Speech CODEC,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 819-822, July 1995.

[76] J. F. Jensen, G. Raghavan, A. E. Cosand, and R. H. Walden, “A3 .2 -GHz Second- Order Delta-Sigma Modulator Implemented in InP HBT Technology,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 1119-1127, Oct. 1995.

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