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Final Report and Periodic Project Report (Year 3 - 2003)

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Final Report and Periodic Project Report (Year 3 - 2003) INFORMATION SOCIETY TECHNOLOGIES (IST) PROGRAMME Future and Emerging Technologies (FET) SODAMOS - project IST-2000-26475 (SOurce Drain Architecture for Advanced MOS technology) Final Report and Periodic Project Report (Year 3 - 2003) Consortium: IEMN/ISEN - CNRS - UC LOUVAIN - ST Microelectronics - IET Operative Commencement date: January 1st, 2001 Duration: 3 years Coordination: E. DUBOIS, IEMN/ISEN, Cité Scientifique, Avenue Poincaré, BP 69 59652 Villeneuve d’Ascq, France [email protected] General Introduction - page -2 SODAMOS - project IST-2000-26475 (SOurce Drain Architecture for Advanced MOS technology) Final Report and Periodic Project Report (Year 3 - 2003) Contents Chapter 0 General Introduction Chapter 1 Material Engineering (Workpackage 1) Chapter 2 Simulation (Workpackage 2) Chapter 3 Device fabrication and characterization (Workpackage 3) Chapter 4 Assessment of the silicide process in industrial environment (Workpackage 4) Chapter 5 General Conclusion General Introduction - page -1 Chapter 0 General Introduction Content page 0.1 Recall of the project objectives 1 0.1.1 Background 1 0.1.2 Position of the problem to solve 1 0.1.3 Solution studied in the frame of the SODAMOS project 3 0.1.4 Goals and organization of the research 4 0.2 Organization of this report 5 0.2.1 Chapter 1: Material engineering (WP1) 5 0.2.2 Chapter 2: Simulation (WP2) 6 0.2.3 Chapter 3: Device fabrication and characterization (WP3) 6 0.2.4 Chapter 4: Assessment of the silicide process in industrial 7 environment (WP4) 0.3 Summary on management and consortium exchanges 8 0.4 Dissemination / publications 9 0.5 Status of deliverables 11 0.6 References of general introduction 14 General Introduction - page 0 Chapter 0 General Introduction 0.1 Recall of the project objectives 0.1.1 Background Normal operation of MOSFETs with ultra-thin gate oxide and effective channel length below 50 nm has been reported in the literature [1][2]. Further reduction in device dimension probably requires more complicated architectures such as double gate structures that significantly deviates from the standard [3][4]. During the past decade, a significant effort has also been devoted to the study of electronic transport in nanometer-size structures in order to pursue down- scaling below 50 nm of channel length. It can be expected that CMOS technology will remain the leading mainstream technology down to 10 nm of channel length and that normal operation will be observed as far as room temperature is concerned. This explains why there has been much recent interest in new MOS architectures, e.g. electronic devices that uses the field effect to modulate electronic transport through lateral tunneling barriers between source and drain terminals. One typical example is the Schottky-barrier transistor pro- posed by Lepselter and Sze [5] three decades ago and recently re-actualized in the literature: gate- induced band-bending is used to modulate a Schottky barrier present at the interface between a metal or a silicide and a semiconductor channel. Following this approach, down-scaling to 10 nm of channel length appears feasible based on theoretical and simulation considerations [6]. 0.1.2 Position of the problem to solve Historically device scaling remains the primary method by which the semiconductor industry has improved productivity and performances. From the 130 nm technology node, upcoming CMOS technologies will have to face many grand challenges. Among them, a new dielectric gate stack that incorporates a high κ insulator will be needed. The objective of this project is to focus on another critical problem associated with deeply scaled devices: the optimis- General Introduction - page 1 ation of the source/drain architecture. In the near term perspective, the difficulty will consist in the formation of ultra-shallow junctions with a highly controlled extension depth and a sufficient abruptness to control short channel effects. It is worth noting that contacting the source/drain regions with a low sheet resistance material and a low specific contact resistivity is also a chal- lenge for conventional silicide processes. In order to better understand the major problems of source/drain engineering, Table 1 summarizes selected informations issued from the International Technology Roadmap for Semiconductors (ITRS’99) [7] that outline the strong constraints imposed to doping and contact technologies. Down to the 100 nm technology node, the main dif- ficulties are: - dopant activation above solid solubility to achieve low junction sheet resistance (e.g. 200 Ω/r @ 20 nm junction depth) - steep 2 D dopant profiling - boron penetration in gate oxide (p-MOS) - low contact sheet resistance (silicide) and low contact specific resistivity (silicide/silicon interface) while minimizing the silicon consumption and reducing the contact area - maximum activated dopant concentration at the silicide/silicon interface - increased interdependency of doping and silicide processes Inspection of table 1 clearly shows that many technical solutions are still inexistent for projected near-term and long-term technological generations. Referring to the 70 nm technology node, source/drain doping and contacting could become showstoppers if new solutions to reduce series resistances are not emerging. As stated in the ITRS’01 for a long term perspective, the grand challenge below the 70 nm node may be crudely formulated as the transistor structure. This means that a completely new architecture is needed to achieve sufficiently low series resistances (< 10 % of the total device resistance) and ensure immunity against short channel effects as far as the source/drain architecture is concerned. General Introduction - page 2 Table 1: Selected data from the ITRS’01 that illustrate constraints imposed by down scaling to the doping and contact technologies ROADMAP ITRS 2001 year - 2001 2004 2007 2010 2013 2016 Technology node (DRAM 1/2 pitch) nm 130 90 65 45 32 22 MPU printed gate length nm 90 53 35 25 18 13 MPU physical gate length nm 65 37 25 18 13 9 Minimum logic Vdd (HP/LOP/LSTP) Volt 1.2/1.2/1.2 1/1.1/1.2 0.7/0.9/1.1 0.6/0.8/1 0.5/0.7/0.9 0.4/0.6/0.9 Equivalent gate oxide thickness nm 1.6/2.4/2.8 1.4/1.8/2.2 1.1/1.4/1.6 0.8/1.2/1.3 0.6/1.1/1.2 0.4/1/1.1 n-MOS current drive (HP/LOP/LSTP) mA/µm 0.9/0.6/0.3 0.9/0.6/0.4 0.9/0.7/0.5 1.2/0.7/0.5 1.5/0.8/0.6 1.5/0.9/0.7 n-MOS leakage (HP/LOP/LSTP) nA/µm 10/0.1/0.001 100/0.3/0.001 1000/0.7/0.001 1200/1/3 1500/3/7 1500/10/10 n-MOS charging time τ (HP/LOP/LSTP) ps 1.6/2.5/4.6 1/1.8/2.6 0.7/1.1/1.8 0.4/0.8/1.4 0.2/0.5/0.9 0.1/0.3/0.6 Contact junction depth nm 48/95 27/45 18/37 13/26 10/19 7/13 Extension junction depth nm 27/45 15/25 10/17 7/12 5/9 4/6 Lateral abruptness of source nm/dec 7.2 4.1 2.8 2 1.4 1 extension Sidewall spacer thickness nm 27/45 15/25 10/17 7/12 5/9 4/6 Silicide thickness nm 35.8 20.4 13.8 9.9 7.2 5 Maximum silicon nm 23/46 13/26 9/18 6/13 5/9 3/6 consumption by silicidation Max contact specific resistivity Ω.cm2 4.1 10-7 2.1 10-7 1.1 10-7 6.4 10-8 3.8 10-8 2.4 10-8 Contact silicide sheet resistance Ω/r 4.2 7.4 10.9 15.2 21 30.3 Channel dopant concentration at.cm-3 4 1018 1.1 1019 2.3 1019 5 1019 1.3 1020 5 1020 solution being pursued no known solutions 0.1.3 Solution studied in the frame of the SODAMOS project Several theoretical studies and scaling methods [8][9][10][11] tend to demonstrate that conventional MOSFET architectures fabricated on a bulk silicon substrate will not survive below ~50 nm of gate length without a severe degradation of the device performances (control of short channel effect, Ion/Ioff trade-off, power consumption, frequency of operation...). Alternative archi- tectures are mainly based on the use of a very thin film SOI substrate (Silicon-On-Insulator): typ- ical active SOI layer thicknesses ranging between 2 to 20 nm are proposed for 10 to 40 nm gate length MOSFETs. Beyond the introduction of a thin SOI film, the novelty of the MOSFET archi- tecture proposed within the frame of this project lies in the use of low Schottky barrier (ideally 0 eV) contacts that replace the conventional ohmic contacts on a highly doped source/drain region. Unlike other published Schottky barrier MOSFETs, the principle of operation is based on the General Introduction - page 3 accumulation mode. This structure is hereafter called the “Accumulation Low Schottky Barrier MOSFET” (ALSB-SOI-MOS) (patent application [12]). The innovative character of this MOS technology is widely described in section 5. 0.1.4 Goals and organization of the research under the SODAMOS framework A complete validation of the ALSB-SOI technology is proposed in order to move from a laboratory concept to an industrially attractive solution. The design, optimization and fabrication of the ALSB-SOI MOSFET are the essential objectives of the SODAMOS project. This includes the demonstration of improved performances over conventional MOS architectures: i) immunity to short channel effects ii) use of a lightly doped SOI substrate for suppression of the sensitivity to dopant fluctua- tions in the channel iii) use of Schottky source/drain (S/D) contacts to suppress issues associated to the tight control of S/D doping iv) reduced S/D specific contact resistance In order to achieve these goals, the relevant points to address are: - reproducibility of very low hole Schottky barrier contact (Pt or Ir -based silicides) - obtaining of very low electron Schottky barrier contact (Er-based), including both experi- mental and theoretical studies - demonstrated capability to improve MOSFETs performances (high current and transconduc- tance, high-frequency operation, best Ion/Ioff trade-off...) over conventional highly-doped source/drain architectures.
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