DOCSLIB.ORG

Jul 2 0 2011 Libraries

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Jul 2 0 2011 Libraries Technically Superior But Unloved: A Multi-Faceted Perspective on Multi-core's Failure to Meet Expectations in Embedded Systems by MASSACHUSETTS INSTITE' Daniel Thomas Ledger OF TECHNOLOGY B.S. Electrical Engineering JUL 2 0 2011 Washington University in St. Louis 1996 LIBRARIES B.S., Computer Engineering Washington University in St. Louis 1997 ARCHIVES SUBMITTED TO THE SYSTEM DESIGN AND MANAGEMENT PROGRAM IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ENGINEERING AND MANAGEMENT AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY JUNE 2011 @2011 Daniel Thomas Ledger. All rights reserved. The author hereby grants to MIT permission to reproduce and to distribute publicly paper and electronic copies of this thesis document in whole or in part medium now known or hereafter created. K,- /II Signature of Author: Daniel Thomas Ledger Fellow, System, ign and Management Program ^// May 6 h, 2011 Certified By: Senior Lecturer, Engineering ystems Division and the Sloan School of Management Thesis Supervisor Accepted By: Patrick Hale Senior Lecturer, Engineering Systems Division Director, System Design and Management Fellows Program Technically Superior But Unloved: A Multi-Faceted Perspective on Multi-core's Failure to Meet Expectations in Embedded Systems By Daniel Thomas Ledger Submitted to the System Design and Management Program on May 6th, 2011 in Partial Fulfillment of the Requirements for the Degree of Master of Science in Engineering and Management Abstract A growing number of embedded multi-core processors from several vendors now offer several technical advantages over single-core architectures. However, despite these advantages, adoption of multi-core processors in embedded systems has fallen short of expectations and not increased significantly in the last 3-4 years. There are several technical challenges associated with multi-core adoption that have been well studied and are commonly used to explain slow adoption. This thesis first examines these technical challenges of multi-core adoption from an architectural perspective through the examination of several design scenarios. We first find that the degree of the technical challenge is highly related to the degree of architectural change required at the system level. When the nature of adoption requires higher degrees of architectural change, adoption is most difficult due to the destruction of existing product design and knowledge assets. However, where adopting firms can leverage existing architectural design patterns to minimize architectural change, adoption can be significantly easier. In addition to the architectural challenges, this thesis also explores several other factors that influence adoption related to management strategy, organization, ecosystem, and human cognitive and behavioral tendencies. Finally, this thesis presents a set of heuristics for potential adopters of multi-core technology to assess the suitability and risk of multi-core technology for their firm's products, and a second set of heuristics for supplier firms developing or selling multi-core processors to determine their likely success. Thesis Supervisor: Michael A.M. Davies Title: Senior Lecturer, Engineering Systems Division and Sloan School of Management Page 2 of 106 Acknowledgements I would like to offer my gratitude to the colleagues who have contributed to this thesis and my degree at MIT. Thank you for your precious time, your ideas, and the great discussions - your insights have been invaluable in shaping this thesis. To the community of students and professors at MIT, thank you for an incredible experience over the last 30 months. It's been a pleasure and an honor getting to know so many wonderful and talented people. To my thesis advisor, Michael Davies, thank you for the time, support and encouragement over the last year. The knowledge and guidance you've provided as both a professor and a thesis advisor have been so valuable. To Pat Hale and the SDM team, thank you for creating and running such an incredible program. To my better half, Lauren, and our two young boys, Andrew and David - thank you for the love, patience, support, compassion, understanding and help over the last 30 months. It goes without saying that none of this would have been possible without you. To my friends and extended family, thank you all for the love, support and tolerance. To my employer, Analog Devices, thank you for flexibly and support in allowing me to pursue this degree on a part time basis. Page 3 of 106 Table of Contents Abstract................................................................................................................................. 2 A cknow ledgem ents............................................................................................................ 3 Table of Contents............................................................................................................... 4 List of Figures....................................................................................................................... 8 1 Introduction and M otivation...................................................................................... 10 2. Theory Creation M ethodology .................................................................................... 12 3. A rchitecture, Innovation and D om inant Designs........................................................ 15 Structure & Architecture.................................................................................................. 15 Com plexity and Com plicatedness............................................................................... 15 D ecom position & M odularity ...................................................................................... 16 H ierarchy......................................................................................................................... 18 Design Patterns ............................................................................................................ 19 Dynam ics of Technology Evolution and Innovation...................................................... 20 Product K now ledge and A ssets ................................................................................... 20 D om inant Designs....................................................................................................... 21 Technology Innovation ............................................................................................... 22 4. Em bedded System s .................................................................................................... 25 Em bedded System s and Em bedded Processors ............................................................. 25 Em bedded Operating System s ........................................................................................ 27 System and Processor D iversity................................................................................. 28 M ore Lim ited Resources............................................................................................. 29 Platform "Stickiness"................................................................................................ .29 Product Life Cycle & Legacy ................................................................................. .. 30 Real Tim e Constraints.......................................................................................... .. 31 Page 4 of 106 Platform Certification ..................................................................................................... 31 Sum m ary......................................................................................................................... 31 5. Form s of Parallelism & Concurrency............................................................................. 33 Granularity .......................................................................................................................... 33 Types of parallelism ........................................................................................................ 33 Bit Level Parallelism ................................................................................................... 34 Instruction Level Parallelism (ILP) ................................................................................ 34 Task Parallelism & Operating System s ....................................................................... 36 Sum m ary......................................................................................................................... 40 6. Attributes of M ulti-core Processors............................................................................ 41 N um ber of cores............................................................................................................... 41 Types of Cores - Hom ogeneous and H eterogeneous ...................................................... 41 Resource Sharing ................................................................................................................ 42 M emory A rchitecture....................................................................................................... 43 Shared M em ory.......................................................................................................... 45 Distributed M em ory..................................................................................................... 47 Hybrid Variants.........................................................................................................
Load more

Recommended publications
  • Bootstomp: on the Security of Bootloaders in Mobile Devices
    BootStomp: On the Security of Bootloaders in Mobile Devices Nilo Redini, Aravind Machiry, Dipanjan Das, Yanick Fratantonio, Antonio Bianchi, Eric Gustafson, Yan Shoshitaishvili, Christopher Kruegel, and Giovanni Vigna, UC Santa Barbara https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/redini This paper is included in the Proceedings of the 26th USENIX Security Symposium August 16–18, 2017 • Vancouver, BC, Canada ISBN 978-1-931971-40-9 Open access to the Proceedings of the 26th USENIX Security Symposium is sponsored by USENIX BootStomp: On the Security of Bootloaders in Mobile Devices Nilo Redini, Aravind Machiry, Dipanjan Das, Yanick Fratantonio, Antonio Bianchi, Eric Gustafson, Yan Shoshitaishvili, Christopher Kruegel, and Giovanni Vigna fnredini, machiry, dipanjan, yanick, antoniob, edg, yans, chris, [email protected] University of California, Santa Barbara Abstract by proposing simple mitigation steps that can be im- plemented by manufacturers to safeguard the bootloader Modern mobile bootloaders play an important role in and OS from all of the discovered attacks, using already- both the function and the security of the device. They deployed hardware features. help ensure the Chain of Trust (CoT), where each stage of the boot process verifies the integrity and origin of 1 Introduction the following stage before executing it. This process, in theory, should be immune even to attackers gaining With the critical importance of the integrity of today’s full control over the operating system, and should pre- mobile and embedded devices, vendors have imple- vent persistent compromise of a device’s CoT. However, mented a string of inter-dependent mechanisms aimed at not only do these bootloaders necessarily need to take removing the possibility of persistent compromise from untrusted input from an attacker in control of the OS in the device.
    [Show full text]
  • FAN53525 3.0A, 2.4Mhz, Digitally Programmable Tinybuck® Regulator
    FAN53525 — 3.0 A, 2.4 MHz, June 2014 FAN53525 3.0A, 2.4MHz, Digitally Programmable TinyBuck® Regulator Digitally Programmable TinyBuck Digitally Features Description . Fixed-Frequency Operation: 2.4 MHz The FAN53525 is a step-down switching voltage regulator that delivers a digitally programmable output from an input . Best-in-Class Load Transient voltage supply of 2.5 V to 5.5 V. The output voltage is 2 . Continuous Output Current Capability: 3.0 A programmed through an I C interface capable of operating up to 3.4 MHz. 2.5 V to 5.5 V Input Voltage Range Using a proprietary architecture with synchronous . Digitally Programmable Output Voltage: rectification, the FAN53525 is capable of delivering 3.0 A - 0.600 V to 1.39375 V in 6.25 mV Steps continuous at over 80% efficiency, maintaining that efficiency at load currents as low as 10 mA. The regulator operates at Programmable Slew Rate for Voltage Transitions . a nominal fixed frequency of 2.4 MHz, which reduces the . I2C-Compatible Interface Up to 3.4 Mbps value of the external components to 330 nH for the output inductor and as low as 20 µF for the output capacitor. PFM Mode for High Efficiency in Light Load . Additional output capacitance can be added to improve . Quiescent Current in PFM Mode: 50 µA (Typical) regulation during load transients without affecting stability, allowing inductance up to 1.2 µH to be used. Input Under-Voltage Lockout (UVLO) ® At moderate and light loads, Pulse Frequency Modulation Regulator Thermal Shutdown and Overload Protection . (PFM) is used to operate in Power-Save Mode with a typical .
    [Show full text]
  • Embedded Computer Solutions for Advanced Automation Control «
    » Embedded Computer Solutions for Advanced Automation Control « » Innovative Scalable Hardware » Qualifi ed for Industrial Software » Open Industrial Communication The pulse of innovation » We enable Automation! « Open Industrial Automation Platforms Kontron, one of the leaders of embedded computing technol- ogy has established dedicated global business units to provide application-ready OEM platforms for specifi c markets, includ- ing Industrial Automation. With our global corporate headquarters located in Germany, Visualization & Control Data Storage Internet-of-Things and regional headquarters in the United States and Asia-Pa- PanelPC Industrial Server cifi c, Kontron has established a strong presence worldwide. More than 1000 highly qualifi ed engineers in R&D, technical Industrie 4.0 support, and project management work with our experienced sales teams and sales partners to devise a solution that meets M2M SYMKLOUD your individual application’s demands. When it comes to embedded computing, you can focus on your core capabilities and rely on Kontron as your global OEM part- ner for a successful long-term business relationship. In addition to COTS standards based products, Kontron also of- fers semi- and full-custom ODM services for a full product port- folio that ranges from Computer-on-Modules and SBCs, up to embedded integrated systems and application ready platforms. Open for new technologies Kontron provides an exceptional range of hardware for any kind of control solution. Open for individual application Kontron systems are available either as readily integrated control solutions, or as open platforms for customers who build their own control applications with their own look and feel. Open for real-time Kontron’s Industrial Automation platforms are open for Real- Industrial Ethernet Time operating systems like VxWorks and Linux with real time extension.
    [Show full text]
  • Emerging Technologies Multi/Parallel Processing
    Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ...........
    [Show full text]
  • Corecommander for Microprocessors and Microcontrollers
    CORECOMMANDER FOR MICROPROCESSORS AND MICROCONTROLLERS Factsheet Direct access to memory and peripheral devices (I/O) for testing, debugging and in-system programming • Direct access to memory and peripheral (I/O) devices of a micro- processor through its (JTAG) debug interface • Read data from, write data to memory and peripherals without software programming • At-speed execution of read and write cycles • Testing and debugging of the connectivity of processor memory and peripherals with at-speed bus cycles without software programming • Easy programming of processor flash memory without software programming Corecommander provides high-level functions to write data to and read data from microprocessor memory Order information CoreComm Micro (core) and I/O addresses without software programming. (core) = ARM 7, ARM 9, ARM 11, Cortex-A, Cortex-R, CoreCommander functions are applied via the JTAG Cortex-M, Blackfin, PXA2xx, PXA3xx, IXP4xx, PowerPC- interface. MPC500 family, PowerPC-MPC5500 family, PowerPC- MPC5600 family, C28x, XC166, Tricore, PIC32 Applications CoreCommander is used in design debug, manufactu- ring test and (field) service for many different applica- [1] if the uProcessor also contains a boundary-scan register then teh tests and in-system tions such as: programming operations can also be done using the boundary-scan register instead of the CoreCommander. Whether in that case the CoreCommander or the boundary-scan register is used depends on preference or performance. • Diagnosing “dead-kernel” boards; no embedded code is required to perform memory reads and Background writes. A uP performs read and write operations on its bus to ac- cess memory and I/O locations. The read and write cycles • Determining the right settings for the peripheral normally result when the uP executes a program that is controller (DDR controller, flash memory controller, stored in memory.
    [Show full text]
  • High Performance Computing Systems: Status and Outlook
    Acta Numerica (2012), pp. 001– c Cambridge University Press, 2012 doi:10.1017/S09624929 Printed in the United Kingdom High Performance Computing Systems: Status and Outlook J.J. Dongarra University of Tennessee and Oak Ridge National Laboratory and University of Manchester [email protected] A.J. van der Steen NCF/HPC Research L.J. Costerstraat 5 6827 AR Arnhem The Netherlands [email protected] CONTENTS 1 Introduction 1 2 The main architectural classes 2 3 Shared-memory SIMD machines 6 4 Distributed-memory SIMD machines 8 5 Shared-memory MIMD machines 10 6 Distributed-memory MIMD machines 13 7 ccNUMA machines 17 8 Clusters 18 9 Processors 20 10 Computational accelerators 38 11 Networks 53 12 Recent Trends in High Performance Computing 59 13 HPC Challenges 72 References 91 1. Introduction High Performance computer systems can be regarded as the most power- ful and flexible research instruments today. They are employed to model phenomena in fields so various as climatology, quantum chemistry, compu- tational medicine, High-Energy Physics and many, many other areas. In 2 J.J. Dongarra & A.J. van der Steen this article we present some of the architectural properties and computer components that make up the present HPC computers and also give an out- look on the systems to come. For even though the speed of computers has increased tremendously over the years (often a doubling in speed every 2 or 3 years), the need for ever faster computers is still there and will not disappear in the forseeable future. Before going on to the descriptions of the machines themselves, it is use- ful to consider some mechanisms that are or have been used to increase the performance.
    [Show full text]
  • Tousimojarad, Ashkan (2016) GPRM: a High Performance Programming Framework for Manycore Processors. Phd Thesis
    Tousimojarad, Ashkan (2016) GPRM: a high performance programming framework for manycore processors. PhD thesis. http://theses.gla.ac.uk/7312/ Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non-commercial research or study This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the Author When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given Glasgow Theses Service http://theses.gla.ac.uk/ [email protected] GPRM: A HIGH PERFORMANCE PROGRAMMING FRAMEWORK FOR MANYCORE PROCESSORS ASHKAN TOUSIMOJARAD SUBMITTED IN FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF Doctor of Philosophy SCHOOL OF COMPUTING SCIENCE COLLEGE OF SCIENCE AND ENGINEERING UNIVERSITY OF GLASGOW NOVEMBER 2015 c ASHKAN TOUSIMOJARAD Abstract Processors with large numbers of cores are becoming commonplace. In order to utilise the available resources in such systems, the programming paradigm has to move towards in- creased parallelism. However, increased parallelism does not necessarily lead to better per- formance. Parallel programming models have to provide not only flexible ways of defining parallel tasks, but also efficient methods to manage the created tasks. Moreover, in a general- purpose system, applications residing in the system compete for the shared resources. Thread and task scheduling in such a multiprogrammed multithreaded environment is a significant challenge. In this thesis, we introduce a new task-based parallel reduction model, called the Glasgow Parallel Reduction Machine (GPRM).
    [Show full text]
  • Network Working Group S. Kirkpatrick Request for Comments: 1166 M
    Network Working Group S. Kirkpatrick Request for Comments: 1166 M. Stahl Obsoletes RFCs: 1117, 1020, 997, 990, 960, 943, M. Recker 943, 923, 900, 870, 820, 790, 776, 770, 762, July 1990 758, 755, 750, 739, 604, 503, 433, 349 Obsoletes IENs: 127, 117, 93 INTERNET NUMBERS Status of this Memo This memo is a status report on the network numbers and autonomous system numbers used in the Internet community. Distribution of this memo is unlimited. Table of Contents Introduction.................................................... 1 Network Numbers................................................. 4 Class A Networks................................................ 7 Class B Networks................................................ 8 Class C Networks................................................ 47 Other Reserved Internet Addresses............................... 100 Network Totals.................................................. 101 Autonomous System Numbers....................................... 102 Documents....................................................... 111 Contacts........................................................ 115 Security Considerations......................................... 182 Authors' Addresses.............................................. 182 Introduction This Network Working Group Request for Comments documents the currently assigned network numbers and gateway autonomous systems. This RFC will be updated periodically, and in any case current information can be obtained from Hostmaster at the DDN Network Information
    [Show full text]
  • PDF 19308 Kb ADSP-Bf50x Blackfin ® Processor Hardware Reference
    ADSP-BF50x Blackfin® Processor Hardware Reference Revision 1.2, February 2013 Part Number 82-100101-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .................................................................. li Intended Audience .......................................................................... li Manual Contents ........................................................................... lii What’s New in This Manual ........................................................... lv Technical Support .........................................................................
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • Totalview Reference Guide
    TotalView Reference Guide version 8.8 Copyright © 2007–2010 by TotalView Technologies. All rights reserved Copyright © 1998–2007 by Etnus LLC. All rights reserved. Copyright © 1996–1998 by Dolphin Interconnect Solutions, Inc. Copyright © 1993–1996 by BBN Systems and Technologies, a division of BBN Corporation. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, elec- tronic, mechanical, photocopying, recording, or otherwise without the prior written permission of TotalView Technologies. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. TotalView Technologies has prepared this manual for the exclusive use of its customers, personnel, and licensees. The infor- mation in this manual is subject to change without notice, and should not be construed as a commitment by TotalView Tech- nologies. TotalView Technologies assumes no responsibility for any errors that appear in this document. TotalView and TotalView Technologies are registered trademarks of TotalView Technologies. TotalView uses a modified version of the Microline widget library. Under the terms of its license, you are entitled to use these modifications. The source code is available at: ftp://ftp.totalviewtech.com/support/toolworks/Microline_totalview.tar.Z. All other brand names are the trademarks of their respective holders. Book Overview part I - CLI Commands 1
    [Show full text]
  • Mips 16 Bit Instruction Set
    Mips 16 bit instruction set Continue Instruction set architecture MIPSDesignerMIPS Technologies, Imagination TechnologiesBits64-bit (32 → 64)Introduced1985; 35 years ago (1985)VersionMIPS32/64 Issue 6 (2014)DesignRISCTypeRegister-RegisterEncodingFixedBranchingCompare and branchEndiannessBiPage size4 KBExtensionsMDMX, MIPS-3DOpenPartly. The R12000 has been on the market for more than 20 years and therefore cannot be subject to patent claims. Thus, the R12000 and old processors are completely open. RegistersGeneral Target32Floating Point32 MIPS (Microprocessor without interconnected pipeline stages) is a reduced setting of the Computer Set (RISC) Instruction Set Architecture (ISA):A-3:19, developed by MIPS Computer Systems, currently based in the United States. There are several versions of MIPS: including MIPS I, II, III, IV and V; and five MIPS32/64 releases (for 32- and 64-bit sales, respectively). The early MIPS architectures were only 32-bit; The 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MiPS32/64 differs primarily from MIPS I-V, defining the system Control Coprocessor kernel preferred mode in addition to the user mode architecture. The MIPS architecture has several additional extensions. MIPS-3D, which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX (MaDMaX), which is a more extensive set of SIMD instructions using 64-bit floating current registers, MIPS16e, which adds compression to flow instructions to make programs that take up less space, and MIPS MT, which adds layered potential. Computer architecture courses in universities and technical schools often study MIPS architecture. Architecture has had a major impact on later RISC architectures such as Alpha.
    [Show full text]