DOCSLIB.ORG

Embedded Computer Solutions for Advanced Automation Control «

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Embedded Computer Solutions for Advanced Automation Control « » Embedded Computer Solutions for Advanced Automation Control « » Innovative Scalable Hardware » Qualifi ed for Industrial Software » Open Industrial Communication The pulse of innovation » We enable Automation! « Open Industrial Automation Platforms Kontron, one of the leaders of embedded computing technol- ogy has established dedicated global business units to provide application-ready OEM platforms for specifi c markets, includ- ing Industrial Automation. With our global corporate headquarters located in Germany, Visualization & Control Data Storage Internet-of-Things and regional headquarters in the United States and Asia-Pa- PanelPC Industrial Server cifi c, Kontron has established a strong presence worldwide. More than 1000 highly qualifi ed engineers in R&D, technical Industrie 4.0 support, and project management work with our experienced sales teams and sales partners to devise a solution that meets M2M SYMKLOUD your individual application’s demands. When it comes to embedded computing, you can focus on your core capabilities and rely on Kontron as your global OEM part- ner for a successful long-term business relationship. In addition to COTS standards based products, Kontron also of- fers semi- and full-custom ODM services for a full product port- folio that ranges from Computer-on-Modules and SBCs, up to embedded integrated systems and application ready platforms. Open for new technologies Kontron provides an exceptional range of hardware for any kind of control solution. Open for individual application Kontron systems are available either as readily integrated control solutions, or as open platforms for customers who build their own control applications with their own look and feel. Open for real-time Kontron’s Industrial Automation platforms are open for Real- Industrial Ethernet Time operating systems like VxWorks and Linux with real time extension. Open for soft-PLCs and fi eldbuses We qualify our platforms for use with IEC61131-3 Soft-PLC‘s and fi eldbuses. Open for future development Industrial Vision Machine Control & Visualization Base Technologies With their open interface structure, Kontron systems are de- CompactPCI® / Industrial BoxPC Touch Monitor Computer-on-Modules signed for easy adaptation for future requirements. CompactPCI® Serial Embedded Motherboards 2 www.kontron.com » HMI – Scalable Panel PCs and Touch Monitors « Intelligent. Intuitive. Scalable. Solutions for today and tomorrow. Your benefi ts at a glance: Modern industrial design, usability and fl exibility – these are » Application Ready Platforms » High-performance devices with » Long-term availablity the most important challenges for today's HMIs. Inspired by » Ready to run, easy to use embedded multicore processor » Closed cabinets for use in rugged consumer-oriented products, industrial HMIs are facing new » Reliable and powerful technology environments challenges. They are becoming more than just a functional add- » State-of-the-art industrial design » Scalable display sizes: 10.4" to 21.5" on. HMIs as an integral part of the user experience have to be user-friendly, intuitive and have fl exible interfaces all while of- fering a state-of-the-art look and feel. Kontron's HMIs are the perfect answer to these demanding and increasing requirements as they are intelligent, intuitive and scalable. The product line of the new HMI systems offers a wide range of processor capaci- ties and display dimensions from 10.4" up to 21.5". Widescreen displays in 16:9 format allow the visualization of more detailed and additional data at one glance. Multi-touch functionalities in- crease the intuitive usability of the user interface and glass front displays ensure a modern industrial design. Besides capacitive touch screens, Kontron also offers a wide range of resistive touch displays. Kontron's industrial HMIs are ready-to-run systems as- suring the compatibility of hardware and software. The 100% industry-capable touch panels and displays meet the toughest industrial requirements concerning shock, vibration and temper- ature resistance. No matter what your requirements are, Kontron OmniView OmniClient Micro Client 3W Micro Client 3 provides you with modifi ed standard and full-custom HMIs and Monitor Complex Factory Automation Control of Production Lines Control of Production Lines long life support for your control and visualization applications taking into account the latest requirements in your market. » Can be utilized as a stand alone » Industrial Panel PCs & Workstations » Fanless Panel PC » Fanless Panel PC monitor or connected to a IPC or » Large multi-touch displays: » Display 15.6", 18.5" (16:9) with » 10.4" – 17" (4:3) with resistive touch OmniClient rear CPU section as 15.6", 18.5" and 21.5" with PCAP PCAP (projected capacitive touch, » Higher performance with Intel® Remote Solution (projected capacitive touch) glass front) Atom™ D2550 dual core processor Application » Three widescreen (16:9) display sizes » Chipset: 3rd Generation Intel® Core™ » Higher performance with Intel® » Outstanding graphical performance, (21.5", 18.5" and 15.6") with seam- i7/ i5 processors Atom™ D2550 dual core processor second graphical output less glass front design » Longer life time due to LED backlights » Outstanding graphical performance, » WiFi and RFID options » Projected capacitive (PCAP) multi- (> 50 kh) second graphical output » Maintenance-free confi guration touch performance and durability » Max. 16 GB DDR3 RAM » WiFi and RFID options available » VESA mounting pattern for easy » WiFi, Blue Tooth, RFID options » Maintenance-free confi guration attachment to a standard VESA stand available » DVI input, Display port and VGA inputs as standard CriticalC i i l andd complexl reall timei applicationsli i Due to their scalability Kontron's high performance HMIs are ideally suited for critical and complex real time applications. Kontron's Panel PC families are the perfect fi t for real time ma- chine control and visualization on one system facilitating com- patibility and interoperability among software and hardware. 4 www.kontron.com » Scalable Box PC family « Boundless possibilites » Long term availability » Compact design » Rich feature set » Easy customization Kontron’s scalable Box PCs are suitable for machines and cabinets used in a large variety of automation applications (system control, process control, fi eldbus environments etc.) and offer scaleability in performance, connectivity, and size. Kontron’s Box PCs fi t nearly all applications in an industrial environment. When EMC, temperature, vibration and shock become an issue, Kontron’s Box PCs are the right choice. Application KBox A-101 KBox B-101 KBox C-100 KBox C-101 Compact fanless Box PC Exteme computing power Kontron Intelligent Control Industrial BoxPC » Maintenance free Box-IPC » With 2 independent display support » Two interface sides: upper and lower » Maintenance free design » D2250 Intel® ATOM™ D2550 and SSD side » Fanless 4th Gen Intel® Core™ i dual core processor » Ideal fi t for high end computing in » Compact Industrial PC based on processors » Ultra Slim design and low a compact form factor Kontron COMe Modules with 24V » Scalable & expandable (COMe) power consumption » Based on 4th Generation Intel® CPUs Power Supply » 2x miniPCIe & 2x PCIe x 4 » Fieldbus extensions » Long term available embedded » Wide Performance Span from third » 2x SATA SSD/HDD exchangeable » 2x USB 3.0 Mini-ITX Motherboard with Intel® generation Intel® Celeron to Intel® on front side » MSATA and 2,5" SSD/HDD H81Chipset Core™ i7 » 3x Gigabit Ethernet with » 24V Power Supply » High graphics performance incl. » 4x Gigabit Ethernet with IEEE1588 IEEE 1588 support Improving Performance 2x Display Port support, 7 USB 2.0, 128 Kbyte » 24V Power Supply » Removable HDD/SSD NVRAM » Control cabinet mounting As a global technology leader in the print media industry, » 2x USB 3.0 » One PCIe x1 slot for Low Profi le working with partners who have the same philosophy of high Fieldbus ADD ON cards quality as ourselves is especially crucial. We have relied on Kontron's innovative technology in our printing presses for over 15 years. The ability to develop solutions with a long service life that are geared to our individual specifications is highly important to us. This is why we opt for Kontron when it comes to our operating computers that are close to the heart of our products. 6 www.kontron.com » CompactPCI® «» CompactPCI® Serial « CompactPCI® provides solutions for high-density, integrated With Kontron's vast CompactPCI® ecosystem, engineers and CompactPCI® Serial is the new vendor-independent and market- » New high-density connectors supporting for data rates of systems with excellent EMI shielding and optimized cooling system designers have many options to confi gure systems independent multipurpose platform for bandwidth-hungry appli- up to 12Gb/s concepts. The standard utilizes the Euro-card form factor which is according to application demands. From redundant, multi-core cations. CompactPCI® Serial describes a new base standard that » Latest interface technologies available on the backplane – optimized for harsh industrial environments. Kontron integrates platforms over IO loaded racks up to RAID systems for mass- is the logical enhancement of the very successful and worldwide- PCI Express® 3.0, Ethernet, USB 3.0, SATA 6Gb/s all these characteristics into a wide range of CompactPCI® storage, each platform represents a perfect individual solution accepted CompactPCI® specifi cations. It enables a new genera- » A mechanical design
Load more

Recommended publications
  • Bootstomp: on the Security of Bootloaders in Mobile Devices
    BootStomp: On the Security of Bootloaders in Mobile Devices Nilo Redini, Aravind Machiry, Dipanjan Das, Yanick Fratantonio, Antonio Bianchi, Eric Gustafson, Yan Shoshitaishvili, Christopher Kruegel, and Giovanni Vigna, UC Santa Barbara https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/redini This paper is included in the Proceedings of the 26th USENIX Security Symposium August 16–18, 2017 • Vancouver, BC, Canada ISBN 978-1-931971-40-9 Open access to the Proceedings of the 26th USENIX Security Symposium is sponsored by USENIX BootStomp: On the Security of Bootloaders in Mobile Devices Nilo Redini, Aravind Machiry, Dipanjan Das, Yanick Fratantonio, Antonio Bianchi, Eric Gustafson, Yan Shoshitaishvili, Christopher Kruegel, and Giovanni Vigna fnredini, machiry, dipanjan, yanick, antoniob, edg, yans, chris, [email protected] University of California, Santa Barbara Abstract by proposing simple mitigation steps that can be im- plemented by manufacturers to safeguard the bootloader Modern mobile bootloaders play an important role in and OS from all of the discovered attacks, using already- both the function and the security of the device. They deployed hardware features. help ensure the Chain of Trust (CoT), where each stage of the boot process verifies the integrity and origin of 1 Introduction the following stage before executing it. This process, in theory, should be immune even to attackers gaining With the critical importance of the integrity of today’s full control over the operating system, and should pre- mobile and embedded devices, vendors have imple- vent persistent compromise of a device’s CoT. However, mented a string of inter-dependent mechanisms aimed at not only do these bootloaders necessarily need to take removing the possibility of persistent compromise from untrusted input from an attacker in control of the OS in the device.
    [Show full text]
  • FAN53525 3.0A, 2.4Mhz, Digitally Programmable Tinybuck® Regulator
    FAN53525 — 3.0 A, 2.4 MHz, June 2014 FAN53525 3.0A, 2.4MHz, Digitally Programmable TinyBuck® Regulator Digitally Programmable TinyBuck Digitally Features Description . Fixed-Frequency Operation: 2.4 MHz The FAN53525 is a step-down switching voltage regulator that delivers a digitally programmable output from an input . Best-in-Class Load Transient voltage supply of 2.5 V to 5.5 V. The output voltage is 2 . Continuous Output Current Capability: 3.0 A programmed through an I C interface capable of operating up to 3.4 MHz. 2.5 V to 5.5 V Input Voltage Range Using a proprietary architecture with synchronous . Digitally Programmable Output Voltage: rectification, the FAN53525 is capable of delivering 3.0 A - 0.600 V to 1.39375 V in 6.25 mV Steps continuous at over 80% efficiency, maintaining that efficiency at load currents as low as 10 mA. The regulator operates at Programmable Slew Rate for Voltage Transitions . a nominal fixed frequency of 2.4 MHz, which reduces the . I2C-Compatible Interface Up to 3.4 Mbps value of the external components to 330 nH for the output inductor and as low as 20 µF for the output capacitor. PFM Mode for High Efficiency in Light Load . Additional output capacitance can be added to improve . Quiescent Current in PFM Mode: 50 µA (Typical) regulation during load transients without affecting stability, allowing inductance up to 1.2 µH to be used. Input Under-Voltage Lockout (UVLO) ® At moderate and light loads, Pulse Frequency Modulation Regulator Thermal Shutdown and Overload Protection . (PFM) is used to operate in Power-Save Mode with a typical .
    [Show full text]
  • Low-Power Ultra-Small Edge AI Accelerators for Image Recog- Nition with Convolution Neural Networks: Analysis and Future Directions
    Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 16 July 2021 doi:10.20944/preprints202107.0375.v1 Review Low-power Ultra-small Edge AI Accelerators for Image Recog- nition with Convolution Neural Networks: Analysis and Future Directions Weison Lin 1, *, Adewale Adetomi 1 and Tughrul Arslan 1 1 Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh EH9 3FF, UK; [email protected]; [email protected] * Correspondence: [email protected] Abstract: Edge AI accelerators have been emerging as a solution for near customers’ applications in areas such as unmanned aerial vehicles (UAVs), image recognition sensors, wearable devices, ro- botics, and remote sensing satellites. These applications not only require meeting performance tar- gets but also meeting strict reliability and resilience constraints due to operations in harsh and hos- tile environments. Numerous research articles have been proposed, but not all of these include full specifications. Most of these tend to compare their architecture with other existing CPUs, GPUs, or other reference research. This implies that the performance results of the articles are not compre- hensive. Thus, this work lists the three key features in the specifications such as computation ability, power consumption, and the area size of prior art edge AI accelerators and the CGRA accelerators during the past few years to define and evaluate the low power ultra-small edge AI accelerators. We introduce the actual evaluation results showing the trend in edge AI accelerator design about key performance metrics to guide designers on the actual performance of existing edge AI acceler- ators’ capability and provide future design directions and trends for other applications with chal- lenging constraints.
    [Show full text]
  • Tegra Linux Driver Package
    TEGRA LINUX DRIVER PACKAGE RN_05071-R32 | March 18, 2019 Subject to Change 32.1 Release Notes RN_05071-R32 Table of Contents 1.0 About this Release ................................................................................... 3 1.1 Login Credentials ............................................................................................... 4 2.0 Known Issues .......................................................................................... 5 2.1 General System Usability ...................................................................................... 5 2.2 Boot .............................................................................................................. 6 2.3 Camera ........................................................................................................... 6 2.4 CUDA Samples .................................................................................................. 7 2.5 Multimedia ....................................................................................................... 7 3.0 Top Fixed Issues ...................................................................................... 9 3.1 General System Usability ...................................................................................... 9 3.2 Camera ........................................................................................................... 9 4.0 Documentation Corrections ..................................................................... 10 4.1 Adaptation and Bring-Up Guide ............................................................................
    [Show full text]
  • NVIDIA Tegra 4 Family CPU Architecture 4-PLUS-1 Quad Core
    Whitepaper NVIDIA Tegra 4 Family CPU Architecture 4-PLUS-1 Quad core 1 Table of Contents ...................................................................................................................................................................... 1 Introduction .............................................................................................................................................. 3 NVIDIA Tegra 4 Family of Mobile Processors ............................................................................................ 3 Benchmarking CPU Performance .............................................................................................................. 4 Tegra 4 Family CPUs Architected for High Performance and Power Efficiency ......................................... 6 Wider Issue Execution Units for Higher Throughput ............................................................................ 6 Better Memory Level Parallelism from a Larger Instruction Window for Out-of-Order Execution ...... 7 Fast Load-To-Use Logic allows larger L1 Data Cache ............................................................................. 8 Enhanced branch prediction for higher efficiency .............................................................................. 10 Advanced Prefetcher for higher MLP and lower latency .................................................................... 10 Large Unified L2 Cache .......................................................................................................................
    [Show full text]
  • 130 Demystifying Arm Trustzone: a Comprehensive Survey
    Demystifying Arm TrustZone: A Comprehensive Survey SANDRO PINTO, Centro Algoritmi, Universidade do Minho NUNO SANTOS, INESC-ID, Instituto Superior Técnico, Universidade de Lisboa The world is undergoing an unprecedented technological transformation, evolving into a state where ubiq- uitous Internet-enabled “things” will be able to generate and share large amounts of security- and privacy- sensitive data. To cope with the security threats that are thus foreseeable, system designers can find in Arm TrustZone hardware technology a most valuable resource. TrustZone is a System-on-Chip and CPU system- wide security solution, available on today’s Arm application processors and present in the new generation Arm microcontrollers, which are expected to dominate the market of smart “things.” Although this technol- ogy has remained relatively underground since its inception in 2004, over the past years, numerous initiatives have significantly advanced the state of the art involving Arm TrustZone. Motivated by this revival ofinter- est, this paper presents an in-depth study of TrustZone technology. We provide a comprehensive survey of relevant work from academia and industry, presenting existing systems into two main areas, namely, Trusted Execution Environments and hardware-assisted virtualization. Furthermore, we analyze the most relevant weaknesses of existing systems and propose new research directions within the realm of tiniest devices and the Internet of Things, which we believe to have potential to yield high-impact contributions in the future. CCS Concepts: • Computer systems organization → Embedded and cyber-physical systems;•Secu- rity and privacy → Systems security; Security in hardware; Software and application security; Additional Key Words and Phrases: TrustZone, security, virtualization, TEE, survey, Arm ACM Reference format: Sandro Pinto and Nuno Santos.
    [Show full text]
  • Low-Power Ultra-Small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions
    electronics Review Low-Power Ultra-Small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions Weison Lin *, Adewale Adetomi and Tughrul Arslan Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh EH9 3FF, UK; [email protected] (A.A.); [email protected] (T.A.) * Correspondence: [email protected] Abstract: Edge AI accelerators have been emerging as a solution for near customers’ applications in areas such as unmanned aerial vehicles (UAVs), image recognition sensors, wearable devices, robotics, and remote sensing satellites. These applications require meeting performance targets and resilience constraints due to the limited device area and hostile environments for operation. Numerous research articles have proposed the edge AI accelerator for satisfying the applications, but not all include full specifications. Most of them tend to compare the architecture with other existing CPUs, GPUs, or other reference research, which implies that the performance exposé of the articles are not comprehensive. Thus, this work lists the essential specifications of prior art edge AI accelerators and the CGRA accelerators during the past few years to define and evaluate the low power ultra-small edge AI accelerators. The actual performance, implementation, and productized examples of edge AI accelerators are released in this paper. We introduce the evaluation results showing the edge AI accelerator design trend about key performance metrics to guide designers. Citation: Lin, W.; Adetomi, A.; Last but not least, we give out the prospect of developing edge AI’s existing and future directions Arslan, T. Low-Power Ultra-Small Edge AI Accelerators for Image and trends, which will involve other technologies for future challenging constraints.
    [Show full text]
  • Parallel Applications Mapping Onto Heterogeneous Mpsocs Interconnected Using Network on Chip Dihia Belkacemi, Daoui Mehammed, Samia Bouzefrane
    Parallel Applications Mapping onto Heterogeneous MPSoCs interconnected using Network on Chip Dihia Belkacemi, Daoui Mehammed, Samia Bouzefrane To cite this version: Dihia Belkacemi, Daoui Mehammed, Samia Bouzefrane. Parallel Applications Mapping onto Hetero- geneous MPSoCs interconnected using Network on Chip. The 6th International Conference on Mobile, Secure and Programmable Networking, Oct 2020, Paris (virtuel), France. 10.1007/978-3-030-67550- 9_9. hal-03122083 HAL Id: hal-03122083 https://hal.archives-ouvertes.fr/hal-03122083 Submitted on 26 Jan 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Parallel Applications Mapping onto Heterogeneous MPSoCs interconnected using Network on Chip Dihia Belkacemi1, Mehammed Daoui1, and Samia Bouzefrane2 1 Laboratoire de Recherche en Informatique, Universit´ede Tizi-Ouzou, Algeria 2 CEDRIC Lab, CNAM, France [email protected] Abstract. To meet the growing requirements of today's applications, multiprocessor architectures (MPSoCs) interconnected with a network on chip (NoC) are considered as a major solution for future powerful embedded systems. Mapping phase is one of the most critical challenge in designing these systems. It consists of assigning application' tasks on the target platform which can have a considerable influence on the per- formance of the final system.
    [Show full text]
  • Experiences Using Tegra K1 and X1 for Highly Energy Efficient Computing
    Experiences Using Tegra K1 and X1 for Highly Energy Efficient Computing Gaurav Mitra Andrew Haigh Luke Angove Anish Varghese Eric McCreath Alistair P. Rendell Research School of Computer Science Australian National University Canberra, Australia April 07, 2016 Introduction & Background Overview 1 Introduction & Background 2 Power Measurement Environment 3 Experimental Platforms 4 Approach 5 Results & Analysis 6 Conclusion Mitra et. al. (ANU) GTC 2016, San Francisco April 07, 2016 2 / 20 Introduction & Background Use of low-powered SoCs for HPC Nvidia Jetson TK1: ARM + GPU SoC Nvidia Jetson TX1: ARM + GPU SoC TI Keystone II: ARM + DSP SoC Adapteva Parallella: ARM + 64-core NoC TI BeagleBoard: ARM + DSP SoC Terasic DE1: ARM + FPGA SoC Rockchip Firefly: ARM + GPU SoC Freescale Wandboard: ARM + GPU SoC Cubieboard4: ARM + GPU SoC http://cs.anu.edu.au/systems Mitra et. al. (ANU) GTC 2016, San Francisco April 07, 2016 3 / 20 Introduction & Background Use of low-powered SoCs for HPC In order for SoC processors to be considered viable exascale building blocks, important factors to explore include: Absolute performance Balancing use of different on-chip devices Understanding the performance-energy trade-off Mitra et. al. (ANU) GTC 2016, San Francisco April 07, 2016 4 / 20 Introduction & Background Contributions Environment for monitoring and collecting high resolution power measurements for SoC systems Understanding the benefits of exploiting both the host CPU and accelerator GPU cores simultaneously for critical HPC kernels Performance and energy comparisons
    [Show full text]
  • Towards System-Wide Security Analysis of Embedded Systems
    THESE DE DOCTORAT DE SORBONNE UNIVERSITE préparée à EURECOM École doctorale EDITE de Paris n◦ ED352 Spécialité: «Informatique, Télécommunications et Électronique» Sujet de la thèse: Towards System-Wide Security Analysis of Embedded Systems Thèse présentée et soutenue à Biot, le 53/29/4242, par Nassim Corteggiani Président Prof. Marc Dacier EURECOM Rapporteurs Prof. Jean-Louis Lanet INRIA Prof. Konrad Rieck TU Braunschweig Examinateurs Dr. Renaud Pacalet Télécom Paristech Dr. Marie-Lise Flottes Univ. Montpellier / CNRS Stéphane Di Vito Maxim Integrated Nicusor Penisoara NXP Semiconductors Directeur de thèse Prof. Aurélien Francillon EURECOM Preface Even if only my name is written on the cover of this Ph.D. thesis, many people around me deserved credits for its completion. Therefore, I would like to present my grateful to people who have helped for the preparation of this thesis. First and foremost a special mention to my supervisor, Aurelien Fran- cillon, who has always been helpful, of good advice, and always present for discussions and last-minute reviews. I would like to thank my collaborators and co-authors. In particular, I would like to thank Giovanni Camurati. Designing and developing the con- cepts behind this thesis was a huge undertaking that was successful thanks to his precious collaboration. Then, I would like to thank my colleagues at EURECOM and at Maxim Integrated, for their feedbacks, discussions and cooperation. I would like to thank the committee members for their time, support, and guidance during the proofreading of this manuscript. Especially, Prof. Jean-Louis Lanet, Prof. Marc Dacier, and Dr. Renaud Pacalet for their extensive feedback on an earlier draft of this manuscript.
    [Show full text]
  • Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems
    1 ”This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.” arXiv:2007.12271v1 [cs.OH] 23 Jul 2020 2 Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems Dharmesh Tarapore∗, Shahin Roozkhosh∗, Steven Brzozowski∗ and Renato Mancuso∗ ∗Boston University, USA fdharmesh, shahin, sbrz, [email protected] Abstract—The vast majority of high-performance embedded systems implement multi-level CPU cache hierarchies. But the exact behavior of these CPU caches has historically been opaque to system designers. Absent expensive hardware debuggers, an understanding of cache makeup remains tenuous at best. This enduring opacity further obscures the complex interplay among applications and OS-level components, particularly as they compete for the allocation of cache resources. Notwithstanding the relegation of cache comprehension to proxies such as static cache analysis, performance counter-based profiling, and cache hierarchy simulations, the underpinnings of cache structure and evolution continue to elude software-centric solutions. In this paper, we explore a novel method of studying cache contents and their evolution via snapshotting. Our method complements extant approaches for cache profiling to better formulate, validate, and refine hypotheses on the behavior of modern caches. We leverage cache introspection interfaces provided by vendors to perform live cache inspections without the need for external hardware. We present CacheFlow, a proof-of-concept Linux kernel module which snapshots cache contents on an NVIDIA Tegra TX1 SoC (system on chip). Index Terms—cache, cache snapshotting, ramindex, cacheflow, cache debugging F 1 INTRODUCTION content. Importantly, our technique is not meant to replace other The burgeoning demand for high-performance embedded cache analysis approaches.
    [Show full text]
  • Tegra X1 Developer Tools Sebastien Domine, Sr
    TEGRA X1 DEVELOPER TOOLS SEBASTIEN DOMINE, SR. DIRECTOR SW ENGINEERING NVIDIA DEVELOPER TOOLS BUILD. DEBUG. PROFILE. C/C++ IDE INTEGRATION STANDALONE TOOLS HARDWARE SUPPORT CPU AND GPU DEBUGGING & PROFILING PICK A PLATFORM/API DEVELOPMENT FLOW PC SW IP Development Remote TADP Toolchain Setup Device Cross-compilation JetPack Porting Executing Nsight EE Tegra Remote Graphics Nsight Debugging Debugger Cuda-gdb Tegra VSE Debugging CPU/GPU Cuda-memcheck Tegra Tegra Remote System Graphics PerfKit CUPTI Profiler Debugger Profiling Profiling System/CPU/GPU/IO/… CUDA Visual Profiler nvprof Prosper JETSON DEVELOPMENT PACK JetPack For Linux Ubuntu 14.04 JUMP STARTS developing for Jetson platform INSTALLS Linux ARM cross-compilation tool chain INSTALLS Developer tools, CUDA, OpenCV, Libraries FLASHES Jetson OS Image REFERENCE documentation and samples COMPILES code samples, pushes them to devkit And RUNS one sample… TEGRA ANDROID DEVELOPMENT PACK ANDROID DEVELOPER PACK TADP For Windows, OSX, Linux Android Java Eclipse SDK/NDK JUMP STARTS developing for Tegra on Android INSTALLS all tools, SDKs, NDKs, Java,… REFERENCE docs, samples & tutorials TEGRA ANDROID TOOLKIT FLASHES Tegra DevKit with OS Image Tools COMPILES code samples, pushes them to devkit Docs Samples And RUNS one sample… ANDROID OS IMAGES Jelly Bean Kit Kat Lollipop Coordinated updates Per-component action selection System tray notification Concurrent uploads Multi-component dependency management Pause/uploads 7 NVIDIA® NSIGHT™ ECLIPSE EDITION Homogeneous application development for CPU+GPU
    [Show full text]