Technically Superior But Unloved: A Multi-Faceted Perspective on Multi-core's Failure to Meet Expectations in Embedded Systems by MASSACHUSETTS INSTITE' Daniel Thomas Ledger OF TECHNOLOGY B.S. Electrical Engineering JUL 2 0 2011 Washington University in St. Louis 1996 LIBRARIES B.S., Computer Engineering Washington University in St. Louis 1997 ARCHIVES SUBMITTED TO THE SYSTEM DESIGN AND MANAGEMENT PROGRAM IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ENGINEERING AND MANAGEMENT AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY JUNE 2011 @2011 Daniel Thomas Ledger. All rights reserved. The author hereby grants to MIT permission to reproduce and to distribute publicly paper and electronic copies of this thesis document in whole or in part medium now known or hereafter created. K,- /II Signature of Author: Daniel Thomas Ledger Fellow, System, ign and Management Program ^// May 6 h, 2011 Certified By: Senior Lecturer, Engineering ystems Division and the Sloan School of Management Thesis Supervisor Accepted By: Patrick Hale Senior Lecturer, Engineering Systems Division Director, System Design and Management Fellows Program Technically Superior But Unloved: A Multi-Faceted Perspective on Multi-core's Failure to Meet Expectations in Embedded Systems By Daniel Thomas Ledger Submitted to the System Design and Management Program on May 6th, 2011 in Partial Fulfillment of the Requirements for the Degree of Master of Science in Engineering and Management Abstract A growing number of embedded multi-core processors from several vendors now offer several technical advantages over single-core architectures. However, despite these advantages, adoption of multi-core processors in embedded systems has fallen short of expectations and not increased significantly in the last 3-4 years. There are several technical challenges associated with multi-core adoption that have been well studied and are commonly used to explain slow adoption. This thesis first examines these technical challenges of multi-core adoption from an architectural perspective through the examination of several design scenarios. We first find that the degree of the technical challenge is highly related to the degree of architectural change required at the system level. When the nature of adoption requires higher degrees of architectural change, adoption is most difficult due to the destruction of existing product design and knowledge assets. However, where adopting firms can leverage existing architectural design patterns to minimize architectural change, adoption can be significantly easier. In addition to the architectural challenges, this thesis also explores several other factors that influence adoption related to management strategy, organization, ecosystem, and human cognitive and behavioral tendencies. Finally, this thesis presents a set of heuristics for potential adopters of multi-core technology to assess the suitability and risk of multi-core technology for their firm's products, and a second set of heuristics for supplier firms developing or selling multi-core processors to determine their likely success. Thesis Supervisor: Michael A.M. Davies Title: Senior Lecturer, Engineering Systems Division and Sloan School of Management Page 2 of 106 Acknowledgements I would like to offer my gratitude to the colleagues who have contributed to this thesis and my degree at MIT. Thank you for your precious time, your ideas, and the great discussions - your insights have been invaluable in shaping this thesis. To the community of students and professors at MIT, thank you for an incredible experience over the last 30 months. It's been a pleasure and an honor getting to know so many wonderful and talented people. To my thesis advisor, Michael Davies, thank you for the time, support and encouragement over the last year. The knowledge and guidance you've provided as both a professor and a thesis advisor have been so valuable. To Pat Hale and the SDM team, thank you for creating and running such an incredible program. To my better half, Lauren, and our two young boys, Andrew and David - thank you for the love, patience, support, compassion, understanding and help over the last 30 months. It goes without saying that none of this would have been possible without you. To my friends and extended family, thank you all for the love, support and tolerance. To my employer, Analog Devices, thank you for flexibly and support in allowing me to pursue this degree on a part time basis. Page 3 of 106 Table of Contents Abstract................................................................................................................................. 2 A cknow ledgem ents............................................................................................................ 3 Table of Contents............................................................................................................... 4 List of Figures....................................................................................................................... 8 1 Introduction and M otivation...................................................................................... 10 2. Theory Creation M ethodology .................................................................................... 12 3. A rchitecture, Innovation and D om inant Designs........................................................ 15 Structure & Architecture.................................................................................................. 15 Com plexity and Com plicatedness............................................................................... 15 D ecom position & M odularity ...................................................................................... 16 H ierarchy......................................................................................................................... 18 Design Patterns ............................................................................................................ 19 Dynam ics of Technology Evolution and Innovation...................................................... 20 Product K now ledge and A ssets ................................................................................... 20 D om inant Designs....................................................................................................... 21 Technology Innovation ............................................................................................... 22 4. Em bedded System s .................................................................................................... 25 Em bedded System s and Em bedded Processors ............................................................. 25 Em bedded Operating System s ........................................................................................ 27 System and Processor D iversity................................................................................. 28 M ore Lim ited Resources............................................................................................. 29 Platform "Stickiness"................................................................................................ .29 Product Life Cycle & Legacy ................................................................................. .. 30 Real Tim e Constraints.......................................................................................... .. 31 Page 4 of 106 Platform Certification ..................................................................................................... 31 Sum m ary......................................................................................................................... 31 5. Form s of Parallelism & Concurrency............................................................................. 33 Granularity .......................................................................................................................... 33 Types of parallelism ........................................................................................................ 33 Bit Level Parallelism ................................................................................................... 34 Instruction Level Parallelism (ILP) ................................................................................ 34 Task Parallelism & Operating System s ....................................................................... 36 Sum m ary......................................................................................................................... 40 6. Attributes of M ulti-core Processors............................................................................ 41 N um ber of cores............................................................................................................... 41 Types of Cores - Hom ogeneous and H eterogeneous ...................................................... 41 Resource Sharing ................................................................................................................ 42 M emory A rchitecture....................................................................................................... 43 Shared M em ory.......................................................................................................... 45 Distributed M em ory..................................................................................................... 47 Hybrid Variants.........................................................................................................