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Operating Systems II — Additional Information — Contents Operating Systems II | Additional Information | Steven Hand Lent Term 2004 Contents 1 A Comparison of Page Tables 2 1.1 Multi-Level Page Tables . 2 1.2 Linear Page Tables . 3 1.3 Inverted Page Tables . 5 1.4 Guarded Page Tables . 7 1.5 Clustered Page Tables . 10 1.6 Discussion . 12 2 Virtual Memory Case Studies 13 2.1 Unix . 13 2.2 VMS . 18 2.3 Mach . 22 2.4 Windows NT . 24 3 File System Case Studies 26 3.1 FAT16 & FAT32 . 26 3.2 BSD FFS . 28 3.3 OS/2 HPFS . 29 3.3.1 HPFS Volume Structure . 29 3.3.2 Files and Fnodes . 30 3.3.3 Directories . 31 3.3.4 Extended Attributes . 32 3.3.5 Performance Issues . 33 3.3.6 Fault Tolerance . 35 3.3.7 Summary . 36 1 1 A Comparison of Page Tables 1.1 Multi-Level Page Tables Multi-level page tables (MPTs) are perhaps the simplest practical form of map- ping structure. A virtual address is treated as a structured word containing a small number of fields, with the width of each field being fixed. Translation of a virtual address proceeds by treating each field (starting with the most signif- icant) as an index into an array. The result of a single step of translation is either a pointer to another array, a translation fault or, in the ultimate step, a page table entry (PTE). A page table entry contains enough information to compute the physical address. This is illustrated in Figure 1. Base Register Virtual Address L1 Address L1 Idx L2 Idx L3 Idx Offset L1 Page Table 0 L2 Page Table n L2 Address 0 L3 Page Table n L3 Address 0 N n Leaf Entry N N Figure 1: Multi-Level Page Tables The location of the first array (the \root page table") is typically stored in an internal processor register, or some well defined location. Due to the simplicity of the structure, it is relatively easy to implement in hardware: this frees the programmer from concerns about address translation, and also may allow ef- ficient interaction with the processor pipeline structure. Contemporary CPUs which provide hardware support for MPTs include the ARM series and the x86 family. However MPTs also have a number of disadvantages: Potentially poor space overhead. • While best case overhead is superb (when all mapped virtual address are contiguous), in the average case, half of every bottom level page table will be empty, almost doubling the required space for mapping, while if memory is allocated in a `random' fashion, overhead can push towards 2 75%. Poor superpage support [a superpage is a naturally aligned region of 2n • pages, n 0]. ≥ The use of superpages can considerably improve TLB usage in certain cases, in particular if one may select an appropriate superpage size for a given application. However, MPTs effectively constrain superpage size to one of those sizes mapped by a particular level of the page table. Memory reference behaviour. • The page table is always walked from the top down. This means that n memory references are typically required for a successful lookup in an n-level MPT, although superpage mappings will be successfully resolved in fewer steps. Inflexibility. • As MPTs are typically implemented in hardware, they require that all levels of the page table be in physical memory at all times. Additionally, by hardwiring the choices for level-size and page table format, operating system designers have little flexibility in modifying the structures to better support alternative address space models. In conclusion, although MPTs tend to be the mapping structure of choice for hardware implementations due to their simplicity, they have several undesirable properties. 1.2 Linear Page Tables For machines in which the TLBs are filled by software (e.g. MIPS, Alpha), one may use a slight variation on the MPT scheme: linear page tables (LPTs). A LPT is a large array of PTEs in the virtual address space, where pages of the page table are mapped on demand using a secondary lookup scheme. Consider for example a virtual load in an application program which causes a TLB miss. The processor stalls the pipeline and vectors to a software TLB miss handler. This handler simply uses the page number of the faulting virtual address as an index into the LPT and performs a virtual load. If this load succeeds, then the TLB may be filled using the retrieved PTE, and the faulting instruction may be restated However it is possible that this load may itself cause a TLB miss which must be handled. Some processors (e.g. the DEC alpha series) provide a separate vector for double misses; in others the writer of the TLB miss handler must somehow recognise that a nested TLB miss has occurred. Regardless of this, the faulting virtual address must somehow be translated and loaded into the TLB. This secondary page table lookup can usually be simpler than the general purpose one; the protection bits may be synthesised, for example, since one knows the mode of the faulting access. In addition, since the LPT spans a contiguous region, a standard MPT may be used with less fear of poor memory utilisation. 3 Figure 2 shows how a (software) implementation of LPTs works on the Alpha 21164 processor: Initial TLB Miss 63 43 42 13 12 0 00.......00 Page Number Offset Linear Page Table (8Gb in Virtual Address Space) 1 PFN SID CTL Nested TLB Miss (Potentially) 2 63 33 32 2322 13 12 0 00.....01000 SyL1 SyL2 Offset 3 L1 System Page Table (Physical Memory) 6 Install Mapping L2 System Page Table (Physical Memory) L2 Addr 4 Install Mapping PFN CTL 5 Translation Buffer Figure 2: Translating Virtual Addresses with Linear Page Tables Notice that the nested lookup is only required if the relevant page of the linear page table has no translation cached in the TLB. Hence if a second user-level TLB miss occurs on a page mapped by the same part of the LPT, only stages and are required. This means the TLB fill routines are very efficient if the code being executed exhibits spatial locality of reference. LPTs have several advantages: Good memory reference behaviour. • In many cases, a TLB miss may be resolved with only a single memory reference. In particular if a number of consecutive TLB misses occur within a \page squared" (i.e. the range of virtual addresses spanned by a page in the linear page table), the cost of the secondary page table lookup is amortised across all of these. Simple and fast (first level) TLB miss handler. • On most architectures, the PTE lookup can be implemented in very few instructions | determine page number, scale and add to page table base, and load PTE. Pageable page tables. • On operating systems which provide an address space per process, the 4 space overhead of maintaining a large number of resident page tables can be large. Using a linear page table allows per-process regions of the address space to be mapped by pages which themselves may be paged, thus saving space. Potentially good sharing. • On operating systems with multiple virtual address spaces, it is possible to share the entire LPT; only the secondary TLB fill mechanism need be context switched. In addition, certain \page squared" regions of the virtual address space can be efficiently shared between processes by use of process id (PID) tags, if supported by the TLB. Despite these features, LPTs also share several of the poor properties of MPTs. In particular, the space overhead in the case of sparse mappings grows rapidly, and once again there is only limited support for variable sized pages. An LPT also requires a statically allocated region of the virtual address space, although this is seldom a problem. Added to these is the complexity of handling nested misses; this essentially pre- cludes hardware implementations (although the VAX did use a similar scheme), and requires the instruction set to support a \physical load" instruction (one can conceivably implement LPTs without this, but it is more difficult). Nonethe- less, LPTs are an attractive solution to the mapping problem for machines with the appropriate hardware support. 1.3 Inverted Page Tables Inverted page tables (IPTs) are based on the observation that the virtual ad- dress space is typically several orders of magnitude larger than the physical address space. Hence one should focus upon maintaining one PTE per mapped frame rather than per allocated virtual page. They were first used in the IBM System/38 in 1981, and more recently in the IBM 801 minicomputer. An IPT is a fixed size hash table containing one entry for each physical frame of memory. In its simplest form, each of these IPT entries (IPTEs) holds either a virtual page number, or some distinguished value ! which identifies an invalid mapping. When a TLB miss occurs, the page number of the faulting virtual address, vpn, is hashed to obtain a table index, k. If the kth entry contains the matching page number, then a TLB entry is constructed which maps the faulting virtual address onto the kth physical frame of memory. Hence the choice of hash function determines the mappings from virtual to physical addresses. An inverted page table is illustrated in Figure 3. There are several nice features of this scheme: If a TLB miss is taken on a page currently in memory, the successful • lookup requires only a hash (hopefully not too expensive) and a single 5 Virtual Address Virtual Page Number Offset vpn Inverted Page Table # k=h(vpn) 0 k vpn bits N Figure 3: Inverted Page Tables memory reference.
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