Dp83843 Phyter

DP83843 DP83843 PHYTER Literature Number: SNLS021B DP83843BVJE PHYTER Nov 2013 DP83843BVJE PHYTER General Description Features TheDP83843BVJEisafullfeaturePhysicalLayerdevice —IEEE 802.3 ENDEC with AUI/10BASE-T transceivers withintegratedPMDsublayerstosupportboth10BASE-T and built-in filters and 100BASE-X Ethernet protocols. —IEEE 802.3u 100BASE-TX compatible - directly drives ThisVLSIdeviceisdesignedforeasyimplementationof standard Category 5 UTP, no need for external 10/100Mb/sEthernetLANs.ItinterfacesdirectlytoTwisted 100BASE-TX transceiver Pairmediathroughanexternaltransformerortofiber —Fully Integrated and fully compliant ANSI X3.263 TP- mediaviaindustrystandardelectrical/opticalfiberPMD PMD physical sublayer which includes adaptive equal- transceivers.Thisdevicealsointerfacesdirectlytothe ization and BLW compensation MAClayerthroughtheIEEE802.3ustandardMediaInde- —IEEE802.3u100BASE-FXcompatible-connectsdirect- pendentInterface(MII),ensuringinteroperabilitybetween ly to industry standard Electrical/Optical transceivers products from different vendors. —IEEE 802.3u Auto-Negotiation for automatic speed se- TheDP83843isdesignedwithNationalSemiconductor's lection advancedCMOSprocess.Itssystemarchitectureisbased ontheintegrationofseveralofNational'sindustryproven —IEEE 802.3u compatible Media Independent Interface core technologies: (MII) with Serial Management Interface —IEEE 802.3 ENDEC with AUI/10BASE-T transceiver —Integrated high performance 100 Mb/s clock recovery module to provide the 10 Mb/s functions circuitry requiring no external filters —ClockRecovery/GeneratorModulesfromNational'sFast —Full Duplex support for 10 and 100 Mb/s data rates Ethernet and FDDI products —MII Serial 10 Mb/s mode —FDDI Stream Cipher scrambler/descrambler for —Fully configurable node/switch and 100Mb/s repeater TP-PMD modes —100BASE-Xphysicalcodingsub-layer(PCS)andcontrol —Programmableloopbackmodesforflexiblesystemdiag- logicthatintegratesthecoremodulesintoadualspeed nostics Ethernet physical layer controller —Flexible LED support —ANSI X3T12 Compliant TP-PMD Transceiver —Single register access to complete PHY status technology with Baseline Wander (BLW) compensation —MDIO interrupt support —Individualized scrambler seed for 100BASE-TX applications using multiple PHYs —Low power consumption for multi-port applications —Small footprint 80-pin PQFP package System Diagram 10BASE-T or 100BASE-TX MII 10 AND/OR 100 Mb/s 10BASE-T ETHERNET MAC OR DP83843 10/100 Mb/s RJ-45 or 100Mb/s REPEATER 100BASE-TX CONTROLLER ETHERNET PHYSICAL LAYER MAGNETICS 25 MHz STATUS CLOCK LEDS 100BASE-FX/ AUI ThunderLAN® is a registered trademark of Texas Instruments. TWISTER™ is a trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation www.national.com Block Diagram MII HARDWARE CONFIGURATION SERIAL PINS MANAGEMENT (REPEATER, SERIAL10, SYMBOL, , RX_EN RX_ER TX_ER TX_EN TX_CLK MDIO RX_CL AN0, AN1,FXEN RX_DV COL CRS TXD[3:0] MDC RXD[3:0] PHYAD[4:0]) MII INTERFACE/CONTROL RX_DATA RX_CLK RX_DATA TX_DATA RX_CLK TX_DATA TX_CLK TRANSMIT CHANNELS & REGISTERS RECEIVE CHANNELS & STATE MACHINES STATE MACHINES MII 100 MB/S 10 MB/S 100 MB/S 10 MB/S 4B/5B PHY ADDRESS 4B/5B ENCODER NRZ TO DECODER AUTO MANCHESTER MANCHESTER NEGOTIATION TO NRZ SCRAMBLER ENCODER CODE GROUP DECODER NODE/RPTR ALIGNMENT PARALLEL TO CLOCK SERIAL PCS CONTROL DESCRAMBLER RECOVERY LINK PULSE GENERATOR 10BASE-T SERIAL TO PARALLEL NRZ TO NRZI 100BASE-X ENCODER NRZI TO NRZ LINK PULSE DECODER TRANSMIT DETECTOR BINARY TO FILTER MLT-3 CLOCK RECOVERY ENCODER FAR-END-FAULT STATE MACHINE MLT-3 TO RECEIVE BINARY FILTER 10/100 COMMON DECODER OUTPUT DRIVER ADAPTIVEEQ AND SMART AUTO-NEGOTIATION BLW SQUELCH STATE MACHINE COMP. 10/100 COMMON INPUT BUFFER CLOCK GENERATION LED DRIVERS TXAR100 TPTD+/− LEDS FXRD/AUIRD+/− TPRD+/− FXTD/AUITD+/− SYSTEM CLOCK FXSD/CD+/− REFERENCE 2 www.national.com Table of Contents 1.0 Pin Descriptions . 5 7.0 User Information . 42 1.1 MII Interface . 5 7.1 Link LED While in Force 100Mb/s Good Link . 42 1.2 10 Mb/s and 100 Mb/s PMD Interface . 6 7.2 False Link Indication When in Forced 10Mb/s . 42 1.3 Clock Interface . 8 7.3 10Mb/s Repeater Mode . 42 1.4 Device Configuration Interface . 8 7.4 Resistor Value Modifications . 42 1.5 LED Interface . 10 7.5 Magnetics . 43 1.6 PHY Address Interface . 11 7.6 Next Page Toggle Bit Initialization . 43 1.7 Reset . 11 7.7 Base Page to Next Page Initial FLP Burst Spacing 1.8 Power And Ground Pins . 12 43 1.9 Special Connect Pins . 12 7.8 100Mb/s FLP Exchange Followed by Quiet . 43 2.0 Functional Description . 13 7.9 Common Mode Capacitor for EMI improvement 44 2.1 802.3u MII . 13 7.10 BAD_SSD Event Lockup . 44 2.2 100BASE-TX TRANSMITTER . 15 8.0 Register Block . 45 2.3 100BASE-TX RECEIVER . 18 8.1 Register Definitions . 45 2.4 10BASE-T TRANSCEIVER MODULE . 22 9.0 Electrical Specifications . 63 2.5 100 BASE-FX . 24 9.1 DC Electrical Specification . 64 2.6 AUI . 26 9.2 CGM Clock Timing . 66 3.0 Configuration . 28 9.3 MII Serial Management AC Timing . 66 3.1 Auto-Negotiation . 28 9.4 100 Mb/s AC Timing . 67 3.2 PHY Address and LEDs . 30 9.5 10 Mb/s AC Timing . 74 3.3 Half Duplex vs. Full Duplex . 31 9.6 Auto-Negotiation Fast Link Pulse (FLP) Timing 80 3.4 100 Mb/s Symbol Mode . 32 9.7 100BASE-X Clock Recovery Module (CRM) Timing 3.5 100BASE-FX Mode . 32 80 3.6 10 Mb/s Serial Mode . 32 9.8 Reset Timing . 82 3.7 10 Mb/s AUI Mode . 32 9.9 Loopback Timing . 83 3.8 Repeater vs. Node . 33 9.10 Isolation Timing . 84 3.9 Isolate Mode . 33 10.0 Test Conditions . 85 3.10 Loopback . 33 10.1 FXTD/AUITD+/- Outputs (sourcing AUI levels) . 85 4.0 Clock Architecture . 34 10.2 FXTD/AUITD+/- Outputs (sourcing PECL) . 85 4.1 Clock Generation Module (CGM) . 34 10.3 CMOS Outputs (MII and LED) . 85 4.2 100BASE-X Clock Recovery Module . 36 10.4 TPTD+/- Outputs (sourcing 10BASE-T) . 85 4.3 10 Mb/s Clock Recovery Module . 36 10.5 TPTD+/- Outputs (sourcing 100BASE-TX) . 85 4.4 Reference Clock Connection Options . 36 10.6 Idd Measurement Conditions . 85 5.0 Reset Operation . 37 11.0 Package Dimensions inches (millimeters) unless other- 5.1 Power-up / Reset . 37 wise noted . 87 5.2 Hardware Reset . 37 5.3 Software Reset . 37 6.0 DP83843 Application . 38 6.1 Typical Node Application . 38 6.2 Power And Ground Filtering . 38 6.3 Power Plane Considerations . 38 3 www.national.com Connection Diagram NC ATP_GND NC NC LED_COL/PHYAD[0] LED_TX/PHYAD[1] CP_AGND NC CPTW_DVDD CPTW_DVSS CP_AVDD TWREF FXSD-/CD- AUIFX_VDD AUIFX_GND FXSD+/CD+ FXTD-/AUITD- FXRD-/AUIRD- FXTD+/AUITD+ FXRD+/AUIRD+ 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BGREF 61 40 LED_RX/PHYAD[2] NC 62 39 LED_LINK/PHYAD[3] THIN/REPEATER 63 38 LED_FDPOL/PHYAD[4] TW_AGND 64 37 IO_VSS5 TPRD- 65 36 IO_VDD5 VCM_CAP 66 35 MDC TPRD+ 67 34 MDIO TW_AVDD 68 33 TX_CLK SERIAL10 69 DP83843BVJE 32 IO_VSS4 SUB_GND1 70 PHYTER 31 TXD[0] CD_GND0 71 30 TXD[1] CD_VDD0 72 29 TXD[2] TPTD- 73 28 TXD[3] TPTD+ 74 27 IO_VSS3 CD_GND1 75 26 IO_VDD3 CD_VDD1 76 25 TX_EN SUB_GND2 77 24 TX_ER TXAR100 78 23 RX_EN TR_AVDD 79 22 CRS/SYMBOL TR_AGND 80 21 COL/FXEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 X2 X1 NC AN1 AN0 RXD[3] RXD[2] RXD[1] RXD[0] RX_DV RESET RX_ER RX_CLK IO_VSS1 IO_VSS2 IO_VDD1 IO_VDD2 SPEED10 PCS_VSS PCS_VDD Order Number DP83843BVJE NS Package Number VJE80 4 www.national.com 1.0 Pin Descriptions The DP83843 pins are classified into the following interface — DEVICE CONFIGURATION INTERFACE categories. Each interface is described in the sections that — LED INTERFACE follow. — PHY ADDRESS INTERFACE — MII INTERFACE — RESET — 10/100 Mb/s PMD INTERFACE — POWER AND GROUND PINS — CLOCK INTERFACE — SPECIAL CONNECT PINS 1.1 MII Interface Signal Name Type Pin # Description MDC I 35 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 2.5 MHz. There is no minimum clock rate. MDIO I/O, Z 34 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pul- lup resistor. CRS I/O, Z 22 CARRIER SENSE: This pin is asserted high to indicate the presence of carrier due to (SYMBOL) receive or transmit activities in 10BASE-T or 100BASE-X Half Duplex modes. In Repeater or Full Duplex mode, this pin is asserted high to indicate the presence of carrier due only to receive activity. In Symbol mode this pin indicates the signal detect status of the TP-PMD (active high). COL I/O, Z 21 COLLISION DETECT: Asserted high to indicate detection of collision condition (asser- (FXEN) tion of CRS due to simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex modes. While in 10BASE-T Half Duplex mode with Heartbeat enabled (bit 7, register 18h), this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test). During Repeater mode the heartbeat function is disabled. In Full Duplex mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. TX_CLK O, Z 33 TRANSMIT CLOCK: Transmit clock output from the DP83843: 25 MHz nibble transmit clock derived from Clock Generator Module's (CGM) PLL in 100BASE-TX mode. 2.5 MHz transmit clock in 10BASE-T Nibble mode. 10 MHz transmit clock in 10BASE-T Serial mode. TXD[3] I28TRANSMIT DATA: Transmit data MII input pins that accept nibble data during normal TXD[2] 29 nibble-wide MII operation at either 2.5 MHz (10BASE-T mode) or 25 MHz (100BASE-X mode).

Load more