DOCSLIB.ORG

Design Space Exploration of Heterogeneous Soc Platforms for a Data-Dominant Application

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Design Space Exploration of Heterogeneous Soc Platforms for a Data-Dominant Application Design Space Exploration of heterogeneous SoC Platforms for a Data-Dominant Application Universitat Aut`onomade Barcelona ETSE Engineering Superior Technical School PhD in Computer Science (Computer Engineering) Antoni Portero Trujillo Director: Prof. Jordi Carrabina Bordoll Advisor: Prof. Francky Catthoor 08193 Bellaterra, Spain June 22, 2009 " Wir lassen nie vom Suchen ab, und doch, am Ende allen unseren Suchens , sind wir amb ausgangspunkt zuruck¨ und werden diesen Ort zum ersten Mal erfassen... T.S. Eliot ...fur¨ Myrna Minkoff, Marla Singer, Judith Olofernes und Tofupax(2005/02/06) ..." 2 Acknowledgments Thanks to my academic Director Dr. Jordi Carrabina, for giving me the oppor- tunity to write this thesis and join the Microelectronics and Electronics Systems Department MiSE at the University Aut`onomade Barcelona. Thanks a lot to Guillermo Talavera for investing in me his last two years and giving a push to my thesis work. Thanks to Joaquim Saiz, Dr. Llu´ısRibas, and J.A. Velasco, because I cannot thank them enough for the opportunities and protect me and stay with me in the hard moments. Thanks for the teaching people who I worked for during these long years, Raul Aragon`es,Mercedes Rullan, Jordi Aguil´o,Elena Valderrama and all the professors and teachers of the MiSE Department. I also want to thank the excellent Depart- ment staff for their support, Toni Guerra, and all the other people that is not here anymore but they're in my mind, Montse,... Thanks to all my colleagues at work, Oscar Navas, Ramon Pla, Marius, Aitor, Borja, Marc for their support and criti- cism, part of this work is theirs. Thanks to the CEPHIS team, David Castell, Eloi Ramon, Ramon, Enric, Marc, Jorge Luis, Pablo, Jordi, Victor, Andreu, Miquel, and Cesar. Many thanks to Dr. Francky Catthoor for the guidance and for sharing his expert knowledge and helping me to take decisions of this thesis. I also want to thank the people I met at IMEC, Nacho, Pol, Yang ("Punk")...etc. Thanks to my sister Dolores for encouraging me to finish this thesis, her constant support throughput these years; she's always believed in me. I could not have reached this without her. Thanks to my dad and mum. I hope you will be proud of me, I am proud of you. Thanks to my brother Pedro, his wife Ana and my nieces Patricia and Aida. Thanks to the family that I met in Brussels, Fran, Asis, Joanma, Pierre (and his wife I hope) and all the people who were in the Samaritaine. I miss you a lot. Thanks to the people that I met at Luton University, UK, Don Dent and Richard. Thanks for all proofreading help that Ramon Carrabina offered while I was writing this thesis. Thank you to my Adventures' colleagues, Clemente, Rodrigo, David, Jose, Dani ...and my current flat mates David, Miki and Pedro. Thank you to all the girls who took part of my hearth during these long years, Agata, Ana, Sonia, Vanina, Leatitia, Juliet, Janet, Julia...and so forth, so long... And to all the people that I have convinced to develop their final career projects with me. In the chapter, there is an introduction to the system under study. State-of-the-art is presented, where existing different platforms that can implement the compressor are 3 explained. Hence, it makes clear that till now there is not a comparative of a complex IP where the different platforms hardware trade-offs could be observed. We have made an overall description of our model and different platforms. We explained the work-flow scheme and C++ model where there is an explanation about the MPEG functionality, sensor model and memory access. We have also explained the platform controller that is the responsible to get the pixels from L2 in macro-blocks size to L1. Furthermore, it is responsible to decide what type of frame is going to be compressed. We give details that we have made an accurate calibrated exploration and target comparison. Finally, we explain the platform independent transformation that we have achieved to the code. In the chapter, there is an introduction to the system under study. State-of-the-art is presented, where existing different platforms that can implement the compressor are explained. Hence, it makes clear that till now there is not a comparative of a complex IP where the different platforms hardware trade-offs could be observed. We have made an overall description of our model and different platforms. We explained the work-flow scheme and C++ model where there is an explanation about the MPEG functionality, sensor model and memory access. We have also explained the platform controller that is the responsible to get the pixels from L2 in macro-blocks size to L1. Furthermore, it is responsible to decide what type of frame is going to be compressed. We give details that we have made an accurate calibrated exploration and target comparison. Finally, we explain the platform independent transformation that we have achieved to the code. In the chapter, there is an introduction to the system under study. State-of-the-art is presented, where existing different platforms that can implement the compressor are explained. Hence, it makes clear that till now there is not a comparative of a complex IP where the different platforms hardware trade-offs could be observed. We have made an overall description of our model and different platforms. We explained the work-flow scheme and C++ model where there is an explanation about the MPEG functionality, sensor model and memory access. We have also explained the platform controller that is the responsible to get the pixels from L2 in macro-blocks size to L1. Furthermore, it is responsible to decide what type of frame is going to be compressed. We give details that we have made an accurate calibrated exploration and target comparison. Finally, we explain the platform independent transformation that we have achieved to the code. In the chapter, there is an introduction to the system under study. State-of-the-art is presented, where existing different platforms that can implement the compressor are explained. Hence, it makes clear that till now there is not a comparative of a complex IP where the different platforms hardware trade-offs could be observed. We have made an overall description of our model and different platforms. We explained the work-flow scheme and C++ model where there is an explanation about the MPEG functionality, sensor model and memory access. We have also explained the platform controller that is the responsible to get the pixels from L2 in macro-blocks size to L1. Furthermore, it is responsible to decide what type of frame is going to be compressed. We give details that we have made an accurate calibrated exploration and target comparison. Finally, we explain the platform independent transformation that we have achieved to the code. 4 Contents 1 Electronics Spectrum of Solutions: Architectures and Languages 13 1.1 Electronic Systems Design........................... 14 1.2 Architecture Platform and Network Platform................ 17 1.3 Taxonomy of Architecture Platforms for Multimedia............ 17 1.4 MPSoC Platform................................ 18 1.4.1 Platform Definition.......................... 18 1.4.2 Communication within Process Elements (PE) tiles......... 19 1.4.3 Segmented Buses............................ 19 1.4.4 Network on Chip (NoC)........................ 20 1.4.5 IP block or core............................ 20 1.5 Custom and Configurable Processor Platform................ 21 1.5.1 Mono Core and Multi Core: WLP, ILP and TLP.......... 22 1.5.2 Advantages and disadvantages of Multi Core............ 23 1.5.3 Homogeneous and Heterogeneous Processor Platform........ 24 1.6 Architectural Options............................. 24 1.6.1 General-Purpose Processor Platform................. 25 1.6.2 Generic Digital Signal Processors................... 27 1.6.3 Media Processors............................ 30 1.6.4 Video Signal Processors........................ 30 1.6.5 Co-Processors.............................. 31 1.7 Domain Specific Integrated Processors.................... 32 1.7.1 Instruction Set Processor Platforms................. 33 1.8 Custom Hardware Architectures....................... 36 1.8.1 Application Specific Integrated Circuit - ASIC platform...... 36 1.8.2 Field Programmable Gate Array - FPGA platform......... 36 1.9 Introduction to Languages for Architecture Description.......... 39 1.9.1 High Level Specification Languages.................. 41 1.10 Thesis contributions and table of contents.................. 44 1.11 Summary.................................... 46 2 The Video Compression Framework 47 2.1 The Human Visual System . 47 2.2 Video Quality . 48 2.2.1 Objective Quality Measurement . 50 2.2.2 The MPEG VIDEO Compression Standard . 51 2.2.2.1 MPEG-1 video History . 51 5 Contents 2.2.2.2 Introduction to MPEG-2 standard . 52 2.2.2.3 Main characteristics . 52 2.2.2.4 Video coding scheme . 53 2.2.2.5 MPEG-2 Audio encoding . 56 2.2.3 Introduction to MPEG-3 . 56 2.2.4 Introduction to MPEG-4 . 56 2.2.5 Introduction to MPEG-7 . 57 2.2.6 MPEG-21 Multimedia Framework.................. 58 2.3 MPEG-A: Multimedia Application Formats................. 59 2.4 MPEG Encoder and Decoder . 60 2.5 MPEG Data Stream . 62 2.5.1 I Video Object Picture format . 63 2.5.2 P Video Object Picture format . 63 2.5.3 B Video Object Picture format . 63 2.6 Discrete Cosinus Transform (DCT) Behaviour . 65 2.6.1 Reconstruction of Missing Compressed Data: DCT coefficients . 66 2.6.1.1 Fast One-Dimensional DCT Techniques . 67 2.6.1.2 Two-Dimensional DCT algorithms . 67 2.6.1.3 Three-Dimensional DCT algorithms............ 68 2.6.2 Defining an Invariant Measure of Error . 68 2.6.3 Adding Human Visual Factors . 70 2.7 Entropy Coding .
Load more

Recommended publications
  • Download the Compiled Program File Onto the Chip
    International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1].
    [Show full text]
  • White Paper - Investigate the High-Level HDL Chisel
    White Paper - Investigate the high-level HDL Chisel Florian Heilmann, Christian Brugger, Norbert Wehn Microelectronics Research Group, University Kaiserslautern Kaiserslautern, Germany [email protected], [email protected], [email protected] Abstract— Chisel (Constructing Hardware in a Scala designer can simply not use it. Another approach involves embedded language) is a new programming language, which using a language suited for the domain of the target application. embedded in Scala, used for hardware synthesis. It aims to Examples include Esterel [4], which has been modeled for increase productivity when creating hardware by enabling reactive programs and DIL[5], which is an intermediate designers to use features present in higher level programming programming language used to target pipelined reconfigurable languages to build complex hardware blocks. In this paper, the architectures like PipeRench. Moreover, there are languages most advertised features of Chisel are investigated and compared like BlueSpec[6] which is essentially a subset of to their VHDL counterparts, if present. Afterwards, the authors’ SystemVerilog putting emphasis on avoiding race conditions opinion if a switch to Chisel is worth considering is presented. by automatically generating scheduling and arbitration logic Additionally, results from a related case study on Chisel are from a set of “rules” which express synthesizable behavior. briefly summarized. The author concludes that, while Chisel has promising features, it is not yet ready for use in the industry. These languages are usually designed to support a specific design domain. This, however, leads to these approaches performing poorly when used outside the domain they were intended for. Keywords—Hardware design; Chisel; VHDL; HDL III.
    [Show full text]
  • The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014
    The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014 We will hate the tools (FCCM 1996 prediction for 2001) We will still hate the tools (FCCM 1998 prediction for 2003) We will merely dislike the tools (FCCM 2000 prediction for 2005) We [will] hate the tools more (FCCM 2007 prediction for 2012) 1 Motivation used for hardware design will be presented in an attempt to outline where weaknesses in the currently available tool-chains for hardware de- Since the introduction of integrated circuits, sign are found. Due to the sheer amount of hardware complexity has increased rapidly and different approaches made over the years and constantly. This complexity naturally is a hard tools that were developed with the intention of thing for humans to handle once it reaches a helping to improve the design process, it is not certain threshold. As a consequence, the need possible to look at them all or in more detail. for tools arises to enable the people involved in Instead, in the following, an overview over ap- the hardware design process to continue work- proaches made to create tool-chains for hard- ing on, advancing and improving the matter. ware design or single tools to be used in them, While this is a fact for any evolving branch of shall be given. It will also be outlined, what science and production, the speed, by which the their current state in productive use is. tools adapt varies greatly. Taking software de- velopment as a comparison, we find that there are often a lot of tools available for one task, 2 Criteria each one of them filling a niche or being tai- lored with a special use-case in mind.
    [Show full text]
  • Concepmon ( G ~ E Janvier
    CONCEPMONET MISE EN CE= D'UN SYST~MEDE RECONFIOURATION DYNAMIQUE PRESENTE EN VUE DE L'OBTENTION DU DIP~MEDE WSERs SCIENCES APPLIQUEES (G~EÉLE~QUE) JANVIER2000 OCynthia Cousineau, 2000. National Library Bibliothèque nationale I*I of Canada du Canada Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 395 Wellington Street 395, rue Wellington OttawaON K1AON4 Ottawa ON K1A ON4 Canada Canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, loan, distribute or sel1 reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de microfiche/film, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts f?om it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Ce mémoire intitulé: CONCEFMONET MISE EN OEWRE D'UN SYST&MEDE RECONFIGURATION DYNAMIQUE présenté par : COUSINEAU Cvnthia en vue de l'obtention du diplôme de : Maîtrise ès sciences amliauees a été dûment accepté par le jury d'examen constitué de: M. BOIS GUY, Ph.D., président M. SAVARIA Yvon, Ph.D., membre et directeur de recherche M. SAWAN Mohamad , Ph.D., membre et codirecteur de recherche M.
    [Show full text]
  • Review of FPD's Languages, Compilers, Interpreters and Tools
    ISSN 2394-7314 International Journal of Novel Research in Computer Science and Software Engineering Vol. 3, Issue 1, pp: (140-158), Month: January-April 2016, Available at: www.noveltyjournals.com Review of FPD'S Languages, Compilers, Interpreters and Tools 1Amr Rashed, 2Bedir Yousif, 3Ahmed Shaban Samra 1Higher studies Deanship, Taif university, Taif, Saudi Arabia 2Communication and Electronics Department, Faculty of engineering, Kafrelsheikh University, Egypt 3Communication and Electronics Department, Faculty of engineering, Mansoura University, Egypt Abstract: FPGAs have achieved quick acceptance, spread and growth over the past years because they can be applied to a variety of applications. Some of these applications includes: random logic, bioinformatics, video and image processing, device controllers, communication encoding, modulation, and filtering, limited size systems with RAM blocks, and many more. For example, for video and image processing application it is very difficult and time consuming to use traditional HDL languages, so it’s obligatory to search for other efficient, synthesis tools to implement your design. The question is what is the best comparable language or tool to implement desired application. Also this research is very helpful for language developers to know strength points, weakness points, ease of use and efficiency of each tool or language. This research faced many challenges one of them is that there is no complete reference of all FPGA languages and tools, also available references and guides are few and almost not good. Searching for a simple example to learn some of these tools or languages would be a time consuming. This paper represents a review study or guide of almost all PLD's languages, interpreters and tools that can be used for programming, simulating and synthesizing PLD's for analog, digital & mixed signals and systems supported with simple examples.
    [Show full text]
  • Pymtl As an Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework
    Appears in the Proceedings of the First Workshop on Open-Source EDA Technology (WOSET’18), November 2018 An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework Shunning Jiang Christopher Torng Christopher Batten School of Electrical and Computer Engineering, Cornell University, Ithaca, NY { sj634, clt67, cbatten }@cornell.edu pytest coverage.py hypothesis ABSTRACT Host Language HDL We present an overview of previously published features and work (Python) (Verilog) in progress for PyMTL, an open-source Python-based hardware generation, simulation, and verification framework that brings com- FL DUT CL DUT pelling productivity benefits to hardware design and verification. generate Verilog synth RTL DUT PyMTL provides a natural environment for multi-level modeling DUT' using method-based interfaces, features highly parametrized static Sim FPGA/ elaboration and analysis/transform passes, supports fast simulation cosim ASIC and property-based random testing in pure Python environment, Test Bench Sim and includes seamless SystemVerilog integration. Figure 1: PyMTL’s workflow – The designer iteratively refines the hardware within the host Python language, with the help from 1 INTRODUCTION pytest, coverage.py, and hypothesis. The same test bench is later There have been multiple generations of open-source hardware reused for co-simulating the generated Verilog. FL = functional generation frameworks that attempt to mitigate the increasing level; CL = cycle level; RTL = register-transfer level; DUT = design hardware design and verification complexity. These frameworks under test; DUT’ = generated DUT; Sim = simulation. use a high-level general-purpose programming language to ex- press a hardware-oriented declarative or procedural description level (RTL), along with verification and evaluation using Python- and explicitly generate a low-level HDL implementation.
    [Show full text]
  • Application of the FPGA Technology for the Development of Multi-Version Safety-Critical NPP Instrumentation and Control Systems
    УДК 004.056(274) Doi: https://doi.org/10.32918/nrs.2020.2(86).07 Application of the FPGA Technology for the Development of Multi-Version Safety-Critical NPP Instrumentation and Control Systems Perepelitsyn A. National Aerospace University «KhAI», Kharkiv, Ukraine ORCID: https://orcid.org/0000-0002-5463-7889 Illiashenko O. National Aerospace University «KhAI», Kharkiv, Ukraine ORCID: https://orcid.org/0000-0002-4672-6400 Duzhyi V. National Aerospace University «KhAI», Kharkiv, Ukraine ORCID: https://orcid.org/0000-0002-3383-1893 Kharchenko V. National Aerospace University «KhAI», Kharkiv, Ukraine Research and Production Corporation «Radiy», Kropyvnytskyi, Ukraine ORCID: https://orcid.org/0000-0001-5352-077X The paper overviews the requirements of international standards on application of diversity in safety-critical NPP instrumentation and control (I&C) systems. The NUREG 7007 classification of version redundancy and the method for diversity assessment are described. The paper presents results from the analysis of instruments and design tools for FPGA-based embedded digital devices from leading manufacturers of programmable logics using the Xilinx and Altera (Intel) chips, which are used in NPP I&C systems, as an example. The most effective integrated development environments are analyzed and the results of comparing the functions and capabilities of using the Xilinx and Altera (Intel) tools are described. The analysis of single failures and fault tolerance using diversity in chip designs based on the SRAM technology is presented. The results from assessment of diversity metrics for RadICS platform-based multi-version I&C systems are discussed. Keywords: FPGA, diversity, safety, instrumentation and control system. © Perepelitsyn A., Illiashenko O., Duzhyi V., Kharchenko V., 2020 is becoming more complicated, their sensitivity Introduction to single failures (single-event upsets (SEUs)) due to high-energy particles generated by cosmic rays Programmable logic devices (PLD) have proved increases.
    [Show full text]
  • C/VHDL Codesign for Lhcb VELO Zero Suppression Algorithms
    C/VHDL Codesign for LHCb VELO zero suppression algorithms Manfred Muecke European Organization for Nuclear Research CERN, CH-1211 Geneva 23 Switzerland Abstract—We present a workflow to generate cycle-accurate C II. REQUIREMENTS and VHDL code from one common description to accelerate and unify algorithm implementation and simulation for real-time After an initial algorithm specification and coding phase DSP applications in particle detectors. optimization often takes place on the RTL-level to minimize We use Confluence as description language which compiles resource-usage and -sharing within the FPGA. It is however into C-code (for simulation) and VHDL code (for implementation expected, that even after optimization a modification to the on FPGAs). We demonstrate the improved portability and original algorithm might be suggested due to improved system simulation speed while assuring bit- and cycle-accuracy. Our or physics knowledge. The chosen language should support a approach solves the problem of having to maintain two source high-level description of datapath-oriented designs yet provide codes (for simulation and implementation) in parallel and therefore minimizes workload and the danger of inconsistent the ability to control generated hardware transparently to models. This is crucial in an environment where algorithm assure the use for both foreseen tasks i.e. specification implementation is expected to cycle through several design mapping and resource RTL-level optimization. iterations. As the algorithms have to be integrated in
    [Show full text]
  • FPGA-Based Implementation of Signal Processing Systems
    FPGA-based Implementation of Signal Processing Systems Roger Woods Queen’s University, Belfast, UK John McAllister Queen’s University, Belfast, UK Gaye Lightbody University of Ulster, UK Ying Yi University of Edinburgh, UK A John Wiley and Sons, Ltd., Publication FPGA-based Implementation of Signal Processing Systems FPGA-based Implementation of Signal Processing Systems Roger Woods Queen’s University, Belfast, UK John McAllister Queen’s University, Belfast, UK Gaye Lightbody University of Ulster, UK Ying Yi University of Edinburgh, UK A John Wiley and Sons, Ltd., Publication This edition first published 2008 2008 John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom For details of our global editorial offices, for customer services and for information about how to apply for permission to reuse the copyright material in this book please see our website at www.wiley.com. The right of the author to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by the UK Copyright, Designs and Patents Act 1988, without the prior permission of the publisher. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic books. Designations used by companies to distinguish their products are often claimed as trademarks.
    [Show full text]
  • Reusability Is FIRRTL Ground
    Reusability is FIRRTL Ground: Hardware Construction Languages, Compiler Frameworks, and Transformations Adam Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, Jonathan Bachrach Department of Electrical Engineering and Computer Sciences, University of California, Berkeley fadamiz, jack.koenig3, psli, rlin, angie.wang, magyar, dgkim, colins, chick, ucbjrl, [email protected] Abstract—Enabled by modern languages and retargetable compilers, paper revisits them in the sole context of providing a platform software development is in a virtual “Cambrian explosion” driven by a for which to develop hardware libraries. critical mass of powerfully parameterized libraries; but hardware devel- • An open-source implementation of a hardware compiler frame- opment practices lag far behind. We hypothesize that existing hardware construction languages (HCLs) and novel hardware compiler frameworks work (HCF) to isolate RTL from implementation constraints: As (HCFs) can put hardware development on a similar evolutionary path software retargetable compilers transform general-purpose code by enabling new hardware libraries to be independent of underlying into platform-specific assembly, HCFs transform general RTL process technologies including FPGA mappings. We support this claim into target-specific RTL. By formalizing these transformations by (1) evaluating the degree with which Chisel, an existing HCL, can support powerfully parameterized libraries, and (2) introducing into a compiler framework, we can enable robust and reusable the concept and implementation of an HCF that uses an open-source RTL transformations. hardware intermediate representation, FIRRTL (Flexible Intermediate • An evaluation of many transformations that demonstrates Representation for RTL), to transform target-independent RTL into the wide-ranging applicability of our framework: Our HCF technology-specific RTL.
    [Show full text]
  • Nasa Handbook Nasa-Hdbk 8739.23A Measurement
    NASA HANDBOOK NASA-HDBK 8739.23A National Aeronautics and Space Administration Approved: 02-02-2016 Washington, DC 20546 Superseding: NASA-HDBK-8739.23 With Change 1 NASA COMPLEX ELECTRONICS HANDBOOK FOR ASSURANCE PROFESSIONALS MEASUREMENT SYSTEM IDENTIFICATION: METRIC APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED NASA-HDBK 8739.23A—2016-02-02 Mars Exploration Rover (2003) 2 of 161 NASA-HDBK 8739.23A—2016-02-02 DOCUMENT HISTORY LOG Document Status Approval Date Description Revision Initial Release Baseline 2011-02-16 (JWL4) Editorial correction to page 2 figure caption Change 1 2011-03-29 (JWL4) Significant changes were made in this revision, including: expanded content; reflected terminology and technology from the NASA-HDBK-4008, Programmable Revision A 2016-02-02 Logic Devices (PLD) Handbook (released in 2013); eliminated duplication with the PLD Handbook; and, incorporated other clarifications and corrections. (MW) 3 of 161 NASA-HDBK 8739.23A—2016-02-02 This page intentionally left blank. 4 of 161 NASA-HDBK 8739.23A—2016-02-02 This page intentionally left blank. 6 of 161 NASA-HDBK 8739.23A—2016-02-02 TABLE OF CONTENTS 1 OVERVIEW ................................................................................................................ 12 1.1 Purpose .......................................................................................................................... 12 1.2 Scope ............................................................................................................................. 12 1.3 Anticipated
    [Show full text]
  • (19) United States (12) Reissued Patent (10) Patent Number: US RE44,365 E Vorbach Et Al
    USOORE44365E (19) United States (12) Reissued Patent (10) Patent Number: US RE44,365 E Vorbach et al. (45) Date of Reissued Patent: Jul. 9, 2013 (54) METHOD OF SELF-SYNCHRONIZATION OF (56) References Cited CONFIGURABLE ELEMENTS OFA PROGRAMMABLE MODULE U.S. PATENT DOCUMENTS 2,067.477 A 1/1937 Cooper (76) Inventors: Martin Vorbach, Lingenfield (DE); 3,242.998 A 3, 1966 Gubbins 3,564,506 A 2f1971 Bee et al. Robert M. Minch, Zug (DE) 3,681,578 A 8, 1972 Stevens (21) Appl. No.: 12/909,061 (Continued) FOREIGN PATENT DOCUMENTS (22) Filed: Oct. 21, 2010 DE 4221. 278 1, 1994 Related U.S. Patent Documents DE 44 16881 11, 1994 Reissue of: (Continued) (64) Patent No.: 7,036,036 OTHER PUBLICATIONS Issued: Apr. 25, 2006 Li, Zhiyuan, et al., “Configuration prefetching techniques for partial Appl. No.: 10/379,403 reconfigurable coprocessor with relocation and defragmentation.” Filed: Mar. 4, 2003 International Symposium on Field Programmable Gate Arrays, Feb. U.S. Applications: 1, 2002, pp. 187-195. (60) Division of application No. 12/109,280, filed on Apr. 24, 2008, which is a continuation of application No. (Continued) 09/369,653, filed on Aug. 6, 1999, now Pat. No. 6,542, Primary Examiner — Paul Yanchus, III 998, which is a continuation-in-part of application No. (74) Attorney, Agent, or Firm — Bechen PLLC PCT/DE98/00334, filed on Feb. 7, 1998, and a contin uation-in-part of application No. 08/946,812, filed on (57) ABSTRACT Oct. 8, 1997, now Pat. No. 6,081,903. A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided.
    [Show full text]