th NASA Symp osium on VLSI Design

Reliable Interface Design for Combining

Asynchronous and Synchronous Circuits

Luli Josephson Erik L Brunvand Ganesh Gopalakrishan John F Hurdle

Computer Science Department

University of Utah

Salt LakeCity Utah

Email flulielbganeshhurdlegcsutahedu

Abstract In order to successfully integrate asynchronous and synchronous de

signs great care must b e taken at the interface b etween the twotyp es of systems

Synchronizing asynchronous inputs with a free running clo ck can cause well

known problems with metastability in the synchronization circuits Stretchable

clo cks allow a clo ck cycle to expand dynamically in resp onse to the metastability

eects of sampling asynchronous inputs We use an interface organization where

the sp ecial circuitry for detecting metastability and for stretching the clo ck that

is delivered to the synchronous part of the system is encapsulated in a Qop

based interface This provides a very convenient metho d for interfacing mixed

systems as the interface and clo ck generation circuitry are isolated into one sp e

cial mo dule and neither the asynchronous nor the synchronous system need b e

mo died internally to accommo date the interface This is esp ecially imp ortant

when standard synchronous comp onents are used as there is no opp ortunityto

mo dify these parts Weshow that this interface mo dule is suitable for most

mixed design needs and conclude with an example

Introduction

As VLSI technology improves hardware systems b ecome larger faster and more complex

Along with these improvements however come many problems directly asso ciated with

the sp eed and scale of the new systems Asynchronous and selftimed design techniques

are currently attracting renewed interest as a metho d for coping with some of the problems

asso ciated with the scale of mo dern systems These systems that do not rely on a global clo ck

to keep system comp onents synchronized have b een shown to exhibit a number of inherent

advantages more robust b ehavior in terms of pro cess and environmental variations a

capability for higher p erformance op eration decreased p ower consumption and inherently

higher reliability in high sp eed applications However for many applications designing

completely asynchronous circuits is currently an impractical approach Because of the large

b o dy of work related to synchronous system design and the manytoolsavailable for this

style of design mixed asynchronoussynchronous design is an imp ortant approach

One domain where this mixed design style may b e esp ecially appropriate is in embedded

systems and controllers These systems typically use a commo ditytype synchronous con

troller but resp ond to a variety of external inputs that are not synchronized to the system

clo ck Pro cessing the asynchronous input data as it arrives may b e b est accomplished using

a sp ecialized asynchronous circuit with overall system resp onse b eing co ordinated bythe

synchronous controller When these devices are used in remote lo cations there is a real need

for lowpower control circuits that are extremely robust under signicant temp erature and

power supply variation These types of systems present an inherent opp ortunity for highly

parallel control interaction that must op erate correctly and whose b ehavioral parameters are

well proven and understo o d due to the extreme remote nature of their op eration and the

resultant exp ense of repair

In order to successfully integrate asynchronous and synchronous designs great care must

be taken at the interface b etween the twotyp es of systems Synchronizing asynchronous

inputs with a free running clo ck can cause wellknown problems with metastability in the

synchronization circuits Toachieve this interfacing successfullywe implementaninter

faceclo ck generation mo dule based on Qops sp ecial ipops that signal when they have

exited metastability and stretchable clo cks Stretchable clo cks allowa clock cycle to expand

dynamically in resp onse to the metastability eects of sampling asynchronous inputs In our

scheme the sp ecial circuitry for detecting these events and for stretching the clo ckthatisde

livered to the synchronous part of the system is encapsulated in a Qopbased interface as

an extension of Rosenbergers QMo dule organization This provides a very convenient

metho d for interfacing mixed systems as the interface and clo ck generation is isolated into

one sp ecial mo dule and neither the async hronous nor the synchronous system need b e mo d

ied internally to accommo date the interface This is esp ecially imp ortant when standard

synchronous comp onents are used as there is no opp ortunity to mo dify these parts

In spite of the natural inertia from the mass of existing synchronous designs there is

currently a renaissance in asynchronous circuit design As one asp ect of our asynchronous

systems design work welookforways to exploit the rediscovered advantages of asynchronous

designs while capitalizing on the prep onderance of previously designed synchronous parts

One approachinvolves designing globally asynchronous lo cally synchronous systems here

after called mixed systems We use Qmo dulebased interfaceclock generation elements

as shown in Figure and describ ed in Section to safely co ordinate and synchronize inter

actions b etween the dierent regions in these mixed systems Unlike other valuereliable

synchronization circuits such as stretchable or stoppable clo ck metho ds Qmo dules inter

nally clo cked delay insensitive circuits conform naturally to the selftimed asynchronous

design style that we advocate in our asynchronous systems research

One goal for this work is to devise an interface scheme that will allow us to use previously

designed synchronous parts as is We consider this category of synchronous parts to

include otheshelf parts design library mo dules and mo dules synthesized from a b ehavioral

sp ecication by a highlevel synthesis system This allows us to fo cus our eorts on the to

us more interesting asynchronous design asp ects yet avail ourselves as necessary of existing

synchronous circuits

The asynchronous circuits we consider in this pap er are all built using twophase dela y

insensitive DI control circuits the individual control mo dules may b e sp eed indep endent

but exhibit delayinsensitiveinterfaces and bundled data paths

This pap er describ es our approach to building globally asynchronous selftimed systems

that incorp orate lo cally synchronous regions First we discuss mixedsystem design issues

then review typical synchronization approaches and list their limitations Next we present a Qmo dulebased interface implementation which combines synchronization and clo ck gen

th NASA Symp osium on VLSI Design

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Figure Qmo dule organization

eration and facilitates the mixedsystem design style we are advocating Wefollowthisby

an example using the interface in a mixed asynchronoussynchronous implementation for a

Finite Input Resp onse FIR lter Finallywedraw some conclusions ab out the metho d

and indicate future extensions to this work

Mixed Systems Combining Asynchronous and Syn

chronous Regions

As system sizes and circuit technology sp eeds increase it b ecomes more dicult to satisfy the

high frequency clo ck requirements of robust hazard and racefree clo ckschemes and small

skew global clo ck distribution Using autonomous lo cally clo cked andor asynchronous

subsystems can facilitate large system design As a corollary global communication require

ments are reduced since most communications can b e lo calized However communications

among synchronous systems not sharing a common clo ckmust b e synchronized

Synchronization Issues in Mixed Systems

In synchronous systems whenever ipop timing constraints such as minimum pulse width

setup or hold times are not met there is a nite probability that instead of resolving to a

state matching the input value the ipop will enter a metastable state This metastable

state mayeventually resolve to the correct output state or it may resolve to an incorrect

output state If it takes longer than one clo ck p erio d for the metastability to resolve and

the synchronous system is allowed to pro ceed the metastable output maybeinterpreted as

aby part of the system and by the rest We refer to this eect as value failure

Metastability o ccurrence is probabalistic and exp onentially related to the synchronous

clo ck rate and the asynchronous data rate the mean time b etween failure is shorter at

high asynchronous data rates and high fast synchronizing clo ck frequencies Converselythe

longer one waits b efore using the sampled data the lower the probabilityofsynchronizer

failure Conventional techniques for decreasing the probability of metastable failure

include using fast devices allowing for extended settling times and employing masking and

redundancy These techniques all amounttoallowing a long but b ounded amount of time

for metastability to resolve accepting the nite probability that failures will o ccur Thus

these metho ds trade the advantage of timecertainty for the p ossibilityofvalue failure

Conventional Interface Techniques

Because of its probabilistic nature metastabilityishardtocharacterize detect and repro

duce As circuit technologies improve and circuit sp eeds increase handling metastability

issues b ecomes more imp ortant Although the consequences of ignoring its eects are p o

tentially catastrophic it is still considered a very dicult problem to treat correctly in the

design of interface circuits Evidence for this is the number of interface sp ecication systems

that completely disregard this issue For example a range of interface sp ecication metho ds

are b eing developed in conjunction with several highlevel synthesis systems The implemen

tations synthesized from these descriptions either include conventional synchronizers on the

asynchronous inputs or only handle signals related to the same clo ckinternally

or externally For highsp eed valuecritical system interfaces these metho ds

cannot guarantee the required combination of valuereliability plus sp eed

Reliable Value Synchronization Metho ds

Alternatively less conventional metho ds using stoppable or stretchable clo cks trade a degree

of timeuncertainty for valuereliability Stoppable clo cks can b e used

for interfacing asynchronoussynchronous circuits communicating via sp ecic proto cols and

when the synchronous system do es not require a continuously running clo ck The lo cally

generated clo ck is stopp ed synchronously and the system passively awaits the next asyn

chronous input The clo ck is then restarted asynchronously by the asynchronous input with

known value but unknown arrival time For circuits that op erate using this restricted inter

face mo del this scheme avoids metastability b ecause it avoids sampling a changing signal

However stoppable clo ck circuits require careful delay analysis in their design to ensure

correct circuit op eration Often redesign of the synchronous part itself is required as

well Thus stoppableclo ck based interface schemes are applicable only in certain restricted

cases

Stretchable clo ck circuits can b e used in the more general case when neither the value

nor the arrival time of the incoming asynchronous signal is known in advance In stretchable

clo ck circuits a comparatorbased metastability detector is used to delay

the next clo ck edge when a p otentially changing input is sampled Again critical timing

conditions must b e met in the design and op eration

th NASA Symp osium on VLSI Design

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Figure QMo dulebased interface

QMo duleBased Interfaces

The goal is to build valuesafe interfaces for combining synchronous and asynchronous de

signs The main diculty with the stoppablestretchable clo ck based approaches is that

they require sp ecialized and somewhat hardtobuild circuits Yet interfaces based on these

metho ds would facilitate the decoupled mixeddesign style we are advocating allowing us

to incorp orate synchronous parts into an asynchronous design without redesign of the syn

chronous parts Because they are the more general of the twoschemes we fo cus primarily

on stretchable clo cktechniques for our interfaces

We implement a stretchable clo ckinterface where the metastabillty detection circuitry

is encapsulated in a sp ecial mo dule called a Qmo dule shown in Figure and describ ed

in Rosenberger et al Qmo dules are internally clo cked delayinsensitive state ma

chines Data inputs are sampled on one clo ckevent using Qops these sp ecial ipops use

comparatorbased circuits to acknowledge when metastability has resolved and values are

stable The acknowledgements from the Qops and the state registers are used to generate

the next clo ckevent

We extend the Qmo dule organization by altering the Clo ck Generation element to pro

vide the appropriate clo ck signal to the synchronous side of the interface Note that in the

normal case the p erio d of this exp orted clo ck signal is regular and set bythedelay through

the clo ck generator element with any additional delay needed to mo del the combinational

delay time or to achieve a particular minim um clo ck frequency If the internal Qops

stall waiting to resolve metastability due to asynchronous inputs the clo ck signal will b e

stretched automatically until the data resolve

In contrast to conventional stretchable clo ck implementations b ecause Qops acknowl

edge when they are ready to accept new inputs as well as acknowledging when the storage

op eration is completed the clo ck generation utilizes a delayinsensitive proto col Clo ck

generation and distribution are also simpler delay through the combinational logic imple

menting the state function provides the single delay constraint that must b e satised in

the clo ck generation and distribution for the Qmo dule itself For our interfaces we use

Qmo dules b oth to synchronize the asynchronous inputs and to act as clo ck generators The

internal twophase single wire clo ck used for internal sequencing is exp orted to form the

synchronous part clo ck input as is shown in Figure Thus wehave to adjust the single

delay constraintintheClock Generation element to provide the minimum clo ck frequency

required by the synchronous part

The goal for this work is to demonstrate an interfacing metho d to allowvaluereliable

synchronization b etween selftimed asynchronous and conventional synchronous systems

In contrast to the stretchable and stoppable clo ck metho ds discussed ab ove Qmo dules

provide the safety generality and simplicity required of an easily designed interface Our

Qmo dule interfaceclock generation circuits avoid synchronization failure by ensuring that

storage elements have resolved b efore using the stored values by dynamically adjusting the

additional delay

Contrast this with the xed time delay that is normally introduced for synchronization

in conventional clo cked circuits for example by including extra latching stages or dividing

down the clo ck for sampling latches In the Qmo dulebased interface valuesafety is assured

at the exp ense of an o ccasional stretching in the clo ck p erio d In conventional clo cked

circuits the clo ckperiodmust always b e long enough to allow sucient time for metastability

to resolve with as high a probability as p ossible Yet b ecause the resolution time is xed

and b ounded in conventional techniques there is always a nite probabilityofvalue failure

and subsequent circuit failure

An Example MixedSystem Design

Nowwe discuss a relatively small example a mixed asynchronoussynchronous circuit im

plementation for an FIR lter This circuit incorp orates a Qmo dulebased interface for

valuesafe synchronization and clo ck generation This circuit contains all the typical ele

ments of a larger mixedsystem design but is simple enough to allow us to fo cus on the

imp ortantinterface details For example synchronous arithmetic parts are inexp ensive

generally compact and readily available Their use can b e very cost eective in a circuit

which is otherwise asynchronous The FIR lter circuit b elow is designed to op erate in an

asynchronous environment and so it must present an asynchronous interface to the external

world However in addition to the asynchronous data buering parts it uses synchronous

computation parts internally and so requires synchronization at that internal interface The

asynchronous control structure will allow the datadep endent pro cessing time of the required

arithmetic calculations to enhance the averagecase p erformance of the lter

The circuit describ ed represents a class of circuits where mixed design is appropriate

For example embedded control using standard synchronous controllers resp onding to asyn

chronous events are an excellent target for the synchronization strategy we describ e here

Circuit Description

We implement a universal FIR lter for asynchronous inputs This is a sixth order lter

with input and output done in parallel The symmetric co ecient algorithm is used which

reduces the number of multiplications bya halfover the standard lter For the bit input

vector x and for three bit co ecientvectors k k k the bit output vector y is

n a b c n

computed as

y nk ࣿ x x k ࣿ x x k ࣿ x x

a n n b n n c n n

th NASA Symp osium on VLSI Design

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Figure Toplevel diagram for mixed asynchronoussynchronous FIR implementation

The FIR lter circuit as shown in Figure consists of an asynchronous datafetching unit

Asynch and a synchronous computation unit Synch A Qmo dulebased interface part

AsynchtoSynch Interface between the asynchronous mo dule and the synchronous

mo dule links the control of b oth parts synchronizes the data and generates the clo ck for the

synchronous part The external interface is selftimed using twophase transition signaling

and databundling The environment issues a Req when the next input data value is ready

The FIR returns an Ack when the FIR computation completes and a new output value is

available The asynchronous selftimed interface constrains event sequencing rather than

event timing The environment can supply data and use results at any rate as long as the

sequence of sendReq receiveAckisobeyed

The datafetching part Asynch is an asynchronous shift register with data taps im

plemented as a Sutherland micropip elinedbased FIFO It uses twophase selftimed

control with databundling

The Qmo dulebased interface part AsynchtoSynch Interface Figure provides

synchronized asynchronous data and the clo ckforuseby the synchronous computation unit

A Qop is used to detect metastabilitywhenlatching the b egin next computation control

signal REQIN is received from the asynchronous part The clo ck generation circuit waits

for metastability to resolve b efore initiating the next clo ck pulse and latching the outputs

The clo ck is exp orted to the synchronous part and is continuously running While the

maximum p erio d mayvary the minimum clo ck p erio d to match the synchronous part delay

is guaranteed bythedelayintheclock generation circuit

Since the asynchronous interface communicates via a twophase proto col and the syn

chronous interface ob eys a fourphase proto col the interface circuit includes a to phase

proto col converter part This asynchronous converter circuit takes the place of the combi

national logic implementing the state function in a regular Qmo dule For this very simple

interface no additional logic or stateholding Qops are required This is not usually the

case Weareworking on more complicated examples where state information and feedback within the Qmo dule are required

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Figure AsynchtoSynchInterface Implementation

The synchronous computation unit Synch consists of ve adders and three synchronous

multipliers The multipliers have datadep endent completion times so the numb er of cycles

for each FIR computation will vary Output data are latched and so remain valid until

the next FIR computation starts For historical reasons this mo dule ob eys a fourphase

synchronous selftimed proto col

Implementation Details

A prototyp e version of the mixed asynchronoussynchronous FIR lter has b een designed

for implementation in Actel FPGAs It was built and functionally simulated using the

asynchronous macro cells describ ed in and the synchronous parts provided as Actel Macro

Library soft macros and contains logic mo dules

Qops used in the interface are not available as standard digital parts Although Qops

cannot b e built using FPGAs b ecause it is not p ossible to implement the required analog

comparator circuit wehave designed circuits that mimic the b ehavior of a Qop using Actel

FPGAs These FPGA circuits use a xed delay to resolve metastability and so are

not valuesafe but they allow us to prototype designs quickly that can then b e upgraded to

use custom Qops as required

Wehave built and tested actual Qops in a varietyoftechnologies including CMOS

and Gallium Arsenide The next step is to implement the asynchronous parts of this

interface design in another technology where the actual analog metastability resolver parts

can b e used

Results and Future Work

Qops are found in several circuit libraries Combining Qops with

control logic to form delayinsensitive state machine mo dules Qmo dules has b een ex

tensively describ ed by Rosenb erger et al in Sutherland and Sproull suggest such

an asynchronous state machine built using Qops as an asynchronous replacementfora

conventional registerbased synchronizer plus synchronous state machine in a three p ort

memory controller in In this pap er weintro duce a Qmo dulebased interface circuit

for valuesafe synchronization and clo ck generation We demonstrate its use in a mixed

asynchronoussynchronous FIR circuit implementation

th NASA Symp osium on VLSI Design

In general these interface mo dules can b e used in mixed systems whenever synchroniza

tion and clo ck generation are required and the synchronous element can tolerate some o cca

sional clo ck elongation Valuesafety is assured Chapiro has done studies that indicate

clo ck sp eeds can actually b e increased now that synchronization delay can b e dynamically

adapting In contrast to other recentwork no redesign of the synchronous part is re

quired to accommo date it in the globally asynchronous selftimed environment This makes

the metho d esp ecially suitable for correctly including previously designed synchronous parts

in mixed systems

There are many kinds of mixed systems where these interfaces can b e used This pap er

describ es one example circuit containing asynchronous and synchronous regions that need

to synchronize Traver describ es a metho d for interfacing multiple lo callysynchronous

but mutuallyasynchronous circuits Synchronization problems arise in embedded controllers

using synchronous circuits but resp onding to asynchronous events These types of systems

are often installed in remote lo cations and must b e robust under a varietyofenvironmental

conditions that tend to make synchronization problems worse Our technique could b e used

in b oth of these applications

The FIR is a small mixedsystem demonstration circuit As asynchronous systems evolve

in size such an approach will b ecome a necessityuntil suitable asynchronous computation

comp onents are commonly available One systemsize example weareworking on in our

lab is interfacing a synchronous otheshelf math copro cessor chip to a fully selftimed

asynchronous micropro cessor Yet another example involves connecting synchronous

analogtodigital input con verters and digitaltoanalog output converters to an asynchronous

neural net classier system also b eing constructed in our lab The issues involved in

successfully combining more than two systems using these interfaces are b eing explored as

describ ed in

For a variety of reasons including limitations in current asynchronous design to ols de

signing completely asynchronous circuits maynotalways b e practical or desirable With

the addition of the interface metho d describ ed here the selftimed circuit design style we

advo cate allows us to design and implement globally asynchronous designs that incorp o

rate correctly synchronized lo cally synchronous regions Mixed systems retain manyofthe

highlevel advantages of asynchronous designs while exploiting existing synchronous designs

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