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Reliable Interface Design for Combining Asynchronous And th NASA Symp osium on VLSI Design Reliable Interface Design for Combining Asynchronous and Synchronous Circuits Luli Josephson Erik L Brunvand Ganesh Gopalakrishan John F Hurdle Computer Science Department University of Utah Salt LakeCity Utah Email flulielbganeshhurdlegcsutahedu Abstract In order to successfully integrate asynchronous and synchronous de signs great care must b e taken at the interface b etween the twotyp es of systems Synchronizing asynchronous inputs with a free running clo ck can cause well known problems with metastability in the synchronization circuits Stretchable clo cks allow a clo ck cycle to expand dynamically in resp onse to the metastability eects of sampling asynchronous inputs We use an interface organization where the sp ecial circuitry for detecting metastability and for stretching the clo ck that is delivered to the synchronous part of the system is encapsulated in a Qop based interface This provides a very convenient metho d for interfacing mixed systems as the interface and clo ck generation circuitry are isolated into one sp e cial mo dule and neither the asynchronous nor the synchronous system need b e mo died internally to accommo date the interface This is esp ecially imp ortant when standard synchronous comp onents are used as there is no opp ortunityto mo dify these parts Weshow that this interface mo dule is suitable for most mixed design needs and conclude with an example Introduction As VLSI technology improves hardware systems b ecome larger faster and more complex Along with these improvements however come many problems directly asso ciated with the sp eed and scale of the new systems Asynchronous and selftimed design techniques are currently attracting renewed interest as a metho d for coping with some of the problems asso ciated with the scale of mo dern systems These systems that do not rely on a global clo ck to keep system comp onents synchronized have b een shown to exhibit a number of inherent advantages more robust b ehavior in terms of pro cess and environmental variations a capability for higher p erformance op eration decreased p ower consumption and inherently higher reliability in high sp eed applications However for many applications designing completely asynchronous circuits is currently an impractical approach Because of the large b o dy of work related to synchronous system design and the manytoolsavailable for this style of design mixed asynchronoussynchronous design is an imp ortant approach One domain where this mixed design style may b e esp ecially appropriate is in embedded systems and controllers These systems typically use a commo ditytype synchronous con troller but resp ond to a variety of external inputs that are not synchronized to the system clo ck Pro cessing the asynchronous input data as it arrives may b e b est accomplished using a sp ecialized asynchronous circuit with overall system resp onse b eing co ordinated bythe synchronous controller When these devices are used in remote lo cations there is a real need for lowpower control circuits that are extremely robust under signicant temp erature and power supply variation These types of systems present an inherent opp ortunity for highly parallel control interaction that must op erate correctly and whose b ehavioral parameters are well proven and understo o d due to the extreme remote nature of their op eration and the resultant exp ense of repair In order to successfully integrate asynchronous and synchronous designs great care must be taken at the interface b etween the twotyp es of systems Synchronizing asynchronous inputs with a free running clo ck can cause wellknown problems with metastability in the synchronization circuits Toachieve this interfacing successfullywe implementaninter faceclo ck generation mo dule based on Qops sp ecial ipops that signal when they have exited metastability and stretchable clo cks Stretchable clo cks allowa clock cycle to expand dynamically in resp onse to the metastability eects of sampling asynchronous inputs In our scheme the sp ecial circuitry for detecting these events and for stretching the clo ckthatisde livered to the synchronous part of the system is encapsulated in a Qopbased interface as an extension of Rosenbergers QMo dule organization This provides a very convenient metho d for interfacing mixed systems as the interface and clo ck generation is isolated into one sp ecial mo dule and neither the async hronous nor the synchronous system need b e mo d ied internally to accommo date the interface This is esp ecially imp ortant when standard synchronous comp onents are used as there is no opp ortunity to mo dify these parts In spite of the natural inertia from the mass of existing synchronous designs there is currently a renaissance in asynchronous circuit design As one asp ect of our asynchronous systems design work welookforways to exploit the rediscovered advantages of asynchronous designs while capitalizing on the prep onderance of previously designed synchronous parts One approachinvolves designing globally asynchronous lo cally synchronous systems here after called mixed systems We use Qmo dulebased interfaceclock generation elements as shown in Figure and describ ed in Section to safely co ordinate and synchronize inter actions b etween the dierent regions in these mixed systems Unlike other valuereliable synchronization circuits such as stretchable or stoppable clo ck metho ds Qmo dules inter nally clo cked delay insensitive circuits conform naturally to the selftimed asynchronous design style that we advocate in our asynchronous systems research One goal for this work is to devise an interface scheme that will allow us to use previously designed synchronous parts as is We consider this category of synchronous parts to include otheshelf parts design library mo dules and mo dules synthesized from a b ehavioral sp ecication by a highlevel synthesis system This allows us to fo cus our eorts on the to us more interesting asynchronous design asp ects yet avail ourselves as necessary of existing synchronous circuits The asynchronous circuits we consider in this pap er are all built using twophase dela y insensitive DI control circuits the individual control mo dules may b e sp eed indep endent but exhibit delayinsensitiveinterfaces and bundled data paths This pap er describ es our approach to building globally asynchronous selftimed systems that incorp orate lo cally synchronous regions First we discuss mixedsystem design issues then review typical synchronization approaches and list their limitations Next we present a Qmo dulebased interface implementation which combines synchronization and clo ck gen th NASA Symp osium on VLSI Design ◆ ✁✂ ❙✂✄✂ ❙✂✄✂ ❉ ◗ ❈✏✑✒✓✏✔ ★ ✚✒ ✒ ❘ ▲ ✕ ✔✏ ❈ ▲ ✓❘ ✳ ✣✤✥ ✳ ✳ ❙ ✟☎✠✡ ☛☞☎ ✌✍ ✎ ✂ ✂ ❖✝ ✆✝ ✞ ✳ ✳ ✳ ❉ ◗ ✧✢ ❆✞ ✟☎✠✡ ☛☞☎☞ ✝✞ ❋✔✏✦ ✖ ❙ ✟☎✠✡ ☛☞☎✌ ✍ ✎ ✣✤✥ ✩✪ ✫ ✂ ■☎ ✆✝ ✞ ✖ ✂ ■☎✆ ✝ ✞ ✿ ✖ ✿ ❉ ◗ ✧✢ ❋✔✏✦ ✘ ❆✠ ✓❘✑✛❘✜✢ ❈ ✔✏❈✗ ✘ ✬✭☞✠ ✣✤✥ ✩✪ ✫ ❱✏✙ ✚ ▲ ❘✑ Figure Qmo dule organization eration and facilitates the mixedsystem design style we are advocating Wefollowthisby an example using the interface in a mixed asynchronoussynchronous implementation for a Finite Input Resp onse FIR lter Finallywedraw some conclusions ab out the metho d and indicate future extensions to this work Mixed Systems Combining Asynchronous and Syn chronous Regions As system sizes and circuit technology sp eeds increase it b ecomes more dicult to satisfy the high frequency clo ck requirements of robust hazard and racefree clo ckschemes and small skew global clo ck distribution Using autonomous lo cally clo cked andor asynchronous subsystems can facilitate large system design As a corollary global communication require ments are reduced since most communications can b e lo calized However communications among synchronous systems not sharing a common clo ckmust b e synchronized Synchronization Issues in Mixed Systems In synchronous systems whenever ipop timing constraints such as minimum pulse width setup or hold times are not met there is a nite probability that instead of resolving to a state matching the input value the ipop will enter a metastable state This metastable state mayeventually resolve to the correct output state or it may resolve to an incorrect output state If it takes longer than one clo ck p erio d for the metastability to resolve and the synchronous system is allowed to pro ceed the metastable output maybeinterpreted as aby part of the system and by the rest We refer to this eect as value failure Metastability o ccurrence is probabalistic and exp onentially related to the synchronous clo ck rate and the asynchronous data rate the mean time b etween failure is shorter at high asynchronous data rates and high fast synchronizing clo ck frequencies Converselythe longer one waits b efore using the sampled data the lower the probabilityofsynchronizer failure Conventional techniques for decreasing the probability of metastable failure include using fast devices allowing for extended settling times and employing masking and redundancy These techniques all amounttoallowing a long but b ounded amount of time for metastability to resolve accepting the nite probability that failures will o ccur Thus these metho ds trade the advantage of timecertainty for the p ossibilityofvalue failure Conventional Interface Techniques Because of its probabilistic nature metastabilityishardtocharacterize detect and repro duce As circuit technologies improve and circuit sp eeds increase handling metastability issues b ecomes more imp ortant Although
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