Lecture Overview

Microprocessors & Interfacing • AVR ISA • AVR Instructions & Programming (I) – Basic construct implementation AVR ISA & AVR Programming (I)

Lecturer : Dr. Annie Guo

S2, 2008 COMP9032 Week2 1 S2, 2008 COMP9032 Week2 2

Atmel AVR AVR Registers

• 8-bit RISC architecture • General purpose registers – Most instructions have 16-bit fixed length – 32 8-bit registers, R0 ~ R31 or r0 ~ r31 – Most instructions take 1 clock cycle to execute. – Can be further divided into two groups • Load-store memory access architecture • First half group: R0 ~ R15 and second half group: R16 ~ R31 – All calculations are on registers • Some instructions work only on the second half group • Internal program memory and data memory R16~R31 – Due to the limitation of instruction encoding bits • Wide variety of on-chip peripherals (digital » Will be covered later I/O, ADC, EEPROM, UART, pulse width – E.g. ldi rd, #number ;rd ∈ R16~R31 modulator (PWM), …).

S2, 2008 COMP9032 Week2 3 S2, 2008 COMP9032 Week2 4 AVR Registers (cont.) AVR Registers (cont.)

• General purpose registers • I/O registers – The following register pairs can work as address – 64 8-bit registers indexes • Their names are defined in the m64def.inc file • X, R27:R26 – Used in input/output instructions • Y, R29:R28 • Mainly storing data/addresses and control signal bits • Z, R31:R30 – Some instructions work only with I/O registers, others with general purpose registers – don’t – The following registers can be applied for specific confuse them use • E.g. in rd, port ; port must be an I/O register • R1:R0 store the result of multiplication instruction – Will be covered in detail later • R0 stores the data loaded from the program memory • Status register (SREG) – A special I/O register

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The Status Register in AVR The Status Register in AVR (cont.)

• The Status Register (SREG) contains information about the result of the most recently executed I T H S V N Z C arithmetic instruction. This information can be used for altering program flow in order to perform Bit 7 6 5 4 3 2 1 0 conditional operations. • SREG is updated after any of ALU operations by • Bit 7 – I: Global Enable hardware. – Used to enable and disable . • SREG is not automatically stored when entering an interrupt routine and restored when returning from an – 1: enabled. 0: disabled. interrupt. This must be handled by software. – The I-bit is cleared by hardware after an interrupt – Using in/out instruction to store/restore SREG has occurred, and is set by the RETI instruction to enable subsequent interrupts.

S2, 2008 COMP9032 Week2 7 S2, 2008 COMP9032 Week2 8 The Status Register in AVR (cont.) The Status Register in AVR (cont.)

I T H S V N Z C I T H S V N Z C Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0

• Bit 6 – T: Bit Copy Storage – The Bit Copy instructions BLD (Bit LoaD) and BST • Bit 5 – H: Half (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the – The Half Carry Flag H indicates a Half Carry can be copied into T by the BST (carry from bit 4) in some arithmetic operations. instruction, and a bit in T can be copied into a bit – Half Carry is useful in BCD arithmetic. in a register in the Register File by the BLD instruction.

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The Status Register in AVR (cont.) The Status Register in AVR (cont.)

I T H S V N Z C I T H S V N Z C Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0

• Bit 4 – S: Sign Bit – Exclusive OR between the Negative Flag N and • Bit 2 – N: Negative Flag the Two’s Complement V ( S = N – N is the most significant bit of the result. ⊕V). • Bit 1 – Z: • Bit 3 – V: Two’s Complement Overflow Flag – Z indicates a zero result in an arithmetic or logic – The Two’s Complement Overflow Flag V supports operation. 1: zero. 0: Non-zero. two’s complement arithmetic.

S2, 2008 COMP9032 Week2 11 S2, 2008 COMP9032 Week2 12 The Status Register in AVR (cont.) AVR Address Spaces

• Three address spaces I T H S V N Z C – Data memory • Storing data to be processed Bit 7 6 5 4 3 2 1 0 – Program memory • Storing program code and some constants • Bit 0 – C: Carry Flag – EEPROM memory – Its meaning depends on the operation. • Large permanent data storage • For addition X+Y, it is the carry from the most significant bit • For subtraction x-y, where x and y are unsigned integers, it indicates whether x

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Data Memory Space Program Memory Space

Data Memory • Covers • Covers Program Memory – Register file 32 General purpose 0x0000 – 16 bit Flash Memory Working Registers 0x0000 • I.e. registers in the register • Read only file also have memory 0x1F address 0x20 – Instructions are Program Flash Memory 64 Input/Output retained when power (1K bytes~128K bytes) – I/O registers Registers off • I.e. I/O registers have two 0x5F 0x60 – Can be accessed with versions of addresses Internal SRAM 16 Bits – I/O addresses (128~4K bytes) special instructions – Memory addresses • LPM – SRAM data memory External SRAM • SPM • The highest memory End Address location is defined as 8 bits RAMEND End Address

S2, 2008 COMP9032 Week2 15 S2, 2008 COMP9032 Week2 16 EEPROM Memory Space AVR Instruction Format

• Covers • For AVR, almost all instructions are 16 bits

– 8-bit EEPROM Data EEPROM Memory long memory 0x0000 – For example, • Use to permanently store large set of data • add Rd, Rr • sub Rd, Rr – Can be accessed EEPROM Memory using load and store (64~4K bytes) • mul Rd, Rr instructions with • brge k special control bit 8 bits • Few instructions are 32 bits long settings – For example • Not covered in this ≤ ≤ course • lds Rd, k ( 0 k 65535 ) End address – loads 1 byte from the SRAM to a register.

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Examples (1) Examples (2) - 16 bits long - 32 bit long • Clear register instruction • Unconditional branch Syntax: clr Rd Syntax: jmp k Operand: 0 ≤ d ≤ 31 Operand: 0 ≤ k < 4M Operation: Rd ← 0 Operation: PC ← K • Instruction format • Instruction format 0 0 1 0 0 1 d dd d d d d d d d 15 0 1 0 0 1 0 1 0 kk k k k 1 1 0 k 15 0 – OpCode uses 6 bits (bit 10 to bit 15). – The operand uses the remaining 10 bits (only 5 bits, bit 0 to k k k k k k k kk k k k k k k k bit 4, are actually needed). 31 16 • Execution time • Execution time 3 clock cycles 1 clock cycle

S2, 2008 COMP9032 Week2 19 S2, 2008 COMP9032 Week2 20 Examples (3) AVR Instructions - with variable cycles • Conditional branch • AVR has the following classes of instructions: Syntax: breq k – Arithmetic and Logic Operand: -64 ≤ k < +63 – Data transfer Operation: If Rd=Rr(Z=1) then PC ← PC+k+1, else – Program control PC PC+1 – Bit and Others • Instruction format • Bit and Bit test 1 1 1 1 0 0 k kk k k k k 0 0 1 • MCU Control • An overview of the instructions are given in • Execution time the next slides. 1 clock cycle if condition is false 2 clock cycles if condition is true

S2, 2008 COMP9032 Week2 21 S2, 2008 COMP9032 Week2 22

AL Instructions Transfer Instructions

• Arithmetic • Logic • GP register • Memory – addition • E.g. AND Rd, Rr • E.g. MOV Rd, Rr – Data memory • E.g. ADD Rd, Rr • Shift • I/O registers • E.g. LD Rd, X ST X, Rr – Program memory – Subtraction • E.g. LSL Rd • E.g. IN Rd, PORTA • E.g. SUB Rd, Rr OUT PORTB, Rr • E.g. LPM – EEPROM memory – Increment/decrement • Stack • Not covered in this course • E.g INC Rd • PUSH Rr – Multiplication • POP Rd • E.g. MUL Rd, Rr • Immediate values • E.g. LDI Rd, K8

S2, 2008 COMP9032 Week2 23 S2, 2008 COMP9032 Week2 24 Program Control Instructions Bit & Other Instructions

• Branch • Call subroutine • Bit • Others – Conditional • E.g. RCALL k – Set bit • NOP • Jump to address • Return from subroutine • E.g. SBI PORTA, b • BREAK – BREQ des • SLEEP • E.g. RET – Clear bit » test ALU flag and jump • WDR to specified address if • E.g CBI PORTA, b the test was true • skip – Bit copy – SBIC k • E.g. BST Rd, b » test a bit in a register or an IO register and skip the next instruction if the test was true. – Unconditional • Jump to the specified address – RJMP des

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AVR Instructions (cont.) AVR Addressing Modes

• Not all instructions are implemented in all • Immediate AVR controllers. • Register direct • Refer to the data sheet of a specific • Memory related – Data memory • Direct • Refer to online AVR instruction document for • Indirect the detail description of each instruction • Indirect with Displacement • Indirect with Pre-decrement • Indirect with Post-increment – Program memory – EPROM memory • Not covered in this course

S2, 2008 COMP9032 Week2 27 S2, 2008 COMP9032 Week2 28 Immediate Addressing Register Direct Addressing

• The operands come from the instructions • The operands come from general purpose • For example registers • For example andi r16, $0F and r16, r0 – Bitwise logic AND operation • Clear upper nibble of register r16 – r16 r16 AND r0 • Clear upper nibble of register r16 if r0=0x0F

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Register Direct Addressing

• The operands come from I/O registers • For example

in r25, PINA Data Memory Addressing -- r25 PIN A

S2, 2008 COMP9032 Week2 31 S2, 2008 COMP9032 Week2 32 Data Direct Addressing Indirect Addressing

• The data memory address is given directly • The address of memory data is from an from the instruction address pointer (X, Y, Z) • For example • For example

lds r5, $F123 ld r11, X -- r5 Mem($F123), or r5 ($F123) -- r11 Mem(X), or r11 (X)

S2, 2008 COMP9032 Week2 33 S2, 2008 COMP9032 Week2 34

Indirect Addressing with Indirect Addressing with Pre- Displacement decrement • The address of memory data is from (Y,Z)+q • The address of memory data is from an address pointer (X, Y, Z) and the value of the pointer is auto- • For example decreased before each memory access. • For example std Y+10 , r14 std -Y, r14 -- (Y+10) r14 -- Y Y-1, (Y) r14

S2, 2008 COMP9032 Week2 35 S2, 2008 COMP9032 Week2 36 Indirect Addressing with Post- increment • The address of memory data is from an address pointer (X, Y, Z) and the value of the pointer is auto- increased after each memory access. • For example std Y+ , r14 Program Memory Addressing -- (Y) r14, Y Y+1

S2, 2008 COMP9032 Week2 37 S2, 2008 COMP9032 Week2 38

Direct Program Addressing Relative Program Addressing

• The instruction address is from instruction • The instruction address is PC+k+1 • For example • For example rjmp k -- (PC) (PC)+k+1 jmp k -- (PC) k

S2, 2008 COMP9032 Week2 39 S2, 2008 COMP9032 Week2 40 Program Memory Constant Indirect Memory Addressing Addressing • The instruction address is implicitly stored in • The address of the constant is stored in Z Z register register

icall – The address is a byte address. -- PC(15:0) (Z), PC(21:16) 0 • For example: lpm -- r0 (Z)

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Program Memory Addressing with AVR Programming Post-increment • For example • Refer to the online AVR Instruction Set documentation for the complete list of AVR

lpm r16, Z+ instructions -- r16 (Z), Z Z+1 – http://www.cse.unsw.edu.au/~cs9032/refs/AVR- Instruction-Set.pdf • The rest of the lecture covers – Programming to implement some basic constructs with examples

S2, 2008 COMP9032 Week2 43 S2, 2008 COMP9032 Week2 44 Arithmetic Calculation (1/4) What instructions do you need? - example • Expressions • sub z === 2x −−− xy −−− x2 • mul • ldi – where all data including products from multiplications are 8-bit unsigned numbers; and x, • mov y, z are stored in registers r2, r3, and r4, respectively.

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Subtract without Carry Multiply Unsigned

• Syntax: sub Rd, Rr • Syntax: mul Rd, Rr • Operands: Rd, Rr ∈{r0, r1, …, r31} • Operands: Rd, Rr ∈{r0, r1, …, r31} • Operation: Rd ←Rd–Rr • Operation: r1:r0 ←Rr*Rd • Flags affected: H, S, V, N, Z, C – (unsigned ←unsigned * unsigned ) • Words: 1 • Flags affected: Z, C • Cycles: 1 – C is set if bit 15 of the result is set; cleared otherwise. • Words: 1 • Cycles: 2

S2, 2008 COMP9032 Week2 47 S2, 2008 COMP9032 Week2 48 Load Immediate Copy Register

• Syntax: ldi Rd, k • Syntax: mov Rd, Rr • Operands: Rd ∈{r16, …, r31 }, 0 ≤ k ≤ • Operands: Rd, Rr ∈{r0,r1,…,r31} 255 • Operation: Rd ←Rr • Operation: Rd ←k • Flag affected: None • Flag affected: None • Words: 1 • Words: 1 • Cycles: 1 • Cycles: 1 • Encoding: 1110 kkkk dddd kkkk • Example: ldi r16, $42 ; Load $42 to r16

S2, 2008 COMP9032 Week2 49 S2, 2008 COMP9032 Week2 50

Arithmetic Calculation (2/4) Arithmetic Calculation (3/4)

• AVR code for z === 2x −−− xy −−− x2 • Expressions – where all data including products from multiplications are 8- z === 2x −−− xy −−− x2 bit unsigned numbers; and x, y, z are stored in registers r2, r3, and r4, respectively. z === x(2 −−− (x +++ y)) – where all data including products from ldi r16, 2 ; r16 2 multiplications are 8-bit unsigned numbers; and x, mul r16, r2 ; r1:r0 2x y, z are stored in registers r2, r3, and r4, mov r5, r0 ; r5 2x respectively. mul r2, r3 ; r1:r0 xy sub r5, r0 ; r5 < 2x-xy mul r2, r2 ; r1:r0 x2 sub r5, r0 ; r5 2x-xy- x2 mov r4, r5 ; r4 z

– 8 instructions and 11 cycles S2, 2008 COMP9032 Week2 51 S2, 2008 COMP9032 Week2 52 What instructions do you need? Add without Carry

• sub • Syntax: add Rd, Rr • mul • Operands: Rd, Rr ∈{r0, r1, …, r31} • ldi • Operation: Rd ←Rd + Rr • mov • Flags affected: H, S, V, N, Z, C • add • Words: 1 • Cycles: 1

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Control Structure (1/2) Arithmetic Calculation (4/4) - example • AVR code for z === 2x −−− xy −−− x2 • IF-THEN-ELSE control structure z === x(2 −−− (x +++ y)) if(x<0) – where all data including products from multiplications are 8- z=1; bit unsigned numbers; and x, y, z are stored in registers r2, else r3, and r4, respectively. z=-1; mov r5, r2 ; r5 x – Numbers x, z are 8-bit signed integers and stored in add r5, r3 ; r5 x+y registers. You need to decide which registers to use. ldi r16, 2 ; r16 2 sub r16, r5 ; r16 < 2-(x+y) • Instructions interested mul r2, r16 ; r1:r0 x(2-(x+y)) – Compare mov r4, r0 ; r4 z – Conditional branch – Unconditional jump – 6 instructions and 7 cycles

S2, 2008 COMP9032 Week2 55 S2, 2008 COMP9032 Week2 56 Compare Compare with Immediate

• Syntax: cp Rd, Rr • Syntax: cpi Rd, k • Operands: Rd ∈{r0, r1, …, r31} • Operands: Rd ∈{r16, r17, …, r31} and 0 ≤ • Operation: Rd–Rr (Rd is not changed) k ≤ 255 • Flags affected: H, S, V, N, Z, C • Operation: Rd – k (Rd is not changed) • Words: 1 • Flags affected: H, S, V, N, Z, C • Cycles: 1 • Example: • Words: 1 cp r4, r5 ; Compare r4 with r5 • Cycles: 1 brne noteq ; Branch if r4 ≠ r5 ... noteq: nop ; Branch destination (do nothing)

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Conditional Branch Relative Jump

• Syntax: brge k • Syntax: rjmp k • Operands: -64 ≤ k < 64 • Operands: -2K ≤ k < 2K • Operation: If Rd ≥Rr (N ⊕V=0) then PC ←PC+k+1, • Operation: PC ←PC+k+1 else PC PC+1 if condition is false • Flag affected: None • Flag affected: None • Words: 1 • Words: 1 • Cycles: 2 • Cycles: 1 if condition is false; 2 if condition is true

S2, 2008 COMP9032 Week2 59 S2, 2008 COMP9032 Week2 60 Control (2/2) Loop (1/2)

• IF-THEN-ELSE control structure • WHILE loop if(a<0) sum =0; b=1; i=1; else while (i<=n){ b=-1; sum += i*i; – Numbers x, z are 8-bit signed integers and stored i++; in registers. You need to decide which registers to } use. – Numbers i, sum are 8-bit unsigned integers and .def a=r16 stored in registers. You need to decide which .def b=r17 cpi a, 0 ;a-0 registers to use. brge ELSE ;if a ≥≥≥0, to to ELSE ldi b, 1 ;b=1 rjmp END ;end of IF statement ELSE: ldi b, -1 ;b=-1 S2, 2008END: … COMP9032 Week2 61 S2, 2008 COMP9032 Week2 62

Loop (2/2) Homework

• WHILE loop 1. Refer to the AVR Instruction Set

.def i = r16 documentation (available at .def n = r17 http://www.cse.unsw.edu.au/~COMP9032/re .def sum = r18 fs/AVR-Instruction-Set.pdf). ldi i, 1 ;initialize clr sum Study the following instructions: loop: – Arithmetic and logic instructions cp n, i brlo end • add, adc, adiw, sub, subi, sbc, sbci, subiw, mul, muls, mul i, i mulsu add sum, r0 • and, andi, or, ori, eor inc i • com, neg rjmp loop end: rjmp end

S2, 2008 COMP9032 Week2 63 S2, 2008 COMP9032 Week2 64 Homework Homework

1. Study the following instructions (cont.) 2. Implement the following functions with AVR – Branch instructions assembly language • cp, cpc, cpi 1) 2-byte addition (i.e, addition on 16-bit numbers) • rjmp 2) 2-byte signed subtraction • breq, brne 3) 2-byte signed multiplication • brge, brlt • brsh, brlo 3. Inverse a string of ten characters that is – Data transfer instructions stored in the registers r0~r9; and store the • mov inversed string in registers r10~r19 • ldi, ld, st

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Homework Reading Material

4. Translate the following if-then-else statement, • AVR Instruction Set online documentation where x is an 8-bit unsigned integer. – Instruction Set Nomenclature – I/O Registers if(x<0) z=1; – The Program and Data Addressing else – Arithmetic instructions, program control z=255; instructions

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