Lecture Overview Microprocessors & Interfacing • AVR ISA • AVR Instructions & Programming (I) – Basic construct implementation AVR ISA & AVR Programming (I) Lecturer : Dr. Annie Guo S2, 2008 COMP9032 Week2 1 S2, 2008 COMP9032 Week2 2 Atmel AVR AVR Registers • 8-bit RISC architecture • General purpose registers – Most instructions have 16-bit fixed length – 32 8-bit registers, R0 ~ R31 or r0 ~ r31 – Most instructions take 1 clock cycle to execute. – Can be further divided into two groups • Load-store memory access architecture • First half group: R0 ~ R15 and second half group: R16 ~ R31 – All calculations are on registers • Some instructions work only on the second half group • Internal program memory and data memory R16~R31 – Due to the limitation of instruction encoding bits • Wide variety of on-chip peripherals (digital » Will be covered later I/O, ADC, EEPROM, UART, pulse width – E.g. ldi rd, #number ;rd ∈ R16~R31 modulator (PWM), …). S2, 2008 COMP9032 Week2 3 S2, 2008 COMP9032 Week2 4 AVR Registers (cont.) AVR Registers (cont.) • General purpose registers • I/O registers – The following register pairs can work as address – 64 8-bit registers indexes • Their names are defined in the m64def.inc file • X, R27:R26 – Used in input/output instructions • Y, R29:R28 • Mainly storing data/addresses and control signal bits • Z, R31:R30 – Some instructions work only with I/O registers, others with general purpose registers – don’t – The following registers can be applied for specific confuse them use • E.g. in rd, port ; port must be an I/O register • R1:R0 store the result of multiplication instruction – Will be covered in detail later • R0 stores the data loaded from the program memory • Status register (SREG) – A special I/O register S2, 2008 COMP9032 Week2 5 S2, 2008 COMP9032 Week2 6 The Status Register in AVR The Status Register in AVR (cont.) • The Status Register (SREG) contains information about the result of the most recently executed I T H S V N Z C arithmetic instruction. This information can be used for altering program flow in order to perform Bit 7 6 5 4 3 2 1 0 conditional operations. • SREG is updated after any of ALU operations by • Bit 7 – I: Global Interrupt Enable hardware. – Used to enable and disable interrupts. • SREG is not automatically stored when entering an interrupt routine and restored when returning from an – 1: enabled. 0: disabled. interrupt. This must be handled by software. – The I-bit is cleared by hardware after an interrupt – Using in/out instruction to store/restore SREG has occurred, and is set by the RETI instruction to enable subsequent interrupts. S2, 2008 COMP9032 Week2 7 S2, 2008 COMP9032 Week2 8 The Status Register in AVR (cont.) The Status Register in AVR (cont.) I T H S V N Z C I T H S V N Z C Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 • Bit 6 – T: Bit Copy Storage – The Bit Copy instructions BLD (Bit LoaD) and BST • Bit 5 – H: Half Carry Flag (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the – The Half Carry Flag H indicates a Half Carry Register File can be copied into T by the BST (carry from bit 4) in some arithmetic operations. instruction, and a bit in T can be copied into a bit – Half Carry is useful in BCD arithmetic. in a register in the Register File by the BLD instruction. S2, 2008 COMP9032 Week2 9 S2, 2008 COMP9032 Week2 10 The Status Register in AVR (cont.) The Status Register in AVR (cont.) I T H S V N Z C I T H S V N Z C Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 • Bit 4 – S: Sign Bit – Exclusive OR between the Negative Flag N and • Bit 2 – N: Negative Flag the Two’s Complement Overflow Flag V ( S = N – N is the most significant bit of the result. ⊕V). • Bit 1 – Z: Zero Flag • Bit 3 – V: Two’s Complement Overflow Flag – Z indicates a zero result in an arithmetic or logic – The Two’s Complement Overflow Flag V supports operation. 1: zero. 0: Non-zero. two’s complement arithmetic. S2, 2008 COMP9032 Week2 11 S2, 2008 COMP9032 Week2 12 The Status Register in AVR (cont.) AVR Address Spaces • Three address spaces I T H S V N Z C – Data memory • Storing data to be processed Bit 7 6 5 4 3 2 1 0 – Program memory • Storing program code and some constants • Bit 0 – C: Carry Flag – EEPROM memory – Its meaning depends on the operation. • Large permanent data storage • For addition X+Y, it is the carry from the most significant bit • For subtraction x-y, where x and y are unsigned integers, it indicates whether x<y or not. If x<y, C=1; otherwise, C=0. S2, 2008 COMP9032 Week2 13 S2, 2008 COMP9032 Week2 14 Data Memory Space Program Memory Space Data Memory • Covers • Covers Program Memory – Register file 32 General purpose 0x0000 – 16 bit Flash Memory Working Registers 0x0000 • I.e. registers in the register • Read only file also have memory 0x1F address 0x20 – Instructions are Program Flash Memory 64 Input/Output retained when power (1K bytes~128K bytes) – I/O registers Registers off • I.e. I/O registers have two 0x5F 0x60 – Can be accessed with versions of addresses Internal SRAM 16 Bits – I/O addresses (128~4K bytes) special instructions – Memory addresses • LPM – SRAM data memory External SRAM • SPM • The highest memory End Address location is defined as 8 bits RAMEND End Address S2, 2008 COMP9032 Week2 15 S2, 2008 COMP9032 Week2 16 EEPROM Memory Space AVR Instruction Format • Covers • For AVR, almost all instructions are 16 bits – 8-bit EEPROM Data EEPROM Memory long memory 0x0000 – For example, • Use to permanently store large set of data • add Rd, Rr • sub Rd, Rr – Can be accessed EEPROM Memory using load and store (64~4K bytes) • mul Rd, Rr instructions with • brge k special control bit 8 bits • Few instructions are 32 bits long settings – For example • Not covered in this ≤ ≤ course • lds Rd, k ( 0 k 65535 ) End address – loads 1 byte from the SRAM to a register. S2, 2008 COMP9032 Week2 17 S2, 2008 COMP9032 Week2 18 Examples (1) Examples (2) - 16 bits long - 32 bit long • Clear register instruction • Unconditional branch Syntax: clr Rd Syntax: jmp k Operand: 0 ≤ d ≤ 31 Operand: 0 ≤ k < 4M Operation: Rd ← 0 Operation: PC ← K • Instruction format • Instruction format 0 0 1 0 0 1 d dd d d d d d d d 15 0 1 0 0 1 0 1 0 kk k k k 1 1 0 k 15 0 – OpCode uses 6 bits (bit 10 to bit 15). – The operand uses the remaining 10 bits (only 5 bits, bit 0 to k k k k k k k kk k k k k k k k bit 4, are actually needed). 31 16 • Execution time • Execution time 3 clock cycles 1 clock cycle S2, 2008 COMP9032 Week2 19 S2, 2008 COMP9032 Week2 20 Examples (3) AVR Instructions - with variable cycles • Conditional branch • AVR has the following classes of instructions: Syntax: breq k – Arithmetic and Logic Operand: -64 ≤ k < +63 – Data transfer Operation: If Rd=Rr(Z=1) then PC ← PC+k+1, else – Program control PC PC+1 – Bit and Others • Instruction format • Bit and Bit test 1 1 1 1 0 0 k kk k k k k 0 0 1 • MCU Control • An overview of the instructions are given in • Execution time the next slides. 1 clock cycle if condition is false 2 clock cycles if condition is true S2, 2008 COMP9032 Week2 21 S2, 2008 COMP9032 Week2 22 AL Instructions Transfer Instructions • Arithmetic • Logic • GP register • Memory – addition • E.g. AND Rd, Rr • E.g. MOV Rd, Rr – Data memory • E.g. ADD Rd, Rr • Shift • I/O registers • E.g. LD Rd, X ST X, Rr – Program memory – Subtraction • E.g. LSL Rd • E.g. IN Rd, PORTA • E.g. SUB Rd, Rr OUT PORTB, Rr • E.g. LPM – EEPROM memory – Increment/decrement • Stack • Not covered in this course • E.g INC Rd • PUSH Rr – Multiplication • POP Rd • E.g. MUL Rd, Rr • Immediate values • E.g. LDI Rd, K8 S2, 2008 COMP9032 Week2 23 S2, 2008 COMP9032 Week2 24 Program Control Instructions Bit & Other Instructions • Branch • Call subroutine • Bit • Others – Conditional • E.g. RCALL k – Set bit • NOP • Jump to address • Return from subroutine • E.g. SBI PORTA, b • BREAK – BREQ des • SLEEP • E.g. RET – Clear bit » test ALU flag and jump • WDR to specified address if • E.g CBI PORTA, b the test was true • skip – Bit copy – SBIC k • E.g. BST Rd, b » test a bit in a register or an IO register and skip the next instruction if the test was true. – Unconditional • Jump to the specified address – RJMP des S2, 2008 COMP9032 Week2 25 S2, 2008 COMP9032 Week2 26 AVR Instructions (cont.) AVR Addressing Modes • Not all instructions are implemented in all • Immediate AVR controllers. • Register direct • Refer to the data sheet of a specific • Memory related addressing mode microcontroller – Data memory • Direct • Refer to online AVR instruction document for • Indirect the detail description of each instruction • Indirect with Displacement • Indirect with Pre-decrement • Indirect with Post-increment – Program memory – EPROM memory • Not covered in this course S2, 2008 COMP9032 Week2 27 S2, 2008 COMP9032 Week2 28 Immediate Addressing Register Direct Addressing • The operands come from the instructions • The operands come from general purpose • For example registers • For example andi r16, $0F and r16, r0 – Bitwise logic AND operation • Clear upper nibble of register r16 – r16 r16 AND r0 • Clear upper nibble of register r16 if r0=0x0F S2, 2008 COMP9032 Week2 29 S2, 2008 COMP9032 Week2 30 Register Direct Addressing • The operands come from I/O registers • For example in r25, PINA Data Memory Addressing -- r25 PIN A S2, 2008 COMP9032 Week2 31 S2, 2008 COMP9032 Week2 32 Data Direct Addressing Indirect Addressing • The data memory address is given directly • The address of memory data is from an from the instruction address pointer (X, Y, Z) • For example • For example lds r5, $F123 ld r11, X -- r5 Mem($F123), or r5 ($F123) -- r11 Mem(X), or r11 (X) S2, 2008 COMP9032 Week2 33 S2, 2008 COMP9032 Week2 34 Indirect Addressing with Indirect Addressing with Pre- Displacement decrement • The address of memory data is from (Y,Z)+q • The address of memory data is from an address pointer (X, Y, Z) and the value of the pointer is auto- • For example decreased before each memory access.