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The Unadbridged Pentium 4: IA32 Processor Genealogy world-class technical training Are your company’s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge technologies. We understand the challenges companies have when searching for quality, effective training which reduces the students’ time away from work and provides cost-effective alternatives. MindShare offers many fl exible solutions to meet those needs. Our courses are taught by highly-skilled, enthusiastic, knowledgeable and experienced instructors. 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We are proud to be the preferred training provider at an extensive list of clients that include: ADAPTEC • AMD • AGILENT TECHNOLOGIES • APPLE • BROADCOM • CADENCE • CRAY • CISCO • DELL • FREESCALE GENERAL DYNAMICS • HP • IBM • KODAK • LSI LOGIC • MOTOROLA • MICROSOFT • NASA • NATIONAL SEMICONDUCTOR NETAPP • NOKIA • NVIDIA • PLX TECHNOLOGY • QLOGIC • SIEMENS • SUN MICROSYSTEMS SYNOPSYS • TI • UNISYS 4285 SLASH PINE DRIVE COLORADO SPRINGS, CO 80908 USA M 1.602.617.1123 O 1.800.633.1440 [email protected] www.mindshare.com The Unabridged Pentium® 4 IA32 Processor Genealogy First Edition MINDSHARE, INC. TOM SHANLEY TECHNICAL EDIT BY BOB COLWELL ADDISON-WESLEY DEVELOPER’S PRESS Reading, Massachusetts • Harlow, England • Menlo Park, California New York • Don Mills, Ontario • Sydney Bonn • Tokyo • Amsterdam • Mexico City • Seoul San Juan • Madrid • Singapore • Paris • Taipei • Milan Many of the designations used by manufacturers and sellers to distinguish their prod- ucts are claimed as trademarks. Where those designators appear in this book, and Add- ison-Wesley was aware of the trademark claim, the designations have been printed in initial capital letters or all capital letters. The authors and publishers have taken care in preparation of this book but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connec- tion with or arising out of the use of the information or programs contained herein. Library of Congress Cataloging-in-Publication Data ISBN: 0-321-24656-X Copyright ©2004 by MindShare, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopy- ing, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States of America. Published simultaneously in Canada. Sponsoring Editor: Project Manager: Cover Design: Set in 10 point Palatino by MindShare, Inc. 1 2 3 4 5 6 7 8 9-MA-999897 First Printing, July 2004 Addison-Wesley books are available for bulk purchases by corporations, institutions, and other organizations. For more information please contact the Corporate, Govern- ment, and Special Sales Department at (800) 238-9682. Find A-W Developers Press on the World Wide Web at: http://www/aw.com/devpress/ At-a-Glance Table of Contents Part 1, Introduction, introduces the processor’s role in the system. It consist of the following chapter: • “Overview of the Processor Role” on page 9. Part 2, Single-/Multi-Task OS Background, introduces the goals of single-task and multi-task OSs and consists of the following chapters: • “Single-Task OS and Application” on page 23. • “Definition of Multitasking” on page 27. • “Multitasking Problems” on page 31. Part 3, The 386, provides a detailed description of the 386 processor, the base- line ancestor of the IA32 processor family. It consists of the following chapters: • “386 Real Mode Operation” on page 39. • “Protected Mode Introduction” on page 103. • “Intro to Segmentation in Protected Mode” on page 109. • “Code Segments” on page 133. • “Data and Stack Segments” on page 157. • “Creating a Task” on page 171. • “Mechanics of a Task Switch” on page 191. • “386 Demand Mode Paging” on page 209. • “The Flat Model” on page 247. • “Interrupts and Exceptions” on page 251. • “Virtual 8086 Mode” on page 329. • “The Debug Registers” on page 375. Part 4, 486, provides an introduction to the 486 processor’s hardware design. The 486 was the first IA32 processor to incorcorate a cache and all subsequent IA32 processors include on-die caches. For this reason, a cache primer is pro- vided. Finally, a detailed description of the 486 software enhancements is pro- vided. This part consists of the following chapters: • “Caching Overview” on page 385. • “486 Hardware Overview” on page 411. • “486 Software Enhancements” on page 431. Part 5, Pentium®, provides an overview of the Pentium® processor’s hardware design and a detailed description of its software enhancements. It consists of the following chapters: • “Pentium® Hardware Overview” on page 463. • “Pentium® Software Enhancements” on page 489. Part 6, Intro to the P6 Core and FSB, provides a brief introduction to the P6 roadmap, the P6 processor core, and the P6 FSB. It consists of the following chapters: • “P6 Road Map” on page 539. • “P6 Hardware Overview” on page 543. Part 7, Pentium® Pro Software Enhancements, provides a detailed description of the software enhancements introduced in the Pentium® Pro processor. It also provides a detailed description of the Microcode Update feature which was introduced on the Pentium® Pro processor. This part consists of the following chapters: • “Pentium® Pro Software Enhancements” on page 553. • “MicroCode Update Feature” on page 631. Part 8, Pentium® II, provides an overview of the Pentium® II’s hardware design, a detailed description of its power management features, software enhancements, and a description of the Pentium® II Xeon processor (the very first Xeon). This part consists of the following chapters: • “Pentium® II Hardware Overview” on page 657. • “Pentium® II Power Management Features” on page 683. • “Pentium® II Software Enhancements” on page 695. • “Pentium® II Xeon Features” on page 719. Part 9, Pentium® III, provides an overview of the Pentium® III’s hardware design, a detailed description of its software enhancements, and a description of the Pentium® III Xeon processor. This part consists of the following chapters: • “Pentium® III Hardware Overview” on page 741. • “Pentium® III Software Enhancements” on page 757. • “Pentium® III Xeon Features” on page 795. Part 10, Pentium® 4, provides a detailed description of the hardware design and software enhancements encompassed in the Pentium® 4 processor family. It consists of the following chapters: • “Pentium® 4 Road Map” on page 813. • “Pentium® 4 System Overview” on page 823. • “Pentium® 4 Processor Overview” on page 835. • “Pentium® 4 PowerOn Configuration” on page 855. • “Pentium® 4 Processor Startup” on page 875. • “Pentium® 4 Core Description” on page 897. • “Hyper-Threading” on page 965. • “The Pentium® 4 Caches” on page 1009. • “Pentium® 4 Handling of Loads and Stores” on page 1061. • “The Pentium® 4 Prescott” on page 1091. • “Pentium® 4 FSB Electrical Characteristics” on page 1115. • “Intro to the Pentium® 4 FSB” on page 1137. • “Pentium® 4 CPU Arbitration” on page 1149. • “Pentium® 4 Priority Agent Arbitration” on page 1165. • “Pentium® 4 Locked Transaction Series” on page 1177. • “Pentium® 4 FSB Blocking” on page 1189. • “Pentium® 4 FSB Request Phase” on page 1201. • “Pentium® 4 FSB Snoop Phase” on page 1225.
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