DOCSLIB.ORG

Intel® C112 and C114 Scalable Memory Buffer Datasheet

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Intel® C112 and C114 Scalable Memory Buffer Datasheet Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Reference Number: 332444-001 IntelLegal Lines and Disclaimerstechnologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com/design/literature.htm Intel and the Intel logo are trademarks of Intel Corporation in the U. S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2015, Intel Corporation. All Rights Reserved. 2 Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Contents 1Introduction..............................................................................................................7 1.1 Document Scope .................................................................................................7 1.2 Intel® C112/C114 Scalable Memory Buffer Overview ...............................................7 1.3 Intel® Xeon Processor E7 V3.Intel® C112/C114 Scalable Memory Buffer Interfaces....7 1.3.1 Intel® Scalable Memory Interconnect 2 Channel Interface .............................8 1.3.2 DDR Bus Interface....................................................................................8 1.3.3 SMBus Slave Interface ..............................................................................9 1.3.4 JTAG Interface .........................................................................................9 1.4 References .........................................................................................................9 1.5 List of Terms and Abbreviations .......................................................................... 10 2 Electrical and Power Specifications.......................................................................... 11 2.1 Overview ......................................................................................................... 11 2.2 Storage Conditions ............................................................................................ 11 2.3 Electrical DC Absolute Maximum Ratings .............................................................. 11 2.3.1 Intel® C112/C114 Scalable Memory Buffer Operating DC Parameters............ 12 2.3.2 Intel® C112/C114 Scalable Memory Buffer Power Specifications................... 12 2.4 DC Specifications ............................................................................................. 13 2.4.1 Intel SMI 2 Signal DC Specifications.......................................................... 13 2.4.2 DDR4 Signal DC Specifications ................................................................. 13 2.4.3 DDR3 Signal DC Specifications ................................................................. 14 3 Signal List ............................................................................................................... 19 3.1 Conventions ..................................................................................................... 19 3.2 Intel® C112/C114 Scalable Memory Buffer Component Pin Description List............... 19 3.2.1 Dual Use DDR3/DDR4 Signals .................................................................. 23 4 Intel® C112/C114 Scalable Memory Buffer ............................................................. 25 5Resets..................................................................................................................... 51 5.1 Cold power up sequence..................................................................................... 51 6 Configuration Registers ........................................................................................... 53 6.1 Overview ......................................................................................................... 53 6.1.1 Register Attributes ................................................................................. 53 6.1.2 Register Addressing................................................................................ 54 6.1.3 Number Notations .................................................................................. 54 6.2 Intel® C112/C114 Scalable Memory Buffer Memory Buffer Register Descriptions ....... 54 6.2.1 PCI Express* Configuration Header........................................................... 54 6.2.2 Error Logging Registers........................................................................... 57 Figures 1-1 Intel® C112/C114 Scalable Memory Buffer Interfaces ..............................................8 2-1 Differential Clock Crosspoint Specification............................................................ 16 2-2 Differential Clock Waveform............................................................................... 17 4-1 Ballout - Left Hand Side ..................................................................................... 25 4-2 Ballout - LHS to Middle....................................................................................... 26 4-3 Ballout - Middle................................................................................................. 27 4-4 Ballout - Middle to RHS ...................................................................................... 28 4-5 Ballout - Right Hand Side ................................................................................... 28 5-1 Intel® C112/C114 Scalable Memory Buffer Cold Power-Up Reset Sequence .............. 51 Tables 2-1 Storage Condition Ratings .................................................................................. 11 Intel® C112/C114 Scalable Memory Buffer 3 Datasheet May 2015 2-2 Absolute Maximum Ratings Over Operating Free-Air Temperature Range...................12 2-3 Intel® C112/C114 Scalable Memory Buffer Operating DC Electrical Parameters..........12 2-4 Intel® C112/C114 Scalable Memory Buffer Active Power Specifications.....................13 2-5 DDR4 Signal DC Specifications.............................................................................13 2-6 DDR3 and DDR3L Signal DC Specifications ............................................................14 2-7 SMBus DC Specifications.....................................................................................16 2-8 System Reference Clock (100 Mhz) Specifications ..................................................16 2-9 JTAG Signals DC Specifications ............................................................................17 3-1 Signal Naming Conventions.................................................................................19 3-2 Intel® C112/C114 Scalable Memory Buffer Signal List ............................................20 3-3 Intel® C112/C114 Scalable Memory Buffer Power Pins ...........................................23 3-4 Dual Use DDR3/DDR4 Signals..............................................................................23 4-1 Intel® C112/C114 Scalable Memory Buffer Ball List................................................29 6-1 Register Base Attributes Definitions......................................................................53 6-2 Register Attribute Modifier Definitions...................................................................53 6-3 Number Notations..............................................................................................54 4 Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Revision History Document Revision Description Date Number Number 332444 001 • Initial release of the document. May 2015 § Intel® C112/C114 Scalable Memory Buffer 5 Datasheet May 2015 6 Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Introduction 1 Introduction 1.1 Document Scope This specification describes the operations, register interface, and external interfaces of Intel® C112/C114 Scalable Memory Buffer. Information critical to the Intel® C112/C114 Scalable Memory Buffer design appears in other specifications, with specific cross-references provided.This document, along with these other specifications, must be treated as a whole. Section 1.4 provides a complete list of all other specifications referenced in this document. In all cases, when
Load more

Recommended publications
  • Timing Circuit Design in High Performance DRAM
    Chapter 11 Timing Circuit Design in High Performance DRAM Feng (Dan) Lin Abstract The need for high performance dynamic random access memory (DRAM) becomes a pressing concern with processor speeds racing into the multi-gigahertz range. For a high performance computing system, such as high-end graphics cards or game consoles, memory bandwidth is one of the key limitations. One way to address this ever increasing bandwidth requirement is by increasing the data transfer rate. As the I/O speed jumps up, precise timing control becomes critical and challenge with variations and limitations in nano-scaled DRAM processes. In this chapter, we will explore two most important timing circuits used in high performance DRAM: clock distribution network (CDN) and clock synchronization circuits (CSC). Keywords Memory interface • DRAM • Memory bandwidth • Clock distribu- tion network (CDN) • Clock synchronization circuit (CSC) • Source-synchronous • Analog phase generator (APG) • De-skewing • Duty-cycle correction (DCC) Delay-locked loop (DLL) • 3D integration 11.1 Introduction 11.1.1 Memory Interface A typical memory system, shown in Fig. 11.1, generally includes a memory control- ler, DRAM devices and memory channels between them. As part of the DRAM device, memory interface serves as a gateway between the external world and internal periphery logics (i.e. array interface and command and address logic). The state-of-art memory interface may include data transceivers, SERDES (serializer/deserializer), F. Lin (*) Senior Member of Technical Staff, Micron Technology, Inc. e-mail: [email protected] K. Iniewski (ed.), CMOS Processors and Memories, 337 Analog Circuits and Signal Processing, DOI 10.1007/978-90-481-9216-8_11, © Springer Science+Business Media B.V.
    [Show full text]
  • Table of Contents Table of Contents
    Table of Contents Table of Contents UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 Form 10-K (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2010 or TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 000-22339 RAMBUS INC. (Exact name of registrant as specified in its charter) Delaware 94 -3112828 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification Number) 1050 Enterprise Way, Suite 700 94089 Sunnyvale, California (Zip Code) (Address of principal executive offices) Registrant’s telephone number, including area code: (408) 462-8000 Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $.001 Par Value The NASDAQ Stock Market LLC (The NASDAQ Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes No Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes No Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • UNITED STATES SECURITIES and EXCHANGE COMMISSION Form
    Use these links to rapidly review the document TABLE OF CONTENTS PART IV Table of Contents UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 Form 10-K (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2011 or TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 000-22339 RAMBUS INC. (Exact name of registrant as specified in its charter) Delaware 94-3112828 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification Number) 1050 Enterprise Way, Suite 700 Sunnyvale, California 94089 (Address of principal executive offices) (Zip Code) Registrant's telephone number, including area code: (408) 462-8000 Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $.001 Par Value The NASDAQ Stock Market LLC (The NASDAQ Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes No Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes No Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • RAMBUS INC. (Exact Name of Registrant As Specified in Its Charter) ______
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 ________________ Form 10-K ________________ (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2011 or TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 000-22339 ________________ RAMBUS INC. (Exact name of registrant as specified in its charter) ________________ Delaware 94-3112828 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification Number) 1050 Enterprise Way, Suite 700 94089 Sunnyvale, California (Zip Code) (Address of principal executive offices) Registrant’s telephone number, including area code: (408) 462-8000 ________________ Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $.001 Par Value The NASDAQ Stock Market LLC (The NASDAQ Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None ________________ Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes No Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes No Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-To-Digital Conversion Angeli, Nico (2020)
    All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion Angeli, Nico (2020) DOI (TUprints): https://doi.org/10.25534/tuprints-00012975 Lizenz: CC-BY-NC-ND 4.0 International - Creative Commons, Namensnennung, nicht kom- merziell, keine Bearbeitung Publikationstyp: Dissertation Fachbereich: 18 Fachbereich Elektrotechnik und Informationstechnik Quelle des Originals: https://tuprints.ulb.tu-darmstadt.de/12975 All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion Digitale Taktsignal Kalibrierung für schnelle quellsynchrone I/O Links basierend auf Phasen-zu-digital Wandlung Zur Erlangung des akademischen Grades Doktor-Ingenieur (Dr.-Ing.) genehmigte Dissertation von M.Sc. Nico Angeli aus Würzburg Tag der Einreichung: 13. März 2020, Tag der Prüfung: 01. Juli 2020 Darmstadt — D 17 1. Gutachten: Prof. Dr.-Ing. Klaus Hofmann 2. Gutachten: Prof. Dr.-Ing. Chihao Xu Fachgebiet Integrierte Elektronische Systeme All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion Digitale Taktsignal Kalibrierung für schnelle quellsynchrone I/O Links basierend auf Phasen-zu-digital Wandlung Genehmigte Dissertation von M.Sc. Nico Angeli aus Würzburg 1. Gutachten: Prof. Dr.-Ing. Klaus Hofmann 2. Gutachten: Prof. Dr.-Ing. Chihao Xu Tag der Einreichung: 13. März 2020 Tag der Prüfung: 01. Juli 2020 Darmstadt — D 17 Bitte zitieren Sie dieses Dokument als: URN: urn:nbn:de:tuda-tuprints-129758 URL: http://tuprints.ulb.tu-darmstadt.de/12975 Dieses Dokument wird bereitgestellt von tuprints, E-Publishing-Service der TU Darmstadt http://tuprints.ulb.tu-darmstadt.de [email protected] Die Veröffentlichung steht unter folgender Creative Commons Lizenz: Namensnennung – Keine kommerzielle Nutzung – Keine Bearbeitung 4.0 International https://creativecommons.org/licenses/by-nc-nd/4.0/deed.de Erklärungen zur Dissertation § 8 Abs.
    [Show full text]
  • Session 27 Overview DRAM and Eram
    ISSCC 2007 / SESSION 27 / DRAM AND eRAM / OVERVIEW Session 27 Overview DRAM and eRAM Chair: Martin Brox, Qimonda, Neubiberg, Germany Associate Chair: Kazuhiko Kajigaya, Elpida Memory, Sagamihara, Japan Demand growth for electronic systems has been driven by new consumer and computing applica- tions. The most popular examples are the next-generation, high-resolution game-consoles. These systems heavily leverage the performance of today’s memories and processors. Yet, these applica- tions are still unable to create a life-like experience due to the limitations of the on- and off-chip memory bandwidth available to the processing functions. Careful optimization of the memory hier- archy bandwidth is necessary to improve system performance. High-speed embedded-DRAM (eDRAM) has evolved as a serious contender to embedded-SRAM (eSRAM), while external data- rates continue their rapid rise. However, speed improvements cannot stand on their own as system costs must be kept reasonable. To this end, good test and repair solutions reduce cost and facilitate higher levels of integra- tion. The presentations in this session report recent advances that address these challenges. Paper 27.1 by IBM introduces an innovative sense-amplifier for use in an eDRAM macro operating at a random-cycle frequen- cy of 500MHz. This macro, which occupies only 32% of an equivalent eSRAM-macro in the same SOI-technology, enables higher-density cache implementations improving system level performance. Cost, test strategy and system integration are the focus of the next two presentations. Paper 27.2 by Renesas, Shikino and Daioh, explores strategies needed for known-good-die (KGD) applications with the example of an eSRAM-macro.
    [Show full text]
  • Computer Technology an Introduction
    APEX TUTORS Page | 1 Computer Technology An Introduction Installation, Configuration, Connection, Troubleshooting A guide to configuring, installing, connecting and troubleshooting computer systems Page | 2 Table of Contents Table of Contents ........................................................................................................... 2 Preface............................................................................................................................ 4 Introduction .................................................................................................................... 5 CHAPTER 1 CPU.......................................................................................................... 7 CPU Packages ................................................................................................................ 7 CHAPTER 2 RAM ...................................................................................................... 19 RAM Variations ........................................................................................................... 22 CHAPTER 3 Hard Drive Technologies ....................................................................... 25 RAID ............................................................................................................................ 32 Implementing RAID .................................................................................................... 34 Solid State Disks .........................................................................................................
    [Show full text]
  • Dell EMC Poweredge R740xd2 Technical Guide
    Dell EMC PowerEdge R740xd2 Technical Guide June 2021 Rev. A08 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2017 - 2021 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge R740xd2 helps you plan for future growth with large internal storage and cost-efficient drive capacities. Deliver two-socket compute performance with flash and fast networking options to meet streaming demands. Simplify management of large data sets with automated administration and front-serviceable drives. The R740xd2 lets you keep your data safely on-premise with built-in security, even as you scale capacity. The R740xd2 is Dell EMC's latest 2-socket, 2U rack server designed to run data-heavy workloads using scalable memory, I/O, and network options. The systems feature the 2nd Generation Intel® Xeon® Processor Scalable Family, up to 16 DIMMs, PCIe 3.0 enabled expansion slots, and a choice of OCP technologies. New technologies The following table shows new technologies incorporated in the PowerEdge R740xd2: Table 1. New technologies Technology Detailed Description 2nd Generation Intel® Xeon® The 2nd Generation Intel® Xeon® processor scalable family has advanced features Processor Scalable Family that deliver exceptional performance and value.
    [Show full text]
  • Dell EMC Poweredge Mx740c Technical Guide
    Dell EMC PowerEdge MX740c Technical Guide Regulatory Model: E04B Series Regulatory Type: E04B001 © 2019 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. April 2020 Rev. A04 Contents 1 System overview ......................................................................................................................... 5 Introduction............................................................................................................................................................................ 5 New Technologies................................................................................................................................................................. 5 2 System features...........................................................................................................................7 Product comparison ............................................................................................................................................................. 7 Specifications......................................................................................................................................................................... 8 3 Chassis view and features............................................................................................................ 11 Front view of the system.....................................................................................................................................................11
    [Show full text]
  • Pdfdownload.Jsp?Path=/Datasheet/Timing Device/DDR Device Operation.Pdf 9
    SpringerBriefs in Electrical and Computer Engineering For further volumes: http://www.springer.com/series/10059 Chulwoo Kim • Hyun-Woo Lee Junyoung Song High-Bandwidth Memory Interface 2123 Chulwoo Kim Hyun-Woo Lee Department of Electrical Engineering SK-Hynix Korea University Gyeonggi-do Seongbuk-gu, Seoul Korea Korea Junyoung Song Department of Electrical Engineering Korea University Seongbuk-gu, Seoul Korea ISSN 2191-8112 ISSN 2191-8120 (electronic) ISBN 978-3-319-02380-9 ISBN 978-3-319-02381-6 (eBook) DOI 10.1007/978-3-319-02381-6 Springer NewYork Heidelberg Dordrecht London Library of Congress Control Number: 2013950761 © The Author(s) 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law.
    [Show full text]
  • Displays, Memory and Storage Selector Guide
    DRAM FLASH - SSD FLASH MCP STORAGE DISPLAYS PRODUCT SELECTION DISPLAYS, MEMORY AND STORAGE GUIDE 1H 2017 CONTACTS Samsung Semiconductor, Inc. Samsung continues to lead the industry with the broadest portfolio of memory products and display technology. Its DRAM, flash, mobile and graphics memory are found in many computers — from ultrabooks to powerful servers — and in a wide range of handheld devices such as smartphones and tablets. Samsung is also a leader in display panels for smartphones, TVs and monitors and public information displays. In addition, Samsung provides the industry’s widest line of storage products from the consumer to enterprise levels. These include flash storage, such as Solid State Drives, and a range of embedded flash storage products. Markets DRAM SSD FLASH ASIC LOGIC LCD/OLED MOBILE/WIRELESS NOTEBOOK PCs/ ULTRABOOKS™ DESKTOP PCs/ WORKSTATIONS SERVERS NETWORKING/ COMMUNICATIONS CONSUMER ELECTRONICS www.samsung.com/us/samsungsemiconductor TABLE OF CONTENTS DRAM DRAM PAGES 4–13 samsung.com/dram • DDR4 SDRAM • Graphics DRAM • DDR3 SDRAM • Mobile DRAM • DDR2 SDRAM • Ordering Info FLASH - SSD PAGES 14–15 samsung.com/flash • eMMC • Solid State Drives (SSD) • Universal Flash Storage (UFS) MULTI-CHIP PACKAGES PAGES 16 samsung.com/mcp • eMMC + LPDDR2 • eMMC + LPDDR3 STorAGE PAGES 17–19 samsung.com/flash-ssd • Solid State Drives (SSD) DISPLAyS PAGES 20-21 samsungdisplay.com • Public Information Display (PID) • Indoor PID Product Classification • E-Board • SNB/UNB • Outdoor PID CONTACTS PAGES 22–23 samsung.com/semiconductor/sales-network
    [Show full text]
  • Product Selection Guide
    2H 2014 MemoryDisplays, Storage and GUIDE SELECTION PRODUCT contACTS DISPLAYS StorAGE MCP FLASH - SSD DRAM Samsung Semiconductor, Inc. Samsung continues to lead the industry with the broadest portfolio of memory products and display technology. Its display panels, DRAM, flash, mobile and graphics memory are found in many computers – from ultrabooks to powerful servers – and in a wide range of handheld devices such as smartphones and tablets. Samsung is also a leader in TV displays. In addition, Samsung provides the industry’s widest line of storage products from the consumer to enterprise levels. These include optical disc drives as well as flash storage, such as Solid State Drives, and a range of embedded flash storage products. Markets DRAM SSD FLASH ASIC LOGIC TFT/LCD ODD MOBILE/WIRELESS NOTEBOOK PCs/ ULTRABOOKS™ DESKTOP PCs/ WORKSTATIONS SERVERS NETWORKING/ COMMUNICATIONS CONSUMER ELECTRONICS To access our online sales portal, visit: https://smarttools.ssi.samsung.com www.samsung.com/us/oem-solutions M A TABLE OF CONTENTS DR DRAM PAGES 4–13 samsung.com/dram • DDR4 SDRAM • Mobile DRAM • DDR3 SDRAM • Ordering Info • DDR2 SDRAM • Graphics DRAM FLASH - SSD PAGES 14–15 samsung.com/flash • eMMC • Solid State Drives (SSD) MULTI-CHIP PACKAGES PAGES 16–17 samsung.com/mcp • eMMC + LPDDR2 • eMMC + LPDDR3 storAGE PAGES 18–20 samsung.com/flash-ssd samsungodd.com • Solid State Drives • Optical Disc Drives DISPLAYS PAGES 21–22 samsungdisplay.com • Public Information Display • E-Board (PID) Product Classification • Outdoor PID • SNB/UNB • Tablets
    [Show full text]