Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Reference Number: 332444-001 IntelLegal Lines and Disclaimerstechnologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com/design/literature.htm Intel and the Intel logo are trademarks of Intel Corporation in the U. S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2015, Intel Corporation. All Rights Reserved. 2 Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Contents 1Introduction..............................................................................................................7 1.1 Document Scope .................................................................................................7 1.2 Intel® C112/C114 Scalable Memory Buffer Overview ...............................................7 1.3 Intel® Xeon Processor E7 V3.Intel® C112/C114 Scalable Memory Buffer Interfaces....7 1.3.1 Intel® Scalable Memory Interconnect 2 Channel Interface .............................8 1.3.2 DDR Bus Interface....................................................................................8 1.3.3 SMBus Slave Interface ..............................................................................9 1.3.4 JTAG Interface .........................................................................................9 1.4 References .........................................................................................................9 1.5 List of Terms and Abbreviations .......................................................................... 10 2 Electrical and Power Specifications.......................................................................... 11 2.1 Overview ......................................................................................................... 11 2.2 Storage Conditions ............................................................................................ 11 2.3 Electrical DC Absolute Maximum Ratings .............................................................. 11 2.3.1 Intel® C112/C114 Scalable Memory Buffer Operating DC Parameters............ 12 2.3.2 Intel® C112/C114 Scalable Memory Buffer Power Specifications................... 12 2.4 DC Specifications ............................................................................................. 13 2.4.1 Intel SMI 2 Signal DC Specifications.......................................................... 13 2.4.2 DDR4 Signal DC Specifications ................................................................. 13 2.4.3 DDR3 Signal DC Specifications ................................................................. 14 3 Signal List ............................................................................................................... 19 3.1 Conventions ..................................................................................................... 19 3.2 Intel® C112/C114 Scalable Memory Buffer Component Pin Description List............... 19 3.2.1 Dual Use DDR3/DDR4 Signals .................................................................. 23 4 Intel® C112/C114 Scalable Memory Buffer ............................................................. 25 5Resets..................................................................................................................... 51 5.1 Cold power up sequence..................................................................................... 51 6 Configuration Registers ........................................................................................... 53 6.1 Overview ......................................................................................................... 53 6.1.1 Register Attributes ................................................................................. 53 6.1.2 Register Addressing................................................................................ 54 6.1.3 Number Notations .................................................................................. 54 6.2 Intel® C112/C114 Scalable Memory Buffer Memory Buffer Register Descriptions ....... 54 6.2.1 PCI Express* Configuration Header........................................................... 54 6.2.2 Error Logging Registers........................................................................... 57 Figures 1-1 Intel® C112/C114 Scalable Memory Buffer Interfaces ..............................................8 2-1 Differential Clock Crosspoint Specification............................................................ 16 2-2 Differential Clock Waveform............................................................................... 17 4-1 Ballout - Left Hand Side ..................................................................................... 25 4-2 Ballout - LHS to Middle....................................................................................... 26 4-3 Ballout - Middle................................................................................................. 27 4-4 Ballout - Middle to RHS ...................................................................................... 28 4-5 Ballout - Right Hand Side ................................................................................... 28 5-1 Intel® C112/C114 Scalable Memory Buffer Cold Power-Up Reset Sequence .............. 51 Tables 2-1 Storage Condition Ratings .................................................................................. 11 Intel® C112/C114 Scalable Memory Buffer 3 Datasheet May 2015 2-2 Absolute Maximum Ratings Over Operating Free-Air Temperature Range...................12 2-3 Intel® C112/C114 Scalable Memory Buffer Operating DC Electrical Parameters..........12 2-4 Intel® C112/C114 Scalable Memory Buffer Active Power Specifications.....................13 2-5 DDR4 Signal DC Specifications.............................................................................13 2-6 DDR3 and DDR3L Signal DC Specifications ............................................................14 2-7 SMBus DC Specifications.....................................................................................16 2-8 System Reference Clock (100 Mhz) Specifications ..................................................16 2-9 JTAG Signals DC Specifications ............................................................................17 3-1 Signal Naming Conventions.................................................................................19 3-2 Intel® C112/C114 Scalable Memory Buffer Signal List ............................................20 3-3 Intel® C112/C114 Scalable Memory Buffer Power Pins ...........................................23 3-4 Dual Use DDR3/DDR4 Signals..............................................................................23 4-1 Intel® C112/C114 Scalable Memory Buffer Ball List................................................29 6-1 Register Base Attributes Definitions......................................................................53 6-2 Register Attribute Modifier Definitions...................................................................53 6-3 Number Notations..............................................................................................54 4 Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Revision History Document Revision Description Date Number Number 332444 001 • Initial release of the document. May 2015 § Intel® C112/C114 Scalable Memory Buffer 5 Datasheet May 2015 6 Intel® C112/C114 Scalable Memory Buffer Datasheet May 2015 Introduction 1 Introduction 1.1 Document Scope This specification describes the operations, register interface, and external interfaces of Intel® C112/C114 Scalable Memory Buffer. Information critical to the Intel® C112/C114 Scalable Memory Buffer design appears in other specifications, with specific cross-references provided.This document, along with these other specifications, must be treated as a whole. Section 1.4 provides a complete list of all other specifications referenced in this document. In all cases, when