DOCSLIB.ORG

Researching Methods for Efficient Hardware Specification, Design and Implementation of a Next Generation Communication Architecture

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Researching Methods for Efficient Hardware Specification, Design and Implementation of a Next Generation Communication Architecture Researching methods for efficient hardware specification, design and implementation of a next generation communication architecture Inauguraldissertation zur Erlangung des akademischen Grades eines Doktors der Naturwissenschaften der Universität Mannheim vorgelegt von Dipl.-Inf. Patrick R. Haspel aus Mannheim Mannheim, 2006 Dekan: Professor Dr. M. Krause, Universität Mannheim Referent: Professor Dr. U. Brüning, Universität Mannheim Korreferent: Professor Dr. V. Lindenstruth, Universität Heidelberg Tag der mündlichen Prüfung: 4. Mai 2007 Abstract The objective of this work is to create and implement a System Area Network (SAN) ar- chitecture called EXTOLL embedded in the current world of systems, software and stan- dards based on the experiences obtained during the ATOLL project development and test. The topics of this work also cover system design methodology and educational issues in order to provide appropriate human resources and work premises. The scope of this work in the EXTOLL SAN project was: • the Xbar architecture and routing (multi-layer routing, virtual channels and their arbi- tration, routing formats, dead lock aviodance, debug features, automation of reuse) • the on-chip module communication architecture and parts of the host communication • the network processor architecture and integration • the development of the design methodology and the creation of the design flow • the team education and work structure. In order to successfully leverage student know-how and work flow methodology for this research project the SEED curricula changes has been governed by the Hochschul Didaktik Zentrum resulting in a certificate for "Hochschuldidaktik" and excellence in university ed- ucation. The complexity of the target system required new approaches in concurrent Hardware/Soft- ware codesign. The concept of virtual hardware prototypes has been established and exces- sively used during design space exploration and software interface design. Zusammenfassung Das Ziel dieser Arbeit ist der Entwurf sowie die Implementierung einer System Area Net- work (SAN) Architektur namens EXTOLL, die in die heutige Welt der Rechensysteme, Software und Standards eingebettet ist. Diese Arbeit beinhaltet auch die Aspekte der Systementwurfsmethodik und Ausbildungs- fragen um eine geeignete Arbeitsumgebung sowei ein kompetentes Team zu gewährleisten. Die Beiträge zu der EXTOLL SAN Architektur sind: • Die XBar Architektur sowie Routing (multi-layer routing, Virtuelle Kanäle sowie deren Arbitrierung, Routingformate, Deadlockvermeidung, Testeigenschaften, Automa- tisierung der Wiederverwendung) • Die on-chip Modulkommunikationsarchitektur und Teile der Hostkommunikation • Netzwerkprozessorarchitektur und Integration • Die Entwicklung einer Entwurfsmethodik und die Erstellung eines Designflows Um den erforderlichen Ausbildungsstand der Studenten sowie eine geeignete Arbeit- sabläufe für dieses Forschungsprojekt sicherzustellen wurden die Änderungen des SEED Lehrplanes von dem Hochschuldidaktikzentrum begleitet und dabei als Ergebnis das Zer- tifikat für Hochschuldidaktik und Exzellenz in der Lehre verliehen. Die Komplexität des Zielsystems erforderte neue Ansätze im simultanen Hardware/Soft- ware Codesign. Das Konzept virtueller Hardwareprototypen wurde geschaffen und intensiv während der Entwurfraumanalyse und dem Entwurf der Softwareschnittstellen genutzt. Inaugural Dissertation Patrick R. Haspel 1 Introduction ................................................................................................................. 1 1.1 Objectives ............................................................................................................ 1 1.2 Topics of this work .............................................................................................. 2 1.2.1 Creating the work/design environment ................................................... 2 1.2.2 Architecture definition ............................................................................ 3 1.2.3 Hardware/Software design methodology ................................................ 3 1.3 Thesis organization .............................................................................................. 3 2 Cluster Computing and Implementations .................................................................... 5 2.1 Communication demands of distributed and parallel computing ........................ 5 2.2 State of the art hardware support ......................................................................... 7 2.2.1 QsNetII by Quadrics ................................................................................ 8 2.2.2 Myrinet by Myricom ............................................................................. 17 2.2.3 Pathscale ................................................................................................ 19 2.2.4 PCI-ASI (Advanced Switching Interconnect) ....................................... 21 2.2.5 IBM Blue Gene BG/L ........................................................................... 23 2.2.6 Mellanox Infiniband .............................................................................. 25 2.2.7 Cray XT3 ............................................................................................... 26 2.2.8 10GigEthernet by Chelsio ..................................................................... 28 3 SANs in general ......................................................................................................... 30 3.1 Functions, Features and important quality metrics of a SAN ............................ 31 3.1.1 Latency .................................................................................................. 31 3.1.2 Bandwidth ............................................................................................. 37 3.1.3 Network Topology ................................................................................ 40 3.1.4 Supported Parallel Programming Model ............................................... 48 3.1.5 Cost ........................................................................................................ 50 3.1.6 Communication to / Location of the Network Interface Controller ...... 50 4 Methods - Approach .................................................................................................. 53 4.1 Providing the basis for efficiency in hardware design ....................................... 53 4.1.1 Education ............................................................................................... 53 4.1.2 EDA tooling .......................................................................................... 57 4.1.3 Realization - SEED Project ................................................................... 58 4.1.4 The System Realisation Bi-Cone .......................................................... 60 4.2 Hardware/Software Codesign and Cosimulation ............................................... 63 4.2.1 Concurrent development of hardware and related low level software .. 70 Table of Contents Page I Inaugural Dissertation Patrick R. Haspel 4.2.2 Seamless hardware/software interfacing ............................................... 70 4.2.3 Integrity and completeness of software required functionality ............. 71 4.3 FPGA based ASIC prototyping ......................................................................... 71 4.4 Physical design impact of UDSM designs ......................................................... 74 4.4.1 Creating a leading-edge design flow ..................................................... 74 4.4.2 UDSM characteristics ............................................................................ 75 5 Architecture and Function Scope of Building Blocks ............................................... 78 5.1 Top-Level Architecture Decisions ..................................................................... 78 5.2 NPU (Network Processing Unit) ....................................................................... 80 5.2.1 NPU Features and Overview ................................................................. 81 5.2.2 Reasons for a dedicated compute resource in a SAN ............................ 83 5.2.3 Instruction Set enhancements ................................................................ 85 5.2.4 Implementation details .......................................................................... 86 5.3 Network Switch ................................................................................................. 89 5.3.1 Design Space Exploration - Approach and Methods ............................ 91 5.3.2 Functional Enhancements ...................................................................... 95 5.4 Hostinterface and EXTOLL block level communication ................................ 114 5.4.1 Intermodule Communication Architecture .......................................... 115 5.4.2 The Slave interface Unit ...................................................................... 119 5.4.3 The Master Interface Unit ................................................................... 126 6 Conclusion and Outlook .......................................................................................... 135 7 References ............................................................................................................... 137 Table of Contents Page II Inaugural Dissertation Patrick R. Haspel 1 Introduction System Design is a highly complex challenge requiring the breath and depth of more than one
Load more

Recommended publications
  • End-To-End Performance of 10-Gigabit Ethernet on Commodity Systems
    END-TO-END PERFORMANCE OF 10-GIGABIT ETHERNET ON COMMODITY SYSTEMS INTEL’SNETWORK INTERFACE CARD FOR 10-GIGABIT ETHERNET (10GBE) ALLOWS INDIVIDUAL COMPUTER SYSTEMS TO CONNECT DIRECTLY TO 10GBE ETHERNET INFRASTRUCTURES. RESULTS FROM VARIOUS EVALUATIONS SUGGEST THAT 10GBE COULD SERVE IN NETWORKS FROM LANSTOWANS. From its humble beginnings as such performance to bandwidth-hungry host shared Ethernet to its current success as applications via Intel’s new 10GbE network switched Ethernet in local-area networks interface card (or adapter). We implemented (LANs) and system-area networks and its optimizations to Linux, the Transmission anticipated success in metropolitan and wide Control Protocol (TCP), and the 10GbE area networks (MANs and WANs), Ethernet adapter configurations and performed sever- continues to evolve to meet the increasing al evaluations. Results showed extraordinari- demands of packet-switched networks. It does ly higher throughput with low latency, so at low implementation cost while main- indicating that 10GbE is a viable intercon- taining high reliability and relatively simple nect for all network environments. (plug and play) installation, administration, Justin (Gus) Hurwitz and maintenance. Architecture of a 10GbE adapter Although the recently ratified 10-Gigabit The world’s first host-based 10GbE adapter, Wu-chun Feng Ethernet standard differs from earlier Ether- officially known as the Intel PRO/10GbE LR net standards, primarily in that 10GbE oper- server adapter, introduces the benefits of Los Alamos National ates only over fiber and only in full-duplex 10GbE connectivity into LAN and system- mode, the differences are largely superficial. area network environments, thereby accom- Laboratory More importantly, 10GbE does not make modating the growing number of large-scale obsolete current investments in network infra- cluster systems and bandwidth-intensive structure.
    [Show full text]
  • Oriented Conferences Four Solutions
    Delivering Solutions and Technology to the World’s Design Engineering Community Four Solutions- Oriented Conferences • System-on-Chip Design Conference • IP World Forum • High-Performance System Design Conference • Wireless and Optical Broadband Design Conference Special Technology Focus Areas January 29 – February 1, 2001 • Internet and Information Exhibits: January 30–31, 2001 Appliance Design Santa Clara Convention Center • Embedded Design Santa Clara, California • RF, Optical, and Analog Design NEW! • IEC Executive Forum International Engineering Register by January 5 and Consortium save $100 – and be entered to win www.iec.org a Palm Pilot! Practical Design Solutions Practical design-engineering solutions presented by practicing engineers—The DesignCon reputation of excellence has been built largely by the practical nature of its sessions. Design engineers hand selected by our team of professionals provide you with the best electronic design and silicon-solutions information available in the industry. DesignCon provides attendees with DesignCon has an established reputation for the high design solutions from peers and professionals. quality of its papers and its expert-level speakers from Silicon Valley and around the world. Each year more than 100 industry pioneers bring to light the design-engineering solutions that are on the leading edge of technology. This elite group of design engineers presents unique case studies, technology innovations, practical techniques, design tips, and application overviews. Who Should Attend Any professionals who need to stay on top of current information regarding design-engineering theories, The most complete educational experience techniques, and application strategies should attend this in the industry conference. DesignCon attracts engineers and allied The four conference options of DesignCon 2001 provide a professionals from all levels and disciplines.
    [Show full text]
  • Parallel Computing at DESY Peter Wegner Outline •Types of Parallel
    Parallel Computing at DESY Peter Wegner Outline •Types of parallel computing •The APE massive parallel computer •PC Clusters at DESY •Symbolic Computing on the Tablet PC Parallel Computing at DESY, CAPP2005 1 Parallel Computing at DESY Peter Wegner Types of parallel computing : •Massive parallel computing tightly coupled large number of special purpose CPUs and special purpose interconnects in n-Dimensions (n=2,3,4,5,6) Software model – special purpose tools and compilers •Event parallelism trivial parallel processing characterized by communication independent programs which are running on large PC farms Software model – Only scheduling via a Batch System Parallel Computing at DESY, CAPP2005 2 Parallel Computing at DESY Peter Wegner Types of parallel computing cont.: •“Commodity ” parallel computing on clusters one parallel program running on a distributed PC Cluster, the cluster nodes are connected via special high speed, low latency interconnects (GBit Ethernet, Myrinet, Infiniband) Software model – MPI (Message Passing Interface) •SMP (Symmetric MultiProcessing) parallelism many CPUs are sharing a global memory, one program is running on different CPUs in parallel Software model – OpenPM and MPI Parallel Computing at DESY, CAPP2005 3 Parallel computing at DESY: Zeuthen Computer Center Massive parallel PC Farms PC Clusters computer Parallel Computing Parallel Computing at DESY, CAPP2005 4 Parallel Computing at DESY Massive parallel APE (Array Processor Experiment) - since 1994 at DESY, exclusively used for Lattice Simulations for simulations of Quantum Chromodynamics in the framework of the John von Neumann Institute of Computing (NIC, FZ Jülich, DESY) http://www-zeuthen.desy.de/ape PC Cluster with fast interconnect (Myrinet, Infiniband) – since 2001, Applications: LQCD, Parform ? Parallel Computing at DESY, CAPP2005 5 Parallel computing at DESY: APEmille Parallel Computing at DESY, CAPP2005 6 Parallel computing at DESY: apeNEXT Parallel computing at DESY: apeNEXT Parallel Computing at DESY, CAPP2005 7 Parallel computing at DESY: Motivation for PC Clusters 1.
    [Show full text]
  • Data Center Architecture and Topology
    CENTRAL TRAINING INSTITUTE JABALPUR Data Center Architecture and Topology Data Center Architecture Overview The data center is home to the computational power, storage, and applications necessary to support an enterprise business. The data center infrastructure is central to the IT architecture, from which all content is sourced or passes through. Proper planning of the data center infrastructure design is critical, and performance, resiliency, and scalability need to be carefully considered. Another important aspect of the data center design is flexibility in quickly deploying and supporting new services. Designing a flexible architecture that has the ability to support new applications in a short time frame can result in a significant competitive advantage. Such a design requires solid initial planning and thoughtful consideration in the areas of port density, access layer uplink bandwidth, true server capacity, and oversubscription, to name just a few. The data center network design is based on a proven layered approach, which has been tested and improved over the past several years in some of the largest data center implementations in the world. The layered approach is the basic foundation of the data center design that seeks to improve scalability, performance, flexibility, resiliency, and maintenance. Figure 1-1 shows the basic layered design. 1 CENTRAL TRAINING INSTITUTE MPPKVVCL JABALPUR Figure 1-1 Basic Layered Design Campus Core Core Aggregation 10 Gigabit Ethernet Gigabit Ethernet or Etherchannel Backup Access The layers of the data center design are the core, aggregation, and access layers. These layers are referred to extensively throughout this guide and are briefly described as follows: • Core layer—Provides the high-speed packet switching backplane for all flows going in and out of the data center.
    [Show full text]
  • Organising Committees
    DATE 2005 Executive Committee GENERAL CHAIR PROGRAMME CHAIR Nobert Wehn Luca Benini Kaiserslautern U, DE DEIS – Bologna U, IT VICE CHAIR & PAST PROG. CHAIR VICE PROGRAMME CHAIR Georges Gielen Donatella Sciuto KU Leuven, BE Politecnico di Milano, IT FINANCE CHAIR PAST GENERAL CHAIR Rudy Lauwereins Joan Figueras IMEC, Leuven, BE UP Catalunya, Barcelona, ES DESIGNERS’ FORUM DESIGNERS’ FORUM Menno Lindwer Christoph Heer Philips, Eindhoven, NL Infineon, Munich, DE SPECIAL SESSIONS & DATE REP AT DAC FRIDAY WORKSHOPS Ahmed Jerraya Bashir Al-Hashimi TIMA, Grenoble, FR Southampton U, UK INTERACTIVE PRESENTATIONS ELECTRONIC REVIEW Eugenio Villar Wolfgang Mueller Cantabria U, ES Paderborn U, DE WEB MASTER AUDIO VISUAL Udo Kebschull Jaume Segura Heidelberg U, DE Illes Baleares U, ES TUTORIALS & MASTER COURSES FRINGE MEETINGS Enrico Macii Michel Renovell Politecnico di Torino, IT LIRMM, Montpellier, FR AUTOMOTIVE DAY BIOCHIPS DAY Juergen Bortolazzi Christian Paulus DaimlerChrysler, DE Infineon, Munich, DE PROCEEDINGS EXHIBITION PROGRAMME Christophe Bobda Juergen Haase Erlangen U, DE edacentrum, Hannover, DE UNIVERSITY BOOTH UNIVERSITY BOOTH & ICCAD Volker Schoeber REPRESENTATIVE edacentrum, Hannover, DE Wolfgang Rosenstiel Tuebingen U/FZI, DE AWARDS & DATE REP. AT ASPDAC PCB SYMPOSIUM Peter Marwedel Rainer Asfalg Dortmund U, DE Mentor Graphics, DE TRAVEL GRANTS COMMUNICATIONS Marta Rencz Bernard Courtois TU Budapest, HU TIMA, Grenoble, FR LOCAL ARRANGEMENTS PRESS LIASON Volker Dueppe Fred Santamaria Siemens, DE Infotest, Paris, FR ESF CHAIR & EDAA
    [Show full text]
  • Exhibition Report
    Exhibition Report Japan Electronics and Information Technology Industries Association (JEITA) Contents Exhibition Outline 1 Exhibition Configuration 2 1. Scope of Exhibits 2 2. Conference 2 3. Number of Exhibitors and Booths 2 4. Suite Exhibits 2 5. Exhibitors 3 Conference Activities 4 1. Exhibitor Seminars 4 2. Keynote Speech 4 3. Special Event Stage 4 4. The 13th FPGA/PLD Design Conference 4 5. FPGA/PLD Design Conference User’s Presentations 4 6. IP(Intellectual Property) Flea Market in EDSFair 4 7. System Design Forum 2006 Conference 4 Other Events and Special Projects 5 1. Opening Ceremony 5 2. University Plaza 5 3. Venture Conpany Pavilion 5 4. EDAC Reception 5 5. Press 5 Number of Visitors 6 Results of Visitor Questionnaire 6-7 Exhibition Outline Name . Electronic Design and Solution Fair 2006 (EDSFair2006) Duration . Thursday, January 26 and Friday, January 27, 2006 (2 days) 10:00 a.m. to 6:00 p.m. Location . Pacifico Yokohama (Halls C-D hall and Annex Hall) 1-1-1 Minato Mirai, Nishi-ku, Yokohama 220-0012, Japan Admission. Exhibition: Free (registration required at show entrance) Conference: Fees charged for some sessions Sponsorship . Japan Electronics and Information Technology Industries Association (JEITA) Cooperation . Electronic Design Automation Consortium (EDAC) Support . Ministry of the Economy, Trade and Industry, Japan (METI) Embassy of the United States of America in Japan Distributors Association of Foreign Semiconductors (DAFS) City of Yokohama Assistance . Institute of Electronics, Information and Communication Engineers (IEICE) Information Processing Society of Japan (IPSJ) Japan Printed Circuit Association (JPCA) Spacial Assistance. Hewlett-Packard Japan, Ltd. Sun Microsystems K.K Management .
    [Show full text]
  • 28Th IEEE VLSI Test Symposium (VTS 2010) Santa Cruz, CA, April 19-21, 2010
    28th IEEE VLSI Test Symposium (VTS 2010) Santa Cruz, CA, April 19-21, 2010 Preliminary Program (as of 3/25/10) Monday, 4/19/10 Plenary Session (9:00 – 11:00) Break (11:00 – 11:15) Sessions 1 (11:15 – 12:15) Session 1A: Delay & Performance Test 1 Moderator: M. Batek - Broadcom Fast Path Selection for Testing of Small Delay Defects Considering Path Correlations Z. He, T. Lv - Institute of Computing Technology, H. Li, X. Li - Chinese Academy of Sciences Identification of Critical Primitive Path Delay Faults without any Path Enumeration K. Christou, M. Michael, S. Neophytou - University of Cyprus Path Clustering for Adaptive Test T. Uezono, T. Takahashi - Tokyo Institute of Technology, M. Shintani , K. Hatayama - Semiconductor Technology Academic Research Center, K. Masu - Tokyo Institute of Technology, H. Ochi, T. Sato - Kyoto University Session 1B: Memory Test & Repair Moderator: P. Prinetto - Politecnico di Torino Automatic Generation of Memory Built-In Self-Repair Circuits in SOCs for Minimizing Test Time and Area Cost T. Tseng, C. Hou, J. Li - National Central University Bit Line Coupling Memory Tests for Single Cell Fails in SRAMs S. Irobi, Z. Al-ars, S. Hamdioui - Delft University of Technology Reducing Test Time and Area Overhead of an Embedded Memory Array Built-In Repair Analyzer with Optimal Repair Rate J. Chung, J. Park - The University of Texas at Austin, E. Byun, C. Woo - Samsung Electronics, J. Abraham - The University of Texas at Austin IP Session 1C: Innovative Practices in RF Test Organizer: R. Parekhji - Texas Instruments Moderator: TBA Test Time Reduction Using Parallel RF Test Techniques R.
    [Show full text]
  • PLM Industry Summary Editor: Christine Bennett Vol
    PLM Industry Summary Editor: Christine Bennett Vol. 11 No. 4 Friday 23 January 2009 Contents Acquisitions _______________________________________________________________________ 2 Autodesk Completes Acquisition of ALGOR, Inc. _____________________________________________2 Mentor Graphics Extends High Level Synthesis Leadership with Acquisition of Agility Design Solutions Inc. C Synthesis Suite ____________________________________________________________________3 Company News _____________________________________________________________________ 3 Anark Names Chris Garcia Senior Vice President, Business Development ___________________________3 Autodesk Manufacturing Community to Select 2008 Inventor of the Year Award Winner ______________4 Delcam Offers Free ArtCAM Demo Software for Artistic Users __________________________________5 DP signs Agreement with Italian Lathe Manufacturer GRAZIANO Tortona S.r.l. _____________________6 DP Technology Moves its Midwest Team to a Larger, New and Improved Site _______________________6 DP Technology Signs Agreement with Italian Machine-Tool Builder Salvadeo S.r.l. __________________7 Kalypso and Endeca Announce Partnership in Support of Engineering and PLM-Related Information Visibility Solutions ______________________________________________________________________7 New WorkXPlore 3D Website Allows Engineers to Download High Speed Collaborative CAD Viewer Free _____________________________________________________________________________________8 Si2’s Open Modeling Coalition Releases Document on Statistical
    [Show full text]
  • Comparing Ethernet and Myrinet for MPI Communication
    Comparing Ethernet and Myrinet for MPI Communication Supratik Majumder Scott Rixner Rice University Rice University Houston, Texas Houston, Texas [email protected] [email protected] ABSTRACT operating system. In addition, TCP is a carefully developed This paper compares the performance of Myrinet and Eth- network protocol that gracefully handles lost packets and ernet as a communication substrate for MPI libraries. MPI flow control. User-level protocols can not hope to achieve library implementations for Myrinet utilize user-level com- the efficiency of TCP when dealing with these issues. Fur- munication protocols to provide low latency and high band- thermore, there has been significant work in the network width MPI messaging. In contrast, MPI library impleme- server domain to optimize the use of TCP for efficient com- nations for Ethernet utilize the operating system network munication. protocol stack, leading to higher message latency and lower message bandwidth. However, on the NAS benchmarks, GM This paper evaluates the performance differences between messaging over Myrinet only achieves 5% higher applica- GM over 1.2 Gbps Myrinet and TCP over 1 Gbps Ethernet tion performance than TCP messaging over Ethernet. Fur- as communication substrates for the Los Alamos MPI (LA- thermore, efficient TCP messaging implmentations improve MPI) library. The raw network unidirectional ping latency communication latency tolerance, which closes the perfor- of Myrinet is lower than Ethernet by almost 40 µsec. How- mance gap between Myrinet and Ethernet to about 0.5% ever, a considerable fraction of this difference is due to in- on the NAS benchmarks. This shows that commodity net- terrupt coalescing employed by the Ethernet network inter- working, if used efficiently, can be a viable alternative to face driver.
    [Show full text]
  • Designing High-Performance and Scalable Clustered Network Attached Storage with Infiniband
    DESIGNING HIGH-PERFORMANCE AND SCALABLE CLUSTERED NETWORK ATTACHED STORAGE WITH INFINIBAND DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Ranjit Noronha, MS * * * * * The Ohio State University 2008 Dissertation Committee: Approved by Dhabaleswar K. Panda, Adviser Ponnuswammy Sadayappan Adviser Feng Qin Graduate Program in Computer Science and Engineering c Copyright by Ranjit Noronha 2008 ABSTRACT The Internet age has exponentially increased the volume of digital media that is being shared and distributed. Broadband Internet has made technologies such as high quality streaming video on demand possible. Large scale supercomputers also consume and cre- ate huge quantities of data. This media and data must be stored, cataloged and retrieved with high-performance. Researching high-performance storage subsystems to meet the I/O demands of applications in modern scenarios is crucial. Advances in microprocessor technology have given rise to relatively cheap off-the-shelf hardware that may be put together as personal computers as well as servers. The servers may be connected together by networking technology to create farms or clusters of work- stations (COW). The evolution of COWs has significantly reduced the cost of ownership of high-performance clusters and has allowed users to build fairly large scale machines based on commodity server hardware. As COWs have evolved, networking technologies like InfiniBand and 10 Gigabit Eth- ernet have also evolved. These networking technologies not only give lower end-to-end latencies, but also allow for better messaging throughput between the nodes. This allows us to connect the clusters with high-performance interconnects at a relatively lower cost.
    [Show full text]
  • When Innovation Is Hard
    WhenWhen InnovationInnovation isis HardHard Does the Open Source Development Model Work in Hardware? ilkka.tuomi meaningprocessing.com © I. Tuomi 2 Oct. 2008 page: 1 ThesesTheses • 1. Software and hardware are epistemologically different artifacts • This leads to different innovation and conflict models in software and hardware projects • The success of the open distributed approach in ”close-to-hardware” software development (e.g. Linux kernel) is partly explained by this epistemological difference • 2. Close-to-hardware software, social software, and hardware are different • Close-to-hardware software development is easy to distribute because the developer community consists of a homogenous network of people and tools • There exists a ”phenomenological bottleneck:” Real hardware can only be approximated using digital representations; distributed hardware projects can therefore be really hard • There also exists a ”political bottleneck:” Social software can be hard as there are multiple interpretations and systems of meaning © I. Tuomi 2 Oct. 2008 page: 2 DifferentDifferent TypesTypes ofof AnimalsAnimals RequireRequire DifferentDifferent StylesStyles ofof BreedingBreeding • Close-to-hardware SW • HW • In a given HW environment: • The context is the open world: SW is both the description and the Unmodeled features matter implementation Systems wear, tear and break down Mapping between software and the Although dominant voices are loudest, functionality of the system is one-to-one evaluation criteria have to be negotiated Technical functionality can be empirically from multiple perspectives tested • A homogenous developer community, • A homogenous developer community, rooted in its own ”objective reality.” rooted in its own ”professional reality.” or: • A network of interacting communities, each with their own stocks of knowledge.
    [Show full text]
  • Inside the Lustre File System
    Inside The Lustre File System Technology Paper An introduction to the inner workings of the world’s most scalable and popular open source HPC file system Torben Kling Petersen, PhD Inside The Lustre File System The Lustre High Performance Parallel File System Introduction Ever since the precursor to Lustre® (known as the Object- Based Filesystem, or ODBFS) was developed at Carnegie Mellon University in 1999, Lustre has been at the heart of high performance computing, providing the necessary throughput and scalability to many of the fastest supercomputers in the world. Lustre has experienced a number of changes and, despite the code being open source, the ownership has changed hands a number of times. From the original company started by Dr. Peter Braam (Cluster File Systems, or CFS), which was acquired by Sun Microsystems in 2008—which was in turn acquired by Oracle in 2010—to the acquisition of the Lustre assets by Xyratex in 2013, the open source community has supported the proliferation and acceptance of Lustre. In 2011, industry trade groups like OpenSFS1, together with its European sister organization, EOFS2, took a leading role in the continued development of Lustre, using member fees and donations to drive the evolution of specific projects, along with those sponsored by users3 such as Oak Ridge National Laboratory, Lawrence Livermore National Laboratory and the French Atomic Energy Commission (CEA), to mention a few. Today, in 2014, the Lustre community is stronger than ever, and seven of the top 10 high performance computing (HPC) systems on the international Top 5004 list (as well as 75+ of the top 100) are running the Lustre high performance parallel file system.
    [Show full text]