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Time Stamp Counter
Meltdown and Spectre Understanding And
Extended Memory 64 Technology Software Developer's Manual
Class-Action Lawsuit
Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B
The Speculation Meltdown
Deploying Lttng on Exotic Embedded Architectures
Pentium Pro Processor Specification Update
Cache Missing for Fun and Profit
CPU Performance Counters
Enabling Usable and Performant Trusted Execution
PC Desktop Performance and Hardware Performance Counters
Clock Synchronization for Modern Multiprocessors
Intel® Xeon® Processor 5600 Series Specification Update February 2015 Contents
How to Benchmark Code Execution Times on Intel ® IA-32 and IA
Master Thesis Submitted in Partial Satisfaction of the Requirements for the Degree of Master of Engineering (M
Hyper-Threading Technology Architecture and Micro-Architecture
Big Iron Lessons, Part 3: Performance Monitoring and Tuning Page 1 of 18
Meltdown and Spectre
Top View
Clock Synchronization for Modern Multiprocessors
Intel® 64 and IA-32 Architectures Software Developer's Manual
An Exploratory Analysis of Microcode As a Building Block for System Defenses
Exploiting Speculative Execution Through Port Contention
Uncore Design Sandy Bridge-HE
Are There Spectre-Based Malware on Your Android Smartphone?
Application Note 274
High-Precision Relative Clock Synchronization Using Time Stamp Counters
Intel® Processor Identification and the CPUID Instruction Application Note
4. Instruction Tables Lists of Instruction Latencies, Throughputs and Micro-Operation Breakdowns for Intel, AMD, and VIA Cpus
Formal Specification of the X86 Instruction Set Architecture
Xtratum for Powerpc
CPU Performance Monitoring Using the Time-Stamp Counter Register
How Does Malware Use RDTSC? a Study on Operations Executed by Malware with CPU Cycle Measurement
ESX Server Performance and Resource Management for CPU-Intensive Workloads
Time Stamp Counter Design for Virtualized Environment
Hardware Backdoors in X86 Cpus
64-Bit Intel Xeon Processor MP with 1 MB L2 Cache
Bachelor's Thesis Nr
Feasibility of the Spectre Attack in a Security-Focused Language
Timewarp: Rethinking Timekeeping and Performance Monitoring Mechanisms to Mitigate Side-Channel Attacks
Survey of Transient Execution Attacks
Intel® Xeon® Processor E5 V3 Family Specification Update
A Scalable Ordering Primitive for Multicore Machines
A Study of Linux Perf and Slab Allocation Sub-Systems