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64-Bit Intel Xeon Processor MP with 1 MB L2 Cache 64-bit Intel® Xeon® Processor MP with 1 MB L2 Cache Specification Update May 2009 Notice: The 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update. Document Number: 306752-012 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. 64-bit Intel® Xeon® processors with Intel® EM64T requires a computer system with a processor, chipset, BIOS, OS, device drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device drivers and applications may not be available. Check with your vendor for more information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep, Intel Extended Memory 64 Technology, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2005-2006, Intel Corporation 2 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update Contents Revision History .................................................................................................................5 Preface...............................................................................................................................6 Package Markings..............................................................................................................7 Identification Information ....................................................................................................8 Summary Table of Changes.............................................................................................10 Errata................................................................................................................................16 Specification Changes......................................................................................................40 Specification Clarifications ...............................................................................................41 Documentation Changes..................................................................................................44 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update 3 4 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update Revision History Version Description Date -001 Initial revision of 64-bit Intel® Xeon® processor MP with 1 MB L2 Cache March 2005 Specification Update -002 Added erratum J66. July 2005 -003 Added errata J67. August 2005 -004 Added errata J68-J69; added stepping B0 to S-spec table and summary September 2005 table. -005 Added erratum J70. October 2005 -006 Added erratum J71. November 2005 -007 Added erratum J72. December 2005 -008 Updated erratum J17. January 2006 -009 In Documentation changes, updated reference to IA-32 Intel® Architecture April 2006 Software Developer’s Manual to reflect volumes 3A and 3B. Under 'Codes in Summary Table', updated reference to AA , AB, AD,AE,AF. Added Errata J73 - J77. -010 Added AE and AF to the Codes Summary Table. May 2006 Added erratum J78. -011 Added erratum J79. June 2006 -012 Added erratum J80. May 2009 Added Extended Family/Extended Model/Type Information Added AG through AAL Codes to Summary Table 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update 5 Preface Preface This document is an update to the specifications contained in the Affected/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications, and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. This document may also contain information that was not previously published. Affected/Related Documents Title Document # 64-bit Intel® Xeon® Processor MP with 1 MB L2 Cache Datasheet 306751 IA-32 Intel® Architecture Software Developer's Manual, Volume 1: Basic Architecture 253665 IA-32 Intel® Architecture Software Developer's Manual, Volume 2A: Instruction Set Reference, A-M 253666 IA-32 Intel® Architecture Software Developer's Manual, Volume 2B: Instruction Set Reference, N-Z 253667 IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide 253668 Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L3 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number. Errata are design defects or errors. Errata may cause the processor's behavior to deviate from published specifications. Hardware and software designed to be used with any given processor must assume that all errata documented for that processor are present on all devices unless otherwise noted. Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications. Specification Clarifications describe a specification in greater detail or further highlight a specification's impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications. Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications. 6 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update Package Markings Package Markings 64-bit Intel® Xeon® Processor MP (604-pin FC-mPGA4 package) Figure 1. Top-Side Processor Marking Example 2D Matrix Includes ATPO and Serial Number (front end mark) ATPO Serial Number’ Pin 1 Indicator Figure 2. Bottom-Side Processor Marking Example Pin 1 Indicator Pin Field Cavity 866622RK80546 S-Spec with KF1071M SL84W Components FPO – Serial # Text Line 1 Text Line 2 Text Line 3 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update 7 Identification Information Identification Information The 64-bit Intel® Xeon® processor MP with 1 MB L2 Cache can be identified by the following register contents: Extended Family1 Extended Model2 Type3 Family4 Model5 00000000b 0000b 00b 1111b 0100b NOTES: 1. The Extended Family corresponds to bits [27:20] of the EDX register after RESET, bits [27:20] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2. The Extended Model corresponds to bits [19:16] of the EDX register after RESET, bits [19:16] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan. 3. The Type corresponds to bits [13:12] of the EDX register after RESET, bits [13:12] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 4. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 5. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the AP-485 Intel® Processor
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