DOCSLIB.ORG

High-Precision Relative Clock Synchronization Using Time Stamp Counters

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
High-Precision Relative Clock Synchronization Using Time Stamp Counters QUT Digital Repository: http://eprints.qut.edu.au/ Tian, Guo-Song and Tian, Yu-Chu and Fidge, Colin J. (2008) High-precision relative clock synchronization using time stamp counters. In: 13th IEEE International Conference on Engineering of Complex Computer Systems, 31 March-4 April 2008, Beflast, UK. © Copyright 2008 IEEE Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. 13th IEEE International Conference on Engineering of Complex Computer Systems High-Precision Relative Clock Synchronization Using Time Stamp Counters Guo-Song Tian, Yu-Chu Tian and Colin Fidge Faculty of Information Technology, Queensland University of Technology, Brisbane, QLD 4001, Australia Abstract quirements for relative clock synchronization in control sys- tems are of the order of millisecond or even sub-millisecond In this paper we show how to use a computer proces- precision. For instance, real-time controllers typically as- sor’s Time Stamp Counter register to provide a precise and sume that important events occur at predetermined times, stable time reference, via a high-precision relative clock and the system’s calculations might be wrong if sensors are synchronization protocol. Existing clock synchronization not sampled at the assumed rate or if signals are not sent to techniques, such as the Network Time Protocol, were de- actuators at the expected times. signed for wide-area networks with large propagation de- High-precision clock synchronization can be achieved lays, but the millisecond-scale precision they offer is too either by hardware or software clocks. The clocks may coarse for local-area applications such as instrument mon- be Time-Of-Day (TOD) clocks using an oscillator that is itoring systems, high-quality digital audio systems and sen- consistent with Coordinated Universal Time or a software sor networks. Our new clock synchronization technique clock using other absolute time sources such as Internet does not require specialized hardware but instead uses the time servers or a satellite radio clock. In this paper, how- Time Stamp Counter already available in the widely-used ever, our clock synchronization method is relative only, so Intel Pentium processor. Experimental results show that does not rely on an external high-precision hardware timer. we can achieve a synchronization precision in the order of Generally, the precision of network clock synchroniza- 10 microseconds in a small-scale local area network using tion depends on two aspects: determining the one-way TSC registers, which is much higher than can be achieved transmission delay of timestamp messages and the preci- by using a computer processor’s Time-Of-Day clock. sion of a local clock. The well-known four-timestamp offset-calculation mechanism of the Network Time Proto- col (NTP) is widely used by synchronization protocols to 1 Introduction improve the accuracy of estimated one-way transmission delays. Networks using NTP-like synchronization mech- With the emergence of new time-critical distributed com- anisms typically provide precision of the order of one mil- puting paradigms, such as distributed control converters, lisecond [12]. In our work, the adopted timestamp mecha- human-robot physical interaction and ad hoc networks com- nism is derived from NTP. posed of large numbers of disposable sensors, clock syn- One of keys to achieving high-precision relative clock chronization is again becoming a critical issue in distributed synchronization is the use of high accuracy local clocks computing environments [1, 3, 6, 9, 14, 15]. In a typical because the goal of the synchronization is to correct local business application network, the only synchronization re- clocks accurately before they drift out of acceptable range. quirement is the need to keep clocks in a Wide-Area Net- Unfortunately, Time-Of-Day clocks rely on potentially un- work (WAN) loosely synchronized with an absolute Time- stable crystal oscillators [9]. Compared with an oscillator, Of-Day reference. By contrast, distributed control systems however, we note that a computer processor’s Time Stamp require strong, relative clock consistency in a Local-Area Counter (TSC) register has several advantages for achiev- Network (LAN) [4]. ing high precision relative clock synchronization. The TSC Relative clock synchronization refers to the mechanisms register counts processor cycles and is normally used for and protocols used to maintain mutually-consistent clocks measuring short time intervals. Its time resolution is much in a coordinated network of computers. That is, relative higher than an oscillator’s. For example, for a processor clock synchronization focuses on the time difference be- running at a frequency of 800MHz, its TSC register can pro- tween clocks, not the offset of each clock against absolute vide a time resolution of 1.25 nanoseconds. Also, the time time (sometimes called ‘wall clock time’). The accuracy re- required to read from a TSC register is far less than that of 978-0-7695-3139-7/08 $25.00 © 2008 IEEE 69 DOI 10.1109/ICECCS.2008.39 reading from the computer’s TOD clock. Finally, a com- puter’s Central Processing Unit (CPU) frequency is usually Table 1. Test configuration more stable than that of the oscillator used to drive the TOD Hardware Intel Pentium III 800MHz clock. 256M/512M SDRAM Memory In this paper we present a high-precision relative clock Operating systems Fedora 3/Linux kernel 2.6.12.1 synchronization protocol with a master-slave synchroniza- Network adapter Network adapter 3COM 3c59x tion structure. The protocol is intended to support high- Fast Ethernet Card precision real-time calculations in Local-Area Networks, Ethernet switch Baystack 303 Ethernet Switch rather than the usual low-precision timestamping mecha- nism supported in Internet applications. Since we are in- processors contain a timer that operates at the clock cycle terested in intra-network clock consistency, rather synchro- level. The timer is a special register that gets incremented nizing clocks against an absolute time standard, the pro- every single clock cycle. Although there is no uniform, tocol does not require a high-precision time server whose platform-independent interface by which programmers can precision has to be guaranteed by additional hardware make use of these counters, it is easy to create a program in- clocks [3, 12]. The protocol is suitable for use with net- terface for any specific machine with just a small amount of works of processors that provide access to a TSC register. assembly code. The Time Stamp Counter is a cycle counter Thanks to the stability of the TSC register, the precision used in the P6 microarchitecture (the PentiumPro and its achieved by our protocol can be much greater than that of successors). It is a 64-bit unsigned number, which counts synchronization methods using Time-Of-Day functions, as the number of cycles since the CPU was powered up or last we demonstrate by experiments performed under a simple reset. Although the CPU chip’s frequency is affected by ex- synchronization structure. ternal factors, such as age and operating temperature, higher CPU speeds allow finer time resolution of this counter. 2 TOD clock and TSC clock characterization The current “time” of a TSC clock tt, relative to the CPU’s last start-up or reset, can be calculated easily from This section introduces the characteristics of both Time- the value of the TSC register T and the measured CPU fre- Of-Day and Time Stamp Counter clocks, and compares the quency fm as follows. performance of timing measurement using a TOD clock and T tt = a TSC-based clock. Also the effects of clock skew are mea- f (1) sured using TSC-based clocks. m Maintaining a TOD clock requires the computer to gen- The value of the TSC register can be read by an ‘rdtsc’ in- erate a clock-tick signal at a predetermined rate. The source struction. Unfortunately in non-real-time operating system, of a computer’s system timer is a basic uncompensated it is hard to measure the CPU’s frequency exactly without quartz crystal oscillator whose frequency is 14.31818 MHz. an external high-precision timer, because of effects such as Dividing the basic frequency by 12 gives 1.19318 MHz context switching, caching and branch predication. For ex- (thus the period is 0.8381 microseconds), which is the clock ample, the precision achieved by a coarse CPU frequency frequency used by the computer’s system timers [2]. measurement may be as much as 1.0% [2]. Therefore, a The precision of a TOD clock is affected by not only (relative) TSC-based clock tt and an (absolute) TOD clock t the resolution of the computer’s system timer but also the may run at a different speeds. periodic timer interrupt. The Time-Of-Day function in The precision of a software clock is determined by at general-purpose computers is commonly implemented us- least two factors: the time cost of reading the hardware ing clock readings from an uncompensated quartz crystal clock and the hardware clock’s intrinsic frequency error. oscillator and counter, which delivers a pulse train with The time required to read a hardware clock can be affected a period ranging from 10 to 1 milliseconds. Each pulse by factors such as the scheduling characteristics of the oper- causes a timer interrupt, which increments a software logi- ating system and the CPU’s computational capabilities. The cal clock variable by a fixed value scaled in microseconds intrinsic frequency error of the hardware clock further de- or nanoseconds. Therefore, the precision of a TOD clock teriorates the precision of the derived software clock, and may be greater than 0.8381 microseconds, even as much accumulated errors cause clock drift.
Load more

Recommended publications
  • Meltdown and Spectre Understanding And
    Meltdown and Spectre Prepared by Christopher Clai January 18th, 2018 Understanding and Remediation Strategy Broad Overview The General Law of Cross-Task Information Leakage “In any setting where short-term performance optimizations have global effect, a sufficiently clever task can infer the recent history of other tasks by observing its own performance.” Meltdown and Spectre are two hardware vulnerabilities that target the Central Processing Unit (CPU) of computing systems with cross-task information leakage. They were identified by four separate teams of security researchers who then disclosed the vulnerabilities to the company’s months prior to public disclosure. These vulnerabilities leverage the performance optimization architecture of modern day processors to their advantage. • Meltdown allows an attacker to retrieve kernel memory, which is privileged space in your Operating System that may contain password hashes and private keys for data decryption. • Spectre allows an attacker to retrieve information within the process it operates in, and execute code even if it was isolated in a sandbox within a process. The vulnerabilities require attackers to already have a way into your network, and at most can exfiltrate data from memory. They are unable to cause things such as privilege escalation, holding your data for ransom, or causing business disruption. They data they retrieve however, may be used for that purpose if it contains the information they are seeking. The initial rush of patches and microcode (firmware for CPU) updates have been somewhat brute and simplistic in their methods and only seek to mitigate potential practical exploit paths for these vulnerabilities. Researchers do not believe there will potential to fully prevent these types of exploits.
    [Show full text]
  • Extended Memory 64 Technology Software Developer's Manual
    IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology Software Developer’s Manual Documentation Changes November 2004 Notice: The IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in the specification updates. Document Number: 252046-011 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B
    Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2 NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669. Refer to all five volumes when evaluating your design needs. Order Number: 253669-031US June 2009 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT- ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR IN- TENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUA- TION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "unde- fined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
    [Show full text]
  • The Speculation Meltdown
    Security Now! Transcript of Episode #645 Page 1 of 28 Transcript of Episode #645 The Speculation Meltdown Description: This week, before we focus upon the industry-wide catastrophe enabled by precisely timing the instruction execution of all contemporary high-performance processor architectures, we examine a change in Microsoft's policy regarding non- Microsoft AV systems, Firefox Quantum's performance when tracking protections are enabled, the very worrisome hard-coded backdoors in 10 of Western Digital's My Cloud drives; and, if at first (WEP) and at second (WPA) and at third (WPA2) and at fourth (WPS) you don't succeed, try, try, try, try, try yet again with WPA3, another crucial cryptographic system being developed by a closed members-only committee. High quality (64 kbps) mp3 audio file URL: http://media.GRC.com/sn/SN-645.mp3 Quarter size (16 kbps) mp3 audio file URL: http://media.GRC.com/sn/sn-645-lq.mp3 SHOW TEASE: It's time for Security Now!. Finally, the long-awaited what the heck is going on with Intel processors edition. Steve breaks down Meltdown and Spectre - by the way, it's not just for Intel anymore - and talks about what mitigation might involve and what the consequences of fixing this massive flaw could be. There's lots of other security news, too. It's all coming up next on Security Now!. Leo Laporte: This is Security Now! with Steve Gibson, Episode 645, recorded Tuesday, January 9th, 2018: The Speculation Meltdown. It's time for Security Now!, the show where we cover security, now, now, with Steve Gibson.
    [Show full text]
  • Deploying Lttng on Exotic Embedded Architectures
    Deploying LTTng on Exotic Embedded Architectures Mathieu Desnoyers Michel R. Dagenais École Polytechnique de Montréal École Polytechnique de Montréal [email protected] [email protected] Abstract shipping LTTng with their Linux distribution to provide similar features as in VxWorks. Mon- tavista also integrates LTTng to their Carrier This paper presents the considerations that Grade Linux distribution. comes into play when porting the LTTng tracer to a new architecture. Given the aleady portable LTTng currently supports the following archi- design of the tracer, very targeted additions can tectures : enable tracing on a great variety of architec- tures. The main challenge is to understand the architecture time-base in enough depth to • X86 32/64 integrate it to LTTng by creating a lock-less fast and fine-grained trace clock. The ARM • MIPS OMAP3 LTTng port will be used as an exam- ple. • PowerPC 32/64 • ARM1 1 Introduction • S390 2 Gathering an execution trace at the operating • Sparc 32/643 system level has been an important part of the embedded system development process, as il- • SH644 lustrates the case of the Mars Pathfinder[5] pri- ority inversion, solved by gathering an execu- tion trace. This paper presents the key abstractions re- In the Linux environment, such system-wide quired to port LTTng to a new architecture, facility is just becoming accepted in the main- mainly describing what considerations must be line kernel, but with the kernel developer audi- taken into account when designing a trace clock ence as main target. The portability issues and time source suitable for tracing, meeting the lack of user-oriented tools to manipulate the platform-specific constraints.
    [Show full text]
  • Pentium Pro Processor Specification Update
    Pentium Pro Processor Specification Update Release Date: December 1998 Order Number: 242689-034 The Pentium® Pro processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. 24268934.doc Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® Pro processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. The Specification Update should be publicly available following the last shipment date for a period of time equal to the specific product’s warranty period.
    [Show full text]
  • Cache Missing for Fun and Profit
    CACHE MISSING FOR FUN AND PROFIT COLIN PERCIVAL Abstract. Simultaneous multithreading | put simply, the shar- ing of the execution resources of a superscalar processor between multiple execution threads | has recently become widespread via its introduction (under the name \Hyper-Threading") into Intel Pentium 4 processors. In this implementation, for reasons of ef- ficiency and economy of processor area, the sharing of processor resources between threads extends beyond the execution units; of particular concern is that the threads share access to the memory caches. We demonstrate that this shared access to memory caches pro- vides not only an easily used high bandwidth covert channel be- tween threads, but also permits a malicious thread (operating, in theory, with limited privileges) to monitor the execution of another thread, allowing in many cases for theft of cryptographic keys. Finally, we provide some suggestions to processor designers, op- erating system vendors, and the authors of cryptographic software, of how this attack could be mitigated or eliminated entirely. 1. Introduction As integrated circuit fabrication technologies have improved, provid- ing not only faster transistors but smaller transistors, processor design- ers have been met with two critical challenges. First, memory latencies have increased dramatically in relative terms; and second, while it is easy to spend extra transistors on building additional execution units, many programs have fairly limited instruction-level parallelism, which limits the extent to which additional execution resources can be uti- lized. Caches provide a partial solution to the first problem, while out-of-order execution provides a partial solution to the second. In 1995, simultaneous multithreading was revived1 in order to com- bat these two difficulties [12].
    [Show full text]
  • CPU Performance Counters
    These are Not Your Grand Daddy's CPU Performance Counters CPU Hardware Performance Counters for Security Your Presenters Today Nishad Herath – [email protected] & Anders Fogh – [email protected] Black Hat USA 2015 - These are Not Your Grand Daddy's CPU Performance Counters [email protected], [email protected] Performance Counters for Security Black Hat USA 2015 - These are Not Your Grand Daddy's CPU Performance Counters [email protected], [email protected] Performance Counters for Security ● For the x86/x64 architecture – Other architectures also likely to varying degrees ● Extremely flexible - thank you Intel! ● Hundreds of different low level events that are almost free ● Many great low level indicators of higher level security relevant “weirdness” – For example, use of ROP/JOP/COP/COOP etc. ● Need ring 0 or use (restricted) OS interfaces ● Think: an incredibly flexible low level instrumentation Black Hat USA 2015 - These are Not Your Grand Daddy's CPU Performance Counters [email protected], [email protected] Our Lineup... ● Introducing PMCs – CPU hardware Performance (Monitoring) Counters ● PMCs vs ROP (Return Oriented Programming) ● PMCs vs Rowhammer ● PMCs vs Rootkits ● PMCs vs Cache side channel attacks Black Hat USA 2015 - These are Not Your Grand Daddy's CPU Performance Counters [email protected], [email protected] Your Presenters: Nishad Herath ● Principal malware technologist at Qualys Inc. ● Architecture, research, technical innovation ● Information systems security space
    [Show full text]
  • Enabling Usable and Performant Trusted Execution
    Enabling Usable and Performant Trusted Execution by Ofir Weisse A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Computer Science and Engineering) in The University of Michigan 2020 Doctoral Committee: Assistant Professor Baris Kasikci, Co-Chair Professor Thomas F. Wenisch, Co-Chair Research Professor Peter Honeyman Assistant Professor Jean-Baptiste Jeannin Ofir Weisse [email protected] ORCID iD: 0000-0001-7564-6007 © Ofir Weisse 2020 To my parents, Rachel & Yossi ii ACKNOWLEDGEMENTS A PhD requires more than just overcoming intellectual challenges. Being a grad student in a place far away from home, speaking a language which is not my native tongue would have been significantly more challenging, without help and support from countless people. This help is typically not academical but can be crucial in order to survive, for example, the Michigan winter. I want to thank Peter Honeyman for welcoming me to his home from day -1 (AKA visit day) and being a mentor for both my professional as well as personal life. While we may sometimes have different perspectives on various subjects, it has been a pleasure visiting his office almost every week of my PhD. I want to thank my colleagues whom I worked with during my first steps in the PhD program: Timothy Trippel, Matthew Hicks, and Jeremy Erickson. Step 10 is never possible without steps 1,2, and 3. Finishing this dissertation in a meaningful and impactful way would not have been possible without the guidance and, at times, mental support, from my advisors Baris Kasikci and Tom Wenisch (aka TFW).
    [Show full text]
  • PC Desktop Performance and Hardware Performance Counters
    PC Desktop Performance and Hardware Performance Counters Andy Martin Texas Instruments After years of looking at software and hardware data in a mainframe environment, I had the opportunity to look at what was available on x86 based PCs running Windows 95. It took a while to find useful software data but the hardware data available through the hardware performance counters are very exciting. The paper begins by describing the evolving architecture of desktop PCs and the performance metrics of interest in evaluating them. It then describes some of the more interesting counters, references an earlier study using the counters, talks a little bit about the software to enable use of these counters, and describes typical values of instructions per cycle and other metrics of interest running real PC applications. earlier) paper describing the pipeline for the 360- 1. INTRODUCTION 91 [Tomasulo]. This paper describes some of the issues The emphasis of this paper is on PC systems affecting the hardware performance of desktop running Windows 95. [Chong] gives a good personal computers and some of the ways in description of the structure of Windows 95 and which we can evaluate that performance. The several good references for Microsoft systems paper references a few of the available generally. workloads that use real PC applications to exercise the PC system; such workloads provide One of the difficulties in teaching computer a reasonable context for performance studies. architecture has been the absence of useful lab exercises. The measurement technologies Since the author spent a number of years described later in this paper may be a way to looking at the performance of mainframe address this.
    [Show full text]
  • Clock Synchronization for Modern Multiprocessors
    FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Clock Synchronization for Modern Multiprocessors André dos Santos Oliveira Mestrado Integrado em Engenharia Eletrotécnica e de Computadores Supervisor: Pedro Alexandre Guimarães Lobo Ferreira Souto July 25, 2015 c André dos Santos Oliveira, 2015 Abstract Multi-core architectures, in which multiple processors (cores) communicate directly through shared hardware to performs parallel tasks and that way increasing the execution performance, are becom- ing very present in computer systems, and are increasingly relevant in Real-Time (RT) applica- tions, from data-centers to embedded-systems, not to mention desktops. Clock synchronization is a critical service on many of these systems. This dissertation focuses on clocks in synchronous digital systems, in particular Intel architec- tures, from the distribution and analysis of the clock signal in order to coordinate data paths, to software methods and hardware interactions to maintain a time base accurately across a plurality of interconnected processors with possibly different notions of time. In addition, a clock synchronization algorithm in a shared-memory multi-core architectures is proposed, as if it’s a distributed system, applying a model to filter outlet samples, resulting in a random process that achieves a null offset after a couple of corrections. Some experimental measures were made as well to characterize the speed reading the clock and the communication methods used between different cores. i ii Resumo As arquiteturas multi-core, em que múltiplos processadores (cores) cooperam entre si através de hardware partilhado para realizar tarefas paralelas e assim aumentar a performance de execução, são cada vez mais presentes nos sistemas computacionais, e cada vez mais relevantes em apli- cações de tempo real, desde em centros de dados a sistemas embarcados, para não falar dos desk- tops.
    [Show full text]