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TRIPS architecture
Performance and Energy Efficient Network-On-Chip Architectures
Computer Architecture: Dataflow (Part I)
Configurable Fine-Grain Protection for Multicore Processor Virtualization 1
CG-Ooo Energy-Efficient Coarse-Grain Out-Of-Order Execution
Parallel Computer Architecture III
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
An Evaluation of the TRIPS Computer System
A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective
Designing Heterogeneous Many-Core Processors to Provide High Performance Under Limited Chip Power Budget
Modeling Instruction Placement on a Spatial Architecture
Compiling for EDGE Architectures
Scatter-Add in Data Parallel Architectures
Universal Mechanisms for Data-Parallel Architectures
An FPGA Implementation of an Investigative Many-Core Processor; Fynbos
A Coarse Grained Reconfigurable Architecture Framework Supporting
LLVA: a Low-Level Virtual Instruction Set Architecture
Nagarajanr54359.Pdf (2.985Mb)
Scaling to the End of Silicon with EDGE Architectures
Top View
DSP Extensions to the TRIPS ISA
ALP: Efficient Support for All Levels of Parallelism for Complex Media
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
Pipelining a Triggered Processing Element
Exploiting Concurrency in a General-Purpose One-Instruction Computer Architecture
Simplified Vector-Thread Architectures for Flexible and Efficient Data-Parallel Accelerators
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
Design and Implementation of the TRIPS EDGE Architecture
CS – 15740 Computer Architecture MULTIPROCESSORS on a CHIP
CASH: Supporting Iaas Customers with a Sub-Core Configurable
PERSPECTIVES Billion-Transistor Architectures: There and Back Doug Burger the University of Texas at Austin James R
The Wavescalar Architecture
Gebhart, M and Maher, B and Koons, C and Diammond, J and Grattz, P
An Evaluation of the TRIPS Computer System
Composable Building Blocks to Open up Processor Design
Tiled Microprocessors
Compiling for EDGE Architectures
Constructing and Evaluating Weak Memory Models Sizhuo Zhang