Submitted by, Divya.C.Babu Jyothi Karthika.M.S S5MCA LMCST CONTENTS

 Introduction  Causes for the development  Hypertransport technology solutions  Features  Design goals  Overview  System design easier  Conclusion HISTORY

 In many of today's the data transfer capability is the limiting factor for overall system performance.

 One solution for higher data transfer rates is called HyperTransport. Most users will recognize this from some AMD products.

 In fact, HyperTransport was invented at AMD (with help from some industry partners) although it is now managed and promoted by an independent group called HyperTransportConsortium

The first product to use HyperTransport technology was a HyperTransportHyperTransport--toto--PCIPCI bridge chip, announced in the springspring of 2001. INTRODUCTION

 Hyper transport technology is very fast ,low latency point to point link

 It is designed to increase the commercial speed between integrated circuits in computers,servers,embedded systems etc

 This technology is also used in networking and telecommunications equipment

 This reduces the number of buses in the system

 This was invented by AMD and licenced by Hyper transport technology consortium  AMD's HyperTransport --originallyoriginally named DDataata Transport (LDT) --isis an internal chipchip--toto--chipchip interconnect that provides much greater bandwidth for I/O, coco-- processing and multimulti--processingprocessing functions.

 HyperTransport supports unidirectional pointpoint--toto--pointpoint links in each direction and is capable of achieving a bandwidth of up to 6.4 GBps per connection.

 HyperTransport provides a more than a 20x increase in bandwidth compared with current system interconnects that are capable of running at up to 266 MBps. Hyper transport technology is designed to:

 Support both CPUCPU--toto--CPUCPU communication as well as CPU to i/o transfer

 Provide significantly more band width than current technology

 Use low latency response and low pin count

 Appear transparent to operating system and offer little impact on peripheral devices CAUSES LEAD TO THE DEVELOPMENT OF HYPER TRANSPORT TECHNOLOGY  I/O band width problem

 High pin count

 Higher power consumption

While microprocessors continues to double every eighteen months the performance of I/O architecture has lagged, doubling in approximately every 3 months

 OOver the past 20 years a number of legacy buses are there. They are ISA,VLISA,VL--BUS,AGP,LPC,PCIBUS,AGP,LPC,PCI 32/33,PCI32/33,PCI--XX

 These buses have emerged that must be bridged together to support varying array of devices

 These new technology is responsible for increasing demand for additional bandwidth  Technologies like high speed networking and wireless communication allows the devices to exchange growing amounts of data

 High pincounts increases RF radiation which makes it difficult for the system designs to meet FCC and VDE requiremnets

 Reducing pincoutns helps system designer to reduce power consumption and meet thermal requirements

 In response to these problems AMD began to develop Hyper transport I/O link architecture in 1997  HyperTransport is a pointpoint--toto--pointpoint interconnecting system focused on chipchip--toto--chipchip communications. From its inception it has been designed to offer high speeds and low latency. This is a requirement today and into the future as CPU clock speeds continue to increase. ChipChip--toto-- chip communication especially demands low latency and high performance.  Being a pointpoint--toto--pointpoint interconnect technology, as opposed to a bus system, offers many advantages for chipchip--toto--chipchip communication. One advantage is that the communication do not require multiplexing.  Also, these communication signals experience less interference and therefore experience less and can be transmitted with less power. This all combines for faster, and cleaner, communications.  Another advantage of a pointpoint--toto--pointpoint technology is that it does not suffer from degraded performance, as PCI buses do, as the number of devices connected increases. HyperTransport utilizes a direct connection between two devices only. More devices can be connected only by utilizing a daisy chain method. This means that the performance is the same as more devices are connected. FEATURES Packet Based

 HyperTransport is packetpacket--based.based. This allows HyperTransport to play the interconnect role for many different purposes. This technology can be used to interconnect processing cores, RAM and CPU, or even external memory equipment.. Since the HyperTransport technology is packetpacket--based,based, the hardware that is interconnected forms what most would consider a network. In the case of a supersuper--computercomputer having a network of processors interconnected with a pointpoint--toto--pointpoint technology can be very beneficial Low Packet Overhead

 HyperTransport required an 8 byte read request control packet for read operations. For write operations, HyperTransport uses an 8 byte write request control packet with and a 4 byte read response packet. This is it. That is all the overhead; 8 bytes for a read operation and 12 bytes for a write operation. PCI Express requires 20 to 24 bytes of overhead for its read and write operations. This is obviously a major advantage for HyperTransport.  With HyperTransport, the data packet which follows the control packet(s) can only be from 4 to 64 bytes. The data packet for PCI Express can be up to 4096 bytes. So, in some instances PCI Express can have a lower packet overhead than HyperTransport

Bandwidth

 HyperTransport was originally designed to offer significantly higher bandwidth than other competing technologiestechnologies..OneOneway ititdoes this isisto provide aaDouble Data Rate (DDR).. (DDR) Normally when data isisdigitally transmitted between two points, data isisread as either high or low which represents either aa 11or 00..This data isisread whenever the clock produces aahighhigh signalsignal..With DDR, data can be read on the rising and falling edges of aaclockclock signalsignal..ThisThismeans that ininone full clock cycle aaDDRDDR capable transmission data can be read twice, producing twice the data rate.. rate Low Latency

 Low Latency is a design parameter which has been a focus of the HyperTransport technology since the beginning. HyperTransport can achieve this in part by having a single clock per set of 8 data bit paths. This is significant because other technologies, such as PCI Express, have their clocks embedded in a complicated encoding/decoding scheme at both ends of the data link. The method used by HyperTransport is effective in reducing the latency when compared to other technologies because the transmitting device does not need to spend time encoding the clock and the receiving device does not need to spend time decoding the clock. Priority Request Interleaving

 Another aspect of HyperTransport which contributes to its high performance is what they call Priority Request Interleaving (PRI). This is a really cool idea. Figure 2 below shows how PRI works. The problem PRI solves is this: When the CPU is in the midst of a long communication sequence with peripheral device B and peripheral device A needs to communicate with the CPU device A will normally need to wait until device B is finished communicating in order to proceed with its own communication; this can take quite some time and obviously reduce the overall performance.  PRI technology allows peripheral device A to insert a PRI packet into the data stream of device B. This PRI packet is read by the CPU which can then commence a communication sequence with device A on a different link channel

HYPER TRANSPORT TECHNOLOGY SOLUTIONS  Hyper transport technology is formerly codenamed Lightning Data Transfer [LDT]

 This is to provide high speed, high performance,point to point link for interconnecting IC on the board

 Both and high speed are high speed networking protocol but this technology supports ³In the box´ connectivity

 This technology is targeted at networking,telecommunication, embedded applications etc  This technology implements Fast switching mechanisms, So that it provides low latency as well as high band widths

 This also supports plug & play features and PCI like enumeration DESIGN GOALS

1.1. Improve system performance

1.1. Simplify system design

1.1. Increase I/O flexibility

1.1. Maintain compatibility with legacy system

1.1. Ensure extensibility to new system network architecture buses

1.1. Provide highly scalable multiprocessing systems OVERVIEW

 Architecture of hyper transport I/O link can be mapped into 5 different layers similar to OSI reference model

1.1. Physical layer

1.1. Data link layer

1.1. Protocol layer

1.1. Transaction layer

1.1. Session layer Physical layer

This layer defines the physical and electrical characteristics of the protocol. This layer interfaces with the outside world

±± Commands, addresses, and data (CAD) all use the ssamamee set of wires for signaling, dramatically reducing pin requirements.

±±Enhanced Low--VoltageLow Voltage Differential Signaling

±± The signaling technology used in HyperTransport ttecechnologyhnology is a type of low voltage differential signaling (LVDS ). However, it is not the conventional IEEE LVDS standard. It is an enhanced LVDS technique developed to evolve with the performance of future process technologies. This is designed to help ensure that the HyperTransport technology standard has a long lifespan. LVDS has been widely used in these types of applications because it requires fewer pins and wires. unidirectional data path. width 2,4,8,16 bits can implements either upstream or downstream on device DATA LINK LAYER

Data link layer includes the initialization and Configuration sequence ,periodic cyclic redundany check, disconnect/reconnect sequence,information packets for flow control and error management INITIALIZATION This technology enables devices with transmitter and receiver links of equal width can be easily and directly connected. Devices with asymmetric data paths can also be easily connected. Extra receiver pins are tied to logic 0, while extra transmitter pins are left open. During powerpower--up,up, when RESET# isis asserted and the Control signal is at logic 0, each device transmits a bit pattern indicating the width of its receiver PROTOCOL LAYER

The protocol layer includes commands, the virtual channels in which they run and the ordering rules that govern their flow

TRANSACTION LAYER

The transaction layer uses the elements provided by the protocol layer to perform actions such as read request and read responses SESSION LAYER

The session layer includes link width optimization and link frequency optimization along with interrupt and power state capabilities. LINK WIDTH OPTIMIZATION The initial linklink--widthwidth negotiation sequence may result in links that do not operate at their maximum width potential. All 1616--bit,bit, 32--bit,32 bit, and asymmetrically sized configurations must be enabled by a software initialization step. COMMANDS

All Hyper Transport technology commands are either four or eight bytes long and begin with a 66--bitbit command typetype field. The most commonly used commands are Read Request, Read Response, and Write. A virtual channel contains requests or responses with the same ordering priority Hyper Transport commands and data are separated into one of three types of virtual channels: nonnon--ppostedosted requests, posted requests and responses. NonNon--postepostedd requests require a response from the receiver. All read requests and some write requests are nonnon--postedposted requests. PostedPosted requests do not require a response from the receiver. Write requests are posted requests. Responses are replies to nonnon--postposteded requests. Read responses or target done responses to nonnon--pospostedted writes are types of response messages. ENHANCED LOW VOLTAGE DIFFERENTIAL SIGNALLING

 The signaling technology used in hyper transport technology is LOW VOLTAGE DIFFERENTIAL SIGNALLING (LVDS).This is designed to help ensure that the Hyper transport technology has long life span  LVDS has been widely used in this type of technology because it requires only fewer pins and wires  This is designed to reduce cost and power requirements  Hyper Transport technology uses lowlow--voltagevoltage differential signaling with differential impedance (ZOD) of 100 ohms for CAD, Clock, and Control signals, as illustrated in. Characteristic line impedance is 60 ohms.  The driver supply voltage is 1.2 volts, instead of the conventional 2.5 volts for standard LVDS.  Differential signaling and the chosen impedance provide a robust signaling system for use on lowlow--costcost printed circuit boards.. HyperTransport Base Packet Protocol ƛƛHyperTransport is an efficient data transport mechamechanismnism with the least overhead of any modern I/O interconnect architecture . ƛƛAll HyperTransport information carried is multiplemultiple of 4 bytes. ƛƛCommand information is carried control packet of fourfour or eight bytes. ƛƛHyperTransport data traffic is carried as a data packetpacket that consists of an 88--oror 12--byte12 byte header (one 8--byte8 byte control packet for writes or two control packets, one 44--bytebyte and one 8--byte,8 byte, for reads) followed by a 4--4 64 byte data payload. All HyperTransport information is carried in multiples of four bytes (32(32--bits).bits). ƛƛA single control line is used to determine whetherwhether the link is carrying data packet or control packet. ƛƛHypertransport commands and Data are separated intointo three types of Virtual Channel ƛƛ 11--NonNon--PostedPosted ƛƛ 22--PostedPosted ƛƛ 33--ResponseResponse

HyperTransportƛ Technology Makes System Design Easier  Unlike bus designs that must support existing low cost connectors, long cables,and device sharing, HyperTransport technology has been designed as a chipip-- toto--chipchip interconnect for moving data over short distancesdistances between chips in a system.  It provides maximum bandwidth with minimum latency at low cost, and it achieves this by eliminating many of the constraints in system layout and design. Support for Multiple Packages

 The HyperTransport technology interface built onto chips can be packaged in either ceramic or organic substrates with plastic pin grid array (PGA) or ball grid array (BGA) connectors.  Typically, chipset packages are plastic BGAs with the die wire bonded to them. Awire bond technique uses tiny wires to connect the bare die to the metal leads of the chippackage.  Alternatively, flip chipchip--pinpin grid array packaging can be utilizedutilized where the actualchip is turned over to reduce the inductance in both signal and powerdistribution paths.  For HyperTransport technology, flipflip--chipchip die attachment is recommended overwire bonded die attachment for all but the lo west link frequencies. Technology Makes System Design Easier

 Unlike bus designs that must support existing low cost connectors, long cables,and device sharing, HyperTransport technology has been designed as a chipchip--toto--chipinterconnectchipinterconnect for moving data over sshorthort distancesdistances between chips in a system.

 Easier to lay out:  One of the key considerations to designing boards that can be reliablymanufactured in large quantities is the elimination of ƏskewƐ .  Skew is the timing and phases anomalies in a transmission signal that occur when trace lengthsare not matched. This is a big concern, especially in designs that incorporate highhigh-- speedI/O buses. Electrical Considerations

 The issue with all I/O bus architectures is to keep the length bus traces on a equal so that the signals arrive at their destination with equal delays.

The difference in the time it takes the signal to arrive between the two links is the amount of skew built into the design.

The higher the skew, the more likely data integrity will be compromised.With regards to skew, typical board layout involves multiple designers maintaining a delicate balance between multiple factors. Signal Routing

 When system designers lay out boards, the extra length of board traces connecting pins in multiple packages must be dealt with in a way that minimizes board space while meeting matching requirement.  HyperTransport technology is to route compared with AGP, a connector technology exclusively designed for video cards and the leading video connection technology used in PCs today. How will HyperTransport change the motherboard?  HyperTransporttechnology brings many benefits to motherboard PCB design. It reduces theamount of traces (wires) needed to connect points.  It lowers the voltage requiredfor points to properly operate. It simplifies the overall complexity of PCB design.  Reducing thenumber of traces required for connecting two points; be it chipchip--toto--chipchip orPCI slot to CPU reduces complexity of design.  A motherboard PCB is made up of a series of layers of connections. There just isnƍt sufficient room on a motherboard to connect every point on a single layer. The solution is to stack connection layers on top of each other and connect them twotwo--dimensionallydimensionally and threethree--dimensionallydimensionally through the layers.  If the amount of traces is reduced then three things can happen. The first is that the motherboard itself is simpler to design and produce, theoretically resulting in a lower cost.

 The second is that the reduction in traces results in more space allowing for more devices to be attached on an existing motherboard size.

 The third would be an overall reduction in motherboard size still keeping the same amount of available device connection.

 In the diagram below, the AGP link on the right (purple and red) is an example of the current amount of traces required and on the left is the same AGP link built on HyperTransport technology.The result of less cost or more devices or smaller size depends on the manufacturer ƊƊconsumerconsumer equation. The manufacturer wants to sell more products and this depends on what the consumer wants or rather is told what they want. CROSS TALK CROSS TALK

 Increasing data throughput requires more voltage.As voltage passes through a connection or wire it generates an electrical field which can influence the wire next to it. This is known as crosstalk and crosstalk is similar to hearing someone elseƍs conversation that you didnƍt call on your phone. For a this is bad.  The solutions to reduce the voltage and make connections more efficient in design. HyperTransporttechnology utilizes LVDS (Low Voltage Differential Signaling). IMPLEMENTATION

Hyper Transport technology supports multiple connection topologies including daisy chain topologies, switch topologies and star topologies DAISY CHAIN TOPOLOGY Hyper transport technology has a Daisy chain topology giving the opportunity to connect multiple Hyper transport I/O bridges to a single channel. This is designed to support up to 32 devices. The Hyper transport technology tunneling feature makes daisy chains of up to 31 independently devices possible.  A Hyper Transport technology tunnel is a device with two Hyper Transport technology connections containing a functional device in between .Essentially, the Hyper Transport technology host initializes a daisy chain DAISY CHAIN IMPLEMENTATION SWITCH TOPOLGY

Hyper transport technology switch is a device designed for use in latency sensitive environments supporting multiple processors or special purpose processors. These processors are designed to increase available band widths Hyper transport technology switch passes data to and from one Hyper transport chain to another. In Switch topology device is inserted in to the chain allowing it to be branched. This device is invisible to the host controller which believes that the devices on the chain are daisy chained. SWITCH CONFIGURATION STAR TOPOLOGY

 Daisy chain configurations offer linear bus topologies much like network ³backbone,´ and switch topologies expand these into parallel chains, a star topology approach that distributes Hyper Transport technology links in a spoke fashion around a central host or switch offers a great deal of flexibility HYPERT TRANSPORT STAR CONFIGURATION

HyperTransport signs up further support Monday 15 July 2002 10:02  Eleven companies have joined the HyperTransport Technology Consortium, bringing the total of participating companies to 51. It is just under a year since Advanced Micro Devices formed the group to promote its HyperTransport interconnect technology.  HyperTransport technology enables pointpoint--toto-- point highhigh--speedspeed data exchange between integrated circuits on chips. DataData--transmissiontransmission speeds of up to 12.8Gbps in a 3232--bitbit HyperTransport I/O link can be reached using the technology, compared with 266Mbps using older technologies. HyperTransport allows for simultaneous and bibi--directionaldirectional exchange of data, whereas older technologies only allowed data to flow in one direction at a time. HyperTransportƛ Technology: Optimized for Digital V A  Digital video and audioideo applications & areudio putting strains on PC systems like never  before. System performance is pivotal for compressing digital video and audio into  smaller, more manageable sizes and for rendering effects. For consumerconsumer--levellevel systems,  the processor and accompanying system architecture must be able to decompress data  pumped into the system, move it quickly between the processor and memory so the  stream can be rendered with realreal--timetime special effects,effects, and then recompress the stream into  a suitable format for output. In professional systems, the movement of large uncompressed video within the system is the issue. HyperTransportƛ Technology Solution  The corecore--logiclogic architectures of today, particularlyparticularly the interfaceinterface between the  Northbridge and the , do not support isochronous data transfers in which data  packets are timetime--dependentdependent and must be streamed in a way that ensures fluid playback.  Lack of isochronous support is the leading cause for the inconsistent playback and jittery  images of digital video and the stuttering of digital audio. Another issue is the lack of  concurrency in todayƞs interfaces. The inability to transfer data simultaneously in both  directions is a major limiting factor in nonnon--linealinearr video editing, whether using a softwarebased solution that taxes the processor and memory, or a hardwarehardware--basedbased solution that reliesrelies on a dedicated capture card.  When using a hardwarehardware--basedbased solution, the systemmust be capable of handling very large files while maintaining a continuous,uninterrupted flow of data both to and from the drive. SoftwareSoftware--basedbased solutions make thisequation even tougher. HyperTransportƬ I/O technology supports both isochronous and concurrent connections and has the capability to handle very large amounts of data at very high speeds.  HyperTransport technology, thanks to its highhigh-- bandwidth, low latency  connections, isochronous transport system, and support for concurrent communications,  offers the bandwidth and performance necessary for the next generation of digital video  and audio. HyperTransport technology provides backwards compatibility for PCI  software, drivers, and operating systems, while helping to eliminate bottlenecks and  providing the bandwidth necessary for future highhigh--speed chips and interconnects  standards.

Low latency Physical layers

 A high performance clock forwarded architecture like delivers low latency at the physical layer.A single forwarded clok is used per set of 8 data path bits along with a skewskew--constrainedconstrained PCB.  This enables very low latency pointpoint--pointpoint data transfer  Conversely other chipchip--toto ƛƛchipchip interconnect technologies like PCIPCI--ExpressExpress use non skew constrained PCBs and clock encoded links Low Latency DataLink and Transaction Layers  Adding to its low latency capability,Hyper transport interconnects also feature very efficient datalink and transaction layers due to low packet overhead.Infact Hyper transport requires just 8 bytes for a write operation and just 12 bytes for a read operation.  In case of PCI it is 12(write)12(write)--16(read)16(read) bytes

Applications

 FrontFront--sideside bus replacement  Multiprocessor interconnect  Router or switch bus replacement CONCLUSION

 Although HyperTransport is an excellent technology with many performance benefits there is still a place in the market for other technologies. Engineers need to consider their needs carefully to choose the technology that is right for a specific application.  introduced this Hyper Transport (HT) technoloy in P4 Processor to enhance its processing speed. This technology forces the OS to see TWO Different processors though it is ONE. So it handles the given task more efficiently & quickly