Submitted by, Divya.C.Babu Jyothi Karthika.M.S S5MCA LMCST CONTENTS Introduction Causes for the development Hypertransport technology solutions Features Design goals Overview System design easier Conclusion HISTORY In many of today's computers the data transfer capability is the limiting factor for overall system performance. One solution for higher data transfer rates is called HyperTransport. Most users will recognize this from some AMD products. In fact, HyperTransport was invented at AMD (with help from some industry partners) although it is now managed and promoted by an independent group called HyperTransportConsortium The first product to use HyperTransport technology was a HyperTransportHyperTransport--toto--PCIPCI bridge chip, announced in the sprispringng of 2001. INTRODUCTION Hyper transport technology is very fast ,low latency point to point link It is designed to increase the commercial speed between integrated circuits in computers,servers,embedded systems etc This technology is also used in networking and telecommunications equipment This reduces the number of buses in the system This was invented by AMD and licenced by Hyper transport technology consortium AMD's HyperTransport --originallyoriginally named Lightning DDataata Transport (LDT) --isis an internal chipchip--toto--chipchip interconnect that provides much greater bandwidth for I/O, coco-- processing and multimulti--processingprocessing functions. HyperTransport supports unidirectional pointpoint--toto--pointpoint links in each direction and is capable of achieving a bandwidth of up to 6.4 GBps per connection. HyperTransport provides a more than a 20x increase in bandwidth compared with current system interconnects that are capable of running at up to 266 MBps. Hyper transport technology is designed to: Support both CPUCPU--toto--CPUCPU communication as well as CPU to i/o transfer Provide significantly more band width than current technology Use low latency response and low pin count Appear transparent to operating system and offer little impact on peripheral devices CAUSES LEAD TO THE DEVELOPMENT OF HYPER TRANSPORT TECHNOLOGY I/O band width problem High pin count Higher power consumption While microprocessors continues to double every eighteen months the performance of I/O bus architecture has lagged, doubling in approximately every 3 months OOver the past 20 years a number of legacy buses are there. They are ISA,VLISA,VL--BUS,AGP,LPC,PCIBUS,AGP,LPC,PCI 32/33,PCI32/33,PCI--XX These buses have emerged that must be bridged together to support varying array of devices These new technology is responsible for increasing demand for additional bandwidth Technologies like high speed networking and wireless communication allows the devices to exchange growing amounts of data High pincounts increases RF radiation which makes it difficult for the system designs to meet FCC and VDE requiremnets Reducing pincoutns helps system designer to reduce power consumption and meet thermal requirements In response to these problems AMD began to develop Hyper transport I/O link architecture in 1997 HyperTransport is a pointpoint--toto--pointpoint interconnecting system focused on chipchip--toto--chipchip communications. From its inception it has been designed to offer high speeds and low latency. This is a requirement today and into the future as CPU clock speeds continue to increase. ChipChip--toto-- chip communication especially demands low latency and high performance. Being a pointpoint--toto--pointpoint interconnect technology, as opposed to a bus system, offers many advantages for chipchip--toto--chipchip communication. One advantage is that the communication signals do not require multiplexing. Also, these communication signals experience less interference and therefore experience less noise and can be transmitted with less power. This all combines for faster, and cleaner, communications. Another advantage of a pointpoint--toto--pointpoint technology is that it does not suffer from degraded performance, as PCI buses do, as the number of devices connected increases. HyperTransport utilizes a direct connection between two devices only. More devices can be connected only by utilizing a daisy chain method. This means that the performance is the same as more devices are connected. FEATURES Packet Based HyperTransport is packetpacket--based.based. This allows HyperTransport to play the interconnect role for many different purposes. This technology can be used to interconnect processing cores, RAM and CPU, or even external memory equipment.. Since the HyperTransport technology is packetpacket--based,based, the hardware that is interconnected forms what most would consider a network. In the case of a supersuper--computercomputer having a network of processors interconnected with a pointpoint--toto--pointpoint technology can be very beneficial Low Packet Overhead HyperTransport required an 8 byte read request control packet for read operations. For write operations, HyperTransport uses an 8 byte write request control packet with and a 4 byte read response packet. This is it. That is all the overhead; 8 bytes for a read operation and 12 bytes for a write operation. PCI Express requires 20 to 24 bytes of overhead for its read and write operations. This is obviously a major advantage for HyperTransport. With HyperTransport, the data packet which follows the control packet(s) can only be from 4 to 64 bytes. The data packet for PCI Express can be up to 4096 bytes. So, in some instances PCI Express can have a lower packet overhead than HyperTransport Bandwidth HyperTransport was originally designed to offer significantly higher bandwidth than other competing technologiestechnologies..OneOne way ititdoes this isisto provide aaDouble Data Rate (DDR).. (DDR) Normally when data isisdigitally transmitted between two points, data isisread as either high or low which represents either aa 11or 00..This data isisread whenever the clock produces aahighhigh signalsignal..With DDR, data can be read on the rising and falling edges of aaclockclock signalsignal..ThisThis means that ininone full clock cycle aaDDRDDR capable transmission data can be read twice, producing twice the data rate.. rate Low Latency Low Latency is a design parameter which has been a focus of the HyperTransport technology since the beginning. HyperTransport can achieve this in part by having a single clock signal per set of 8 data bit paths. This is significant because other technologies, such as PCI Express, have their clocks embedded in a complicated encoding/decoding scheme at both ends of the data link. The method used by HyperTransport is effective in reducing the latency when compared to other technologies because the transmitting device does not need to spend time encoding the clock and the receiving device does not need to spend time decoding the clock. Priority Request Interleaving Another aspect of HyperTransport which contributes to its high performance is what they call Priority Request Interleaving (PRI). This is a really cool idea. Figure 2 below shows how PRI works. The problem PRI solves is this: When the CPU is in the midst of a long communication sequence with peripheral device B and peripheral device A needs to communicate with the CPU device A will normally need to wait until device B is finished communicating in order to proceed with its own communication; this can take quite some time and obviously reduce the overall performance. PRI technology allows peripheral device A to insert a PRI packet into the data stream of device B. This PRI packet is read by the CPU which can then commence a communication sequence with device A on a different link channel HYPER TRANSPORT TECHNOLOGY SOLUTIONS Hyper transport technology is formerly codenamed Lightning Data Transfer [LDT] This is to provide high speed, high performance,point to point link for interconnecting IC on the board Both infiniband and high speed ethernet are high speed networking protocol but this technology supports ³In the box´ connectivity This technology is targeted at networking,telecommunication, embedded applications etc This technology implements Fast switching mechanisms, So that it provides low latency as well as high band widths This also supports plug & play features and PCI like enumeration DESIGN GOALS 1.1. Improve system performance 1.1. Simplify system design 1.1. Increase I/O flexibility 1.1. Maintain compatibility with legacy system 1.1. Ensure extensibility to new system network architecture buses 1.1. Provide highly scalable multiprocessing systems OVERVIEW Architecture of hyper transport I/O link can be mapped into 5 different layers similar to OSI reference model 1.1. Physical layer 1.1. Data link layer 1.1. Protocol layer 1.1. Transaction layer 1.1. Session layer Physical layer This layer defines the physical and electrical characteristics of the protocol. This layer interfaces with the outside world ±± Commands, addresses, and data (CAD) all use the ssamamee set of wires for signaling, dramatically reducing pin requirements. ±± Enhanced LowLow--VoltageVoltage Differential Signaling ±± The signaling technology used in HyperTransport ttecechnologyhnology is a type of low voltage differential signaling (LVDS ). However, it is not the conventional IEEE LVDS standard. It is an enhanced LVDS technique developed to evolve with the performance of future process technologies. This is designed to help ensure that the HyperTransport technology standard has a long lifespan. LVDS has