1 Digital Equipment Corporation Maynard, Massachusetts mamDomo

Reference Manual

;1 PDP-15 Systems

-

DEC-15-BRZA-D

PDP-15 SYSTEMS REFERENCE MANUAL

DIGITAL EQUIPMENT CORPORATION 0 MAYNARD. MASSACHUSETTS 1st Printing August 1969

Copyright © 1969 by Digital Equipment Corporation

Instruction times, operating speeds and the like are in­ cluded in this manual for reference only; they are not to be taken as specifications. TABLE OF CONTENTS

Chapter Page

General Description

Introduction 1-1 PDP-15 Highlights 1-1 Summary of PDP-15 Characteristics 1-2

2 PDP-IS System Organization

Central Processor 2-1 Memory 2-1 I/O Processor 2-1 System Peripherals 2-3

3 Organization of the Central Processor

Summary of Characteristics 3-1 Central Processor Description 3-1 Processor Expansion 3-4

4 Memory Organization

Summary of Characteristics 4-1 Core Memory 4-1

5 Organization of the Input/Output Processor

Summary of Characteristics 5-1 I/O Processor 5-1 Addressable I/O Bus 5-7 Program Interrupt Facility 5-9 Automatic Priority Interrupt 5-10 Common I/O Bus 5-12 IOP1, IOP2, IOP4 5-13

6 Addressing

Interpretation of Words From Memory 6-1 Information Retrieval From Memory 6-1 Memory Reference Instructions 6-2 Bank Mode Addressing 6-5 Nonmemory Reference Instructions 6-5 Operate Instructions 6-5 Data Words 6-6 Basic Software Floating-Point Formats 6-7 Boolean Representation 6-8

iii TABLE OF CONTENTS (cont.)

Chapter Page

7 Instruction Repertoire

Instruction Groups 7-1 Transfer Instructions 7-3 Arithmetic Instructions 7-3 Logical Instructions 7-4 Rotate Instructions 7-S Control Instructions 7-S Jump Instructions 7-7 Index and Limit Register Instructions 7-9 Register Control Instructions 7-10 Microcoding 7-11 Input/Output Instruction Group 7-13

8 Internal Options Instruction Set

EAE 8-1 Basic Shift Instructions 8-4 Normalize Instructions 8-6 Arithmetic Instructions 8-7 Automatic Priority Interrupt Instruction Set 8-13 Memory Parity 8-lS Real-Time Clock 8-16 Power Failure 8-16 Memory Protection Option 8-17 Memory Relocation and Protect KT IS 8-19 The Hardware 8-21

9 Peripheral Options

Standard Input/Output Devices 9-1 Mass Storage Devices 9-1 Line Printers and Plotters 9-3 Data Communications Devices 9-3 Display Devices 9-4 Interprocessor Buffer Systems 9-S Analog-to-Digital Converters 9-S Digital-to-Analog Converters 9-6 Operational Amplifier, Type AH03 9-6 I/O Bus Adapter, Type DWIS 9-6

10 PDP-IS Console

Information/Control Switches 10-1 Operate Control Switches 10-3 Special Switches 10-4 Indicators 10-4

iv TABLE OF CONTENTS (cont.)

Chapter Page

11 System Software

PDP-15/10 Compact Software System 11-1 PDP-15/20 Advanced Monitor System 11-2 Common PDP-15 Software 11-3 PDP-15/40 Disk-Oriented BACKGROUND/FOREGROUND System 11-7 Additional Systems Software 11-7 Diagnostics 11-9

Appendix

A Installation Planning

Physical Configuration A-I Placement of Options A-I

v PDP-15 FAMILY OF MANUALS

HARDWARE SOFTWARE

INSTALLATION ACCEPTANCE OPERATORS TE ST GUIDE MANUAL PROCEDURES

MODULE INTERFACE MANUAL MANUAL

~.

UTILITY PROGRAMS MANUAL

MACRO -15 FORTRAN nz::

FOCAL -15 8/15 TRANSLATOR

15-0040 SYSTEM REFERENCE MANUAL - Overview of PDP-15/10 SOFTWARE SYSTEM - COMPACT VOLUME 3, PERIPHERALS (Set of Manuals) - PDP-15 hardware and software systems and op­ software system and BASIC I/O Monitor system Block diagram and functional theory of operation tions; instruction repertoire, expansion features descriptions. of the peripheral devices. Preventive and correc­ and descriptions of system peripherals. tive maintenance data.

USERS GUIDE VOLUME 1, PROCESSOR - PDP-15/20 ADVANCED Monitor Software Sys­ INSTALLATION MANUAL - Power specifica­ Principal guide to system hardware includes sys­ tem - ADVANCED Monitor System descriptions; cations, environmental considerations, cabling tem and subsystem features, functional descrip­ programs include system monitor and language, and other information pertinent to installing tions, machine-language programming consider­ utility and application types; operation, core or­ PDP-15 Systems. ations, instruction repertoire and system expan­ ganization and input/output operations within sion data. the monitor environment are discussed.

ACCEPTANCE TEST PROCEDURES - Step-by­ step procedures designed to insure optimum VOLUME 2 PERIPHERALS - Features function­ PDP-15 Systems operation. tiona I descriptions and programming consider­ PDP-15/30 BACKGROUND / FOREGROUND ations for peripheral devices. Monitor Software System - Background/Fore­ ground Monitor description including the asso­ ciated language, utility and applications pro­ MODULE MANUAL - Characteristics, specifica­ tions, timing and functional descriptions of mod­ grams. OPERATOR'S GUIDE - Procedural data, includ­ ules used in PDP-15 Systems. ing operator maintenance, for using the oper­ ator's console and the peripheral devices asso­ ciated with PDP-15 Systems. -< .-..-.. . INTERFACE MANUAL - Information for inter­ PDP-15/40 Disk-Oriented BACKGROUND/ facing devices to a PDP-15 System. FOREGROUND Monitor Software System - PDP-15/10 SYSTEM USER'S GUIDE - COM­ Background/Foreground Monitor in a disk-ori­ PACT and BASIC I/O Monitor operating proce­ ented environment is described; programs include dures. language, utility, and application types. UTILITY PROGRAMS MANUAL - Utility pro­ grams common to PDP-15 Monitor systems.

PDP-15/20 SYSTEM USER'S GUIDE - Advanced monitor system operating procedures. MAINTENANCE MANUAL VOLUME 1, PRO­ MACRO-15 - MACRO assembly language for the CESSOR - Block diagram and functional theory PDP-15. of operation of the processor logic. Preventive and corrective maintenance data. PDP-15/30 SYSTEM USER'S GUIDE - Back­ ground/Foreground monitor system operating FORTRAN IV - PDP-15 version of the FOR­ procedures. TRAN IV compiler language.

VOLUME 2, PROCESSOR OPTIONS - Block PDP-15/40 SYSTEM USER'S GUIDE - Disk­ diagram and functional theory of operation of FOCAL-15 - An algebraic interactive compiler­ oriented background/foreground monitor system the processor options. Preventive and corrective level language developed by Digital Equipment operating procedures. maintenance data. Corporation. PDP-iS System

viii FOREWORD

PDP-IS Systems offer comprehensive solutions cations programs and special peripheral device to real-time data problems. They combine new handlers without forcing him to become a sys­ design concepts with a wide array of traditional tems programmer and (c) a system that can features that spring from Digital's years of expand naturally with any additional hardware leadership in the medium-scale scientific com­ the user purchases. PDP-IS Systems software puter field. Both elements share the common allows the user to move from a very basic purpose of simplifying the user's tasks in a machine to a sophisticated system environment demanding real-time environment. without the cost and complication of repro­ gramming at each upward step. Since certain types of data-handling tasks re­ The hardware systems were designed with sever­ quire specific hardware and software configura­ al functional objectives in mind. Among these tions, Digital has developed four standard are the complete autonomy between central PDP-IS Systems, ranging in power from the processor, input/output processor, and memory, modestly priced basic PDP-IS / I 0 to the real­ so that processing and I/O operations can occur time disk monitor environment of the concurrently in overlapping cycles; TTL PDP-IS/40. At every level, the capabilities of the integrated-circuit construction for high relia­ hardware are under the control of a monitor bility; fast internal speeds, including an 800-ns designed specifically for them. memory cycle time, to meet the demands of real-time data processing; core memory expan­ The software systems were designed around the sion to 131,072 words for future growth; and a hardware with the user environment in mind. sophisticated memory-protect system for multi­ The principal design objectives were to provide user integrity. Peripheral device handling and (a) a system that is convenient for the user to interfacing to other instruments are easily implement and that affords the user access to accomplished, and system growth potential is the full power of the hardware, (b) a system virtually unlimited with the modular structure that allows the user to easily integrate his appli- of PDP-IS Monitor systems.

ix I

SYSTEM DESCRIPTIONS Users are spared the task of writing system software to handle input/outputs to all standard system peripherals, since appropriate routines PDP-IS/1O: Basic System are supplied with the monitor. The net result is that even inexperienced computer users can get The PDP-IS II 0 is the first level PDP-IS System. their applications programs "on the air" in a The system's design provides limited budget minimum of time. users access to the power, speed, and 18-bit word length of PDP-IS hardware, in the expec­ PDP-IS /20 hardware facilities include not only tation that the system can later be expanded to 8,192-words of core memory and high-speed take full advantage of the advanced software paper-tape facilities but also a DECtape control capabilities inherent in the system's design. unit and two tape transports for convenient mass-memory storage. DECtape is Digital's com­ Hardware includes 4,096 18-bit words of core pact, inexpensive answer to the problems of memory and a Model ASR33 Teletype console program and data storage. A single pocket-sized teleprinter. The system has the rapid PDP-IS reel of tape can accommodate up to ISO,OOO 800-ns memory cycle time which provides 1.6-Ms words of information. The extra-heavy duty add capability. Facilities for later expansion are K S R 3S Teletype unit is included in the prewired into the system; additional memory PDP-IS/20 configuration to guarantee a high and peripherals can be plugged in as they are degree of reliability under the strain of con­ required. tinued heavy use. Also included is the extended arithmetic element described in Chapter 3. This Software is governed by the COMPACT Pro­ unit facilitates high-speed multiplication, divi­ gramming System, a complete package including sion, shifting, normalization, and register mani­ Assembler, Editor, Octal Debugging Technique, pulation. and mathematical and utility routines. All are designed to function in a 4096 word system. The IS /20 Advanced Monitor System provides The software offers complete upward compati­ not only mass-memory supervisory control but bility at the source level and field-proven relia­ also complete device independence, so that pro­ bility. Programs written for execution under grams need not be limited to the use of certain COMP ACT may also run, with little or no specified input/output devices. Simple I/O state­ modification, within all PDP-IS system levels up ments control data handling; and the selection through PDP-IS/30 and PDP-IS/40 BACK­ of physical devices is determined at run time on GROUND/FOREGROUND systems. the actual machine, not when the program is written. This system also allows for easy integra­ tion of real-time I/O level subroutines as new PDP-IS/20: Advanced Monitor System devices are added.

PDP-IS/20 is an 8,192-word mass storage ori­ The Advanced Monitor permits two types of ented system designed for research and engineer­ user interaction. These are (a) batch processing ing environments where real-time data acqui­ for routine production jobs and (b) keyboard sition and control tasks are combined with interaction so that the user operates the system program development and testing. with simple commands typed at the keyboard.

Program development, debugging, and modifi­ Other Advanced Monitor features which utilize cation are all handled under monitor control, processor options, include a real-time clock con­ virtually ending intermediate operations. Unique trol and a priority interrupt control. real-time input/output routines can also be in­ tegrated into the system monitor to accelerate All Advanced Monitor functions, and the variety set-up and recovery. of additional system software routines available,

x have a single aim: to make the system as necessary for concurrent processing of back­ approachable as possible to users who want ground and foreground tasks. "hands-on" interaction, yet as automatic as possible in terms of taking care of routine In addition to the Advanced Monitor programs elements in programming. and routines, PDP-I5/30 users (and all other PDP-I5 system users) can draw on the consider­ able program library and applications knowledge PDP-15/30 BACKGROUND/ of DECUS (the Digital Equipment Computer FOREGROUND System Users Society), the second largest and most active computer users' group in the world. The PDP-I 5 /30 System was designed to meet DECUS members share in the exchange of pro­ the demands of research, engineering, and grams a nd technical papers at regularly industrial environments, where one or more scheduled meetings throughout the year. Pro­ real-time tasks typically require continuous re­ ceedings of society meetings are published and sponsiveness from the computer but do not use distributed to members under Digital sponsor­ 100% of its capacity. ship.

Under the control of the PDP-I5/30 BACK­ PDP-15/40 Disk-Oriented BACKGROUND/ GROUND/FOREGROUND Monitor, real-time FOREGROUND System tasks are handled in the computer foreground and have immediate call on the system's re­ PDP-I5/40 Disk-Based Background/Foreground sources via interrupts. Background time (time System fulfills the demands of industrial and left over between service calls for the real-time engineering environments where the need for a tasks) is available for program development and background/foreground mode of operation is testing or other lower priority computation. compounded by the necessity for large random­ access files. The PDP-15/30 Background/Foreground system contains 16,384 words of core memory and all The PDP-I5/40 System with 24,576 words of the devices standard for the PDP-I5/20. In core memory, high-speed paper"tape facilities, addition, PDP-I5/30 Systems are equipped with and DECtape storage, also incorporates a DEC­ a memory protect system, a real-time clock, disk control and two random access DECdisk automatic priority interrupt, a third DECtape files. The two disks, whose storage capacity of transport and a second on-line teletype for 524,288 18-bit words can be expanded to background use. 2,097,152 words, permit high-speed overlays The Background portion of the PDP-15/30 chaining and system and user loading. System encompasses the Advanced Monitor functions and capabilities: Macro assembler Other hardware features of the PDP-I5/40 in­ (MACRO-15), FORTRAN IV, FOCAL-15, EDIT, clude a memory protect system, background DDT (Dynamic Debugging Technique), DUMP Teletype and a real-time clock. for off-line debugging, PIP-15 for in terdevice file transfers, S-GEN (System Generator), link­ The Disk-Oriented BACKGROUND/ ing and loading, and interactive file access. In FOREGROUND Monitor System handles all the addition, the BACKGROUND/FOREGROUND functions of the 15/30 BACKGROUND/ Monitor contains all the supervisory controls FOREGROUND Monitor in an open/ended high-speed disk environment.

xi

CHAPTER 1 GENERAL DESCRIPTION

INTRODUCTION accomplished through the use of an effective, asynchronous, request scheme. This subsystem Digital Equipment Corporation's PDP-IS Sys­ autonomy facilitates wide-scale expansion of the tems are 18-bit fixed word-length, general pur­ system, increased throughput, high capacity, re­ pose, binary digital computers. These systems liability and maintainability. With this approach, are highly reliable, flexible, and complex tools there is no concern about obsolescence; new which, together with their monitor systems and subsystems incorporating the latest develop­ line of peripherals, can be used to help solve ments in computer technology can be added such diverse problems as data acquisition, pro­ readily, without affecting either program com­ cess control instrumentation, scientific computa­ patibility or the operation of other subsystems. tion and man-machine communications. Central Processor Autonomy - The full capa­ This manual furnishes the reader with enough bility for controlling and executing the stored background information to familiarize himself program is centered in the system's Central with the PDP-IS System's present and potential Processor. The Central Processor, by virtue of its capabilities. control autonomy, coordinates its own opera­ tion with that of other subsystems, thus pro­ viding supervisory control over the PDP-IS. PDP-IS HIGHLIGHTS As the main unit in this integrated control, the Central Processor contains arithmetic and con­ Complete System Autonomy trol logic hardware for a wide range of opera­ tions. These include high-speed, fixed-point The basic PDP-IS System has an organization arithmetic with a hardware multiply and divide consisting of three autonomous subsystems - option, extensive test and branch operations Central Processor, Memory, and I/O Processor - implemented with special hardware registers, each with independent timing and control logic. high-speed input/output instructions, and other Communication between these subsystems is arithmetic and control operations.

1-1 The basic processor includes a number of major Hardware Reliability, Maintainability and Low registers for processor-memory communications, Cost a program counter, an accumulator, an index register and a limit register. Two 18-bit registers A combination of such engineering considera­ are used for memory buffer functions. This tions as worst-case design criteria for propaga­ allows for processor overlap with memory cycle tion delays, over-voltage and over-current pro­ time, and effects faster instruction execution tection, point-of-load regulator cards, minimal times. cable lengths, and extensive control panel (where twenty-four 18-bit groups of signals can Memory Autonomy - Independent read/write be displayed including all major registers and control and buffer logic in each memory bank buses), proven TTL logic, single time-state establishes complete autonomy for the memory. stepping and automatic checkout procedures This means that memories of different cycle provide the PDP-IS with two key characteristics. times can be used together, and also provides for It is an extremely reliable and easily maintain­ the expansion beyond 32,768 words. able digital computer.

Input/Output (I/O) Processor Autonomy - The I/O Processor has prime responsibility for con­ SUMMARY OF PDP-IS CHARACTERISTICS trolling intercommunications between external system devices and the PDP-IS Memory or Description - Programmed Data Processor - fixed Central Processor. This third autonomous sub­ 18-bit word length, parallel mode, autonomous system of the PDP-IS System contains eight operation, TTL circuitry. data channels which may use either single-cycle block transfer devices or multi-cycle devices. Instruction List - Five basic instruction groups: The I/O Processor also contains an addressable I/O bus and provisions to add a real-time clock Memory Reference and an automatic priority interrupt system. Operate Input/Output Transfer The I/O Processor operates in parallel with the Register Control/Transfer system's Central Processor and grants external Extended Arithmetic Element devices access to PDP-IS Memory through the single- or multi-cycle data channels. Core Memory - 800-ns magnetic core memory expandable to 32,768 words; expansion with 4096 word pages or 8192 word memory banks; Real-Time Capabilities independent bank read/write control; provision for expansion beyond 32,768 words to 131,072 The unique combination of a powerful processor words built in. and a very fast autonomous I/O section with such real-time features as an 8-level, 32 channel, Fixed Point Arithmetic (J's and 2's Comple­ automatic priority interrupt system coupled ment) - 18-bit ADD in 1.6 J1S 18-bit multiply* in with a range of monitor systems, gives the user 7.0 J1S, 18-bit divide* in 7.2S J1S. exceptional real-time capabilities on his PDP-IS. Addressing - Single level indirect addressing; direct addressing to 4,096 words, indirect ad­ System Reliability dressing to 32,768 words, indexed to 131,072 words. In bank mode, direct addressing to 8,192 To ensure system reliability, options such as words and indirect to 32,768 words. power fail detection, memory relocation, mem­ ory protection and memory parity are all avail­ able on the PDP-IS System. *With extended arithmetic element.

1-2 Indexing - 1 index register, 8 auto-increment Non-Existent Memory Trap - Accessing non­ locations. existent memory is sensed by a timer performing a watch-dog function. The user is informed of Input/Output - Up to 8 bidirectional channels such errors through an API (level 0) or PI communicating directly between the I/O bus interrupt. and memory; addressable I/O bus normally ser­ vices up to 42 device controllers. Real-Time Clock - Core location 00007 can be incremented by a user determined frequency. The real-time clock interrupts control the CPU Interrupt System - Basic machine has one pro­ when location 00007 overflows. gram interrupt line. As an option there is an 8-level (4 hardware and 4 software) 32-channel Peripheral Equipment - Includes paper-tape sta­ Automatic Priority Interrupt that is expandable tion, card readers, line printers, magnetic tape to eight devices per hardware leveL priority can controllers, disk systems, displays, processors, be changed dynamically under program control. A/D and D/ A equipment and communications equipment. System Console - Includes facility to display twenty-four l8-bit groups of signals including all Options - Extended Arithmetic Element. Power major registers and buses of the processor and Fail, Memory Protection, Memory Parity, Mem­ I/O section. These displays provide both pro­ ory Relocation, Real-Time Clock, Automatic gramming and maintenance information. Priority Interrupt system.

Operating Environmental Specifications

Equipment Temperature Relative Humidity

Processor 00 to 500 C 10% - 95% Typical System * 100 to 350 C 25% - 75%

*Inc1udes paper tape station, card reader, magnetic tape, line-printer, etc.

Power Requirements Average Voltage (AC) Frequency (Hz) Current (± 15%) (±2 Hz) (A)

100 50 33 115 50 30 200 50 18 215 50 17 230 50 16 120 60 29 240 60 16

NOTE Maximum average current includes the 7.5 A that two Type ASR or KSR Teletypes draw through the power control. The above figures represent average (maximum) line current of systems with memory, two Teletypes and maximum internal options connected.

1-3

CHAPTER 2 PDP-15 SYSTEM ORGANIZATION

Three autonomous subsystems - Central Proces­ MEMORY sor, Memory, and I/O Processor - operating together under console control define the The Memory, second of the three autonomous PDP-IS System. Coupled to the PDP-IS I/O subsystems, is the primary storage area for com­ Processor and serviced under the jurisdiction of puter instructions and system data. Memory is the Monitor systems, an extensive line of peri­ organized into pages which are paired into mem­ pherals including mass storage, displays, data ory banks. Each page has 4096 l8-bit binary communications and data acquisition equipment words of high-speed random-access magnetic combine to form the PDP-IS System. Figure 2-1 core storage. Each bank is an asynchronous unit illustrates the relationship of each computer of 8192 words; expansion capability to 32,768 subsystem and the peripherals to the entire words (four banks) is provided for each PDP-IS complex. System. Any word in Memory can be addressed by either the Central Processor or the I/O Processor. The CPU has provisions to address up to 131,768 words of core memory. The autono­ CENTRAL PROCESSOR my of the memory system allows mixing banks with different cycle times. The Central Processor functions as the heart of the computer by carrying on bidirectional com­ munication with both Memory and the I/O I/O PROCESSOR Processor. Provided with the capability of per­ forming all required arithmetic and logical op­ erations, the Central Processor plays the major The third autonomous subsystem satisfies the role in the control and execution of the stored peripheral data transfer needs. A diverse line of program. It accomplishes this with an extensive system peripherals available to the PDP-IS re­ complement of registers, control lines and logic quire this processor to interface three modes of gates. input/ output:

2-1 REAL TIME AUTOMATIC POWER PR lOR I T Y CLOCK FAIL EXTENDED INTERRUPT ARITHMETIC ELEMENT INPUT OUTPUT PROCESSOR

DATA CHANNELS AND ADDRESSABLE lIO BUS CENTRAL PROCESSOR

UP TO 8 DATA CHANNEL • CONTROL FOR SINGLE­ OR MULTI-CYCLE BLOCK TRANSFERS ~I __ --.J

Re _ -.l ~ PAPER TAPE STATION TU55 TU20 OR TU30 TU20 OR TU30 ...... Q -----~ 9L __ ... _

TO OTHER DEVICES

TO LI N E UN ITS

TO OTHER DEY ICES

15· 0017

Figure 2-1. System Organization

2-2 Single cycle block data transfer; blocks of eral devices, it also includes provision for such data transfer at rates up to one million options as the Automatic Priority Interrupt Sys­ words per second. tem and the Real-Time Clock.

Multicycle block data transfer; blocks of data transfer at rates up to 250,000 words SYSTEM PERIPHERALS per second for input and 181,000 words per second for output. The PDP-IS System Peripherals range from sim­ Program controlled data transfers; single ple input/output Teletypes to sophisticated in­ word transfers to/from the accumulator in teractive display processors. These peripherals the Central Processor communicate with the PDP-IS I/O Processor via one 72-wire bidirectional cable called the com­ The I/O Processor provides timing, control and mon I/O bus. data lines for information transfers between .. memory or the Central Processor and the periph- Figure 2-1 depicts the peripherals available with the PDP-IS Syst.ems.

2-3

.. CHAPTER 3 CENTRAL PROCESSOR ORGANIZATION

SUMMARY OF CHARACTERISTICS CENTRAL PROCESSOR DESCRIPTION

Description - 18-bit parallel operation, autono­ mous operation, fixed-point signed and unsigned The Central Processor (CPU) is the nerve center arithmetic (l's and 2's complement) for control and execution of stored programs. By coordinating its own operation with that of Instmction Types - other subsystems, it provides supervisory control over the PDP-IS System. Memory Reference The Central Processor contains arithmetic and Operates control logic hardware for a wide range of Register Transfer and Control operations. These include high-speed fixed-point Extended Arithmetic Element arithmetic with a hardware multiply and divide Input/Output Transfer option, extensive test and branch operations implemented with special hardware registers, Indexing - 1 index register, I limit register, 8 high-speed input/output instructions and other auto-increment locations arithmetic and control operations.

Timing - The PDP-IS Central Processor contains several major registers for processor-memory communi­ Typical Instructions Execute Time cations, a program counter, an instruction regis­ ter, an accumulator, an index register, and a 18-bit ADD 1.6 J.l.s limi t register. 18-bit Multiply* 7.0 J.l.S 18-bi t Divide* 7.25 J.l.S The CPU performs calculations and data process­ 36-bit Shift* 7.25 J.l.S ing in a parallel binary mode through step-by­ 36-bit Normalize* 7.25 J.l.S step execution of individual instructions. Both *With EAE the instructions and the data on which the

3-1 instructions work are stored in the core memory Data Switch Register of the PDP-IS. The arithmetic and logical opera­ tions necessary for the execution of all instruc­ The data switch register receives an 18-bit word tions are performed by the arithmetic unit oper­ through the console bus from data switches on ating in conjunction with central processor regis­ the console. This register buffers the informa­ ters. Figure 3-1 shows a simplified block diagram tion so that the console may either be attached of the Central Processor. to the processor or operated remotely through cabling.

Arithmetic Unit (AU) Link (L)

The PDP-IS arithmetic unit handles all Boolean This I-bit register is used to extend the arithme­ functions and contains an 18-bit, 100-ns adder. tic capability of the accumulator. In l's comple­ The arithmetic unit acts as the transfer path for ment arithmetic, the Link is an overflow indica­ inter-register transfers and shift operations. tor; in 2's complement arithmetic, it logically extends the accumulator to 19 bits and func­ tions as a carry register. The program can check Instruction Register (lR) overflow into the Link to simplify and speed up single- and multi-precision arithmetic routines. Accepts the six most-significant bits of each The Link can be cleared and complemented and instruction word fetched from memory. Of its state sensed independent of the accumulator. these bits, the four most-significant constitute It is included with the accumulator in rotate the operation code, the fifth signals when the operations and in logical shifts. fetched instruction indicates indirect addressing, and the sixth indicates indexing. Program Counter (PC)

Accumulator (AC) The program counter determines the program sequence (the order in which instructions are This 18-bit register retains the result of arithme­ performed). This 18-bit register contains the tic/logical operations for the interim between address of the memory cell from which the next instructions. instruction is to be taken. The least-significant IS bits are used for addressing 32,768 words of core memory. The remaining 3 bits provide the For all program-controlled input-output trans­ capability to address memory systems greater fers, information is transferred between core than 32,768 words. memory and an external device through the AC. The AC can be cleared and complemented. Its Operand Address Register (OA) contents can be rotated right or left with the Link (see below). The contents of the memory, The operand address register contains the effec­ buffered through the memory input register, can tive address of the location where data is cur­ be added to the contents of the AC with the rently being fetched. result left in the AC. The contents of both registers can be combined by the logical opera­ tions AND and exclusive OR, the result remain­ Memory Input and Output Buffer Register (MI) ing in the AC. The inclusive OR can be per­ and MO) formed between the AC and the accumulator switches on the operator console (through the Information is read from a memory cell into the data switch register) and the result left in the memory input register and is interpreted as AC. either an instruction or a data word. Informa-

3-2 TO MEMORY FROM MEMORY

INSTR I REGISTER I

MEMORY MEMORY OUTPUT I INPUT rf REGISTER ~ l REGI STER r--

PROGRAM DATA SWITCH I I I FR OM CONSOLE H COUNTER I I REGI STER I

OPERAND INDEX ADDRESS I I H REGISTER I I REGISTER r--

FROM I LIMIT I/O B US I REGISTER r--

L INPUT GATING J l ARITHMETIC UNI T I r------, I IJ STEP I COUNTER I

J MULTIPLIER ACCUMULATOR ~ -1 -R QUOTIENT r--

L LINK I 1 EXTENDED ARITHMETIC I LiLi~~T______...1 15-0002

Figure 3-1. Central Processor, Simplified Block Diagram

3-3 tion is read from the Central Processor into The console can be ordered in any of three memory through the memory output register different forms: a flush-mounted console which and is interpreted as either an address or a data can be covered by cabinet doors for applications word. The use of two 18-bit registers for mem­ where "hands-off" security is paramount; a ory buffer functions allows processor overlap tilted console with table; or a remote console with memory cycle time to decrease execution attached to the CPU by a single cable. The time and to allow autonomous operation of the console can be remoted up to 100 ft. CPU and memory. Some of the features of the console are:

Index Register (XR) A READ-IN switch to initiate the reading of paper tapes; REGISTER indicators and This 18-bit register is used to perform indexing REGISTER DISPLAY switches to allow operations with no increase in instruction time. continual monitoring of key points in the An indexed operation adds the contents of the system such as the accumulator, index reg­ index register to the address field of the instruc­ ister, limit register, multiplier-quotient reg­ tion operand producing an effective address for ister, program counter, memory address, the data fetch cycle. Index value can be positive interrupt status, input/output bus, or negative in 2's complement form (± 131,072). input/output address, and I/O status.

DAT A switches to establish an 18-bit data or instruction word to be read into mem­ Limit Register (LR) ory by DEPOSIT switch or to be entered into the accumulator by a program instruc­ The limit register enables a program to detect tion. loop completion. The base address of a data array is loaded into the index register and the EXAMINE switch to allow the manual ending address is loaded into the limit register. examination of the contents of any mem­ - Within an indexing loop, add to index and skip ory location.

(AXS) instruction adds a signed value (-256 1 o~ y ~ +255 10 ) to the index register and compares the sum in the index to the contents of the limit register. If the contents of the index register are PROCESSOR EXPANSION equal to or greater than those of the limit register, the next instruction is skipped. The The following additional expansions extend pro­ limit register also provides a means for magni­ cessing capabilities of PDP-15. tude comparison of values between the accumu­ lator and the limit register, through the use of a Extended Arithmetic Element (EAE) similar instruction, AAS (add to the accumu­ lator and skip). The Extended Arithmetic Element (standard on PDP-I 5/20/30/40 Systems) facilitates high-speed PDP-IS Control Console arithmetic operations and register manipu­ lations. Installation of the EAE adds an 18-bit multiplier-quotient register (MQ) to the system The PDP-I 5 's control console contains the keys, as well as a 6-bit step counter register (SC). The switches, and lights required for operator initia­ multiplier-quotient register and accumulator per­ tion, control, and monitoring of the system. Up form as a 36-bit register during shifting, normal­ to twenty-four 18-bit registers can be displayed izing, and multiplication operations. The con­ to provide the user with visual indication of all tents of the multiplier-quotient register are dis­ registers and buses. played by the REGISTER indicators on the

3-4 operator's console when the REGISTER DIS­ The protection option also provides a user/ PLA Y control is in the MQ position. The option monitor mode of operation. When in user mode, and the basic computer cycle operate asynchro­ attempted execution of any privileged instruc­ nously, permitting computations to be perform­ tions results in a trap to the monitor and a ed in the least possible time. Moreover, EAE corresponding error message. These illegal in­ instructions are microcoded so that several oper­ structions include input/output transfers and ations can be performed by one instruction to control, halts, chained executes, any references simplify arithmetic programming and reduce ex­ to the memory protect option itself, or protect­ ecution time. Worst case multiplication time is 7 ed memory. In monitor mode, all instructions /lS; division time is 7.2S /lS. The EAE is option­ are executable. ally available for the PDP-IS II O. Power Failure Protection

Memory Protection The basic PDP-IS is not affected by power interruptions of less than IO-ms duration. Active registers in the processor may lose their contents The memory protection feature, standard on when interrupts of longer duration occur, but PDP-IS/30 and IS/40 Systems, establishes a memory is not disturbed. The Power Failure background/foreground environment for PDP-IS Protection option, available for all PDP-IS processing activity by specifying the boundary Systems, provides for saving the active register between protected (lower) and unprotected (up­ contents in the event of longer power interrupts per) regions of system core memory. Allocation and the automatic restart of the system when of memory locations (in increments of 2S6 power is restored. When the line power failure words) to the protected region is dynamic and occurs, the system must be operating with the program-controlled under the Background­ program interrupt facility or the automatic pri­ Foreground Monitor. The protect feature in­ ority interrupt system enabled in order to sense creases all memory cycle times by 100 ns and the Power Failure Protection's initiation of a write cycles in user mode by an additional 100 program interrupt in time to save the register ns. contents.

3-S/3-6

CHAPTER 4 MEMORY ORGANIZATION

SUMMARY OF CHARACTERISTICS CORE MEMORY

Speed Cycle time - 800 ns The magnetic core memory is the primary stor­ Access time - 400 ns age facility of the PDP-15. It provides rapid, random-access data instruction storage for both the Central Processor and the I/O Processor. The Stack Organization - 3-wire, 3D basic PDP-I 5/1 0 Memory contains 4096 18-bit Core type - extended word locations. The content of each location is temperature 18 mil available for processing in 400 ns. A parity bit Drive Scheme - de can be added as an option to each word for parity checking during transfer of information Environment Temperature - 0 to 50°C into or out of core memory. If the parity option ambient is incorporated into a PDP-15 System, all mem­ ory banks must contain that option and memory cycle time becomes 1.0 MS. The basic subsystem Special Features Single Bus Type - Multiuser, of Memory is the bank, which is organized into bidirectional pages; each bank has two pages of 4096 words Parity (optional) each for a total of 8192 words of 3D 3-wire Bank Selection cores. Further, every bank contains a data buf­ fer, an address buffer and all the necessary read/write and control circuitry to make it an Cycle Types Read - Restore autonomous unit operating on a request/grant Clear - Write basis with either the Central or I/O Processor. Read - Pause - Write Figure 4-1 illustrates the organization of a mem­ ory bank.

4-1 I

Memory Data Transfer next step in its logical sequence of operations and perform useful functions while the write The PDP-15 Memory communicates directly half-cycle is taking place. Thus, main memory with the Central Processor and the Input/Output access operations normally cause the two proces­ (I/O) Processor through the memory bus. Data sors to wait only 400 ns. Delays caused by and instruction words of each bank are read simultaneous requests by the two processors are from and written into individual memory cells discussed later in this section. through a buffered register referred to as the memory data buffer. (See the Memory Block Read Half-Cycle - The read half-cycle copies the Diagram, Figure 4-1.) contents of the memory cell specified by the contents of the memory address buffer into the Words in a memory bank are selected according memory data buffer. If the parity option is to the address in the memory address buffer. present, a parity check bit is copied into the The 13-bit capacity of the memory address memory data buffer at the same time. buffer allows 213 or 8192 words to be refer­ enced in each bank. Write Half-Cycle - The write half-cycle copies The memory address buffer receives the memory the contents of the memory data buffer into the cell address from the Central Processor or I/O addressed memory cell. This half-cycle always Processor. The address provides the coordinates occurs in conjunction with and following a read for locating a word in a memory bank. half cycle, although there may be a "pause" between them, during which the I/O Processor Decoding of the memory address to select a can manipulate the data in its Add-to-Memory particular word location containing 18 bits is mode (see I/O Data Processor Add-to-Memory performed by the memory selection logic. Bit 5 Description, Chapter 5). of the memory cell address selects which page the cell is in, and the remaining bits select the X Parity and Y coordinates of the cell. The parity option provides core planes that have Bits 1 to 4 of the memory bus select lines are 19 bits for each word and parity checking/ used to select which bank of Memory the word generating control logic. When the parity option is in. Up to 4 banks can normally be added to is present, the accuracy of transfers to and from the PDP-I 5 , but a special provision to expand Memory is verified by means of parity checking. memory up to 16 banks can be accommodated A parity bit is added to each word stored in by the 18-bit address registers in the CPU. Memory such that the total number of 1 bits in the word, including the parity bit, is odd. For example, if the 18-bit word to be stored in Memory Cycles Memory contains an even number of Is, the parity bit is automatically made a I, and is Words are read from and written into Memory stored with the word. When the word is later by a fixed sequence of events called a memory read from Memory, the computed parity bit is cycle. The memory cycle consists of a read calculated on the basis of the content of the half-cycle and a write half-cycle. Each type of 18-bit word. The two parity bits are then com­ half cycle requires 400 ns. Thus, the effective pared, if they do not agree, the memory parity cycle time is 800 ns. For most applications, error alarm is turned on, causing a program however, the two processors initiate a memory interrupt or automatic priority interrupt re­ request and wait until the end of the read quest, or simply a Halt. half-cycle only. At this time, the desired data is available for reading or has been accepted at the All 18 bits and the accompanying parity-check memory data buffer for writing, and the Central bit (when present) are transferred in parallel Processor or I/O Processor may proceed to the (simultaneously) between the core array and the

4-2 ------PAGE 0

Y SELECTORS 4096 WORD .. SENSE AMPS a. a. DRIVERS MEMORY STACK INHIBIT DRIVERS

X SELECTORS a. DRIVERS

L..- ______r- PAGE I I I Y SELECTORS 4096 WORD SENSE AMPS 8 I a. DRIVERS MEMORY STACK INHIBIT DRIVERS I I I I I I X SELECTORS I a. DRIVERS I I L -- I I 13 BIT 18 BIT MEMORY MEMORY ADDRESS BUFFER I I ; MEMORY BUS 15-0018

Figure 4-1. PDP-IS Memory Bank

4-3 memory data buffer, as shown in Figure 4-1. Memory Multiplexer The memory data buffer is connected to the memory bus and hence to the rest of the PDP-IS The memory multiplexer allows both the Cen­ System. This is also an 18-bit parallel transfer. tral and I/O Processors to share core memory. In the event that both request a memory cycle simultaneously, the I/O Processor will be ser­ viced first and the Central Processor must wait. However, if only one processor is using Memory, Memory Modularity then both can process at the same time. For example, the Central Processor may be execut­ ing an EAE instruction while the I/O Processor transfers data out of Memory to a DECdisk. The PDP-IS/l 0 System contains one page of 4096 memory words. Additional modules Memory Relocation (pages) may be added to the system. The basic system can accommodate up to 32,768 core Memory relocation is optional on all PDP-IS memory words (eight 4K pages) in the basic Systems. This feature provides a relocation regis­ 19-in. rack mount cabinet. Expansion beyond ter and an upper boundary register to permit 32,768 words requires the addition of another hardware relocation of both system and user cabinet to the system configuration. Memory programs. It allows the relocated program to communicates with the central processor and execu te only wi thin its specified boundary; the I/O processor on the bidirectional, inter­ thereby providing protection for all other pro­ locked party-line memory bus (See Figure 4-2). grams.

1/0 BUS

8K 8K 8K 8K 110 CENTRAL MEMORY MEMORY MEMORY MEMORY PROCESSOR PROCESSOR BANK BANK BANK BANK 0 1 2 3

MEMORY MULTIPLEXER ------MEMORY RELOCATION

I MEMORY BUS IS -0003

Figure 4-2. PDP-IS Memory Bus

4-4 CHAPTER 5 .. ORGANIZATION OF THE INPUT-OUTPUT PROCESSOR

SUMMARY OF CHARACTERISTICS Device Ports - A maximum of 50 physical ports shared between the data channels and the ad­ The I/O Processor contains two subunits, the dressable I/O bus. data channel controller and the addressable I/O bus. Options - API - Eight levels of automatic priority interrupts - Four hardware levels and four software levels Data Channel Controller

Data Transfer Modes - Single and multicycle I/O PROCESSOR block transfer, memory-increment, add-to-mem­ ory The Input/Output Processor (See Figure 5-1) Data Channels - Eight standard contains the control logic and registers necessary ... to transfer up to 18 bits of parallel data on a Options - Real-Time Clock common bidirectional I/O bus. Data may be transferred directly between the I/O Processor and Memory, or between the I/O Processor and Addressable I/O Bus the accumulator (AC) of the CPU. All transfers are made on a request/grant basis, providing Features - Two cycle skip line, program inter­ complete autonomy of processors and memory. rupt, teletype interface, console interface The I/O Processor operates with a 1 I1S cycle time. The processor accesses memory through Data Transfer Modes - Program controlled data the read-pause-write cycle which produces a transfers synchronous memory cycle time of 1 I1S. While

5-1 transfers are being made between Memory and Synchronous and asynchronous devices can the I/O Processor, the CPU is free to operate be handled with equal ease. independently. Requests from the I/O Processor for memory access are, however, given priority over CPU requests by the memory multiplexer; this can cause the CPU an occasional "cycle­ Modes of Data Transfer stealing" delay. The structure of the I/O Proces­ sor provides the following benefits to the user: Peripheral devices may transfer data in anyone of three modes: single-cycle block transfers, mul­ The simultaneity of data transfers and CPU ti-cycle block transfers, and program-controlled computing permits high-speed processing to transfers. meet the demands of real-time applications.

The I/O Processor can be expanded or re­ Data Channel Controller configured at any time without major mod­ ification of the rest of the system. The data channel controller implements the first .. two modes of data transfers and in addition has User-designed or special-purpose equipment an add-to-memory mode and an increment mem­ can be easily and inexpensively interfaced ory mode. The real-time clock option is also to the system. implemented in this section.

14K 4K I r 4K 4K 1 14K 4K I 4K 4K I

MEMORY MUL TI PLEXER

TO CPU

AUTOMATIC REAL TIME PRIORITY CLOCK INTERRUPT INPUT OUTPUT PROCESSOR W -TO CPU DATA CHANNELS AND ADDRESSABLE I/O BUS

UP TO 8 DATA CHANNEL "" CONTROL FOR SINGLE- OR MULTI-CYCLE BLOCK ~ TRANSFERS , TO DEVICE CONTROLLER 15-0020

Figure 5-1. I/O Processor

5-2 Eight data channels are standard on all PDP-15 the monitor that the block transfer is complete. Systems and may serve to concurrently transfer Because these multi-cycle block transfers are data from eight different devices. Four of these completely automatic in nature and do not are normally reserved for multi-cycle block require any CPU attention except for the I/O transfers and the remaining four are reserved for transfer initialization, the CPU is free to com­ single-cycle block transfers. However, the chan­ pute while they are taking place. The only nels are designed to accept any mixture of either limi tation on simultaneity lies in the sharing of single- or multi-cycle devices. memory. The I/O Processor has first priority on memory requests and effectively "locks out" the CPU for three cycles. As data transfer rates Multi-Cycle Block Transfers approach maximum, the CPU can be completely locked out. Normally, four of the eight standard channels are used for multi-cycle block transfers. A two­ Figure 5-3 illustrates how the data channel word packet in core memory is reserved for each controller registers implement the multi-cycle of these channels: locations 30 and 31 for the transfers . • first, 32 and 33 for the second, 34 and 35 for the third, and 36 and 37 for the fourth. The two Assume the two-word core-memory packets words in the packet are used to store the "word assigned to a given multi-cycle data channel have count" (number of words to be transferred in been loaded by the respective I/O service rou­ the block), and the "current address" (where the tine. For the case of data input to memory the data is to be transferred). The I/O Processor following occurs: contains the control logic and an I/O adder to automatically fetch and increment the contents An instruction from the service routine of the two registers. enables the device controller. This allows the controller to request a data transfer from the I/O processor. Data is read into memory in three I/O Processor cycles and is read out in four cycles. (The additional cycle allows I/O bus settling and the When the device controller's data buffer settling of control gates prior to the strobing of registers are full it issues a "data channel the data word into the device buffer register.) request." Three memory cycles are required for both. Maximum input rate is 250,000 words/second The I/O Processor, if not busy, acknow­ and maximum output rate is 181,000 words/ ledges the request by returning a "data second, ensuring data transfer integrity. channel grant."

A multi-cycle block transfer, flowcharted in Figure 5-2, is initiated by an input/output in­ The device controller then generates a fixed struction after the two core registers have been code pointing to its packet address in core initiated by minus the word count and the memory. This is transmitted over the com­ current address minus one. During the first mon I/O bus address lines and is stored into cycle, the contents of the word-count register the data storage register of the data channel are incremented by one and restored. During the controller through the I/O adder. The second cycle, the current address is incremented adder is inhibited during this operation. by one and restored, in addition to being trans­ ferred to the memory address buffer of memory. The I/O Processor then generates a "mem­ During the third cycle (or fourth in the case of ory cycle request." output), the actual data transfer occurs. The I/O Processor continues to transfer data sequentially until the word-count register reaches zero, at The memory multiplexer, when ready, which time an interrupt is generated to notify acknowledges by returning a "grant."

5-3 CENTRAL PROCESSOR

PROGRAM INITIALIZES WORD COUNT AND CURRENT ADDRESS LOCATION l PROGRAM INITIALIZES DEVICE a STARTS DEVICE --- WITH INSTRUCTIONS WHEN DEVICE HAS DATA READY OR I NEEDS DATA A RE- 110 PROCESSOR QUEST IS PLACED ON THE I/O BUS WHEN THE I/O PRO- CESSOR IS READY A GRANT IS ISSUED I TO REQUESTING DEVICE

THE DEVICE • SUPPLIES THE ADD- I RESS OF THE WORD COUNT,CURRENT ADDRESS PAIR I

l DEVICE CLEARS ITS THE 110 PROCESSOR IF WORD COUNT ENABLE AFTER FETCHES ,INCRE- OVERFLOW, THEN AN CURRENT WORD MENTS, a REPLACES OVERFLOW IS SENT HAS BEEN THE WORD COUNT TO DEVICE TRANSFERRED l THE I/O PROCESSOR FETCHES,INCREMENTS, a RESTORES THE CURRENT ADDRESS ~ THE I/O PROCESSOR FETCHES DATA SPECIFIED BY TH CA, PLACES IT ON THE BUS I ~ j:HEI DEVICE STROBES THE DATA INTO ITS REGISTER

IS NO DEVICE STILL ENABLED ? SET A, PROGRAM• YES INTERRUPT TO INDICATE DONE

CPU PROGRAM• I NTER- RUPTED a NOTIFIED THAT DEVICE IS DONE 15 -0004

Figure 5-2. Multicycle Block Transfer, Flowchart

5-4 TO MEMORY BANKS 1

j I r------, + I I I I I I I DATA I STORAGE MEMORY MEMORY I REGISTER GRANT REQUEST I I I I I I I 110 ADDER REQUESTI CENTRAL GRANT PROCESSOR LOGIC

MIXER LOGIC r

BUS BUFFER

110 PROCESSOR L ______~~S.:!S2~.J

IIOOFLO FROM TOIFROM BIDIRECTIONAL DATA DATA //0 BUS I/O BUS DATA II NES CHANNEL CHANNEL ADDRESS GRANT REQUEST LI NES TO 1/0 BUS IS-0005

Figure 5-3_ Multi-Cycle Transfer Implementation

The address data in the data storage register data-channel requests and also to post an is then stored into the memory address interrupt to the Monitor. (MA) register of the memory bank I and the data (word count) from the first word This "word count" operation occurs in one I/O of the packet that the MA is now pointing processor cycle, using one memory cycle_ to, is transmitted out of memory and into the data channel controller's adder. The word count data word is incremented by During the second I/O Processor cycle, the one and stored back into memory_ If dur­ fixed code from the device controller is ing this incrementing the adder overflows gated through the adder and is incremented (indicating that the current address was the by one_ It is then transmitted to the MA last), then an I/O overflow pulse is trans­ register to point to the second word in the mitted back to the device to disable future

5-5 packet - the "current address," which is increments the current address register and the then transmitted back to the adder, incre­ word count register to provide sequential block mented by one and strobed back to mem­ transfer. . ory. During the third I/O processor cycle, the current address is strobed into the MA register to point to the data array word -CPU where the I/O data will be transferred. The PROGRAM INITIATES data is then gated from the device con­ WORD COUNT(WC) a CURRENT ADDRESS troller, through the adder, (which is inhib­ (CAl THEN ENABLES --DEVICE ited during this cycle), and into memory. TI£ DEVICE ~ DEVICE POSTS A SINGLE CYCLE RE- QUEST WHEN A memory request/grant synchronization again 1/0 PROCESSOR READY occurs; and DATA CHANNEL GRANT IS ISSUED J WHEN 110 PRO- The data in the storage register is strobed cEssoR IS READY into the data array ending the cycle. DEVICE SUPPLIES CURRENT ADDRESS AND DATA TO 110 Data output follows the same sequence, BUS, THEN INeRE- MENTS ITS WORD with the exception that one additional I/O DATA CHANNEL COUNTS processor cycle is required to allow the bus CONTROLLER RE- QUESTS MEMORY I to settle before data is strobed out of AND SUPPLIES memory and into the device. CURRENT ADDRESS AND DATA IN STOP NEXT REQUEST SEQUENCE IF WORD COUNT OVERFLOWS

Single-Cycle Block Transfers IS DEVICE YES Single-cycle block transfers, flowcharted in Figure 5-4, are used by high-speed peripherals NO that normally transfer complete records (blocks) ? lEND OF BLOCK of information, such as disks and CRT devices. TRANSFER A single cycle of the I/O Processor takes I JJ.S 15-0006 allowing a maximum transfer rate of up to one million 18-bit words per second. Figure 5-4. Single Cycle Block Transfer, Flowchart

High-speed hardware registers, designed into the device controllers of the high-speed peripherals, When the word count register overflows at the store the "current address" (the memory cell end of a block transfer, an interrupt is generated where data is currently being transferred), and to allow the monitor system to take further the "word count" (the number of words remain­ action. Typically, this action will include discon­ ing to be transferred in a block). These registers necting the device from the I/O bus or reloading are loaded by input/output transfer (lOT) in­ the device controller registers for another block structions issued by the CPU. Device testing and transfer. The maximum number of words that initialization are handled by the CPU via lOTs to may be transferred in a single-block is 32,768. provide supervisory control. A subsequent lOT initiates the data transfer. The I/O Processor Figure 5-3 illustrates how the data-channel con­ uses the current address information to address troller registers handle single-cycle transfers. core memory, then strobes the data between memory and the device controller buffer regis­ Assuming that the program has initiated the ter. Logic within the device controller then word count and current address of the device

5-6 controller, and has then enabled it, the following In add-to-memory mode, the contents of an occurs: external register can be added to the contents of a memory location in four cycles. This feature is The device controller posts a single-cycle extremely valuable in signal averaging and other data channel request to the I/O Processor. processes requiring successive sweeps for signal enhancement. The I/O Processor, as soon as it becomes available, acknowledges the request by re­ The add-to-memory operation is a combination turning a "Data Channel Grant." of multi-cycle data channel input and multi­ cycle data channel output operations. The data transmitted by the device is added to a word The device then strobes both its current read out of memory as specified by the current address and its data onto the I/O bus to the address, and the result is rewritten into the same I/O Processor. location. It is simultaneously transmitted to the device via the I/O bus. Four I/O processor cycles The data channel controller feeds the cur­ are required. rent address through its adder (which is inhibited throughout the single cycles) to the data storage register. A memory cycle is Real-Time Clock requested, and this address is strobed into a memory bank's address buffer. The data is When enabled, the real-time clock counts, in then strobed off the 18 I/O data lines and memory location 00007, the number of cycles into the memory location specified by the completed by anyone of three inputs: current address. a. The line voltage (50 or 60 Hz) During this operation, the device incre­ ments its own word count, and disables b. Any standard DEC clock may be op­ itself on overflow. It then posts an inter­ tionally installed. rupt to the monitor to indicate that its c. A user supplied TTL compatible signal operation has been completed. which can be fed through a coaxial cable to a BNC connector on the PDP-IS.

Increment Memory When location 00007 overflows, an internal program interrupt (or API request, if available) The increment memory mode allows an external is generated informing the monitor that its device to add one to the contents of any preset interval is over. The monitor must either memory location in a single cycle; this feature is disable the clock or reinitialize location 00007 most commonly employed in the accumulation to the 2's complement of the number of counts of data in histogram form. Effectively, the incre­ it needs to tally. ment memory mode simply goes through the word-count cycle of a multi-cycle channel trans­ fer, and then stops. The maximum rate at which The incrementing of location 00007 during a it can increment is 500 kHz. This feature is real-time clock request occurs via the I/O proces­ particularly useful for in-core scaling and count­ sors' increment memory facility. A real-time ing in pulse height analysis. clock request takes priority over API, Pl and lOT requests, but not over block transfers.

Add-To-Memory ADDRESSABLE I/O BUS Add-to-memory is a standard feature of the PDP-IS that adds unique capabilities to the The addressable I/O bus implements the pro­ already powerful I/O facilities. gram-controlled transfers. It also contains the

5-7 program interrupt and the automatic priority discrimination between up to 42 devices, interrupt (API) option. with bits 12 and 13 coded to select an operational mode or subdevice.

Program-Controlled Transfer c. A command code (bits 14 through 17) capable of being microprogrammed to clear Program-controlled transfers, implemented by the AC and issue up to three pulses via the input/output transfer (lOT) instructions, can I/O bus. move up to 18 bits of data between a selected device and the accumulator (AC) in the CPU. The devices involved are connected to the ad­ dressable I/O bus portion of the I/O processor. Operation Device Clear AC at Generate an lOP A total of up to 50 device controllers may be Code 70 Selection Event Time 1 2 Pulse at Event I I ~ attached to this bus and to the data channels. ,,..o----l~------,51(,.. 6--~-' 11 \ . I 2:-1 17 lOT instructions are microcoded to effect re­ sponse only for a particular device. The micro­ coding includes the issuing of both a unique I : : : : ::::: ::::::1 device selection code and the appropriate pro­ cessor-generated input/output pulses to initiate a ,L,-t IJ specific operation. For an "out" transfer, the Sub-Device Generate an Generate an Selection lOP 4 Pulse lOP 1 Pulse at program reads a data word from memory into at Event Event Time 1 the AC. A subsequent lOT instruction places the Time 3 data on the bus, selects the device, and transfers the data to the device. For an "in" transfer, the process is reversed; an lOT instruction selects Figure 5-5. lOT Instruction Format the device and transfers data into the AC. A subsequent instruction in the program transfers the word from the AC to memory. Maximum transfer rate in this mode is 100,000 words per The four machine cycles required to execute an second. lOT instruction consist of the lOT fetch from core memory (memory is not accessed thereafter As previously mentioned, lOT instructions are until completion of the lOT), and three sequen­ also used to initialize the single- and multi-cycle tial cycles each of I /-1S duration designated event channels and the transfer word count and cur­ times I, 2, 3 (lOPI through 4) (Figure 5-6). In rent address information to the single-cycle de­ lOT skip instructions, however, only lOP I is vice controllers. In addition, these instructions used. These are two-cycle instructions. Bits 14 are used to test or clear device flags, select and 17 can be coded to initiate clearing of the modes of device operation, and control a num­ AC and generation of an 10Pl, respectively, ber of processor operations. during event time 1. Bits 16 and IS can be coded to initiate generation of an IOP2 and A PDP-IS lOT instruction, Figure 5-5, contains IOP4 pulse during event times 2 and 3, respec­ the following information: tively. lOT skip instructions are micropro­ grammed to produce an lOP I pulse for testing a a. An operation code of 70s . device status flag. IOP2 pulses are normally used to effect programmed transfers of information b. An 8-bit device selection code to dis­ from a device to the processor. Because the AC criminate between up to 128 user periph­ serves as the data register for both "in" and eral devices (selection logic in a device's I/O "out" transfers, the "clear AC" microinstruction bus interface responds only to its pre­ (bit 14) is usually microprogrammed with the assigned code). In normal practice, bits 6 IOP2 microinstruction; this combination effects through I I perform the primary device clearing the AC during event time I. IOP4 pulses

5-8 are normally used to effect programmed trans­ pulse, but may not be used to initiate either a fers of information from the AC to a selected "load of" or a "read from" a device. device. These conventions do not, however, pre­ clude use of the lOP pulses to effect other lOP2 - Usually used to transfer data to or from external functions if the following restrictions the device to the computer, or to clear device's are observed. information register. May not be used to deter­ mine a "skip" condition.

The usual uses of lOPs are: lOP4 - Used only to transfer data from the computer to the device. May not be used to lOP1 - Normally used in an I/O skip instruction determine a "skip" condition or to transfer data to test a device flag. May be used as a command to or from the computer.

NEXT FETCH EVENT TIME 1 EVENT TIME 2 EVENT TIME 3 FETCH

_ 0.75_ ,- J.l.SEC -, , -,I * r-~------~------~ I I : I I I ' IOP1 I 100 n SEC :-.r -I-- I WORSE CASE I I t- J's1~-1 I : -; * r------i I I , I I ' I I ' (OP2 I 100 n SEC~-- -I-- 0.50 I ·NORSE CASE I -IJ.l.SEC I-- I ,...... -~ I ,--,* I I 100 n SEC~' I___ I I I WORSE CASE , I I I I , IIOP4 I I I L__ r-- 1.0J.l.SEC+ 1.0J.l.SEC -+- 1.0J.l.SEC+ 1.O~SEC----l

* NOMINAL PULSE WIDTH

Figure 5-6. Machine Cycles for lOT Instruction Execution

PROGRAM INTERRUPT FACILITY of I/O device flags to automatically cause a program interrupt. The CPU can continue with The program interrupt (PI) system, standard on execution of a program until a previously select­ all PDP-IS Systems, provides for servicing a ed device signals that it is ready to transfer data. peripheral device at rates up to 50 kHz. At that time, the program in process is inter­ rupted and the contents of the program counter The program interrupt (PI) facility, when en­ (15 bits), memory protect mode (1 bit) and the abled, relieves the main program of the need for link bit (1 bit) is stored in location 000000. The repeated flag checks by allowing the ready status instruction in location 00000 1 is then executed,

5-9 transferring control to an I/O service routine for This group of instructions allows the testing of lOT instructions (see Figure 5-7). When com­ peripheral devices at the programmer's option. pleted, the routine restores the system to the Normally rather than tying the processor up in a status prior to the interrupt, allowing the inter­ "wait" loop, the device signals that its buffer is rupted program segment to continue. Where ready by generating an interrupt. If it is a multiple peripherals are connected to the PI, a program interrupt, the "conditional skip" is search routine containing device-status testing used in a so called "skip chain" to find which (skipping) instructions must be added to deter­ device initiated the interrupt. Each skip instruc­ mine which device initiated the interrupt re­ tion takes 2 f.1s. quest. The program interrupt (PI) control is enabled or disabled by programmed instructions. When disabled the PI ignores all service requests, AUTOMATIC PRIORITY INTERRUPT but such requests normally remain on-line and are answered when the PI is again enabled. The automatic priority interrupt (API) system, standard with the PDP-15/30 and 15/40 Systems and optional with the 15/10 and 15/20 Systems, Mnemonic Octal Code Function ensures effic!ent handling of service requests (without any loss of data) at high rates. ION 700042 Enable the PI 10F 700002 Disable the PI The API system contains eight levels of priority. The lower four of these are allocated to the The PI is automatically disabled when an inter­ monitor systems, the upper four to the I/O rupt is granted or when the I/O RESET key (on Processor. Up to 28 indi~idual interrupts are the console) is depressed. The PI is temporarily available at the I/O processor. They share the inhibited while the automatic priority interrupt four levels of priority, with the restriction that system is processing a priority interrupt request. not more than eight may be on any given level. The PIE indicator (on the console) is lighted while the PI is enabled. A device initiates an interrupt request on its preassigned level by raising a request flag, and identifies itself by posting a unique core address. o * * 8 9 17 There is one unique core address for each of the 28 interrupts (448 through 778). This address I : , : : : : : : : : : : : : : : : I serves as the entry point (trap address) to the device's service routine. II I PC ~n"n" {Rotum ,ddee,,1 ' State of Memory Protection Mode* Each monitor API level services one interrupt Spare (Always Set) and uses a single trap address between locations L..-______Link Content 408 and 438. The monitor requests are initiated by a program issuing an ISA instruction. *Zero if respective option is not present. The I/O interrupts permit the asynchronous Figure 5-7. Program Interrupt, JMS Instruction, operation of many devices, each at its proper or CAL Instruction Storage Word Format* priority level. The software priority levels are used to establish a priority queue for the pro­ cessing of real-time data without inhibiting the Conditional Skip-On Device Status hardware interrupts to service devices.

The PDP-15 order code includes a group of instructions for testing the status of peripherals. API Hardware Instructions of this type direct the processor to skip the next instruction if the tested condition Figure 5-8 relates the activity of the Automatic is true. Priority Interrupt system from the initiation and

5-10 PRIORITY LEVEL ACCEPTANCE ...... "----- DEBREAK API --~~~

-,__ ACTIVE PRIORITY STATE ~--~~~~--~~--~ ,

~ __...l- ______...... ,...-"

,...... J.------~ " PRIORITY LEVEL 6 • PRIORITY LEVEL 7

REQUEST REGISTER

'--_~ ~ ___''-\ __ ~ ______...J

HARDWARE SOFTWARE REQUEST REQUEST

Figure 5-8. API System, Simplified Block Diagram

acceptance of the request, the servIcmg of the debreaking, will fall as long as there is no bar accepted request and the debreak from the present (i.e., no priority level set). If a lower serviced priority level. priority level is set, the debreaking will cease at that level. The request register contains eight levels; four levels are activated by the devices (hardware) on The API request register (RR) buffers the inputs the I/O bus, and four are activated under soft­ from the hardware interrupt on levels 0 through ware supervision. The hardware requests are 3 and the inputs from the monitors on levels 4 assigned the highest priority, and are demon­ through 7. Up to eight interrup,ts may be attach­ strated as requests 0, I, 2, and 3. The software ed to a single level. If two or more of these make requests are demonstrated by requests 4, 5, 6, simultaneous interrupt requests, the interrupt and 7, and are initialized by the ISA instruction with the associated AC bits set. closest to the processor is given priority. An interrupt request sets a bit in the RR according The priority level bars depict the priority level to its preassigned priority level. When the scan­ that is selected by the ISA instruction, or that is ner detects that bit, the API system signals the raised by the API control when it has granted a CPU to stop execution at the completion of its request on that specific level. The priority PL current instruction. It then gates the I/O proces­ bars indicate that any request equal to, or less sor's 15 address lines, which contain the address than (in priority), to the priority level selected of the interrupt's unique core location, into the will not be accepted. At the end of the subrou­ CPU memory output register. The CPU then tine currently being performed by an active requests a memory cycle and executes the in­ request, a debreak and restore instruction is struction it fetched from that location. During issued to lower the priority to the next selected this operation the program counter remains un­ priority level. The baU, representing the priority changed. The instruction is normally a jump to

5-11 subroutine JMS which stores the contents of the becomes necessary to move the data to memory program counter, which points to the location locations B through B + 20. The changes in the where the current program was interrupted, in routine at level 2 must be completed without the first location of the subroutine and begins interrupt once they are started. This is possible execution at the subroutine's second location. by causing the level-6 program to raise itself to The API system also sets a bit in the PL level-2 (devices on the same or lower priority corresponding to the level of the interrupt. This may not interrupt), complete the change, and prevents interrupts on the same level or lower debreak back to level-6. Note that the ISA is levels from interrupting the current interrupt. also used to trigger the API levels dedicated to The scanner continues to sample the higher software priority queues. This unique advantage levels so that higher priority devices can inter­ of this API system lies in the proper use of its rupt lower priority devices. The JMS instruction software levels. In real-time environment, it is allows nesting of all levels. At the completion of necessary to maintain data input/output flow, the interrupt subroutine, a debreak and restore but it is not possible to perform long complex (DBR) instruction must be issued to reset the bit calculations at priority levels which shut out in the PL and in the RR. these data transfers. With the API, a high­ priority data input routine which recognizes the need for complex calculations can call for a The API hardware ensures that simultaneous software-level interrupt. Since the calculation is requests by multiple devices are handled in the performed at a lower priority than the device proper priority sequence. If interrupt requests handling, the latter can go on undisturbed. The occur at different priority levels, the highest monitor task of establishing a multi-priority priority requests will be serviced first. Higher request queue at the software level is greatly priority devices may interrupt lower priority simplified by utilization of the API hardware. devices. The entire API system may be enabled or disabled with a single instruction; however, most devices provide facilities to connect and disconnect their flags from the interrupt sepa­ rately. If the API system is disabled, the device COMMON I/O BUS will automatically signal the program interrupt to obtain a response at that priority level. The I/O Processor contains a common I/O bus Under program control, the level of a priority (see Figure 5-9) to transfer both data and lOT request may be raised to provide dynamic prior­ instructions to the block transfer channels and ity reallocation. It does this by issuing an ISA. to the addressable I/O bus. The bus is the major communication path for I/O devices. It consists ISA 705504 Initiate selected activity. of cables which link all the I/O device control­ The API activity speci­ lers to a common interface point at the I/O fied by a set bit in the Processor. All signal lines for command and data AC is initiated (refer to transmission arising from the data channels, instruction set Chapter 7). addressable I/O bus, operation of the multi-level automatic priority interrupt system, program The ISA instruction places a bit into a priority interrupt, I/O status read, and I/O skip facilities, level specified. This effectively masks all lower are contained on this bus. The bus length can be priority levels. A debreak instruction (DBK) is up to 75 ft. used to reset this bit when the higher priority level is no longer required. For example: a priority-2 interrupt routine is designed to enter Data Lines data in memory locations A through A + 10 during an interim period when the priority-2 device is inactive and, based on a calculation Eighteen data lines constitute the bidirectional made by a software priority-6 routine, it facility for transferring data bytes of up to 18

5-12 - r- - r- Output Control Signals BIDIRE CTiONA L DATA TRAN SFER L INES (18) 1/0 POWER CLEAR Eight output control signals are generated to effect specific functions in a selected device. 110 SYNC PULSE

10Pt

IOP2 I/O Power Clear

IOP4 The I/O power clear signal resets all flip-flops

RE AD STA TUS storing device-to-processor flag indications (e.g., ready, done, busy). It is issued by power tum­ I/O OVER FLOW on, the occurrence of a clear-all-I/O flags (CAF) PROGR AM INT ERRUPT I REOUE ST instruction, and by actuation of the I/O RESET I SKIP REOU EST key on the control console. This pulse is also 0 I used (in conjunction with the device select lines) REA o REO UEST I P 0 to initiate automatic read-in from the selected R WRIT E REO UEST device. 0 0 INCR EMEN T MB C E CURREN T V E AOOR ESS IN HIBIT I/O Sync S OEVIC E SEL ECTION I LI NES (8) S C I/O sync may be used to synchronize I/O device ES (15) 0 ADDRE SS LIN E control timing to the processor. It is issued every R -API REO UEST LINES (4)- I/O processor cycle.

API GRANT LlNES(4)

API EN ABLE LlNES(4) 10Pl, IOP2, IOP4 · ... ATA CHA NNEL REOUEST- Microprogrammable signals are used to effect DATA CHANNE L GRANT lOT instruction-specified operation within a se­ f---DATA CH ANNEL ENABLE lected I/O device. The I/O Processor automati­ I IORU N cally generates IOP2 or IOP4 for input or output transfers. Although they may be used for other DATA OVE RFLOW control functions, the common uses of the lOPs

SINGLE CYCLE REQUEST ~ ~ are: 1~-0007

lOP1 - to test a device flag (in an I/O skip Figure 5-9. Common I/O Bus instruction). It may be used as a command pulse, but it cannot be used to initiate loading of, or reading from, a device buffer register. bits between the I/O Processor and all I/O devices. Transfers are made on a dc basis with IOP2 - to transfer data from a selected device to the processor or device allowing bus settling the processor, or to clear a device register. time before data on the lines is strobed into the receiving register. The data lines convey data between the memory buffer register and a select­ ed device buffer register for block-transfer IOP4 - to transfer data from the processor to a channel operation; they transfer data between selected device register. It may not be used to the accumulator and a selected device buffer determine a skip condition or to transfer data to register for program-controlled transfers. the processor.

5-13 Read Status The 10RS word can contain up to 18 flag bits. Those bits not used are zeroed. The presence of Read status is issued by execution of the input/ a flag is indicated by a 1 state in the correspond­ output read status (I0RS) instruction. It loads ing AC bit. the AC with an 18-bit word containing device flag indications for devices interfaced to the Switching the REGISTER DISPLAY control (on read-sta tus faciIi ty. the console) to the STATUS position simulates execution of the 10RS instruction (with the Input/Output Read Status processor in the "program stop" condition). The contents of the 10RS word (i.e., the states of The input/output read status facility provides the device flags) are displayed in the REGISTER for programmed interrogation of the status of indicators (on the console) at this time. those external devices using this facility. Upon execution of an input/output read status (lORS) I/O Overflow instruction, the states of those device flags (done, busy, not ready, etc.) interfaced to this I/O overflow is issued during the first cycle of facility by the I/O bus are transferred to specific the block-transfer operation if the contents (2's assigned bit positions of the AC. This allows the complement) of the word counter assigned to program to check for specific flag conditions or the currently active channel device becomes 0 display the flag states on the operator's control when incremented. This indicates that the pro­ console. Figure 5-10 shows the bit positions gram-specified number of words will have been associated with the commonly interfaced flags. transferred at completion of the channel transfer

Real Time Program Tape Teletype Clock Tape Reserved For Interrupt Punch Printer Overflow Reader Dectape Special Users On Flag* Flag* Flag * No Tape Flag *+ Devices

r:l n3 n5117 n9 N11 1!21131!41!5 I: 1!71 "--' '--..,..J '--' '--..,..J '--..,..J ~ _ )

Tape Teletype Light Real Time Tape Mag Unassigned Reader Keyboard Pen Clock Punch Tape *tt Flag* Flag* Flag* Enabled No Tape

* Will cause a program interrupt + Inclusive or of transfer completion and error Flags *tt Inclusive or of MTF and EF

Figure 5-10. I/O Read Status Bit Assignments

5-14 in progress. It is normally used to turn off the Write Request - This signal requests that the device, thereby preventing further channel ac­ processor execute a data-channel-write transfer tion by that device until a service subroutine of a data word into the selected device's infor­ reinitializes the channel's word-counter and cur­ mation register. rent-address registers, and the program turns on the device request flag. The overflow signal may MB Increment - This level requests that the also be used to initiate a program interrupt processor increment (by one) the contents of through the program interrupt or automatic the memory location address specified by the priority interrupt facility for access to the ini­ IS-bit address on the I/O bus address lines. tializing subroutine. Additionally, I/O overflow occurs when an I/O increment memory opera­ Current Address Inhibit - This is a special signal tion causes the location to overflow. line required by devices which automatically search for records, etc; typical are DECtape and magnetic tape. The presence of this signal level Data Overflow inhibits normal incrementing of the device­ assigned current address register during a data Data overflow is issued during the third cycle of channel transfer. a four-cycle add-to-memory data transfer when the addition operation overflows. Device Selection Levels - Identification of the current instruction as an lOT causes the bit pattern placed in the CPU MI 6 through 13 at Input Control Levels the fetch of the instruction to be bus-driven and sent via eight bus lines to device selection mod­ Six input control level signals arrive at the I/O ules contained in the control logic for each processor: device. These eight levels form a device selection code and 2-bit subdevice or mode-selection Program Interrupt Request - A device delivers code. this signal to request interruption of the pro­ gram in progress. The program traps to location 00000 when no I/O transfer action of higher Address Lines priority is in progress. The instruction resident in location 0000 1 is fetched and executed. If Fifteen lines constitute an input bus for the more than one device is connected to the pro­ devices which must deliver address data to the gram interrupt, this instruction transfers control processor. There are two uses for the address to a subroutine which determines through a bus: search process (skip chain) the device making the program-interrupt request. The appropriate a. When a device interfaced to the multi­ service routine is then accessed. level automatic priority interrupt system receives an I/O processor grant of its inter­ Skip Request - The return of this signal to the rupt request, it delivers to the CPU a processor indicates that an lOT instruction test hardware-defined address, relating to its for a skip condition in a selected device has been API channel assignment. This channel ad­ satisfied (e.g., a test of ready status). The pro­ dress indicates to the device's service rou­ gram counter is subsequently incremented by tine the location of the unique transfer one to effect a skip of the next instruction of vector. the program in progress. b. When a block-transfer channel device Read Request - This signal requests that the receives a processor grant of its transfer request, it delivers to memory a hardware­ processor execute a data-channel-read transfer of defined address indicating the memory lo­ a data word into the processor. cation of the assigned channel's word-count register.

5-15 Multiplexed Control Lines character code is over a 4-wire cable connecting the Teletype and the control, which is located in Fifteen control lines serve as processor-to­ the I/O Processor. device-control information paths, three for the block transfer channel facility and twelve for the For the ASR units the reader and keyboard are priority levels on which the automatic priority electrically tied together and the punch and interrupt system processes requests for service. printer are mechanically connected. Teletype Control lines are used in the following ways: input functions are logically separated and there­ fore the keyboard/reader and printer/punch may Request - a device transmits a service request to be considered as individual devices. The program the processor via the appropriate request line. must echo any character from the keyboard it There are four automatic priority interrupt re­ wants printed. quest lines (one for each level) and two data channel request lines (single-cycle requests and Hardware controlled read-in facilities are pro­ multi-cycle requests). vided for reading paper tape into memory via • either the ASR or the Type PC 15 High-Speed Grant - the processor indicates a grant of the Reader. This method of reading paper tape is service request. accomplished by placing the tape into the reader and pressing the READ-IN key on the console. Enable - the enable signal controls the priority A hardware program wired into the I/O Pro­ order for answering service requests of devices cessor will read the tape into memory. Control interfaced to the block transfer data channels or is then automatically transferred to the begin­ to one of the API's device channels. Priority for ning of the bootstrap program which initiates a channel (data or API) is allocated in descend­ execution. ing order from the device nearest the processor I/O bus interface. An enable signal permits servicing of the requesting device with the high­ est channel of priority and inhibits all lower­ Priority priority devices from making requests during the In view of the autonomous substructures of the interval of service. PDP-IS, three types of priority must be consid­ ered: memory access priority, priority on the common I/O bus, and priority on the use of the I/O Run CPU. The I/O Run signal is available at the interface for use as the interface designer requires. This Memory Access - The I/O Processor always has bus driven level switches to the +5V level and priority over the CPU in accessing memory. remains there while the RUN flip-flop in the However, once a CPU memory request has been CPU is set. A ground level indicates that the granted it will be allowed to complete it cycle RUN flip-flop has been cleared. (800 ns) before control can be returned to the I/O Processor.

Teletype Interface and Hardware Read-In Common I/O Bus - Prioirity on the I/O bus is of concern only when more than one device is The I/O Processor includes a Teletype control transferring information on the I/O bus and the and Teletype unit as standard input/output I/O bus requests are received by the I/O Proces­ equipment. Teletype Models Types 33 and 35, sor. The following order of priority occurs: KSR or ASR, will operate with this controller. a. Block Data Transfer Channels - The The Teletype is capable of inputting and out­ eight block data transfer channels range in putting at a rate of 10 characters per second. priority from channel I, which has the Serial transmission and reception of an 8-level highest priority to channel 8, which has the

5-16 lowest. Normally, single-cycle block trans­ existing prior to the interrupt, allowing the fer devices are placed on the high-priority interrupted program segment to continue. channels to give them preference over the Where multiple peripherals are connected multi-cycle devices. However, if the data to the PI, a search routine with device­ transfer rate of a single-cycle device is not status testing (skipping) instructions must critical, it can be placed on a lower priority be added to determine which device ini­ channel to give preference to both single­ tiated the interrupt request. and multi-cycle devices. For example, a display processor might be placed on a e. Program-Controlled Transfers at the low-priority channel, since a temporary Main Program Level. delay of data during the refresh cycle is not critical. CPU - Priority on the use of the CPU is established by the API level, the program inter­ b. Real-Time Clock - The real-time clock rupt, and the main program, in that order. has priority after the block data transfer channels. The real-time clock utilizes the I/O processor to fetch the contents of a Latency reserve core memory cell (0000078 ), incre­ ment the count, and then restore the new count. I/O transfer latency is a measure of the time between a device's request for service and the c. Automatic Priority Interrupt - The auto­ actual performance of that service. Regardless of matic priority (API) system adds eight ad­ a device's priority, once its request for service ditional levels of priority to the PDP-15. has been granted, the I/O Processor holds all The upper four levels are assigned to de­ other devices off until the current service re­ vices and are initiated by flags (interrupt quest is complete. For example, a single-cycle requests) from these attached devices. The device on data channel I requesting service just lower four levels are assigned to the pro­ after the initiation of a multi-cycle out-transfer gramming system and are initiated by soft­ would have to wait for four I/O processor cycles ware requests. The priority network insures before using the I/O bus. If a multi-cycle trans­ that high data rate or critical devices will fer request for memory comes just after a grant always interrupt slower device service rou­ to the CPU, an additional 800 ns are added to tines while holding still lower priority­ the latency. Finally, clock synchronization can interrupt requests off-line until they can be take additional time resulting in a worst case serviced. The API identifies the source of latency of less than 6 IlS for the requesting single the interrupt directly, eliminating the need cycle device. The worst-c'lse latency for each for a service routine to flag-search. peripheral (see Table 5-1) on a PDP-l 5/40 Sys­ tem (shown in Figure 5-11) with a 1000-line­ per-minute printer, PR 15 disk pack and CR03B d. Program Interrupt - The program inter­ rupt (PI) facility offers an efficient method 200-card-per-minute card reader, is shown in the of I/O servicing, if the API system is not following table. Devices are listed in the order of used. The computer continues with execu­ priority in which they are serviced. tion of a program until a previously select­ ed peripheral device signals that it is ready. With all of these devices active and transferring At that time, the program in process inter­ data concurrently, less than 50% of the I/O rupts and transfers control to a service processor capacity is utilized. The remainder is subroutine. When completed, the subrou­ available for real-time devices such as A/D and tine restores the computer to the status D/A converters as well as for graphic terminal devices and other peripherals.

5-17 Table 5-1 Worst Case Latency, PDP-15 Peripherals Maximum Worse-Case Latency Transfer Allowable Latency in this system Device Rate (in J.Ls) (in J.Ls)

RPI5 130,000* 14 7 Disk Pack word/second

RS15 62,000 16 12 DECdisk words/second

TU55 5,000 200 17 DECtape words/second

LP15 Line 1,000 lines/minute 40** 36 Printer

Real-Time 1,000 1,000 61 Clock cycles/ second

PC15 Paper 300 characters/ 3,333 62 + subr Tape System second (reader)

CR03 Card 200 cards/ 3,750 190 Reader minute

KSR 35 10 character/ 100,000 250 Teletype second

*The RPI5 is double-buffered with two 36-bit registers. Two I8-bit words are transferred back-to-back on the I/O bus.

**The LP15 transfers two l8-bit words every 40 J.LS.

5-18 REAL TIME AUTOMATIC MEMORY PRIORITY EXTENDED CLOCK PROTECT INTERRUPT AD DR ARITHMETIC INPUT ELEMENT INPUTIOUTPUT PROCESSOR OUTPUT BUS CENTRAL PROCESSOR UNIT

RPI5/RP02 TCI5ITU55 DEC DISK

RFI5/RS09

15-0029

Figure S-I1. Expanded PDP-IS / 40 System

VI I \0

CHAPTER 6 ADDRESSING

This chapter describes the PDP-IS addressing b. Those that deal with control and do not scheme and the basic data word formats. require a memory reference cycle (e.g., Shift the contents of the accumulator two binary bits to the right).

INTERPRETATION OF WORDS FROM MEMORY INFORMATION RETRIEVAL FROM MEMORY Words stored in magnetic core memory are strings of 18 bits. An instruction word is indis­ The basic concept involved in retrieving infor­ tinguishable from a data word. The Central mation from storage is that each piece of infor­ Processor which decodes and implements in­ rna tion has an address, similar in nature to a struction words, differentiates data words from street address to locate a building, or a zip code instruction words by the sequence in which they to locate a postal zone. Integer addresses ranging are retrieved from storage. The program counter from to 32,767 (or 00000 to 77777 ) are is used to point at the location of the next a 10 8 8 used by the PDP-IS to locate information in instruction. The instruction itself, if a memory Memory. Figure 6-1 shows a diagram of the reference instruction, then points to the mem­ program counter register. Bits 3 through 17 are ory location where data is to be fetched or used to address the first 32,768 core locations in stored. There are two types of instruction Memory. words:

a. Those which reference memory by indi­ Bits 3 and 4 select the memory bank being cating in the operand address field the addressed (banks I through 4) and bit S deter­ location of the data necessary to carry out mines which page (page a or page I) of that the operation (e.g., Add the contents of bank the word is in. The remaining positions of memory location 1000 to the accumu­ the address are used to select one of the 4096 lator). words on that page.

6-1 NOTE employed throughout this manual. A PDP-IS word will be construed as an instruction word The PDP-IS is designed to allow only when it has been retrieved from storage and for special expansion to 131,072 transferred into appropriate registers in the Cen­ words of Memory, so that ad­ tral Processor. dress registers such as the pro­ gram counter are 18 bits long. Bit Position

The Program Counter is an 18-bit register which points to the next instruction. This register can be loaded from the console switches to begin to 4,095 storage word address execution of the program. At the beginning of ° each instruction, the program counter is incre­ mented by one to specify the memory location 4,096 to 8,191 storage word of the next instruction. However, this incre­ address menting is performed modulo 4096. When the PC is incremented, only the 12 low-order bits ~-- 8,192 to 16,383 storage word function as a 12-bit counter. There is no over­ address flow into the high order bits.

'-----16,384 to 32,767 storage word address ° 1 3 5 6 17 I: ::::;::::: ::::: :1 Figure 6-1. Program Counter Register I.}T I Address Slgn*1 Block Page There are three fields in the memory reference Bank instruction word; the operation code, the ad­ dress mode (E Field) and the operand address field. To change pages, or banks within a 32K block, a jump indirect is normally used. To change blocks for systems greater than 32K, a jump ° 3 6 17 indexed is used. These instructions replace the contents of the program counter with IS bits or I: : : :':x: :A: : :A: : :A: : :A: I 17 bits, respectively, to effect both a new Operation I E I Address bank-page or 32K block address. Code Field Figure 6-2. Memory Reference Instruction MEMORY REFERENCE INSTRUCTIONS Format

Figure 6-2 shows the format of PDP-J S Central Processor memory reference instructions. The Operation Code Field bit positions in the I8-bit word are numbered from °to 17, counting to the right with bit 17 The 4-bit operation code occupies bits °to 3 of as the low-order bit. This convention will be the word and specifies 1 of the 13 memory reference class of instructions. The remaining *The sign bit is unused in address pointing since the three codes in the operation field are used to PDP-IS System does not reference negative memory. specify the non-memory reference instructions and are discussed later in this chapter.

6-2 Operand Address Field transferred. An indexed instruction can directly address any portion of core memory and does The l2-bit operand address field occupies bits 6 not add any additional time to an instruction's to 17. The number contained in the address field execution time. is the address of a word located in core storage (which is usually one of the operands of the

instruction; e.g., ADD Y) although this address START may be modified before it actually references a word in Memory. Since this field is 12 bits long, the instruction directly addresses 4096 words of NO Memory, or one full page.

Address Mode

The 2-bit address mode or E Field occupies bits 4 and 5. The 2-bit E Field indicates address modification as illustrated by the flowchart, Figure 6-3. There are four combinations as shown by the following: INCREMENT Addressable MEMORY LOCATION E Field Value Operation Memory ~t*

0 0 0 Direct 4K 0 0 Indexed 128K 0 0 2 Indirect 32K .8 3 Indirect· 128K .8 Indexed

*Additional time required for address modification.

E=O No Address Modification - The 12 bits in the address field point directly to the operand's ADD CONTENTS address in the current page where the data will OF INDEX either be fetched or stored. The address pointer REGISTER TO is formed in the operand address register by ADDRESS concatenating the block, bank, and page address stored in the program counter to the l2-bit address field. Since the block, bank, or page address does not change unless a field change instruction is issued Uump indirect or indexed), the term current page address always infers the concatenation process.

Figure 6-3. Address Modification Flowchart E=1 Indexed Address Modification - The con­ tent of the index register (18 bits, including sign) is added to the current page address form­ E=2 Indirect Addressing - When indirect ad­ ing the effective address where data will be dressing is indicated, the current page address is

6-3 taken as containing not the operand but an Form sum of every other word in array called indirect pointer to the location of the operand SAM; the fields are: Tag, Operation, Operand, address. Comments

Tag Operation Operand Comments

o 1 2 3 17

LAC (SAM /LOAD AC WITH /BOTTOM ADDRESS /OF ARRAY Memory Protect PAX /DEPOSIT INTO INDEX T /REGISTER Always Set Mode I ndirect Pointer LAC (SAM+N /LOAD AC WITH /NEXT ADDRESS /AFTER ARRAY PAL /DEPOSIT INTO L1. The indirect pointer is concatenated with the /MIT REGISTER current block address, bits I and 2 of the Begin CLA!CLL /CLEAR AC AND program counter, in the operand address register /L1NK Loop TAD O,X /FORM SUM to form the effective address where data is AXS 2 /ADD TWO TO INDEX transferred. A second memory reference cycle is /REGISTER AND TEST then required for obtaining the actual data. /IF COMPLETE JMP Loop /CONTINUE LOOPING HALT /LOOP COMPLETE Only one level of indirect addressing is permit­ ted. Fifteen bits of the indirect word are used as !indicates a microprogrammed operation the address, permitting 32,768 possible words in a current block to be accessed. The first three bits in the indirect pointer are used to store Auto-Increment Locations - Eight locations status information and are not used for address (108 -1 78 ) of the first 4096-word page act as formation. auto-increment registers. When indirectly ad­ dressed, the contents of an auto increment location are incremented by I and then taken as E=3 Indirect and Indexed Address Modification the effective address of an instruction. When - When both indirect and indexed addressing are directly addressed, these locations act like all indicated, the indirect operation occurs first as other memory locations. shown above. Then, the value of the index register is added to form the effective address. The auto-increment locations are used to loop through sequential data arrays. The "increment Indexing Example - The following example and skip if zero" (lSZ) instruction is used to test shows a typical use of the index register. for loop completion. The following example illustrates their use: A second register, called the limit register, (18 bits), is used to test the index register when it is Form sum of Am + Bm and store in Cm used in a loop. An "Add to Index and Skip" (AXS) instruction causes a signed eight-bit num­ ber, contained in the last eight bits of the AXS instruction, to be added to the index register. Begin CLA!CLL /CLEAR AC AND LINK The index register is then compared to the limit Loop LAC* 10 /GET ADDEND register and if the sum in the index register is TAD* 11 /FORM SUM greater than the limit register, the next instruc­ DAC* 12 [STORE SUM tion is skipped. *indicates indirect addressing

6-4 ISZ Count /TEST FOR COMPLETION output pulses (lOP) to initiate a specific opera­ JMP Loop ICONTINUE LOOPING HALT ILOOP COMPLETE tion. For an "out" transfer, the program reads a Count -N INUMBER OF ITERATIONS, data word from memory into the AC. A subse­ ITWO'S COMPLEMENT quent lOT instruction places data on the bus, 10 L(A)-l IFIRST LOCATION OF ARRAY selects the device, and transfers the data to the IA-l 11 LlB)-l IFIRST LOCATION OF ARRAY device. For an "in" transfer, the process is IB-l reversed. An lOT instruction selects the device 12 L(C)-l IFIRST LOCATION OF ARRAY and transfers data into the AC. A subsequent IC-l instruction in the program transfers the word from the AC to memory.

BANK MODE ADDRESSING I/O Pulse 1 --....., The PDP-IS can be placed into another mode of I/O Pulse 2----, addressing called bank mode addressing_ In this o I/O Pulse 4 J I mode, 8192 words of memory can be directly addressed by memory reference instructions_ This is done by allowing the fifth bit of the instruction to refer to a memory bank rather Octal Code = 70 ~ than to the index register- In this mode, all Device Selection (6 Bits) indexing operations including the use of the Subdevice Selection (2 Bits) limi t register for register-to-register compares are eliminated in favor of bank addressing_ Indirect addressing can be used. lOT instructions are also used to initialize the single- and multi-cycle channels and to transfer The program counter is incremented modulo the word count and current address to the 8192. That is, the low-order 13 bits point at the single-cycle device controllers. In addition, they address within the bank specified by the high­ are used to test or clear device flags, select order bits. When the program counter is incre­ modes of device operation and to control a mented, only the 13 low-order bits function as a number of processor operations. Within a single counter- There is no carry into the high-order lOT instruction, up to 64 unique device­ bits. To change banks, a jump indirect instruc­ selection codes are available and an additional tion is normally used. two bits form up to four subdevice commands. Three microprogrammed pulses (lOP) are also An "enable bank addressing" (EBA) instruction provided to test, initiate transfer, etc. (See the places the Central Processor in bank address lOT instruction for complete details.) mode, and a "disable bank addressing" (DBA) instruction places the Central Processor back into the page address mode where indexing can OPERATE INSTRUCTIONS be used.

Microcoded Operate Instruction NONMEMORY REFERENCE INSTRUCTIONS

Input/Output Instruction Microcoded operate instructions (operate code

of 748 ) are used to sense and/or alter the contents of the AC and Link. Typical functions lOT instructions are microcoded to effect re­ are: conditional or unconditional skips and com­ sponses for a particular device. The microcoding plementing, setting, clearing or rotating the con­ includes issuing a unique device selection code tents of the two registers jointly or independent­ and appropriate processor-generated input/ ly. A HLT instruction is included. Operates are

6-5 o 3 4 17 DATA WORDS

I >: :4: : : : : : : : : : : : : : I Memory reference instructions deal with data Operation I Microcoded Bits used for arithmetic and logical operations and Code are also used for address modifications. The following describes the data formats used in the fetched and executed in one machine cycle; the arithmetic and logical operations. actions are specified by the microprogramming of the instruction code. Each of the 13 bits can There are two types of arithmetic instructions in effect a unique response; hence they are "micro­ the PDP-IS - 2's complement and l's comple­ instructions" to the computer. The important ment. Floating point operations are provided in feature of the operate class is its micropro­ subroutines supplied with the system monitors. gramming capability which allows two or three microinstructions to be combined to form one instruction word and, therefore, to be executed Sign a = positive during one cycle. Those microinstructions that 1 = negative logically conflict and occur in the same event time should not be microprogrammed.

Index Operates Single-Precision Data

o 8 10 17

I>: : :< : : : : : : : : , : : : I Single-Precision Data Operation Code I s I signed quantity Up to 18 bits of data may be contained in a single precision PDP-IS word. Normally, 2's Index operate instructions (operate code of 728 ) complement arithmetic is used, because conven­ are used to clear, load and compare the index tion has adapted only one representation of a in and limi t registers. 2's complement notation, namely +0; l's com­ plement notation has both a +0 and a -0 that can cause ambiguity. EAE Instructions In both complement notations (I's and 2's), the o 3 4 17 sign indicator (bit 0) is a for positive quantities and 1 for negative quantities. The l's comple­ • ment of a quantity is equivalent to the logical I :< :< : : : : : : : : : : : : : I complement of its magnitude and sign; i.e., all Operation I Microcoded Bits Code binary 1s are replaced by as and all binary as are replaced by 1s. The 2's complement of the quantity is equivalent to its l's complement plus

EAE, identified by an operation code of 648 , the addition of 1 to the lowest order, or least performs high-speed data manipulation and mul­ significant, bit. Positive quantities in either nota­ tiply divide operations as specified by micropro­ tion have iden tical representations. For gramming of individual instructions. The micro­ example: + 15, 0 is represented in a PDP-IS data instructions have capabilities for register set-up, word as data shift, normalize, multiply, and divide, re­ spectively. EAE is an option on the PDP-IS /l a s System. For a complete description see the EAE 000 000 000 000 001 III instructions.

6-6 in either I's or 2's complement notation. The I's preCIsIOn data word (sign bit and 17 data bits), complement of -1S t 0 is represented by this relationship becomes:

s I I I I I I I I I I II 110 000

-131 071 t 0 < X < + 131 071 t 0

The 2's complement of -1S t 0 appears as

s Double Precision Data I I I I I I I I I III II 0 00 I A signed double-precision data word consists of A typical PDP-IS instruction sequence for form­ two computer words for a total of 36 bits ing the 2's complement of any number is: (Figure 6-4). The first word contains the sign bit and the 17 most-significant bits; the second LACY word contains the 18 least-significant bits. The TCMA words are stored in consecutively addressed core DACY memory locations for ease of programming.

The TAD (2's complement add) instruction must be used rather than the ADD (I's comple­ ment add) instruction as ADD permits an end­ 1st Word around carry into the low-order bit. o 8 9 17

Magnitudes of Data Words - For 2's complement signed notation, the permissable magnitude of II: : : : : : : :~: : : : : : : : J any quantity, X, is in the range of: most significant half Sign 0= positive I = negative where n is again the number of bits allocated to the storage of data. A single-precision data word 2nd Word has the range: o 8 10 17 I: :::: :::::: :::: : I or -13 I 072 t 0 < X < + 13 I 07l t 0 / least significant half The position of the decimal point is implied in the above ranges. Figure 6-4. Double-Precision Data Word Formats For l's complement signed and sign-and-magni­ tude notations, the permissable magnitude of any quantity, X, is in the range of: The magnitude of double precision in 2's com­ plement is where n is the number of bits allocated to the storage of data in a data word. For a single- -34,359,738,3 68

6-7 I

BASIC SOFTWARE FLOATING-POINT FORMATS

Floating-point representation of a binary num­ ber consists of two parts: the exponent and the o 1 17 mantissa. The mantissa is a fraction with the binary point assumed to be positioned between the sign bit and the most-significant data bit. The mantissa is always stored in a normalized o 17 state, i.e., leading Os are eliminated from the binary representation so that the high-order bit is always a 1. The exponent, as stored, repre­ I : : : : : : : ~a++: : : sents the power of 2 by which the mantissa is multiplied to obtain the number's value for use a. Three-Word Mode in computation.

The PDP-IS floating-point software system of­ o 17 fers two modes for storage of floating-point numbers: three-word mode and two-word mode.

The three-word mode requires three memory o 17 locations for storage of a floating-point binary number (Figure 6-Sa). The exponent, a signed IS:: : ~+ti+a :s+ {ha:ng~ if ~e~ati~e): : : I 17-bit integer in 2's complement notation, occu­ pies the first word, or memory location. The mantissa, a 3S-bit quantity in sign and magni­ b. Two-Word Mode tude notation, is stored in the second and third words. The sign of the mantissa is stored in the high-order bit of the second word. The range is Figure 6-S. Floating Point Formats ± 10 3 9 000 accurate to 9 decimal digits.

The two-word mode requires two memory lo­ BOOLEAN REPRESENTATION cations for storage of a floating-point binary number (Figure 6-Sb). The exponent, an 8-bit integer in 2's complement notation, and its sign o 17 occupy the 9 high-order bits of the first word. The mantissa, a 26-bit quantity in sign and I : : : : : : : : : : : : I : : magnitude notation, is stored in the 9 low-order bits of the first word and in the 17 low-order bits of the second word. The sign of the man­ Boolean operations use unsigned quantities. tissa is stored in the high-order bit of the second word. The range is ± 1060 with an accuracy to 6 Full l8-bit words can be ANDed or exclusive decimal digits. ORed with each other.

6-8 CHAPTER 7 INSTRUCTION REPERTOIRE

This chapter describes the instruction set of the Execll te Time The times shown herein are basic PDP-1S by function, and describes the use worst case times for a and action of each operation. The format is as system without memory follows: parity.

Mnemonic Three to six alphabet char­ acters which represent the INSTRUCTION GROUPS operation code in the MACRO-1S Assembler. Memory Reference Instructions Operation Name A description of the instruc­ tion. The specific operations of the PDP-IS instruc­ tion repertoire. are categorized into the follow­ Octal Code The machine language code mg groups: in octal notation. The symbols listed below will be Transfer Ins truc tions used where applicable. DAC Deposit Accumulator A The bits of the Address LAC Load Accumulator Field DZM Deposi t Zero in Memory

E The E Field Arithmetic Instructions

Indirect Addressing ADD Add, l's Complement TAD Add, 2's Complement x Index Addressing ISZ Increment and Skip if Zero

7-1 Logical Instructions Skip on Register Condition Instructions

XOR Exlusive OR SPA Skip if Accumulator is Posi­ AND AND (Logical Product) tive SAD Skip if Accumulator differ­ SMA Skip if Accumulator is ent from Memory Negative SNA Skip if Accumulator Not Jump and Skip Instructions Zero SZA Skip if Accumulator is Zero CAL Call Subroutine SNL,SML Skip if Link Not Zero JMP Unconditional Jump SZL,SPL Skip if Link Equals Zero JMS Jump to Subroutines Microcoded Instructions Control Instructions LAS=CLA!OAS Load Accumulator from XCT Execute Console LAS!CMA Load Accumulator from l's Complement of Console Operate Instructions CLC= Set Accumulator to all 2's CLA!CMA Rotate Instructions STL= Set the Link to I CLL!CML RAR Rotate Accumulator and STL!CLC Set Link and Accumulator Link I Right to all l's RTR Rotate Accumulator and RCL=CLL! RAL Clear Link and Rotate Left Link 2 Right RCR=CLL!RAR Clear Link and Rotate RAL Rotate Accumulator and Right Link I Left RTL Rotate Accumulator and Index and Limit Register Instructions Link 2 Left Register Transfer Instructions Control Instructions PAX Place Accumulator in Index OPR orNOP No Operation Register HLT Halt PAL Place Accumulator in Limit CLL Clear Link Register CML Complement Link PXA Place Index Register in STL or CCL Set Link Accumulator GLK Get the Link PXL Place Index Register In CLA Clear Accumulator Limit Register CLC Clear and Complement PLA Place Limit Register In Accumulator Accumulator OAS OR Console Accumulator PLX Place Limit Register in In- Switches to Accumulator dex Register lAC Increment the Accumulator SWHA Swap Halves of the Accu­ Register Control Instructions mulator LAW Load Accumulator with this AASn Add n to Accumulator and Instruction skip if result is eq ual to or CMA l's complement the Accu­ greater than Limit Register mulator AXSn Add n to Index Register TCA 2's complement the Accu­ and skip if result is equal to mulator or greater than the limit Re­ SKP Skip Unconditionally gister

7-2 AXRn Add n to the Index Register DZM Deposit Zero in Memory AACn Add n to Accumulator CLX Clear the Index Register o 3 6 17 CLAC Clear the Accumulator CLLR Clear the Limit Register 1:< :4>:e: :A: : :A: : :A: : :A: I Operation I E I Address Code Field Input/Output Instructions Execute Time: 1.6 J.1S IORS Read Flags CAF Clear All Flags The content of the memory location specified IOF Tum Interrupt OFF by the effective address is zeroed. All other ION Tum Interrupt ON registers remain unchanged.

TRANSFER INSTRUCTIONS ARITHMETIC INSTRUCTIONS

DAC Deposit Accumulator ADD ADD, l's Complement

o 3 6 17 o 3 6 17 I : : : >:e: :A: : :A: : :A : : :A : I >: :o>:e: :A: : :A: : :A : : :A: I Operation I E I Address Operation I E I Address Code Field Code Field

Execute Time: 1.6 J.1S Execute Time: 1.6 J.1S The content of the Accumulator replaces the The content of the effective address and the content of the memory location specified by the content of the accumulator are added in l's effective address. The accumulator remains un­ complement arithmetic. The results are put into changed. the accumulator.

LAC Load the Accumulator TAD ADD, 2's Complement

o 3 6 17 I >: :4>:e: :A: : :A: : :A : : :< I Operation I E I Address Operation I E I Address Code Field Code Field

Execute Time: 1.6 J.1S Execute Time: 1.6 J.1S The content of the memory location specified The content of the effective address and the by the effective address replaces the contents of content of the accumulator are added in 2's the accumulator. The content of the memory complement arithmetic. The results are put into location is unchanged. the accumulator.

7-3 ISZ Increment and Skip if Zero AND AND (Logical Product)

o 3 6 17 o 3 6 17 I :< :4>:E: :A: : :< : :A : : :A: I I >: : O>:E: :A: : :A: : :A I, : :A: I Operation I E I Address Operation I E I Address Code Field Code Field

Execute Time: 2.4 f.lS Execute Time: 1.6 f.lS The content of the memory location specified The logical product of the bits of the accumula­ by the effective address is incremented by 1. tor and the content of the memory location Two's complement arithmetic is used for the specified by the effective address replaces the algebraic sum. If the result in memory is equal content of the accumulator. to 0, the next instruction is skipped. If the result is not 0, the next sequential instruction is executed. The content of the accumulator is unchanged. Programming Note - A logical product is used to select or mask specific portions of an operand. If only a selected portion of an operand is re­ quired, it is subjected to a mask placed in the LOGICAL INSTRUCTIONS accumulator. The mask is composed of patterns of Os and Is.

XOR Exclusive OR (Half Add) The AND instruction causes the bits of the operand to appear unchanged in the accumula­ o 3 6 17 tor only in the area of the original mask of 1s bits. The AND instruction can be considered as I >: :4>:E: :A: : :A: : :A : : :A: I "both bits high." Operation I E I Address Code Field For example, to obtain the displacement address Execute Time: 1.6 f.lS for an instruction (least-significant 12 bits), the following operation would be performed. The Exclusive ORed bits of the accumulator and the content of the memory location specified by Operand Content 010110111011110101 the effective address, C(EA), replace the content Accumulator Mask 0000001 11111111111 of the accumulator. Accumulator 000000111011110101 Result Programming Note - The XOR instruction causes the operand to complement its original content only in those bits which have 1s in the accumu­ lator mask. The truth table for the XOR instruc­ The truth table for the AND instruction is as tion is - follows:

(AC) C(EA) RESULT (AC) C(EA) RESULT

0 + 0 0 0 x 0 0 0 + 1 = 0 x 1 = 0 1 + 0 = 1 1 x 0 = 0 + 1 = 0 x 1

7-4 SAD Skip if Accumulator Different RAL Rotate Accumulator and From Memory Link One Left

o 3 6 17 o 3 4 17

I >: :4>:E: : A: : :A: : : A: : : A:"] I :7: : : 4: : : 0; : : 0: : : 1: : : 0: I Operation E I I Address Operation I Microcoded Bits Code Field Code Execute Time: 1.6 JlS Execute Time: 800 ns The content of the memory location specified The contents of the accumulator and Link are by the effective address is compared algebraic­ rotated one bit to the left. Accumulator bit a ally with the content of the accumulator. If they moves into the Link, and the Link moves to are not equal, the program counter is incre­ accumulator bit 17. mented by I, and thus the next instruction is skipped. Neither the contents of the accumula­ tor nor the contents of the specified memory Rotate Accumulator and location are altered. RTL Link Two Left

o 3 4 17 ROTATE INSTRUCTIONS I >: : >: : >: : :a: : :a: : :< I Operation I Microcoded Bits RAR Rotate Accumulator and Code Link One Righ t Execute Time: 800 ns o 3 4 17 The contents of the accumulator and Link are I >: : >: : :< : >: : >: : ;0: I rotated two bits to the left. The Link moves to Operation I Microcoded Bits accumulator bit 16, accumulator bit a moves to Code bit 17 and accumulator bit 1 moves to the Link. Execute Time: 800 ns The contents of the accumulator and Link are rotated one bit to the right. The content of the Link moves into accumulator bit 0, and accumu­ CONTROL INSTRUCTIONS lator bit 17 moves into the Link.

RTR Rotate Accumulator and OPR orNOP No Operation Link Two Right o 3 4 17 o 3 4 17 7 I >: : :< : >: : ;0: : >: : ;0: I 1: : : :4: : :0: : :0: : :-a: : :0: I Operation I Microcoded Bits Operation I Microcoded Bits Code Code

Execute Time: 800 ns Execute Time: 800 ns The contents of the accumulator and Link are rotated two bits to the right. The content of the The OPR or NOP instruction causes a delay of Link moves into accumulator bit I, accumulator one cycle. The program counter is incremented bit 17 moves into bit a and bit 16 moves into and processing continues. the Link.

7-5 CML Complement the Link lAC Increment the Accumulator

o 3 4 17 o 3 4 17 I >: : :< : :< : ;0: : :a: : >: I I :< : >: : ;0: : >: : :< : ;0: I Operation I Microcoded Bits Operation I Microcoded Bits Code Code Execute Time: 800 ns Execute Time: 800ns The content of the Link is complemented. The content of the accumulator is incremented by I in 2's complement. A carry-out comple­ ments the Link. STL or (CCL) Set the Link (Clear and Complement the Link) HLT Halt

o 3 4 17

I>: : :< : >: : >: : >: : >: I Operation I Operation I Microcoded Bits Microcoded Bits Code Code Execute Time: 800ns Execute Time: 800 ns The computer is stopped and must be restarted The content of the Link is set to a one. manually by depressing the console CONTINUE or RESTART buttons. CONTINUE begins exe­ cution at the instruction immediately following CLA Clear the Accumulator the Halt instruction and RESTART loads the contents of the switch register into the location o 3 4 17 counter and begins execution at that address. I>: : >: : :a: : >: : >: : >: I CLL Clear Link Operation I Microcoded Bits Code o 3 4 17 Execute Time: 800 ns I :7: : : 4: : : 4: : : 0: : : 0; : : 0; I The content of the AC is zeroed. Operation I Microcoded Bits Code Execute Time: 800ns The con ten( of the Link is set to zero. OAS OR Console Accumulator Switches to the Accumulator SWHA Swap Halves of the Accumulator o 3 4 17 I >: : >: : >: : :< : >: : >: I o 3 4 17 Operation I Microcoded Bits Code I :< : >: : :< : >: : >: : :0; I Operation I Microcoded Bits Execute Time: 800ns Code Execute Time: 800ns The contents of the console accumulator switches are inclusive ORed with the contents of The high-order 9 bits of the accumulator (0-8) the accumulator, and the results are put into the are exchanged with the low-order bits (9-17). accumulator. The content of the Link is unchanged.

7-6 CMA One's Complement the XCT Execute Accumulator

o 3 4 17 o 3 6 17 1: 7: : :4: : :0: : :0; : :< : :1: I I >: :O>:E: :A: : :A: : :A : : :< I Operation I Microcoded Bits Operation I E I Address Code Code Field

Execute Time: 800 ns Execute Time: 800 ns + Instruction Time The content of the accumulator is replaced by [e.g. XCT (LAC A) = 0.8 + 1.6 = 2.4J1s) its l's complement; i.e., each bit in the accumu­ lator is inverted. The effective address is calculated and the In­ struction stored there is executed. The program counter remains unaltered unless the instruction TCA Two's Complement the of the effective address changes it (if it is JMP, Accumulator JMS, CAL or SKIP).

o 3 4 17 I >: : :< : :0; : >: : :< : : < I SKIP Skip Unconditionally Operation I Microcoded Bits Code o 3 4 17 Execute Time: 800 ns 7 The content of the accumulator is replaced by 1: : : :4: : :1: : :a: : :a: : :0: I its 2's complement. Operation I Microcoded Bits Code

Execute Time: 800ns Load Accumulator with LAW The next sequential instruction is uncondition­ This Instruction ally skipped.

o 3 4 17

1:< : >: : : : : : : : : : : : : I JUMP INSTRUCTIONS Operation I Microcoded Bits Code

Execute Time: 800ns JMP Unconditional Jump This instruction loads itself into the accumulator O~ N ~ 17777. o 3 6 17

Programming Note - This instruction is used for I :< :0:

7-7 JMS Jump to Subroutine instruction is skipped. If the sign is negative (1), the next instruction is executed. The content of o 3 6 17 the accumulator remains unchanged.

I >: : o>:e: :A: : : A: : : A : : : A: I Operation I E I Address SMA Skip if Accumulator is Code Field Negative

Execute Time: 1.6 f.1S o 3 4 17 The content of the program counter, the Link, and the status of the memory protect mode replace the content of the memory location specified by the effective address. The content Operation I Microcoded Bits Code of the program counter is stored in bits 3 through 17, memory protect mode in bit 2 and Execute Time: 800 ns Link in bit O. The effective address plus one The sign (bit 0) of the content of the accumu­ replaces the content of the program counter. lator is tested and, if negative (1), the instruc­ tion is skipped. If the sign is positive, the next CAL Call Monitor sequential instruction is executed. The content of the accumulator is not altered.

o 3 6 17 SNA Skip if Accumulator is Not Zero I ;0: : o>:e: :A: : : A: : : A : : : : : :< : :< : :< : :a: I CAL specifies a JMS 20 to page 0 regardless of Operation I Microcoded Bits the content of the address field. This instruction Code is used to call the monitor while the system is in Execute Time: 800 ns user mode. The address field stores information for the monitor from the user. CAL automatic­ The content of the accumulator is tested. If any ally sets the API to level 4. bits are Is, the next instruction is skipped. If all bits are Os, the next instruction is executed. The If an index bit is set in a CAL instruction, it is content of the accumulator remains unchanged. ignored; i.e., no indexing is done. An indirect bit in the CAL instruction, however, will cause a JMS 120. SZA Skip if Accumulator is Zero SPA Skip if Accumulator is o 3 4 17 Positive I: < : >: : >: : >: : >: : :a: I o 3 4 17 Operation I Microcoded Bits Code I >: : >: : :< : : < : :a: : ;0: J Execute Time: 800 ns Operation I Microcoded Bits Code The content of the accumulator is tested and if all bits are 0, the next instruction is skipped. If Execute Time: 800ns any bits are a I the next instruction is executed. The sign (bit 0) of the content of the accumula­ The contents of the accumulator remain un­ tor is tested and, if positive (0), the next changed.

7-8 SNL or SML Skip if Link Not Zero PAL Place Accumulator in Skip on Minus Link Limit Register

o 3 4 17 o 8 9 17 I>: : >: : >: : >: : >: : >: I 1 >: : :< : >: : :0; : >: : >: I Operation I Microcoded Bits Code Operation Code Execute Time: 800 ns Execute Time: 1.6 J.lS The content of the Link is tested. If it is not 0, The content of the limit register is replaced by then the next instruction is skipped. If it is a 0, the content of the accumulator. The content of the next instruction is executed. The content of the accumulator remains unchanged. the Link remains unchanged.

PXA Place Index Register in SZL or SPL Skip if Link Equal Zero Accumulator Skip on Positive Link o 8 9 17

o 3 4 17 1 >: : :< : >: : :< : >: : >: I I >: : >: : >: : >: : >: : :0; I Operation Code Operation I Microcoded Bits Execute Time: 1.6 J.lS Code The content of the index register replaces the Execute Time: 800 ns content of the accumulator. The content of the index register remains unchanged. The content of the Link is tested. If it is a 0, then the next instruction is skipped. If it is a I, PXL Place Index Register in the next instruction is executed. The content of Limit Register the Link remains unchanged. o 8 9 17 1 >: : >: : :< : >: : >: : :< I INDEX AND LIMIT REGISTER Operation Code INSTRUCTIONS Execute Time: 1.6 J.lS The content of the index register replaces the Register Transfer Instructions content of the limit register. The content of the index register remains unchanged.

PAX Place Accumulator in Place Limit Register in Index Register PLA Accumulator o 8 9 17 o 8 9 17 I>: ::<::< :;o:::a: ::a: I 1 >: : >: : :0; : :a: : >: : :< I Operation Code Operation Code

Execute Time: 1.6 J.lS Execute Time: 1.6 J.lS The content of the index register replaces the The content of the limit register replaces the content of the accumulator. The content of the content of the accumulator. The content of the index register remains unchanged. limit register remains unchanged.

7-9 PLX Place Limit Register in index register. If the sum is greater than or equal Index Register to the content of the limit register, then the program counter is incremented by 1 and thus o 8 9 17 the next instruction is skipped. I>: : >: : >: : :< : >: : :a: I Operation Code AXRn Add to Index Register

Execute Time: 1.6 MS o 8 10 17 The content of the limit register replaces the 1 content of the index register. The content of the 7 : : : : :< : , : I limit register remains unchanged. Operation Code I sin

Execute Time: 1.6 MS REGISTER CONTROL INSTRUCTIONS n, a signed 9-bit (8 bits plus sign) 2's comple­ ment integer is added to the content of the index register, and the result is placed in the AASn Add n to Accumulator and index register. Skip if Result Equal to or Greater Than Limit Register

AACn Add n to Accumulator o 8 10 17

I :< : >: : :< : : : : :< : o 8 10 17 Operation Code n Execute Time: 1.6 MS I>: : >: : >: : : : : :< : : : I n n, a signed 9-bit (8 bits plus sign) 2's comple­ Operation Code ment integer is added to the content of the Execute Time: 1.6 MS accumulator, and the results are placed in the accumulator. If the sum is greater than or equal n, a signed 9-bit (8 bits plus sign) 2's com­ to the content of the limit register, then the plement binary number, is added to the content program counter is incremented by I and thus of the accumulator, and the result is placed into the next instruction is skipped. the accumulator.

AXS n Add n to Index Register and Skip if the Result Equal to or CLX Clear the Index Register Greater than the Limit Register

o 8 10 17 o 8 9 17 I>: : >: : :s: : : : : :< : 1:< : :< : :s: : :a: : :a: : :< I Operation Code n Operation Code

Execute Time: 1.6 MS Execute Time: 1.6 MS n, a signed 9-bit (8 bits plus sign) 2's comple­ ment integer is added to the content of the The content of the index register is replaced index register, and the results are placed in the with all as. Former content is lost.

7-10 CLAC Clear the Accumulator The content of the console switches replaces the content of the accumulator.

o 8 10 17 LAS!CMA Load Accumulator From : ;0: I Console in I's Complement

Operation Code I s I o 3 4 17 Execute Time: 1.6 J,J.S I>: ::< : :< : >: : >: : :s: I The content of the accumulator is replaced with Operation I Microcoded Bits all as. The former content is lost. Code Execute Time: 800 ns The l's complement of the content of the CLLR Clear the Limit Register console accumulator switches replaces the con­ tent of the accumulator. o 8 9 17 TCA= 2's Complement the I :7: : :3: : :6: : : 0: : : 0: : : 0: I CMA!IAC Accumulator Operation Code o 3 4 17 Execute Time: 1.6 J,J.S The content of the limit register is replaced with I>: : >: : :< : :< : >: : >: I all as. The former content is lost. Operation I Microcoded Bits Code Execute Time: 800 ns MICRO CODING The content of the accumulator is replaced by its 2's complement.

Some of the preceding instructions, which do CLC= Set the Accumulator to All Ones not reference memory, can be combined by CLA!CMA inclusive ORing their codes. Figure 7-1 gives the set of all possible pairs of these instructions, and o 3 4 17 indicates which can be meaningfully combined to form higher order sets. From this figure, sets I :7: : : 4: : : 4: : : 0: : : 0: : : 0: I of triplets can also be found, to form even more Operation I Microcoded Bits complex instructions. A summary of the more Code Execute Time: 800 ns useful combinations follows. The content of the accumulator is set to all 1'so Microcoded Instructions The Link is unchanged.

LAS = CLA!OAS Load Accumulator STL= CLL!CML Set the Link to One from Console o 3 4 17 o 3 4 17 I :7: : :4: : : 4: : : 0: : : 0: : :2: I I>: : >: : >: : >: : :< : :< I Operation I Microcoded Bits Operation I Microcoded Bits Code Code Execute Time: 800 ns Execute Time: 800 ns The content of the Link is set to a 1.

7-11 Instruction Mnemonic RAL I RTL / Indicates Valid Instruction RAR / RTR / CLL / / I / I CML I .j CLA I / / / / I / lAC I I / / CMA I / I / / / / / SWHA / / / / / OAS ./ I ./ / ./ .; ./ / .j SMA j ./ / / / / / / / / / I SNA ./ / / / / ./ ./ / / / ./ ./ SPA / / ./ / / / / / / ./ / ./ I SZA / / ./ / ./ ./ ./ / ./ / / ./ / SML SNL / I / / / ./ / I I / / / / / SPL SZL / / / / / / / / / / / / / / SKP / / I / .; .; ./ .; / .; .; /

Figure 7-1. Microcoding PDP-IS Control Instructions

STL! CLC Set Link and Accumulator to GLK = CLA! RAL Get the Link All Ones

o 3 4 17 o 3 4 17 I :< : >: : >: : :0; : ;0: : >: I I >: : >: : >: : :0; : >: : :0; I Operation I Microcoded Bits Operation I Microcoded Bits Code Code Execute Time: 800 ns Execute Time: 800 ns

Both the Link and the accumulator are set to all The accumulator is cleared and the Link shifts l's. into accumulator bit 17.

7-12 RCR= Clear Link and Rotate Right INPUT /OUTPUT INSTRUCTION GROUP CLL! RAR Each internal or peripheral device is assigned a subgroup of the group of instructions called Input/Output Instructions. The format for this o 3 4 17 group is shown below:

I :7: : : 4: : : 4: : : 0: : : 2: : : 0: I Bit-14 asserted clears the accumulator be­ Operation I Microcoded Bits fore a transfer Code Bits 15, 16 and 17 select three control pulses IOP4, IOP2, and 10Pl, respectively. Execute Time: 800 ns The operate code is 70 The Link is cleared to 0, and then the Link and The device and sub device bits select the accumulator are rotated one bit to the right. device's code or address

o 6 7 8 9 10 11 12 13 14 15 16 17

Device Selection Control Pulse Selection

Clear Accumulator Subdevice Selection

Details on the use of input/output instructions its status register onto preassigned data lines. are given in the PDP-IS User Handbook or the The I/O Processor transfers these bits to the PDP-IS Interface Manual. Those instructions accumulator. Figure 7-2 shows the word/status/ which are used in the basic PDP-IS are: bit assignment.

IORS Read Flags CAF Clear all Flags

o 5 6 11 15 17 o 5 6 11 15 17 I >: : :a: : >: : >: : :< : >: I lOT Code Device Select L-J I I lOP'S lOT Code I Device Select L-J II lOP'S Subdevice Select J L Clear AC Subdevice Select J L Clear AC

Execute Time: 4 IlS Execute Time: 4 IlS This instruction gates a pulse to the I/O bus to The read flags instruction causes the transfer of initialize (clear) all flags of any device that can an 18-bit system status word from the I/O bus call for interrupt service. Customer-installed to the accumulator. During this instruction, each equipment should make use of this pulse to reset of the internal and external system devices gates flags and registers that must be cleared for system initiation.

7-13 IOF Turn Interrupt OFF NOTE

o 5 6 11 15 17 For detailed information on pro­ f I gramming with the program interrupt o facility, see the PDP-IS User Hand­ I J ! >: I book or the PDP-IS Applications lOT Code Device Select L....J II lOP'S Manual. Subdevice Select J L Clear AC

Execute Time: 4 f.1S This input/output instruction turns off the pro­ EBA Enable Bank Addressing gram interrupt facility of the exchange. o 5 6 11 15 17 ION Turn Interrupt ON I :< : >: : >: : >: : :< ! :4: I lOT Code Device Select L....J II lOP'S o 5 6 11 15 17 i I Subdevice Select J L Clear AC o I I Execute Time: 4 f.1S lOT Code Device Select L....J II lOP'S The index register is disabled and the thirteenth Subdevice Select J L Clear AC bit, normally used to indicate an indexed opera­ tion, is gated to the memory address field, Execute Time: 4 f.1S permi tting direct addressing of 8,192 words of The program interrupt facility is enabled. memory.

REAL TIME PROGRAM TAPE TELETYPE CLOCK TAPE OTHER INTERRUPT PUNCH PRINTER OVERFLOW READER DECTAPE SYSTEM ON FLAG- FLAG* FLAG* NO TAPE FLAG*t DEVICES I

TAPE TELETYPE LIGHT REAL TAPE MAG RESERVED FOR READER KEYBOARD PEN CLOCK PUNCH TAPE*tt SPECIAL USERS FLAG* FLAG* FLAG* ENABLED NO TAPE DEVICES

* WILL CAUSE A PROGRAM INTERRUPT *t INCLUSIVE OR OF TRANSFER COMPLETION AND ERROR FLAGS *tt INCLUSIVE OR OF MTF AND EF

15-0021

Figure 7-2. laRS Word Status Bit Assignments

7-14 SBA Skip if in Bank Addressing DBA Disable Bank Addressing

o 5 6 11 15 17 o 5 6 11 15 17 I >: : :a: : >: : >: : >: : >: I >: : :a: : :< : >: : :< : >: I lOT Code I Device Select L----1 I I lOP'S lOT Code Device Select L----1 I I lOP'S Subdevice Select J L Clear AC Subdevice Select J L Clear AC

Execute Time: 800 ns Execute Time: 4 J.1.S Bank address mode is disabled, and the PDP-IS If in bank addressing mode the next instruction operates with indexing and addresses 4096 is skipped. words of memory directly.

7-1S

CHAPTER 8 INTERNAL OPTIONS INSTRUCTION SET

The options available with PDp· I 5 systems and The content of the step counter is inclusively the instruction sets for each option are described ORed with accumulator bits 12 to 17, and the in this chapter. result replaces bits 12 to 17 of the accumulator. The contents of accumulator bits 0 to 11, and the step counter are unchanged. EAE

The Extended Arithmetic Element, a Central Processor option, facilitates high-speed multipli­ cation, division, shifting, normalizing and regi­ OMQ Inclusive OR Multiply Quo­ ster manipulation. Installation of this element as tient Register with the Accu­ shown in Figure 8-1 adds an 18-bit multiply mulator quotient register, step counter and additional shift logic to the arithmetic unit, shown in Figure 1-4. The instruction set associated with o 17 this unit is as follows. 1:< : >: : >: : >: : >: : :< I Control Instructions

Execute Time: 1.75 J.1s OSC Inclusive OR The Step Counter With the Accumulator The content of the multiply quotient register is inclusively ORed with the content of the accu­ o 17 mulator, and the results replace the former contents of the accumulator. The content of the I :< : :< : >: : :a: : :a: : : < I multiply quotient register is unchanged. Execute Time: 1.75 J.1S

8-1 B BUS J I J r A BUS I

r------, I I I MULTIPLIER STEP QUOTIENT I I IACCUMULAT~I I COUNTER I I D D I REGI STER 1 I LINK EAE I INHIBIT I i I I J NO SHIFT r- L OR SHIFT I LOGIC J I I L ______EXTENDED ARITHMETIC ELEMENT _-1

NO SHIFT L y OR SHIFT r LOGIC

le-0027 Figure 8-1. Simplified Arithmetic Unit With The Extended Arithmetic Element

CMQ Complement the Multiply OAC Inclusive OR Accumula'tor and Quotient Register Multiply Quotient Register

o 17 o 17 1:< : >: : >: : :a: : >: : :< I I :< : >: : >: : ;0: : >: : :a: I Execute Time: 1.75 J.lS Execute Time: 1.75 J.lS The I's complement (logical inversion) of the The contents of the accumulator and the multi­ multiply quotient register replaces the former ply quotient register are inclusive ORed, and the content of the multiply quotient register. result is placed into the multiply quotient regi­ ster. The content of the accumulator is unchanged.

ABS Replace the Contents of the Accumulator with the Absolute CLQ Clear the Multiply Quotient Value Register

o 17 o 17 :< : >: : >: : :< : >: : :a: I 1:<: >:::a:::a:: >:: >: I Execute Time: 1.75 J.lS Execute Time: 1.75 J.lS If the content of the accumulator is negative - that is, if bit 0 is a I, then the content is I's The content of the multiply quotient register is complemented (logical inversion). replaced with O.

8-2 SHL Shift Accumulator Bit Zero Microcoding in to the Link The control instructions of the extended arith­ o 17 metic element can be microcoded by ORing their instruction codes according to the chart in I :6: : : < : :0: : : 0: : : 0; : : 0: I Figure 8-2. The most useful combinations are explained in detail. Execu te Time: 1. 7 5 /1S The content of accumulator bit 0 is shifted into the Link. The content of accumulator bits 1 LACS= Load Accumulator From through 17 are unchanged. OSC!ECLA Step Counter

o 17 ECLA Clear the Accumulator

o 17 1:< : :< : :< : >: : >: : :< I I :< : >: : >: : >: : >: : >: I Execute Time: 1.75/1s Execute Time: 1. 7 5 /1S The accumulator is cleared and the content of The content of the accumulator is set to o. The the 6-bit step cou~1ter is loaded into accumulator Link remains unchanged. bits 12 to 17.

vi = Valid Combination Instruction Mnemonic

OMQ CMQ I I ECLA I I AGS I I I

OAC I ~ I ..; I

CLQ I ~ I I .;

SHAL I I ~ / I ~ /

Instruction OSC OMQ CMQ ECLA ABS OAC CLQ Mnemonic

Figure 8-2. EAE Control Instruction Microcoding

8-3 LMQ= Load Multiply Quotient BASIC SHIFT INSTRUCTIONS OAC!CLQ Register from Accumulator

LRSn Long Right Shift o 17 I :< : >: : >: : :0; : >: : ;0: I o 17 Execute Time: 1.75 f.1S I >: : >: : >: : :< : : >: : : I The content of the multiply quotient register is Execute Time: 2.75 + 0.1 25(n) replaced with the content of the accumulator. 0<; n:S:;;:; 36 The accumulator remains unchanged. The accumulator and multiply quotient registers together function as a 36-bit shift register. Their contents are shifted n-bits to the right, where n LACQ= Load Accumulator From is specified by the six low-order bits of the OMQ!ECLA Multiply Quotient Register instruction. The step counter is automatically initialized to the 2's complement of n, and shifting stops when the step counter reaches O. o 17 For each step, the content of accumulator bit 17 enters bit 0 of the multiply quotient register, 1:<::<: >:: >:::a:: >: I and bit 17 of the multiply quotient register is lost. The content of the Link, usually initialized Execute Time: 1.75 f.1S to 0, remains unchanged, but enters bit 0 of the The content of the accumulator is replaced with accumulator at each step. The action is represen­ the content of the multiply quotient register. ted below: The multiply quotient register remains un­ changed. o 17 0 17 Accumulator Memory Quotient Lost Register GSM= Get Sign and Magnitude ABSSHAL of Accumulator

o 17 LLSn Long Left Shift I :< : :< : :< : ;0: : :< : :a: I o 17 Execute Time: 1.75 f.1S >: : >: : :a: : >: : : >: : : I The content of accumulator bit 0 is entered into Execute Time: 2.75 + 0.125(n) f.1s the Link, leaving the accumulator unchanged. O:S:;;:; n:S:;;:; 36 Then, if the sign bit (bit 0) is a 1 (negative), the accumulator is l's complemented. The accumulator and multiply quotient registers together function as a 36-bit shift register. Their An instruction which could prove useful in contents are shifted n bits to the left where n is diagnostics is a combination of CLQ OAC ECLA specified by the six low-order bits of the instruc­ OMQ. In this case, the content of the accumula­ tion. The step counter is automatically initial­ tor is loaded into the multiply quotient register, ized to the 2's complement of n, and shifting and then back to the accumulator. The content stops when the step counter reaches O. For each of the accumulator now reflects what was step, bit 0 of the memory quotient register loaded into the multiply quotient register. The enters bit 17 of the accumulator, the content of code is 653002. accumulator bit 0 is lost, and the content of the

8-4 Link, usually initialized to 0, remains unchanged automatically initializing to the 2's complement but enters bit 17 of the multiply quotient of n, reach O. For each shift, the content of the register. Shifting is illustrated below. Link, usually initialized to 0, enters bit 17 of. the accumulator. The bits shifted out of accu­ mulator bit 0 are lost. This action is illustrated o 17 0 below: Lost Accumulator o 17 Lost ~I Accumulator I.. Link ALSn Accumulator Left Shift

o 17 I :< : >: : >: : >: : : >: : : I Microcoding The shift instructions can be microcoded with Execute Time: 2.75 + 0.125(n) JIS certain functions to form more complex instruc­ O~n~ 18 tions. Figure 8-3 lists all possible combinations. The content of the accumulator is shifted n posi­ The event time column indicates which function tions to the left; where n is specified by the six is carried out first during the execute cycle. low-order bits of the instruction word. Shifting Some of the most useful combinations are de­ stops when the contents of the step counter, scribed below.

Instruction V = Indicates Valid Comb ina tion Mnemonic

LLS

ALS

CLO I I I SHAL I ../ I ABS I I I OMQ j I I ECLA I I

Instruction Mnemonic LRS LLS ALS

Figure 8-3. Shift Instruction Microcoding

8-5 LASS n=LRSn SHAL Long Right Shift where n is the number of shifts required to Signed complete the normalize. The accumulator and o 17 multiply quotient registers together function as a 36-bit shift register. Their contents are shifted I :< : >: : I left until: >: : >: : : >: : : a. The content of accumulator bit 0 is Execute Time: 2.75 + 0.125(n) J.ls different from the content of accumu­ O~ n ~ 36 lator bit 1, or The content of accumulator bit 0 enters the Link. Then a long right shift instruction is car­ b. The content of the step counter ried out. (Note that the content of the Link en­ reaches O. ters accumulator bit 0.) The content of the 6-bit step counter, which specifies the step count, is automatically ini­ LLSSn=LLSn SHAL Long Left Shift Unsigned tialized to 448 or 361 0 by the content of the six low-order bits of the instruction. For each shift o 17 step, the content of bit 0 of the multiply quotient register enters bit 17 of the accumu­ I :6: : >: : >: : :< : : >: : lator, and the content shifted out of accumulator bit 0 is lost. The content of the Execute Time: 2.75 + 0.125(n)s Link, usually initialized to 0, enters bit 17 of the O~ n ~ 36 multiply quotient register. If shifting halts be­ The content of the accumulator bit 0 enters the cause accumulator bit 0 does not equal bit 1, the Link. Then a long left shift instruction is carried step counter reflects the number of steps exe­ out. Note that the content of the Link enters cuted to reach that state. Its content (2's multiply quotient bit 17. complement of step count plus the steps exe­ cuted) is accessible with either the OSC or LACS instruction. The NORM operation is indicated ALSSn=ALSn SHAL Accumulator Left below: Signed o 17 o 17 0 17 :< : >: : >: : :< : : >: : : I Multiply Quotient Register Execute Time: 2.75 + 0.125(n) o ~ n ~ 18 The content of accumulator bit 0 enters the Link. Then a long accumulator left shift takes '------.,~ Stop Step Counter ~Step Counter place. Note that the content of the Link enters I accumulator bit 17. This normalize instruction can be combined with the control instruction SHAL, to form a NORMALIZE INSTRUCTIONS normalize signed instruction.

NORM Normalize NORMS Normalize, Signed

o 17 o 17 1:< : >: : >: : >: : >: : >: I I :< : :< : >: : :< : >: : >: I Execute Time: 2.75 + 0.125(n) J.lS Execute Time: 7.25 J.lS

8-6 The content of accumulator bit 0 enters the formed in the accumulator and the multiply Link. The accumulator remains unchanged. quotient register. The most significant 18-bits Then a normalize is carried out. Note that the are contained in the accumulator, and the least content of the Link enters bit 17 of the multiply significant bits in the multiply quotient register. quotient register. Prior to this instruction, the Link must be zeroed, the multiplier entered into the accumu­ lator, and the multiplicand into the address ARITHMETIC INSTRUCTIONS following the MUL instruction.

Multiply At the beginning of a MUL execution, the multiplier is transferred to the multiply quotient register, the accumulator is cleared, and the step MUL Multiply counter is initialized to the 2's complement of 228 (1810 steps) from the six low-order bits of the MUL instruction word. The execution, a o 17 multiplication of one unsigned quantity by an­ other (18 bits, binary point of no consequence) I :< : >: : >: : :< : >: : :< I halts when the step counter reaches O. The Execute Time: 7.0 fJ.S .content of the Link remains 0, the content of the register containing the multiplicand, the one The content of the memory location which following the MUL instruction, remains un­ follows immediately after the MUL instruction changed, and the program continues from the is multiplied with the content of the accumu­ following instruction (two locations after MUL). lator. A double length (36-bit) product is The process is illustrated below:

-- Memory -~:>--+I k!=1<:=----Central Processor Before After

Bits a 17 a 17 a 17 100/MUL X Multiplier PROD UeT 101/ Multipland I I GJ I I I I Accumulator Link Accumulator Multiply I02/Next Set Quotient Instruction to Register Zero

Signed multiplication can be carried out by Register Content using the MUL instruction with the ABS instruc­ Y-4 DACY Store absolute tion and converting the multiplicand into its value of multi­ absolute value. This is done as follows: plicand in Y Register Content Y-3 LAC Load multiplier Multiplier into accumulator Put the Multi­ Y-6 LAC Y-2 ABS Store sign in EAE Multiplicand plicand into the sign bit and con­ accumulator vert Multiplier to Y-5 GSM Stored sign in absolute value Link and Con­ vert

8-7 Y-l MUL Multiply two ab­ This is a combination of MUL and ABS. In solutes; l's com­ signed multiplication, it is assumed that a GSM plement results instruction has already been performed on the if Link differ. multiplicand. See explanation for MUL. Y Multiplicand

DIY Divide Unsigned

The results are illustrated below o 17 a. Memory Location Y Location Y I :< : :4: : : 0: : : < : >: : >: I Absolute Value Execute Time: 7.25 J.l.S S Multiplicand 0 r- of multiplicand 1 The content of the memory location Y which follows immediately after the DIV instruction I S divides the contents of the accumulator and ~l 1 1 multiply quotient register (an unsigned 36-bit link dividend). The resulting quotient appears in the multiply quotient register, and the remainder is in the accumulator. b. Memory Location Accumulator Prior to this instruction, the Link must be S2 Multiplier Absolute Value zeroed, and the dividend must be entered into of Multiplier the accumulator and multiply quotient register. This is done with a LAC (least significant half), LMQ, LAC (most significant half) sequence. If EAE Sign Bit the divisor is not greater than the accumulator portion of the dividend, divide overflow occurs (the magnitude of the quotient exceeds the c. o 17 o 1 17 0 17 18-bit capacity of the multiply/quotient re­ gister) and the Link is set to a I signaling this 10 Absolute Value IX I 0 IAbsolute valuel = roduct overflow condition. In this case, the data in the Accumulator Multiply­ accumulator and multiply quotient registers is of Quotient no value. Register A valid division halts when the step counter,

initialized to the 2's complement of 23 8 (1910 If the EAE sign bit =1= Link, l's complement the steps) by the six low-order bits of the instruc­ product. Clear EAE sign bit in either case. tion, counts to O. The divisor remains unchanged in core, and the program resumes at the next The MUL and ABS instructions can be micro­ instruction - two after the DIV. The process is coded to become the MULS instruction which is indicated below. called Signed Multiply.

MULS Signed Multiply Pre-execu tion L AC,MQ Y o 17 A B

:< : >: : >: : >: : >: : >: I o 35 o 17 Execute Time: 7J.l.s

8-8 Post -execution magnitude) by the contents of memory location (no overflow) Y (the divisor). The resulting quotient appeal'S in the MQ with the algebraically determined sign ill. L AC MQ Y MQo bit 0 and the magnitude (1 's complement) in MQ bits 1 through 17. The remainder is in the r Q B AC with AC bit 0 containing the magnitude (1 's 0 complement). The address of Y is taken to be 0 17 0 17 0 17 sequential to the address of the DIVS instruc­ tion word. The contents of Yare taken to be the absolute value of the divisor; the contents of the (overflow) Link are taken to be the original sign of the divisor (DIVS assumes previous execution of an L AC,MQ Y EAE GSM instruction). Prior to this DIVS in­ struction, the dividend must be entered in the meaningless B AC and MQ (LAC of least significant half, LMQ, and LAC of most significant half). The MQ o 35 o 17 portion of a negative dividend is 1's comple­ mented prior to the division. If the divisor is not greater than the AC portion of the dividend, Instruction Sequence: divide overflow occurs (magnitude of the quotient exceeds the 17 bit plus sign capacity of the MQ), and the Link is set to one to signal the Memory overflow condition; data in the AC and the MQ Location Contents are of no value. A valid division halts when the step counter, initialized to the 2's complement Y-4 LAC Dividend (least of 23 8 (1910 steps), counts up to 0 (the six significant low-order bits of the DIVS instruction word specify the step count). The content of the Link Y - 3 LMQ is cleared to O. The contents of Yare un­ changed. The program resumes at the next Y - 2 LAC Dividend (most instruction (memory location Y + 1). significant half)

Y - I DIV Pre-execution L AC,MQ Y Y Divisor A 10 I IBI Y + I Next instruction G Isisl 012 35 o 17

*original sign of B DIVS Signed Division

Post-Execution o 17 (no overflow) I>: : >: : >: : >: : >: : >: I MQ Y L AC

J,J.S S r Q 0 I B I Execute Time: 7.25 01 1 I lSi I 1 I Divide the contents of the AC and MQ (a 36-bit o 1 17 o 1 17 0 1 17 signed dividend with the sign in ACo and bits 0 and 01, and the remaining 34 bits devoted to (S=Sign A) (S=Sign A V L)

8-9 (overflow) this instruction, the contents of the Link must be 0, and the dividend must be entered in the L AC,MQ Y AC (the set-up phase of FRDIV clears the MQ). meaningless 0 I B I If the divisor is not greater than the dividend, 0] I I divide overflow occurs (magnitude of quotient o 35 0 17 exceeds the 18-bit capacity of the MQ), and the Link is set to 1 to signal the overflow condition; data in the AC and the MQ are of no value. A Instruction Sequence: valid division halts when the step counter, ini­ tialized to 23 8 (1910 steps), counts up to 0 (the six low-order bits of the FRDIV instruction Memory word specify the step count ). The contents of Location Contents the Link remain O. The contents of Yare unchanged. The program resumes at the next Y -7 LAC Divisor instruction (memory location Y + 1).

Y - 6 GSM

Y - 5 DAC Divisor in Y Pre-Execution

Y-4 LAC Dividend (least L AC MQ Y significant half) A xxx I B Y - 3 LMQ 0 I 0 17 35 0 17

Y - 2 LAC Dividend (most Post-Execution significant half) (no overflow) Y - 1 DIVS L AC MQ Y Y Divisor (absolute value) ~ U I Q I I B 17 0 17 0 17 Y - 1 Next Instruction o (Overflow)

FRDIV Fraction Divide Unsigned L AC,MQ Y I meaningless B o 17 o 35 o 17 I :< : :s: : >: : :< : >: : >: I Execute Time: 7.25 J1S Memory Location Contents Divide the contents of the AC and the MQ (AC contains an 18-bit fractional dividend, MQ is Y - 2 LAC Divident zeroed at setup) by the contents of memory location Y (the divisor). The binary point is Y - 1 FRDIV assumed at the left of AC (bit 0). The quotient appears in the MQ; the remainder is in the AC. Y Divisor The address of Y is taken to be sequential to the address of the FRDIV instruction word. Prior to Y + 1 Next Instruction

8-10 FRDIVS Fraction Divide Signed Post-Execution (No overflow) o 8 9 17 L AC MQ Y I >: : :< : >: : >: : >: : >: I G I,----,-sI----.l r II s I Q I I 0 I B I o 17 0 1 17 0 1 17 Execute Time: 7.25 iJ.S Divide the contents of the AC and the MQ (AC (s = Sign A) (s = L V Sign A) contains a signed fractional dividend, MQ is zeroed at set-up) by the contents of memory location Y (the divisor). The binary point is (Overflow) assumed between AC bit 0 and AC bit 1. The resulting quotient appears in the MQ with the L AC,MQ Y algebraically determined sign in MQ bit 0 and the magnitude (l's complement) in MQ bits 1 Q meaningless I ,--IO_I_B--JI through 17. The remainder is in the AC with bit o 35 0 1 17 o containing the original sign of the dividend and bits 1-17 containing the magnitude (l's complement). The address of Y is taken to be sequential to the address of the FRDIVS instruc­ Instruction Sequence: tion word. The contents of Yare taken to be the absolute value of the divisor; the contents of the Memory Link are taken to be the original sign of the Location Contents divisor (FRDIVS assumes previous execution of an EAE GSM instruction). Prior to this FRDIVS Y - 5 LAC Divisor instruction, the dividend must be entered in the AC (the set-up phase of FRDIVS clears the MQ Y-4 GSM and l's complements the dividend, if negative, prior to the division). If the divisor is not greater Y - 3 DAC Divisor (abso­ than the dividend, divide overflow occurs lute value) in Y (magnitude of the quotient exceeds the l8-bit capacity of the MQ) and the Link is set to 1, to Y - 2 LAC Dividend signal the overflow condition. Data in the AC and the MQ are of no value. A valid division Y - 1 FRDIVS halts when the step counter, initialized to the 2's complement of 23 8 (1910 steps), counts up to 0 Y Divisor (absolute (the six low-order bits of the FRDIVS instruc­ value) tion word specify the step count). The contents of the Link are cleared to O. The contents of Y Y + 1 Next Instruction are unchanged. The program resumes at the next instruction (memory location Y + 1).

IDIV Integer Divide Unsigned Pre-Execution

L S AC MQ Y o 8 9 17

[:] I S I A I xox 1 1L...- 0 ...... 1 _I_B1_____ I :-< : >: : >: : >: : >: : >: I o 1 17 35 0 17 Operation Code

*original sign of B Execute Time: 7.25 iJ.S

8-11 Divide the contents of the AC and the MQ (AC IDIVS Integer Divide Signed is 0, MQ contains a l8-bit integer dividend) by the contents of memory location Y (the divisor). The resulting quotient appears in the MQ; the o 8 9 17 remainder is in the AC. The address of Y is taken to be sequential to the address of the IDIV instruction word. Prior to this instruction, I >: : :< : >: : >: : :< : :< I the contents of the Link must be 0, and the Operation Code dividend must be entered in the AC (the set-up phase of IDIV transfers the dividend to the MQ Execute Time: 7.25 J..I.S and clears the AC). Division overflow occurs only if division by 0 is attempted; i.e., the Divide the contents of the AC and the MQ (AC quotient's magnitude will not exceed the l7-bit is 0, MQ contains a signed integer dividend by plus sign capacity of the MQ. The division halts the contents of memory location Y (the divisor). when the step counter, initialized to the 2's The resulting quotient appears in the MQ with the algebraically determined sign in MQ in bit 0 complement of 23 8 (1910 steps), counts up to 0 (the six low-order bits of the IDIV instruction and the magnitude (l's complement) in MQ bits word specify the step count). The content of the 1-17. The remainder is in the AC with AC bit 0 Link is cleared to O. The contents of Yare containing the sign of the dividend and AC bits unchanged. The program resumes at the next 1-17 containing the magnitude (1's comple­ instruction (memory location Y + 1). ment). The address of Y is taken to be sequen­ tial to the address of the IDIVS instruction word. The contents of Y are taken to be the Pre-Execution absolute value of the divisor; the contents of the Link are taken to be the original of the divisor L AC MQ Y (lDIVS assumes previous execution of an EAE A xxx B GSM instruction).Prior to this IDIVS instruc­ ~ tion, the dividend must be entered in the AC 0 17 35 0 17 (the set-up phase of IDIVS transfers the divi­ dend to the MQ, clears the AC, and l's Post-Execution complements the MQ if the dividend is nega­ L AC MQ Y tive). Divide overflow occurs only if division by o is attempted; i.e. the quotient's magnitude will not exceed the l7-bit plus sign capacity of the B W GJ Q MQ. The division halts when the step counter, 0 17 0 17 0 17 initialized to the 2's complement of 23 8 (1910 steps), counts up to 0 (the six low-order bits of If Y = 0 (overflow) the IDIVS instruction word specify the step count). the contents of the Link are cleared to AC,MQ Y L O. The contents of Yare unchanged. The pro­ I meaningless o gram resumes at the next instruction (memory IT1 location Y + 1).

Instruction Sequence: Pre-Execution Memory Location Contents L AC,MQ Y Y - 2 LAC Dividend 8Is\A\ xxx I I 0 I IB I Y - 1 IDIV 0117 35 0 17 Y Divisor Y+l Next Instruction *original sign of B

8-12 Post-Execution AUTOMATIC PRIORITY INTERRUPT INSTRUCTION SET L AC MQ Y

SPI ~ L.--Is ",,--I --,r I 1s I Q 110\ IBI Skip on Priorities Inactive

o 17 0 1 170 1 17 o 5 6 11 15 17 (s=Sign A) (s=L V Sign A) I >: : >: : >: : >: : :a: ! >: I lOT Code Device Select L-.J II lOP'S If Y = 0 (overflow) Subdevice Select J L Clear AC L AC,MQ Y Execute Time: 2 J.ls I meaningless I This instruction compares a condition code in the accumulator with part of the ENABLE bit and priorities active register. If any bit of the condition code matches the corresponding bit of Instruction Sequence: the ENABLE or priority active register and both are set, the next instruction is skipped. Other­ Memory wise the next instruction is executed. The corre­ Location Contents sponding bits are shown below. Y - 5 LAC Divisor

Y-4 GSM ISA Initiate Select Activity

Y - 3 DAC Divisor (abso­ lute value) in Y o 5 6 11 15 17 Y - 2 LAC Dividend 1:< : >: : >: : >: : :< : :< I lOT Code Device Select L-.J II lOP'S Y - 1 IDIVS Subdevice Select J L Clear AC Y Divisor (absolute value) Execute Time: 4 J.lS The content of accumulator bit 0 is placed into Y + 1 Next Instruction the ENABLE flip-flop; accumulator bits 6

2 3 4 5 6 7 8 9

Priorities Active API ENABLE ..... ______... Register

8-13 through 9 are placed into bits 4 to 7 of the API DBR Debreak and Restore req uest register, and accumulator bits 10 through 17 are placed into bits 0 through 7 of o 5 6 11 15 17 the API priorities active register. A diagram of this follows. 1>:::< :>::>:::< ::<1 DBK Debreak lOT Code Device Select L..J II lOP'S Subdevice Select J L Clear AC o 5 6 11 15 17 Execute Time: 4 p.s

This instruction zeroes the highest priority lOT Code Device Select L..J II lOP'S presently in the priority active register, thus Subdevice Select J L Clear AC clearing the way for future requests. It also primes the PDP-15 to restore the Link, the Execute Time: 4 p.s program counter and memory protect mode to This instruction zeroes the highest priority pres­ their status at the time the API request was ently in the decision register and moves the honored. The actual restoration occurs at the masking registers, thus clearing the way for execution of the JMP I instruction exiting the future requests. It must be used to reset the subroutine which must immediately follow the priority active register after an SPA instruction DBR instruction. has raised the status of an interrupt.

ACCUMULATOR J 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 171 •

, , I •• • •• • ~t •• •• •• •• 0 I 4 5 6 7 I 0 I 2 3 4 5 6 7 I ~,------~------)~,------~------) API Request API Priorities Active Register Register

NOTE

The ISA and SPI instructions can be microcoded to 705505. This instruction is used to first test that the program segment currently in progress is not already masked to the requested priority level, and then, if not, to initiate a masking to the requested level.

8-14 RPL Read Priority Levels Execute Time: 4 J..l.S

o 5 6 11 15 17 The content of the API request register is read into accumulator bits 2 to 9, and the content of ~ : < I the priorities active register is read into accumu­ lOT Code I Device Select L-...J II lOP'S lator bits 10 to 17, as shown below. Subdevice Select J L Clear AC

ACCUMULATOR

J 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 171 j j 4~ ~,. 4 4 4 4~ 4~ 4~ 4,.. 4 4 4 4 j

I 0 1 2 3 4 5 6 7 I 0 1 2 3 4 5 6 7 1 ~, ______~ ______~Jl~ ______,~~ ______~J

API Request Register Priorities Active Register

MEMORY PARITY SPE Skip on Parity Error

o 5 6 11 15 17 The option adds a nineteenth bit to each of the I>: : >: : >: : >: : :< ~ >: I words in a 4096 word core-memory module. lOT Code I Device Select L-...J II lOP'S These bits retain the parity indication for their associated words. Parity is generated when a Subdevice Select J L Clear AC word is entered in memory and checked when the word is read out of its memory location. Execute Time: 2 J.lS If the parity error flag is posted, the program Detection of a parity error can initiate a pro­ counter is incremented by 1 and the next in­ gram interrupt or half execution of the program, struction is skipped. as the programmer selects. Systems with memory parity have a 1 J..l.S memory cycle time. If the memory protection or the relocation and CPE Clear Parity Error protect option is added to a system with parity these operations occur in parallel and would not o 5 6 11 15 17 be additive. For parity and memory protection the cycle time remains at I J..l.S, for parity and I :< : >: : >: : >: : >11 ~ : < I relocation and protect the memory cycle is lOT Code I Device Select L-...J II lOP'S 1.025 J..l.s. Subdevice Select J L Clear AC

Execute Time: 4 J..l.S The lOT instructions associated with memory The parity error flag is cleared to 0 when this parity are as follows: instruction is executed.

8-15 REAL-TIME CLOCK CLOF Clock Off

The real-time clock, when enabled, counts in o 5 6 11 15 17 memory location 00007 the number of cycles completed by anyone of three inputs: I>: : >: : >: : :a: : >1, : >: I lOT Code Device Select L.-J I I IOP'S a. The line voltage (50 or 60 Hz) Subdevice Select J L Clear AC b. An M405 R-C Clock which can be set to any frequency from 0 to 10kHz Execute Time: 4 J.1S The real-time clock is disabled, preventing it c. A user supplied TTL compatible signal from incrementing location 00007. which can be fed through a coaxial cable to a BNC connector on the PDP-IS. CLSF Skip On Clock Flag When location 00007 overflows an interval pro­ gram interrupt or API request, if available, is o 5 6 11 15 17 generated informing the monitor that its preset interval is over. The monitor must either disable the clock or reinitialize location 00007 to the lOT Code 2's complement of the number of counts it I Device Select L.-J II IOP'S needs to tally. Subdevice Select J L Clear AC

The incrementing of location 00007 during a Execute Time: 2 J.1S real-time clock request occurs via the I/O proces­ The program counter is incremented and the sor, using its increment-memory facility. A real­ next instruction skipped if the clock flag is set. time clock request takes priority over API, PI and lOT requests. While the facility is enabled, requests for clock breaks have priority of acceptance over API and PI requests. The first clock break may occur at The following lOT instructions are provided for any time up to 17 ms after the facility has been use with the clock: enabled. Subsequent breaks occur at the clock rate (60 or 50 times per second).

CLON Clock On POWER FAILURE o 5 6 11 15 17 The PDP-IS contains circuitry which provides optimum protection of programs during ma­ I >: : >: : :a: : :< : >: : :< I chine turn-on or turn-off, whether accidental or lOT Code I Device Select L.-J I I IOP'S intended. In the basic machine, the circuitry is Subdevice Select J L Clear AC designed to protect the contents of memory. However, the addition of the system power auditor, an option of the I/O Processor, further allows time to store active registers before the Execute Time: 4 J.1S system stops during a power failure, and a system restart and the subsequent restoration of The realtime clock is enabled to begin incre­ these registers when system power is reapplied. menting location 00007, and its flag is cleared.

8-16 The basic PDP-IS is not affected by power of memory locations (in increments of 256 interruptions of less than IS ms duration. Active words) to the protected region is dynamic and registers in the processor (AC, AR, PC, etc.) will program controlled. A boundary register, added lose their contents when interrupts of longer by the option, stores the location of the upper duration occur but memory will not be dis­ limit of the protected region. It is loaded from turbed. The power failure protection option bits 3 through 7 of the AC by a. MPLS instruc­ provides for saving the contents of active regis­ tion. ters in the event of longer power interrupts and for automatic restart of the system when power The KM IS monitors the instruction about to be is restored. The restart feature is switch-selected executed, and the protect feature transfers con­ by the operator to be enabled or disabled. When trol to a monitor program should the instruction enabled, the program in progress resumes exe­ be in the category of "illegal instructions", cution at location 00000. The system must be before the instruction is executed. If a program operating with the program interrupt facility (or tries to reference a nonexistent memory bank, the AID) enabled to sense the option's initiation the KM 15, if it has been enabled, transfers of a program interrupt to save the register control to the monitor program. The protect contents at the time of the line power failure. If feature increases all memory cycle times by 100 API is available the power failure option inter­ ns and write cycles in user mode by an addi­ rupts on its highest level and uses memory tional 100 ns. address 52. The memory protect (or user mode) may be en­ There is only one instruction associated with the abled either by programmed instruction, or by Power Failure Option. That is: depressing the PRTCT switch on the console, and pressing the START key. When enabled, the option will trap the following: PFSF Skip On Power Low Flag lOT Input/Output o 5 6 11 15 17 CAF Clear All Flags

XCT of XCT Chained Execute lOT Code Device Select L.-J 1\ lOP'S Instructions Subdevice Select J L Clear AC HLT Halt Execute Time: 2 J.ls OAS/LAS Load AC From The state of the power low flag is tested, and if Data Switches set, indicating that system line voltage has dropped and that this flag has posted an inter­ References to nonexistent memory rupt, then the reset instruction is skipped. The flag is cleared by the power clear signal when the References to locations below the bound­ power interruption is over. ary limit

Trapping causes the execution of an effective MEMORY PROTECTION OPTION JMS instruction after the machine cycle that attempts to violate. The address referenced by The memory protection feature establishes a the effective JMS instruction will be either foreground/background environment for PDP-IS location absolute 20, if the program interrupt processing activity by specifying the boundary facility is disabled, or location absolute 0, if the between protected (lower) and unprotected (up­ program interrupt facility is enabled. The violat­ per) regions of system core memory. Allocation ion flag is set.

8-17 The nonexistent memory flag is also set if the tions, except for JMP to a protected area. In this violation was caused by a program or I/O Pro­ case, the stored PC will contain the protected cessor reference to nonexistent memory. A address. single cycle I/O processor reference to non­ existent memory probably will be detected by The sole operator control is the PRTCT switch, the KMI5. which has an indicator above it. This indicator lights when in user mode. The PRTCT switch is User mode is disabled in the following ways: used in conjunction with the START key to establish the proper mode at the beginning of I/O RESET Key program execution. If the switch is up, then the program is started in user mode. The switch has The detection of a violation no further effect.

CAL Instruction (which never causes a The 10 RESET key clears the boundary register, violation) violation and nonexistent memory flags, and user mode (i.e., memory protect is turned off). A Program Interrupt

An API Interrupt MPEU Enter User (Protect) Mode

If user mode is enabled when an API break starts, and the API channel address contains a o 5 6 11 15 17 HLT, OAS, or lOT - rather than the normal JMS - that instruction will be inhibited, user mode I>: : :< : >: : >: : >: : >: I will be disabled in the normal fashion and no lOT Code I Device Select L-J I I lOP'S violation will be detected. Subdevice Select J L Clear AC If user mode is disabled when a reference to nonexistent memory is made, the nonexistent Execute Time: 4 JlS memory flag is set, no trap occurs, and the program continues after a 1 JlS pause. If a Memory protect mode will be entered at the end reference to nonexistent memory occurs when of the next instruction that is not an lOT. user mode is enabled, the violation flag is also set and the trap occurs.

HL T, OAS and lOT instructions are totally MPCNE Clear Nonexistent Memory Flag inhibited when the memory protect option is enabled. If the HLT or OAS is combined with any other operate group instruction (micro­ o 5 6 11 15 17 programming), the other parts of the operate group instruction are executed before the trap. I >: : >: : >: : :< : :< : :< I (The exception is SKP which is not executed.) lOT Code I Device Select L-J II lOP'S The second XCT in a chain of XCT instructions Subdevice Select J L Clear AC is trapped before execution.

The state of the protect mode (a 1 for user Execute Time: 4 JlS mode) is stored in bit 1 of the storage word by the operations that save the state of the machine The nonexistent memory flag posted when non­ (CAL, JMS, PI). The stored PC will contain one existent memory has been referenced, is cleared more than the location of the violating instruc- by the lOT.

8-18 MPSK Skip On Violation Flag MPSNE Skip On Nonexistent Memory Flag

0 5 6 11 15 17 0 5 6 11 15 17 I I I I 0 4 I>: : :< : >: : >: : I I ! >: I I>: : :< : >: : :< : I I ~ >: I lOT Code Device Select y ~ lOP'S lOT Code Device Select y ~ lOP'S Subdevice Select Clear AC Subdevice Select Clear AC

Execute Time: 2 f..LS Execute Time: 2 f..LS The memory protect violation flag will be set The nonexistent memory flag is set whenever whenever the execution of an instruction has the processor attempts to reference a non­ violated the provision of memory protection existent area of core. For a 32,768 word (see above). machine, the flag never gets set.

MPCV Clear Violation Flag MEMORY RELOCATION AND PROTECT - o 5 6 11 15 17 KT15 I >: : :< : :< : >: : >: : >: I The relocation and protect hardware will consist lOT Code I Device Select L-J I I lOP'S of two registers. The relocation register and the Subdevice Select J L Clear AC core allocation register. The relocation register provides the lower limit of the user program and Execute Time: 4 f..LS relocates the user upward from real machine­ The violation flag, set if the boundary has been location 0 by the quantity contained in the violated or an illegal instruction attempted, is register. The core allocation register assigns the cleared by this lOT. quantity of locations available to the user. Any attempt by the user to reference core locations exceeding the limit of the core allocation regis­ ter will cause a protect violation. Memory relo­ MPLD Load Memory Protect cation and protect adds 225 ns to each CPU Boundary Register memory reference cycle.

There are two modes of operation in the PDP-IS o 5 6 11 15 17 protect system: user mode and monitor mode. I I In monitor mode, the relocation and protect o hardware is disabled and the machine functions I j ! >: I as it would without protect hardware. The pro­ lOT Code I Device Select L-J II lOP'S gram running in monitor mode addresses real Subdevice Select J L Clear AC locations within the system. In user mode, the relocation and protect hardware is enabled. The machine is programmed as though the user had a Execute Time: 4 f..LS machine all to himself. His memory begins from Load the memory protection register with the location 0 and goes up to the content of the contents of AC 3 through 7. The boundary core allocation register. In the real machine, the register will store the number of 1024 word program is located from the contents of the blocks to be protected. relocation register up, however, with the excep-

8-19 tion of I/O operations and the CAL instructions; device handler. The device handler will run in the user has the machine virtually to himself and monitor mode. The device handler entry will the programs that way. The following special receive the virtual program counter. cases occur in user mode.

Data Channel CAL Instruction Data Channel operations will never be relocated. When in user mode, and the CAL is given, the user mode is disabled, (monitor mode envoked), the CAL goes to location 20 in the real machine Real-Time Clock (not the virtual or relocated machine). The virtual program counter is saved in real 20, and real 21 is executed. The real-time clock will always increment loca­ tion 7 in the real machine; attempts to reference the contents of location 7 in the real machine Program Interrupt must be handled through the monitor (with a CAL instruction). When a program interrupt is given, the user is disabled, the virtual PC is saved in real location 0, and location I is executed. Auto Increment Registers

Automatic Priority Interrupt Each user will have a complete set of auto­ increment registers located at locations 10 to 17 When in user mode, an API causes monitor of the user's virtual machine. In addition, the mode to be entered, and an instruction in the monitor can utilize the auto-increment registers real machine specified by the I/O device is in 10 to 17 of the real machine in monitor executed. This instruction will be a JMS to the mode.

ADDRESS TO MEMORY

SUBTRACTOR -I

o USER CORE RELOCATION EACH REGISTER ALLOCATION REGISTER UP TO IOBITS

LOAD WITH lOTS

ADDRESS FROM PROCESSOR

1~-0008

Figure 8-4. Hardware

8-20 DBR Instruction addresses and detects protect violations (see Figure 8-4). The debreak and restore instruction (DBR) is used when returning from monitor mode to user Two registers of up to 18 bits are utilized in this mode. The instruction primes the PDP-IS to scheme. One register is the relocation register return the Link and the program counter to whose contents are added to each processor­ their status in user mode. The protect bit, if set, supplied address when in user mode. The user will initiate relocation. Since CAL, PI and API core-allocation register is subtracted from each JMS save the virtual PC (not the real PC), the set processor address and if the result is negative, a protect bit causes return to the correct location violation has occurred. The relocation register is in real memory, the virtual PC is restored, and initialized to the user's lower address and the user mode is invoked. core allocation register is initialized to the quan­ tity of core assigned to the user. For example, if a user were to need 4K of core, and the monitor THE HARDWARE determined the first available location was loca­ tion 730 Is; the relocation register would be The hardware involves a box between the pro­ loaded with 7301 s ; and the core allocation cessor and memory which computes relocated register with I OOOOs .

8-21

CHAPTER 9 PERIPHERAL OPTIONS

A wide range of peripheral equipment is avail­ punched on the tape. Fanfold paper tape is able to expand the capabilities of all PDP-IS normally used with the paper-tape reader and systems. punch.

Card Reader and Control, Type CR03B STANDARD INPUT/OUTPUT DEVICES The CR03B Card Reader provides the PDP-IS High-Speed Paper Tape Reader and Punch, with a punched-card data input facility. It reads Type PCIS standard 80-column, 12-row punched cards at a rate of up to 200 cards per minute. Solid-state circuit design and continuous status checks Standard on PDP-lS/20, 15/30, and 15/40 sys­ ensure system reliability. The output hopper can tems. The perforated paper-tape reader can store 450 cards in their original deck orienta­ photoelectrically sense 8-channel paper tape at a tion. rate of 300 characters-per-second. Under pro­ gram control, data may be read in either alpha­ numeric (one character) or binary (three MASS STORAGE DEVICES character) mode. The use of a paper-tape reader buffer and buffer-full flag permits the continua­ tion of processing during the reading functions. DEC tape

The 50 character-per-second paper-tape punch is The DECtape system provides a unique mounted on the same chassis as the reader. A fixed-address magnetic tape facility for program single output instruction causes an 8-bit charac­ and data storage and retrieval. In environments ter to be transferred from the PDP-IS accumu­ where long batch-processing queues are not fre­ lator to a punch buffer, from which it is quently required, DEC tape is an excellent

9-1 substitute for punched cards. A single pocket­ Magnetic Tape Systems sized reel of DECtape can store 150,000 18-bit words; more information than a deck of 5,000 cards. At the same time, it costs considerably PDP-IS offers both 7- and 9-channel IBM­ less than a reel of IBM-compatible magnetic compatible magnetic tape systems. Transports tape. This compact, inexpensive format allows are currently available to operate at either 45 or each user to have his own personal library of 75 ips and at any of three recording densities. programs and data files on a pocket-sized reel, easily mounted on the transport in less than 15 Automatic Magnetic Tape Control, Type TCS9 - seconds. The Automatic Magnetic Tape Control, Type TCS9, transfers data to and from IBM­ DECtape features: compatible transports via the data channel facility. Up to eight transports can be handled Fixed-position addressing to permit the by a single control, and both BCD and binary selective reading or updating of informa­ modes are available. One TCS9 control can tion without the necessity of reading or handle both 7- and 9-channel transports at both rewriting the entire block. 45 and 75 ips. Read/write functions, recording density, and tape manipulation functions are Automatic word transfer, via the PDP-IS controlled by status registers which can be data channel facility, to allow concurrent loaded and read by the PDP-IS. processing and data transfer. Magnetic Tape Transports, Type TU20, TU20A, Bidirectional operation to allow reading, TU30, TU30A - The Type TU20 Magnetic Tape writing, and searching in either direction. Transport can read and write 7-channel IBM­ compatible tapes at 45 ips and 200, 556, or 800 Redundant phase recording which insures bpi. One 18-bit PDP-IS word is written as three transfer reliability, reduces the problem of tape characters on the Type TU20. skewing and minimizes bit dropouts. Its 9-channel counterpart, the Type TU20A Prerecorded timing and mark tracks to Magnetic Tape Transport, operates at the same simplify programming and to permit block speed at 800 bpi. In two-character mode, the and word addressability. TU20A reads or writes two 8-bit characters per 18-bit word (ignoring two bits), while in three­ character mode it reads or writes three 6-bit DECtape Control, Type TCIS - The DECtape characters (one PDP-IS word) as three 8-bit tape Control, Type TC 15, controls up to eight DEC­ characters. tape transports, Type TUSS. Binary information is transferred to and from the PDP-IS at the rate of one 18-bit word every 200 f.J.S, using the data The TU30 and TU30A Magnetic Tape Trans­ channel facility. Mode of operation, function, ports are respectively 7- and 9-channel units that and direction of motion are controlled by status operate at 75 ips. registers which can be loaded and read by the computer. Disk Systems

DEC tape Transport, Type TUSS - The DECtape DECdisk, Type RFIS/RS09 - The Fixed Head Transport, Type TUSS, provides bidirectional Disk System, Type RF IS/RS09 is a new bulk reading and writing of DECtape reels. Each 3-in. storage medium for use with the PDP-IS. The diameter reel can hold 3,000,000 bits of infor­ basic system consists of one RF 15 Control unit mation (over 150,000 18-bit words) recorded at and one RS09 Serial Disk unit, providing a bulk 375 bpi. Tape moves at 80-ips and requires no storage capacity of 262,144 18-bit words. Seven vacuum column pinch rollers, or capstans. additional disk units can be accommodated by

9-2 the control unit, increasing storage capacity to line-per-minute unit. Both models print text in 2,097,152 words. Data transfers ranging from lines of up to 132 characters from a 64 character one word to 32,768 words are performed via the set. multi-cycle data channel facility. Addressing is by disk unit, track and word. Incremental Plotter and Control, Type XY15

Format Specifications The Type XY 15 Incremental Plotter and Con­ trol uses CalComp Model 563 or 565 plotters at Storage Capacity (l8-bit words) - 262,144 rates of 12,000 or 18,000 points-per-minute. Paper width is either 31-in. (Model 563) or 12 expandable to - 2,097,152 in. (Model 565) and plotting increments of 0.005 and 0.01 in. are available. Number of Tracks 128 Words Per Track 2,048 DAT A COMMUNICATIONS DEVICES

Timing Specifications Power Multi-Station Teletype Control, Type LT19 60Hz 50Hz Average Access Time 16.7 ms 20.0 ms The Multi-Station Teletype Control is available Minimum Access Time 250l1s 250l1s to interface from one to five communications Worst-Case Access Time 33.3 ms 40.0 ms terminals to the PDP-IS Central Processor. (See Word-Transfer Rate Figure 9-1.) High 62.5k wd/s 50k wd/s Medium 31.2k wd/s 25k wd/s Teletype Control, Type LT 19 A - The LT 19 A Low 15.6k wd/s 12.5k wd/s can control up to five Teletype Line Units, Type LTI9B.

Disk Pack and Control, Type RP15/RP02 - The Line Units, Type LT19B - LTl9B Line Units are RP 15 controller interfaces the Disk Pack drive full-duplex Teletype interfaces for either KSR or to the PDP-IS. Transfers are made through a ASR models: each LT19B unit handles one single-cycle data channel. Up to eight RP02 Teletype or LT 19C Adapter. drives can be handled on the same control. The total capacities of the RP02 drives are 10.24 EIA Adapters, Type LT19C - The addition of million words. The total bulk storage capacity the EIA Adapter, Type LTl9C, to an LTl9B with eight RP02 drives is 81,920,000 18-bit unit allows the line unit to communicate with words. Average transfer rate with the RP02 drive low-speed data sets. is 135k wd/s. Average access time, including the rotational latency time of 12.5 ms is 62.5 ms. Teletype Control, Type LT 15

LINE PRINTERS AND PLOTTERS The Teletype Control, Type LT IS is standard on the PDP-15/30 and PDP-15/40 Systems. It allows the addition of a second Teletype unit for Automatic Line Printer, Type LP15 use in the Background/Foreground environment.

The Type LPl5 Automatic Line Printer is avail­ Console Teleprinter and Control - The console able in two models: The Type LPl5A is a 300 teleprinter, Teletype Model KSR35, is standard line-per- minute unit. The Type LP 15C is a 1000 on the PDP-15/20, 15/30, 15/40 (ASR33 on the

9-3 LTI9A

1 I

LTI98 LTI98 LTI98 LTI98 LTI98 1 1

LTI9C LTI9C

1 J

TTY TTY TTY DATA SET DATA SET

Figure 9-1. Multi-Station Teletype Control

PDP-15/l0). These Teletypes can be used to sections are double-buffered to permit one full type-in or print-out information at rates up to character transmission time for loading or read­ 10 cps. The keyboard control includes an 8-bit ing the DP09A. buffer to hold the last character (ASCII code) struck on the keyboard and a flag to signal the processor of the presence of a character, while DISPLAY DEVICES the printer control contains an 8-bit buffer to hold one character while it is being printed. When the Model ASR33 Teletype is used as the VPl S Display Family console teleprinter, its paper-tape reader and punch are interfaced to the PDP-15/l0. Three low-cost, point-plotting display systems can be provided through the use of the VP 15 family of display controllers. The various con­ troller/display device combinations allow the Data Communication System Type DP09A selection of a system particularly suited to a given user application.

The Bit-Synchronous Data Communication System, Type DP09A provides interface facili­ Storage Tube Display, Type VPl SA - The Type ties between a PDP-15 and a bit-serial communi­ VPl5A is a unique and extremely useful point­ cation device. The DP09 A serializes the charac­ plotting display terminal which uses a VTO 1 ters for transmission, and assembles the serial Storage Tube Display. Points are plotted on a stream into characters for reception. Operation 1024 by 1024-bit matrix on the 5-1/4 by 6-3/8 is full duplex. Both the receive and transmit in. CRT. Two lOT-selectable modes of opera-

9-4 tion, store and non-store, are provided. In the accumulators or between memories of the inter­ store mode of operation, plotted points remain faced data processors. Data transfers between visible up to 15 minutes. No refresh memory is accumulators occur on a word-by-word basis and required. In the non-store mode of operation, a are called program-controlled transfers. Data point-refreshing rate of at least 30 cps is re­ transfers between memories occur on a block­ quired to keep points visible, but a faster re­ by-block basis and are called data-channel sponse time is achieved. In either case, only one transfers. These use the multi-cycle data channel intensity level is provided. facility.

Oscilloscope Display, Type VP 1 SB - The Type VP 15B Oscilloscope Display provides a point­ ANALOG-TO-DIGITAL CONVERTERS plotting capability at an extremely low cost. The 1024 by 1024-bit raster is displayed on the Tektronix RM503 X/Y Oscilloscope. The Digi tal supplies analog-to-digital conversion RM503 has various intensity levels and can be systems with high speed and wide dynamic used with a light pen and control, Type ranges for up to 1000 channels. Both single­ VP15BL. ended and differential systems are available, and amplifier and sample-and-hold options can be Incremental Display, Type VPlSC - The VPl5C provided. version of the basic VP 15 display controller is for use with the VR 12 display. This provides the user with a display device with useful display dimensions of 7 x 9 in. The VPl5C provides Analog-to-Digital Converter and Multiplexer, various intensity levels. Type AFOIB

The Analog-to-Digital Conversion System, Type INTERPROCESSOR BUFFER SYSTEMS AFO I B, includes a high-speed successive approx­ imation converter with switch-selected word Two interprocessor models are available to facili­ length from 6 to 12 bits. Conversion time varies tate inter-computer communications. with word length from 9 to 35 f.lS and error from ±.025%. The multiplexer handles up to 64 single-ended inputs and analog signal ranges Interprocessor Buffers, Type DB99, DB98 from +10 to -lOY. The AH03 Amplifier and AH02 Sample-and-Hold Devices may be used There are two models of the interprocessor between the converter and multiplexer, while buffer systems. These are established by the the Type ACOIB Sample-and-Hold System may type of programmed data processor interfaced be used before the multiplexer. Each ACO 1B with the system and are the DB99 Interproces­ accommodates up to eight channels. sor Buffer System and the DB98 Interprocessor Buffer System. Integrating Digital Voltmeter System, The Model DB99 Interprocessor Buffer System Type AF04B is used to interface two PDP-IS Programmed Data Processors. The Model DB98 Interproces­ sor Buffer is used to interface a PDP-IS Pro­ The Type AF04B Integrating Digital Voltmeter grammed Data Processor with a PDP-8 Program­ provides an automatic-ranging integrating digital med Data Processor. voltmeter and low-level scanner that can handle analog signals with full scale values from 10m V The interprocessor buffer system permits one to 300V. Resolution is to 10m V. Designed for data processor to communicate with a second three-wire inputs, the Type AF04B can expand data processor and to transfer data between up to 1000 channels.

9-5 DIGIT AL-TO-ANALOG CONVERTERS a full scale excursion in 12 f..lS to 0.02S% accu­ racy. In the hold mode, the droop (decay) is Digital-to-analog converters with 12-bit accuracy less than I m V /ms. are available packaged in groups of three or, for large numbers, with a 0/ A controller.

OPERATIONAL AMPLIFIER, TYPE AH03 Digital-to-Analog Converter Control, Type AAOSB The AH03 Operational Amplifier allows for a number of input voltage ranges between ± ISV. 6 The Type AAOSB Digital-to-Analog Converter Open loop gain is 2 x 10 , unity gain frequency Control permits the multiplexed control of up response is 10 mHz and the input independence to 64 digital-to-analog converter channels. Ran­ between inputs is 6 mn. dom addressing is used, and a channel may be addressed and updated by a single PDP-IS com­ mand. I/O BUS ADAPTER, TYPE OWlS

Sample-and-Hold Option, Type AH02 The OW ISA I/O Bus Adapter converts a positive PDP-IS I/O bus of +2.SV and ground signals to a The AH02 Sample-and-Hold option consists of negative bus of -3V and ground. This adapter a sample-and-hold amplifier capable of tracking interfaces PDP-9 peripherals to PDP-IS Systems.

9-6 CHAPTER 10 PDP-15 CONSOLE

The PDP-IS console (see Figure 10-1) provides accumulator content with s~itches content) in­ access to, or control over, virtually every portion struction in an operating program. Data may be of the PDP-IS. All registers, buses, and controls inserted manually into the machine with these are multiplexed down a single console cable to switches by means of the DEPOSIT and DEPOS­ display the equivalence of 24 registers and 34 IT NEXT keys. control functions. The console provides exten­ sive control for real-time debugging and compre­ Address hensive man-machine interaction during check­ out. The memory address required by the START, READ IN, EXAMINE, and DEPOSIT keys is supplied by these switches. When one of these INFORMA nON/CONTROL SWITCHES keys is depressed, the address given by the address switches is loaded into the MA (memory The following two-position rocker switches are address) register and the key instruction is exe­ on the console keyboard: cuted. Number Designation Number Designation Register Group

18 Data Repeat Selects which of two groups of 12 registers to be IS Address Halt Loop selected by the register select switch. In the OFF I Clock Single Time position the normal registers may be viewed I Register Group Single Step while the ON position allows viewing of the Parity Error Single In- maintenance registers. (See Register Select struction Switch).

Data Clock

These 18 switches may be read indirectly into The ON position disables the real-time clock the accumulator by the execution of a OAS (OR from issuing program interupt (PI) requests.

10-1 Figure 10-1. PDP-IS Console

Parity Error Deposit: This, Next, Examine: This, Next- the Deposit, Deposit Next or Exa­ The ON position disables parity error program mine Next function will be repeated. interrupts from occurring. Depressing STOP or turning off the repeat switch will halt the repeat action. Repeat Halt Loop With this switch in the ON position, the proces­ Used in conjunction with single time, step or sor will repeat the key function depressed by the instruction. Enabling the halt loap switch and operator at the rate specified by the repeat anyone of the other three will cause the clock. processor to continually repeat the time, step or instruction into which it has been advanced. Start - program execution will restart at the repeat speed after the machine halts. Single Time

Execute - the instruction in the data switches Halts execution of the program after each time will be executed at the repeat clock state has been completed. rate. Single Step Continue - program execution will continue at Halts execution of the program after each major the repeat speed after halting. state has been completed.

10-2 Single Instruction Read-In

Halts program execution after each instruction Initiates the read-in of paper tape punched in has been completed. binary code (each set of three 6-bit lines read from tape forms one 18-bit computer word). Storage of words read-in begins at the memory OPERATE CONTROL SWITCHES location specified by the ADDRESS switches. At the completion of tape read-in, the processor The following momentary contact switches are reads the last word entered and executes it. on the console panel. Deposit Number Designation Number Designation Deposits the contents of the data switches into Start Read In the memory location specified by the address Execute Deposit This switches. After the transfer, the memory loca­ Continue Deposit Next tions address is in the OA (operand address) Stop Examine This register and the contents of the accumulator Reset Examine Next switches are in the MO (memory out) register. Protect

Deposit Next Start Deposits the contents of the data switches into Initiates program execution at the location spe­ the location given by OA ± 1. This permits the cified by the address switches. loading of sequential memory locations without the need of loading the address each time. Execute

Executes the instruction in the data switches Examine and halts after execution. Places the contents of the memory location specified by the address switches into the mem­ Continue ory buffer register. The address is loaded into the OA (operand address) register. Resumes program execution from the location specified by the program counter (PC). Also Examine Next used to advance machine while in single time, step or instruction. Places the contents of the memory location specified by the OA + I (operand address plus I) Stop into the memory buffer register. Sequential memory locations may be examined using the Halts the processor after the completion of the Examine-Next switch. present instruction.

Protect Reset Initiates the memory protect feature. When uti­ Generates a power clear signal which clears all lized, the protect feature prevents the read-in of active registers and all control flip-flops except data into the specified "protected" memory the program counter (PC). locations.

10-3 SPECIAL SWITCHES relieves personnel of a large portion of the signal tracing normally associated with the mainte­ nance of electronic systems. The sequences or Register Select maintenance "status words", are supplied as part of the system maintenance data. The 12 position Register Select rotary switch can select the following registers for viewing in Power/Repeat Rate the REGISTER indicators (under control of the Register Group switch). A variable-pot/switch provides the POWER ON/ OFF control at one end of its rotation and Register Group Switch OFF variable repeat speed (approximately 1 Hz to 10 kHz) over the remainder of its rotation. AC Accumulator PC Program Counter INDICATORS OA Operand Address MQ Multiplexer Quotient The console indicator panel displays the follow­ L,SC Priority Level/Step Counter mg: XR Index Register LR Limit Register Memory Buffer (18 bits) EAE EAE Register (18 bits)* DSR Data Storage Register Link lOB I/O Bus Power STA I/O Status Run MO Memory Out Instruction Register IR 0-3 Defer Register Group Switch ON Index Extended Enable ABU A Bus Clock Enable B BU B Bus Parity Error CBU C Bus Protect SFT Shift Bus DCH Active lOA I/O Address API States Active, 0-7 SUM Sum Bus API Enable Ml Maintenance I PI Active M2 Maintenance II PI Enable MDL Memory Data Lines Index Mode MA Memory Address Major States MB Memory Buffer Fetch MST Memory Status Increment Defer Main tenance 1 and 2 EAE Execute Two positions of the Register Select switch M 1 Time States and M2, in conjunction with the Single Time 1 switch, provide a visual display of active control 2 and gating signal levels. For a given instruction, 3 as the processor is stepped through the time states of each major state, the REGISTER in­ *The "register" indicators display the content of dicators display a predictable sequence of en­ the register, bus or status word that is selected abling and strobing signals. The visual display by the setting of the Register Select switch.

10-4 CHAPTER 11 SYSTEM SOFTWARE

PDP-IS/IO COMPACT SOFTWARE SYSTEM COMP ACT Assembler

A 2-pass system requiring less than 3072 words The PDP-IS /1 0 COMPACT software system, of core memory. The COMPACT Assembler has which operates with the hardware configuration a useful set of selected pseudo ops for functions shown in Figure 11-1, is a concise programming such as table formation, symbol table and vari­ system and includes a symbolic assembler, a text able control, and text handling. editor for creating programs on-line, debugging routines, utility routines, and mathematical rou­ tines. The system is designed to operate in the COMPACT Debugging Routines 4K or 8K paper-tape input/output environment of the basic PDP-IS/l O. Installations with 8192 Debugging routines are included in the COM­ words of core memory and high-speed paper PACT Software system. ODT (Octal Debugging tape with or without bulk storage may use the Technique) is a debugging aid that allows the user to conduct an interactive, on-line debugging BASIC I/O MONITOR software to extend sys­ session using octal numbers and teletype com­ tem capabilities. mands.

COMP ACT Editor Utility routines in the COMP ACT software system include a Hardware Read-in Mode (HRM) punch routine, paper-tape handling rou­ Takes advantage of the powerful character tines, teletype I/O routines, an octal dump string, search, and modification commands de­ routine, and a memory scan routine used for veloped for the larger systems. I t provides for scanning areas of memory for a particular bit the creation and/or identification of source pro­ configuration. For systems with DECtape, a grams and other ASCII text material by means FAST system can be used to retrieve frequently of keyboard commands, and offers an efficient used programs. method for on-line processing of paper tapes.

1 I-I 4K MEMORY

ADDR INPUT INPUT/OUTPUT PROCESSOR OUTPUT BUS .. CENTRAL PROCESSOR UNIT

15-0009

Figure 11-1. PDP-15/l0

BASIC Monitor commands that direct the operation of the hardware system (Figure 11-2). These commands This Monitor is available for configurations com­ perform three major functions: prising 8192 words of core memory and high­ speed paper tape reader/punch. It provides the a. Provide information about the system link between the call for I/O, by either user or such as commands available and their func­ system programs, and the actual I/O execution. tions; system configuration, error diagnos­ All input/output calls to system devices are tics, the standard logical-physical I/O de­ serviced by Digital-supplied device handlers vice associations, I/O level programs avail­ which reside in the input/output programming able (device handlers), special memory reg­ system (lOPS). The device handlers actually move the data between the program and the I/O isters and their functions. devices. They are responsible for initialization of b. Permit the standard physical-logic de­ the device and for the performance of all other vice associations to be modified; thereby functions peculiar to a given I/O device, such as enabling the dynamic allocation of devices servicing of interrupts, in a real-time environ­ at load-time. (This is a natural extension of ment. User-supplied device handlers can be in­ device independence provided by the I/O corporated into the system to perform the above monitor section of the Basic I/O Monitor.) functions for special I/O devices. c. Supervise the loading and execution of all system and user programs, their asso­ ciated I/O device handlers, and library sub­ PDP-IS/20 ADVANCED MONITOR SYSTEM routines, in addition to the generation of error messages and recovery procedures. The PDP-I 5/20 Advanced Monitor incorporates all the functions of the Basic I/O Monitor Coupled with keyboard control of system pro­ together with executive control of mass storage grams, the PDP-IS /20 Advanced Monitor per­ devices to provide fully automatic operation, mi ts the user to deal with his entire problem including batch processing, keyboard inter­ ( e d i t i ng, assembling-compiling, load ing, de­ action, and real-time control. The PDP-15/20 bugging and running) in a straightforward Advanced Monitor System has almost 50 basic manner.

11-2 The PDP-lS/20 Advanced Monitor (Figure 11-3) keyboard and printer. All other lOPS device consists of a systems loader, command decoder, handlers will be stored on the system device lOPS routines, real-time clock handler, teletype until required by object programs. handler, an error detector program, and device assignment tables (DATS). The Monitor also contains a device assignment for each table entry that may be used. Since the The bootstrap loader always resides in upper contents of the table can be altered by com­ memory and is responsible for loading the Moni­ mands to the PDP-lS/20 Advanced Monitor, tor into lower memory. Return calls from sys­ actual I/O devices may be changed without tem or user programs cause restoration of con­ altering the program references to these devices. trol to the Monitor.

The Monitor command decoder recognizes re­ quests for system programs and loads the system COMMON PDP-IS SOFTWARE loader to bring in the requested program. In response to control cards or keyboard com­ The following system software is supplied with mands, it also manipulates the device assignment all PDP-IS Systems. table to provide the device-independence. The Monitor input/output system routines (lOPS) FORTRAN IV - The PDP-IS FORTRAN IV include data-handling subroutines, device hand­ compiler is a two-pass system which accepts lers. and interrupt service routines for the prior­ statements written in the FORTRAN language ity interrupt system as well as the teletype and produces a relocatable object code capable

EXTENDED ADDR ARITHMETIC INPUT ELEMENT INPUT/OUTPUT PROCESSOR OUTPUT BUS DATA CENTRAL PROCESSOR UNIT CHANNELS ~~~--La~~--L-~~----~~

DECTAPE TRANSPORTS ~ HIGH SPEED PAPER TAPE STATION 1~-OOIO

Figure 11-2. PDP-lS/20

1 1-3 ADVANCED MONITOR • SYSTEM LOADER • ERROR DETECTOR SYSTEM • COMMAND DECODER CONTROL • CONFIGURATOR TELETYPE • REAL TIME CLOCK HANDLER • TELETYPE HANDLER

INTERACTIVE SCOPES

1~-0026

Figure 11-3. Advanced Monitor System

11-4 of being loaded by the Linking Loader program. repeat functions; It is compatible with USA FORTRAN IV, as defined in the USA Standard X3. 9-1966, modi­ Boolean manipulation; fied to allow the compiler to operate in 8,192 words of core storage. optional octal/symbolic listing; two forms of radix control (octal and This FORTRAN IV compiler operates with the decimal) and two text modes (7-bit ASCII PDP-IS program interrupt facility enabled and and 6-bit trimmed ASCII); generates real-time programs that both operate with the program interrupt enabled and can global symbols for easy linking of sepa­ work in conjunction with assembly language rately assembled programs; programs that recognize and service real-time devices. Subroutines written in either FOR­ choice of output format: relocatable, abso­ TRAN IV or the Macro Assembler language can lute binary (checksummed), or full binary be loaded with and called by FORTRAN IV (unchecksummed), capable of being loaded main programs. Comprehensive source language via the hardware READIN switch; diagnostics are produced during compilation, and a symbol table is generated for use in on-line the ability to call I/O system macros which debugging. expand into lOPS calling sequences

FOCAL - An on-line, interactive (conversational) algebraic language designed to help scientists, Dynamic Debugging Technique (DDT-i5) - A versatile tool for dynamic program checkout and engineers, and students solve numerical prob­ modification. It allows an operator to load a lems. The language consists of short, easy-to­ program and run all, or selected portions, of it in learn English imperative statements. Mathema ti­ a real-time interrupt environment under inter­ cal expressions are usually typed in standard active supervision. notation. FOCAL puts the full calculating power and speed of the PDP-IS under easy conversa­ Control of DDT and program examination and tional control. For example, FOCAL can be modification are obtained via the teletype key­ used for stimulating mathematical models, for board. A set of simple c·ommands is available to curve plotting, for handling sets of simultaneous allow the operator to insert a breakpoint, equations in n-dimensional arrays, and for solv­ specify the number of program iterations before ing many other kinds of problems. interrupting the program, and to start the pro­ gram at any point. Other commands allow the Macro Assembler (MACRO-i5) - Macro operator to examine or alter any location Assembler permits the programmer to use symbolically and then rerun the program. mnemonic symbols to represent operational codes, locations, and numeric data. The pro­ Text Editor - The PDP-IS ADVANCED Soft­ • grammer can direct the assembler's processing ware System provides the ability to create or by means of a full set of pseudo operations. An edit symbolic text utilizing any input or output output listing can be obtained to show the device. The Editor operates on lines of ASCII programmer's source coding as well as the binary text. A "context" method is employed through­ object code produced by the Assembler. PDP-IS out to identify the block of data which the user users can also utilize highly sophisticated macro wishes to modify: that is, the block is specified by its ASCII text rather than by a numbering generating and calling facilities within the con­ scheme imposed externally upon the text and text of a symbolic assembler. Among the fea­ not a part of it. Commands are available which tures of MACRO-IS are: facilitate insertion, deletion, and modification of the ability to define and call nested macros; data in the object file.

conditional assembly based on the com­ Peripheral Interchange Program (PIP-i5) - Facili­ putational results of symbols or expres­ tates the manipulation and transfer of data files sions; from any input device. It can be used to update

11-S file descriptions, verify, delete, segment, or com­ trol, one for off-line program development bine files, perform code conversions and copy and data reduction - at the price of one tape. system.

Linking Loader - Loads in either relocatable or b. Achieve 100% utilization of his system, absolute format any PDP-IS FORTRAN IV or independent of data rates. MACRO-IS object program. Among its tasks are loading and relocation of programs, loading of called subroutines, retrieval and loading of The foreground programs are assumed to be implied subroutines and lOPS routines, and checked out and to operate from requests to the loading and relocation of the necessary symbol program interrupt or priority interrupt facilities. tables. At load time, they have first priority over core memory and I/O devices, and at execution time, Chain and Execu te - Chaining in the PDP-IS they have priority (according to their assigned ADV ANCED Software System is a method of priority levels) over processing time and their segmentation which allows for multiple core own I/O devices. overlay of executable code and certain types of data areas. It reserves a portion of user core from one segment to another so that the user The background program (or sequential series of can communicate between segments. This core is programs) is essentially the same as the single reserved and used by the blank COMMON state­ user program under the Advanced Monitor ment in FORTRAN IV and by the system System; that is. it can be an assembly. a compila­ pointers in MACRO-IS. There are two system tion. a debugging run. a production run. an programs required for chaining. editing task. or batch processing. It may use whatever facilities (core, I/O processing time, a. Chain - a modified version of the Link­ etc.) are available and are not required by the ing Loader which allows the user to build foreground programs. all the various segments (or chains) of his program into an executable file. The BACKGROUND/FOREGROUND Monitor oversees the time-shared use of the PDP-lS/30 b. Execute - a control program which ini­ by the two co-resident programs and performs tiates loading of an executable file and transfers control from one segment (chain) the following functions: to another. schedules processing time:

The PDP-IS/30 BACKGROUND/FORE­ protects the foreground job's core: GROUND Monitor System operat'ing with the hardware configuration shown in Figure I 1-4. is protects the foreground job's I/O devices; an extension of the Advanced Monitor system. allows the sharing of multi-unit device Its open-ended design enables the system to handlers. such as DECtape. by both fore­ handle a wide range of tasks, from high-speed ground and background jobs: data gathering applications such as those in physics to thousand-channel input/output appli­ allows the queuing of jobs by priority cations such as warehouse inventory control. It through use of the software-initiated allows the concurrent. time-shared use of the multi-level automatic priority interrupts PDP-IS /30 by protected foreground user pro­ (API): grams with a background of batch processing. program development or low-priority user pro­ allows the shared use of the system real­ grams. With the BACKGROUND/FORE­ time clock to specified intervals: GROUND Monitor the user can: allows communication between back­ a. Effectively have two processing systems ground and foreground jobs via core-to­ - one for on-line data acquisition and con- core transfers.

11-6 MEMORY BANKS

REAL TIME AUTOMATIC MEMORY PRIORITY EXTENDED CLOCK PROTECT INTERRUPT ADDR ARITHMETIC INPUT ELEMENT INPUT/OUTPUT PROCESSOR OUTPUT BUS CENTRAL PROCESSOR UNIT

HIGH SPEED PAPERTAPE STATION DECTAPE TRANSPORTS

1~-OOIl

Figure 11-4. PDP-15/30 System

PDP-15/40 DISK-ORIENTED BACKGROUND/ bly language to MACRO-I 5 assembly language, FOREGROUND SYSTEM so that they can be assembled and executed within the PDP-15 ADVANCED Software en­ The PDP-15/40 System (Figure 11-5) utilizes a vironment. The purpose of the Translator is not disk version of the BACKGROUND/FORE­ to produce a program which runs on the PDP-15 GROUND Monitor. It contains all of the fea­ by simulating the PDP-8, but rather to do the tures described above in the PDP-15 /30 BACK­ straightforward portion of the translation and GROUND/FOREGROUND Monitor section. clearly indicate to the programmer those parts The disk system allows high-speed overlays, of the code which require review in the light of chaining, and system and user program loading. the PDP-15's greater word length and more The limit of records that can be opened on the power instruction set. disk is limited only by available word space. The PDP-15/40 System contains 524,288 words of disk storage expandable up to 2,097,152 words. STATPAC

ADDITIONAL SYSTEMS SOFTWARE A comprehensive and open-ended package of modular statistical programs designed to operate PDP-8-to-I5 Translator under the PDP-15/20 ADVANCED Monitor, is an easy way for a user with limited computer Used to translate programs written for the knowledge to obtain statistically meaningful re­ PDP-8 in PAL-III, PAL-D, or MACRO-8 assem- sults from data. ST AT PAC includes modules for

11-7 -I -00

o

MEMORY BANKS

AUTOMAT IC REAL TIME MEMORY PRIORITY EXTENDED CLOCK PROTECT INTERRUPT ADDR ARITHMETIC INPUT ELEMENT INPUT/OUTPUT PROCESSOR OUTPUT BUS DATA CENTRAL PROCESSOR UNIT CHANNELS, I I I

DECTAPE CONTROL DECTAPE TRANSPORT HIGH SPEED PAPERTAPE STATION

DEC DISK CONTROL

Figure 11-5. PDP-15/40 System

., control, input, descriptive statistics, stepwise machine. Instructions and procedures for linear regression, and multiple linear regression loading, operating, and interpreting the results functions. of diagnostic tests are written in clear, simple language, so that beginning maintenance techni­ cians can use them easily. DECUS

The Digital Equipment Computer Users Society, Detailed error messages are printed out to tell encourages the exchange of programs and ideas the technician exactly which instruction or bit among its several thousand members. Semi­ configuration, has failed. Error codes help direct annual meetings provide a forum for papers, the troubleshooter to specific modules when a while the program library allows the exchange of fault condition is detected. programs of common interest. Among the MAINDEC diagnostics are: The Basic Processor Test and the Extended Processor DIAGNOSTICS Test. The Basic Test incrementally checks the entire instruction repertoire, performing 1500 unique tests, and in each case, halts with specific MAINDEC Diagnostic Programs instructions for the troubleshooter. If the Basic Test fails to detect the trouble, the Extended MAINDEC Diagnostic programs are provided for Test uses random number techniques to test the locating hardware malfunctions within the logic for many combinations of data manipula­ processor, memory, and I/O equipment. They tion and addressing problems, runs memory test run under a systems exercisor. Simple teletype patterns, performs system tests on I/O devices commands load and execute requested diagnos­ and controls, and many other tests. tics. Several diagnostics may be executed con­ currently to maximize system's interaction. A valuable tool for check-out and trouble­ The diagnostic programs are designed to make shooting, MAINDEC diagnostics contribute to troubleshooting fast and straightforward by the high productivity of the PDP-IS by minimiz­ se 1e c tively exercising every circuit in the ing down time.

11-9/10

APPENDIX A INSTALLATION PLANNING

PHYSICAL CONFIGURATION Other options are added to the PDP-15 by attaching 19-in. cabinets to either side of the The basic PDP-I 5 is housed in a standard 19-in. basic System, according to the configuration cabinet (Figures A-I and A-3 with overall shown in Figure A-4. Connections to these dimensions of 21-11/16 in. wide, 30-in. deep options are made from the PDP-15 I/O Processor and 71-7/16 in. high. The PDP-15 is painted via I/O bus cables. black with grey end panels and a two-tone blue console. The console can be purchased in three Several options including disks, displays, versions: as a flush mounted console which is industry-compatible tape transports, the card table mounted, as a tilted console with a table, reader, line printers and plotters are composed, or as a remote console. The table projects in part, of free standing units. forward 19-5/16 in. and a rear clearance of 18-1/2 in. is needed for access to the logic. PLACEMENT OF OPTIONS All of the standard PDP-15 System logic is housed in a steal enclosure with cooling fans. Cabinets are numbered 1 through n with the Each cabinet uses a large fan which pulls filtered numbers always running from left to right. All air in from the top of the cabinet - keeping the cabinets are standard DEC 19-in. type weighting complete cabinet under pressure. 300 Ibs. with net capacities of 500 Ibs. recommended and 800 Ibs. maximum. Each In the basic PDP-15 cabinet, the console, power cabinet can hold eleven standard 5-1/2-in. supply, API, parity, memory protect, central mounting panels of logic plus a 5-1/2-in. processor, I/O processor, EAE, real-time clock, indicator panel at the top. Figure A-4 shows the power fail and the first 8192 words of memory placement of options and peripherals. are all mounted in the front portion of the cabinet. Additional memory to 32,768 words is Figures A-5 through A-8 show the configuration mounted on the back door. of the PDP-15/10, 20, 30, and 40, respectively.

A-I 1 7 rTI I IB32 REMOVEABLE I END PANEL I BEMOVEABLE END PANEL

63 67JL 711~ I 32 30 , 1 I 1 _L~- ~: NOTE Ir L OVERALL HEIGHT 71~ " TABLE HEIGHT 271~ 8

SWINGING DOOR

Figure A-I. Basic PDP-IS Cabinet Figure A-2. Top View of Basic PDP-IS Cabinet

FANS CARAVEL FAN

LOGO

MEMORY

ENCLOSED 10- 1/2 "(,--_1 CPIIO LOGIC BEZELS

CPIIO

REAR -DOOR CONSOLE

DEC 19" CABINET DOOR----- POWER POWER DIMENSIONS: SUPPLY 30"DEEP SUPPLY 21-11/16"WIDE 71- 7/16" HIGH

Figure A-3. PDP-IS Basic Configuration

A-2 INDICATOR

RS09 RS09 #8 #5 RF 15 DEC DISK DEC DISK DEC DISK CONTROL

RS09 RS09 RS09 #7 #4 #2 DEC DISK DEC DISK DEC DISK

RS09 RS09 RS09 #6 #3 #1 DEC DISK DEC DISK DEC DISK

BLANK BLANK BLANK

INDICATOR TU55 DP09 DATA COMM #8 LT 19 DECTAPE TTY CONTROL FANS

FANS TU55

#7 DB08/09 DECTAPE INTER~PROCESSOR BUFFER

TU55 CR03B #6 CARD CONTROL

DECTAPE FANS

ANALOG TU55

#5 OPTIONS

DECTAPE TC59

MAG TAPE TU55 CONTROL -"4

DECTAPE

FANS

BLANK BLANK

Figure A-4. Option and Peripheral Physical Configuration (Sheet I)

A-3 PDP-15

INDICATOR INDICATOR INDICATOR

MMI5XA INDICATOR BLANK BLANK BK MEM

FANS RP 15 DISKPACK API TU55 CONTROL KPI5 MEMORY PROTECT #3 CENTRAL AND 1/0 MEMORY PARITY DEC TAPE PROCESSORS

EAE TU55 REAL TIME CLOCK DISPLAY #2

DECTAPE FANS PCI5

PAPER TAPE CONSOLE TU55 STATION #1

TABLE DECTAPE BLANK

FANS FANS BLANK

715 BAI5

POWER TCI5 DWI5 SUPPLY DECTAPE BUS CONVERTER CONTROL

Figure A-4. Option and Peripheral Physical Configuration (Sheet 2)

A-4 PDP-15110

4K MEMORY

CENTRAL PROCESSOR AND I/O PROCESSOR

CONSOLE

TABLE

POWER SUPPLY

ASR 33

Figure A-S. PDP-IS/l 0

PDP-15/20

INDICATOR INDICATOR 8K MEMORY FANS

CENTRAL PROCESSOR AND I/O PROCESSOR EAE

DEC TAPE TRANSPORT

• HIGH SPEED DEC TAPE CONSOLE PAPER TAPE TRANSPORT READER/PUNCH

TABLE

FANS FANS

PAPER TAPE POWER STATION CONTROL SUPPLY DEC TAPE CONTROL KSR 35

15-0014 Figure A-6. PDP-IS /20

A-S ;J> I 0\

REAR DOOR

PDP -15/30 BK MEMORY INDICATOR INDICATOR BK MEMORY FANS

API CENTRAL PROCESSOR MEMORY PROTECT DECTAPE AND TRANSPORT 1/0 PROCESSOR EAE REAL TIME CLOCK DECTAPE TRANSPORT

HIGH SPEED PAPER DECTAPE CONSOLE TAPE READER I PUNCH TRANSPORT

TABLE

FANS FANS

POWER PAPER TAPE SUPPLY STATION AND KSR 35 CONT ROL DECTAPE KSR I I KSR CONTROL 33 35

JS OOI~

Figure A-7. PDP-IS/30

'. PDP-15/40

INDICATOR INDICATOR INDICATOR 8K MEMORY FANS

DEC DISK API CONTROL CENTRAL MEMORY PROTECT PROCESSOR AND I/O PROCESSOR EAE DEC DISK REAL TIME DEC TAPE CLOCK TRANSPORT

HIGH SPE ED DEC TAPE CONSOLE PAPER TAPE TRANSPORT DEC DISK READER/PUNCH

TABLE

FANS FANS

PAPER TAPE STATION AND KSR 35 CONTROL POWER SUPPLY DEC TAPE CONTROL

8K MEMORY

8K MEMORY

KSR35 KSR33

15-0016

Figure A-8. PDP-l 5/40

A-7 ~ 00

Table A-I PDP-IS, Extra Memory, Free-Standing Options and Their Controls

Service Cabinet Dimensions Clearance Height of AC Current Heat Power Cable Name Height Width Depth Options Weight Front Rear Interface Nominal Surge Dissipa- Dissipation Length Comments (in.) (in.) (in.) Required (lb) (in.) (in.) (19 in. logic) (amps) (amps) tion (kw) (btu/hr)

Standard PDP-IS 71-7/16 21-11/16 30 -- 20 -

Extra Memory. Rear door of basic Type MM 15 A/B/C cabinet can hold up to three 8K memory banks

Magnetic Tape Transports. 69-1/8 22-1/4 27-1/16 TC59 400 19 19 See TC59D 8 12 2300 0.62 lOft 60°F to 80°F Type TU20 and TU20A 40'Yc to 60'lr

200 cpm Card Reader. 50 30 17 DWI5A 200 -- 6-5/8 - 1.3 7.0 495 0.15 10 ft Type CR03B

Incremental Plotter. See 350 Calcomp Model 563 9-3/4 39-3/8 14-3/4 XYI5 53 - - Control 1.12 2 425 0.125 lOft Calcomp Model 565 9-3/4 18 14-3/4 XYI5 53 - 1.5 3 580 0.17 10 ft

Data Communications (See 680 Handbook) DB98A - - See - 12 ft System. Type 680 DB98A

I I --1... Table A-2 Hardware and Logic Options for 19-Inch Cabinets

Logic Number of Approx Heat Power Name Height Mounting Options Weight AC Current (amps) Dissipation Dissipation Comments (in.) Panels Required (lb) Nominal Surge (btu/hr) (kw)

IPB, Type DB99A 10-1/2 2 -- 0.39 0.72 133 0.042

IPB, Type DB98A PDP-IS or PDP-9 End 10-1/2 2 - 0.39 0.72 133 0.042 PDP-8 End 10-1/2 2 - 0.31 0.6 III 0.032

DECtape ControL Type TC 15 15-3/4 3 - 38 0.60 1.0 207 0.058

DEClape Transport, Type TU55 10-1/2 2 TCO:! 35 0.5 3.0 410 0.170

Magnetic Tape Control 21 4 - 50 2.0 5.0 1000 0.23 Type TC59D

Incremental Plotter Control, 10-1/2 2 - 25 TypeXYI5

Multistation Tektypc Control, 10-1/2 2 -- 25 47 0.014 Type LTI9A

Line Unit. Type L T 19B -- LTI9A 0.13 0.24 -

Tektronix Scope, RM503 or 7 2 VPI5 RM564

ADC/Multiplexer, Type AFOIB 8-3/4 :1 - 50 0.5 189 0.055

IDVM/Scanner, Type AF04B 200 Channels 24 Separate -- 220 4.0 8.8 1564 0.460 Weights include cabinet 400 Channels 34 Cabinet - 240 4.5 9.8 1756 0.517 600 Channels 44 - 260 5.0 I I 1950 0.575 800 Channels 54 Separate - 280 5.5 I I. 9 2100 0.62 1000 Channels 64 Cabinet - 300 6.0 13.2 2350 0.69

DAC Controller. Type AA05B 8-3/4 2 - 60 0.5 J.I 306 0.09

DAC Controller Extension, 8-3/4 2 AA05B 30 0.5 1.J 306 0.09 Type AA07B

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, Digital Equipment Corporation Maynard, Massachusetts

printed in U.S.A.