DOCSLIB.ORG

CSE2021 Computer Organization CSE2021 Computer Organization

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
CSE2021 Computer Organization CSE2021 Computer Organization CSE2021 Computer Organization CSE2021 Computer Organization Instructor: Gulzar Khuwaja, PhD Email: [email protected] Tel: (416) 736-2100 x 77874 Instructor: Gulzar Khuwaja, PhD Course Website: Department of Electrical Engineering https://wiki.eecs.yorku.ca/course_archive/2014-15/S/2021/ & Computer Science Schedule: Lassonde School of Engineering Lectures: R 7:00 – 10:00 pm Room CLH M (206) York University Labs: M 7:00 – 10:00 pm Room LAS 1006 Office Hrs: R 5:00 – 06:30 pm Room LAS 2018 Chapter 1 — Computer Abstractions and Technology — 2 COMPUTER ORGANIZATION AND DESIGN 5th Edition CSE2021 Computer Organization The Hardware/Software Interface Text Books: Computer Organization and Design The Hardware/Software Interface, 5th Edition (2014) by David A. Patterson and John L. Hennessy Chapter 1 Morgan Kaufmann Publishers (Elsevier) ISBN 978-0-12-407726-3 Computer Abstractions MIPS Assembly Language Programming 2003 by Robert Britton, Pearson Publishers ISBN-10:0131420445 and Technology Assessment: Quizzes: 11% Labs: 24% Midterm Exam: 25% Final Exam: 40% Chapter 1 — Computer Abstractions and Technology — 3 Chapter 1 — Computer Abstractions and Technology — 4 § 1.1 Introduction 1.1 COMPUTER ORGANIZATION AND DESIGN 5th Edition The Hardware/Software Interface Moore’s Law Moore’s Law states that integrated circuit Computer Abstractions resources double every 18–24 months. and Technology Moore’s Law resulted from a 1965 prediction of such growth in IC capacity - Introduction - Eight Great Ideas in Computer Architecture made by Gordon Moore, one of the - Below Your Program - Under the Covers founders of Intel. - Technologies for Building Processors and Memory Moore’s Law graph to represent - Performance - The Power Wall designing for rapid change - The Switch from Uniprocessors to Multiprocessors - Concluding Remarks Chapter 1 — Computer Abstractions and Technology — 5 Chapter 1 — Computer Abstractions and Technology — 6 1 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 Moore’s Law Moore’s Law Year of introduction Transistors 4004 1971 2,250 8008 1972 2,500 8080 1974 5,000 8086 1978 29,000 286 1982 120,000 386™ 1985 275,000 486™ DX 1989 1,180,000 Pentium® 1993 3,100,000 Pentium II 1997 7,500,000 Pentium III 1999 24,000,000 Pentium 4 2000 42,000,000 Source: ISSCC 2003 G. Moore “No exponential is forever, but ‘forever’ can be delayed” Chapter 1 — Computer Abstractions and Technology — 7 Chapter 1 — Computer Abstractions and Technology — 8 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 Is Moore’s Law Ending? Is Moore’s Law Ending? (2) Intel’s former chief architect Bob Colwell says: Moore’s law will be dead within a decade (August 2013). The end of Moore's Law is on the horizon, says AMD. Theoretical physicist Michio Kaku believes Moore's Law has about 10 years of life left before ever-shrinking transistor sizes smack up against limitations imposed by the laws of thermodynamics and quantum physics (April 2013). Chapter 1 — Computer Abstractions and Technology — 9 Chapter 1 — Computer Abstractions and Technology — 10 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 Bell’s Law Bell’s Law Bell's Law for the birth and death of computer classes: Bell's law of computer classes formulated by Gordon Bell in 1972 describes how computing systems (computer classes) form, evolve and may eventually die out. Roughly every decade a new, lower priced computer class forms based on a new programming platform, network, and interface resulting in new industry. In 1951, men could walk inside a computer and now, computers are beginning to “walk” inside of us . Source: B Bell, “Bell’s Law for the Birth and Death of Computer Classes”, Comms of ACM, 2008 Chapter 1 — Computer Abstractions and Technology — 11 Chapter 1 — Computer Abstractions and Technology — 12 2 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 The 1st Generation Computer Computers Today Source: http://www.computerhistory.org Chapter 1 — Computer Abstractions and Technology — 13 Chapter 1 — Computer Abstractions and Technology — 14 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 The Computer Revolution The Computer Revolution (2) Progress in computer technology Computers in Automobiles Underpinned by Moore’s Law reduce pollution, improve fuel efficiency via engine controls, and increase safety through Makes novel applications feasible blind spot warnings, lane departure warnings, Computers in Automobiles moving object detection, and air bag inflation Cell Phones to protect occupants in a crash Human Genome project Cell Phones World Wide Web more than half of the planet having mobile Search Engines phones, allowing person-to-person Computers are pervasive communication to almost anyone anywhere in the world Chapter 1 — Computer Abstractions and Technology — 15 Chapter 1 — Computer Abstractions and Technology — 16 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 The Computer Revolution (3) The Computer Revolution (4) Human Genome Project World Wide Web a global effort to identify the estimated 30,000 has transformed our society. Web has genes in human DNA to figure out the replaced libraries and newspapers sequences of the chemical bases that make up human DNA to address ethical, legal, and Search Engines social issues As the content of the web grew in size and in value, many people rely on search engines The cost of computer equipment to map and analyze human DNA sequences was for such a large part of their lives that it would hundreds of millions of dollars. Since, costs be a hardship to go without them continue to drop, we will soon be able to acquire our own genome, allowing medical care to be tailored to us Chapter 1 — Computer Abstractions and Technology — 17 Chapter 1 — Computer Abstractions and Technology — 18 3 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 Classes of Computers Classes of Computers (2) Personal computers Personal computers Computers designed for use by an individual Server computers General purpose, variety of software Supercomputers Subject to cost/performance tradeoff Embedded computers Server computers Computers used for running larger programs for multiple users, often simultaneously Network based High capacity, performance, reliability Range from small servers to building sized Chapter 1 — Computer Abstractions and Technology — 19 Chapter 1 — Computer Abstractions and Technology — 20 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 Classes of Computers (3) The PostPC Era Supercomputers Smart phones represent Consist thousands of processors and many the recent growth in cell terabytes of memory phone industry, and they passed PCs in 2011. High-level scientific and engineering calculations Tablets are the fastest Highest capability and cost but represent a small growing category, nearly fraction of the overall computer market doubling between 2011 Embedded computers and 2012. Hidden as components of systems Recent PCs and traditional cell phone Largest class of computers and span the widest range of applications categories are relatively flat or declining. Strict power/performance/cost limitations Chapter 1 — Computer Abstractions and Technology — 21 Chapter 1 — Computer Abstractions and Technology — 22 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 The PostPC Era (2) The PostPC Era (3) Personal Mobile Devices (PMDs) Cloud computing Small wireless devices Term cloud essentially used for the Internet Battery operated Portion of software run on a PMD and portion Connects to the Internet run in the Cloud Hundreds of dollars Warehouse Scale Computers (WSCs) Big datacenters containing 100,000 servers Smart phones, tablets, electronic glasses Amazon and Google cloud vendors Software as a Service (SaaS) Delivers software and data as a service over the Internet Web search and social networking Chapter 1 — Computer Abstractions and Technology — 23 Chapter 1 — Computer Abstractions and Technology — 24 4 § § 1.1 Introduction 1.1 1.1 Introduction 1.1 What You Will Learn Understanding Performance How programs are translated into Algorithm machine language determines number of operations executed and how hardware executes them Programming language, compiler, architecture The hardware/software interface determine number of machine instructions executed per operation What determines program performance Processor and memory system and how it can be improved determine how fast instructions are executed How hardware designers improve I/O system (including OS) performance determine how fast I/O operations are What is parallel processing executed Chapter 1 — Computer Abstractions and Technology — 25 Chapter 1 — Computer Abstractions and Technology — 26 § § 1.2 Eight Great Ideas in Computer Architecture Computer in Ideas Great Eight 1.2 Architecture Computer in Ideas Great Eight 1.2 Eight Great Design Ideas Eight Great Design Ideas (2) Design for Moore’s Law Performance via Parallelism Computer designs can take years, resources available A form of computation in which many calculations per chip can easily double or quadruple between start are carried out simultaneously and finish of project Performance via Pipelining Anticipate where technology will be when design finishes A particular pattern of parallelism A set of data processing elements connected in Use Abstraction to simplify design series, so that the output of one element is the input Hide lower-level details to offer a simpler model at higher of the next one levels Performance via Prediction Make the Common Case Fast It can be faster on average
Load more

Recommended publications
  • Lecture #2 "Computer Systems Big Picture"
    18-600 Foundations of Computer Systems Lecture 2: “Computer Systems: The Big Picture” John P. Shen & Gregory Kesden 18-600 August 30, 2017 CS: AAP CS: APP ➢ Recommended Reference: ❖ Chapters 1 and 2 of Shen and Lipasti (SnL). ➢ Other Relevant References: ❖ “A Detailed Analysis of Contemporary ARM and x86 Architectures” by Emily Blem, Jaikrishnan Menon, and Karthikeyan Sankaralingam . (2013) ❖ “Amdahl’s and Gustafson’s Laws Revisited” by Andrzej Karbowski. (2008) 8/30/2017 (©J.P. Shen) 18-600 Lecture #2 1 18-600 Foundations of Computer Systems Lecture 2: “Computer Systems: The Big Picture” 1. Instruction Set Architecture (ISA) a. Hardware / Software Interface (HSI) b. Dynamic / Static Interface (DSI) c. Instruction Set Architecture Design & Examples 2. Historical Perspective on Computing a. Major Epochs of Modern Computers b. Computer Performance Iron Law (#1) 3. “Economics” of Computer Systems a. Amdahl’s Law and Gustafson’s Law b. Moore’s Law and Bell’s Law 8/30/2017 (©J.P. Shen) 18-600 Lecture #2 2 Anatomy of Engineering Design SPECIFICATION: Behavioral description of “What does it do?” Synthesis: Search for possible solutions; pick best one. Creative process IMPLEMENTATION: Structural description of “How is it constructed?” Analysis: Validate if the design meets the specification. “Does it do the right thing?” + “How well does it perform?” 8/30/2017 (©J.P. Shen) 18-600 Lecture #2 3 [Gerrit Blaauw & Fred Brooks, 1981] Instruction Set Processor Design ARCHITECTURE: (ISA) programmer/compiler view = SPECIFICATION • Functional programming model to application/system programmers • Opcodes, addressing modes, architected registers, IEEE floating point IMPLEMENTATION: (μarchitecture) processor designer view • Logical structure or organization that performs the ISA specification • Pipelining, functional units, caches, physical registers, buses, branch predictors REALIZATION: (Chip) chip/system designer view • Physical structure that embodies the implementation • Gates, cells, transistors, wires, dies, packaging 8/30/2017 (©J.P.
    [Show full text]
  • Pentium® III Processor Implementation Tradeoffs
    PentiumÒ III Processor Implementation Tradeoffs Jagannath Keshava and Vladimir Pentkovski: Microprocessor Products Group, Intel Corp. sense that the same sequence of operations can be ABSTRACT applied concurrently to multiple data elements. The This paper discusses the implementation tradeoffs of the Internet SSE allows us to express this parallelism explicitly, PentiumÒ III processor. The Pentium III processor but the hardware needs to be able to translate the implements a new extension of the IA-32 instruction set parallelism into higher performance. The P6 superscalar called the Internet Streaming Single-Instruction, Multiple- out-of-order microarchitecture is capable of utilizing Data (SIMD) Extensions (Internet SSE). The processor is explicit as well as extracted implicit parallelism. However, based on the PentiumÒ Pro processor microarchitecture. hardware that supports higher computation throughput improves the performance of these algorithms. The The initial development goals for the Pentium III processor development of such hardware and increasing its were to balance performance, cost, and frequency. utilization were key tasks in the development of the Descriptions of some of the key aspects of the SIMD Pentium III processor. Second, in order to feed the parallel Floating Point (FP) architecture and of the memory computations with data, the system needs to supply high streaming architecture are given. The utilization and memory bandwidth and hide memory latency. effectiveness of these architectures in decoupling memory accesses from computation, in the context of balancing the The implementation section of this paper contains details 3D pipe, are discussed. Implementation choices in some of some of the techniques we used to provide enhanced of the key areas are described.
    [Show full text]
  • Robert P. Colwell
    Case 3:07-cv-04748-VRW Document 57-2 Filed 06/09/2008 Page 1 of 6 ROBERT P. COLWELL 3594 NW BRONSON CREST LOOP PORTLAND, OR 97229 503-690-7139 [email protected] PROFESSIONAL EXPERIENCE Consultant, Portland, OR 2001-present General computer HW/SW consulting to industry and academia Named an Intel Fellow (27 Fellows in Intel's employee population of ~80,000) in 1997; winner of 2005 Eckert-Mauchly Award, highest award in field of computer architecture, for “outstanding achievements in the design and implementation of industry-changing microarchitectures, and for significant contributions to the RISC/CISC architecture debate”; elected to IEEE Fellow and the National Academy of Engineering in 2006 (the highest recognition in field of engineering) for “contributions to turning novel computer architecture concepts into viable, cutting-edge commercial processors.” Chief IA-32 Architect, Intel Corporation, Hillsboro OR, 1992-2001 Lead IA32 architect, responsible for all of Intel's Pentium CPU architecture efforts (my direct management included 40 – 110 people) Initiated and led Intel's Pentium 4 CPU development Senior CPU Architect, Intel Corporation, Hillsboro OR, 1990-1992 One of three senior architects responsible for conceiving Intel's P6 microarchitecture, the core of the company's Pentium II, Pentium III, Celeron, Xeon, and Centrino families Hardware Architect, Multiflow Computer, New Haven, CT 1985-1990 One of seven HW designers who created the world's first VLIW (very long instruction word) scientific supercomputer under direction
    [Show full text]
  • IEEE Computer Society President's Message Design Fragility Hybrid
    Innovative Technology for Computer Professionals January 2004 IEEE Computer Society President’s Message Design Fragility Hybrid CPU/FPGA Chips http://www.computer.org Innovative Technology for Computer Professionals January 2004,Volume 37,Number 1 PERSPECTIVES 30 A Tale of Three Disciplines ... and a Revolution Jesse H. Poore Some disciplines, like circuit and genetic engineering, seem to evolve from theory to practice relatively responsibly. Software engineering, on the other hand, while not yet at the guillotine, has suffered a decided lack of direction. It may be time to storm the gates. 37 The End of Science Revisited John Horgan Because science has advanced so rapidly over the past century or so, we assume that it can and will continue to do so, possibly forever. But science itself tells us that there are limits to our knowledge. COVER FEATURES 47 2003 Technology Roadmap for Semiconductors Don Edenfeld, Andrew B. Kahng, Mike Rodgers, and Yervant Zorian This update to the 2001 ITRS Roadmap shows the industry shifting its focus toward systems on chip, wireless computing, and mobile applications. 59 NASA’S Mission Reliable Patrick Regan and Scott Hamilton Like industrial development organizations, the US space agency struggles with the challenge of creating reliable software. NASA’s deep space community is attacking its software crisis via two complementary approaches—one stressing the power of engineering discipline, the other the potential of automated code generation and Cover design and artwork by Dirk Hagner verification. 69 IT Employment Prospects in 2004: A Mixed Bag ABOUT THIS ISSUE Fred Niederman n this January Outlook issue, Signs of general economic recovery and renewed IT sector growth we continue our tradition of are dampened for IT workers globally by improved productivity and I publishing articles that locally by a global labor market.
    [Show full text]
  • Oral History of Robert P. Colwell (1954- )
    Robert P. Colwell oral history Oral history of Robert P. Colwell (1954- ) Interviewed by Paul N. Edwards, Assoc. Prof., University of Michigan School of Information, at Colwell’s home near Portland, Oregon, on August 24-25, 2009 Robert P. Colwell is an electrical engineer. His PhD work at CMU (1980-1985) demonstrated the theoretical superiority of CISC architectures over RISC. From 1985-1990 he worked at Multiflow, an innovative developer of “minisupercomputers” using a VLIW (very long instruction word) architecture. In 1990 he joined Intel as a microchip designer, serving as the chief architect of Intel’s IA32 line from 1992-2000. He left Intel in 2001. Colwell recounted his experiences at Intel in his book The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips (WIley-IEEE, 2005). Since retirement, he has been a prolific columnist and a consultant on legal and patent issues. This oral history generally follows the chronology of Colwell’s life and career (see table of contents), with occasional digressions. The interviewer chose to avoid the areas discussed in Colwell’s book, which is semi-autobiographical. Some of Robert P. Colwell’s major achievements: • Senior CPU Architect, Intel Corporation, Hillsboro OR, 1990-1992 • Chief IA-32 Architect, Intel Corporation, Hillsboro OR, 1992-2001 o Lead IA32 architect, responsible for all of Intel's Pentium CPU architecture efforts o Initiated and led Intel's Pentium 4 CPU development o One of three senior architects responsible for conceiving Intel's P6 microarchitecture, the core of the company's Pentium II, Pentium III, Celeron, Xeon, and Centrino families • Intel Fellow - 1997 • 2005 Eckert-Mauchly Award from ACM: for “outstanding achievements in the design and implementation of industry-changing microarchitectures, and for significant contributions to the RISC/CISC architecture debate” • 2006 IEEE Fellow and the National Academy of Engineering for “contributions to turning novel computer architecture concepts into viable, cutting-edge commercial processors” 1 of 164 Robert P.
    [Show full text]
  • DARPA Strategic Overview
    Defense Advanced Research Projects Agency Dick Urban Special Assistant to the Director 19th Annual NDIA S&ET Conference March 2018 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited) DARPA’s Mission Breakthrough Technologies and Capabilities for National Security Precision Guidance & Navigation Communications/Networking IR Night Vision UAVs Stealth Radar Arrays 1960s 1970s 1980s 1990s 2000s 2010s 2020s Microelectronics: VLSI, CAD, manufacturing, IR, RF, MEMS ARPAnet/Internet Information Technology: timesharing, client/server, graphics, GUI, RISC, speech recognition Materials Science: semiconductors, superalloys, carbon fibers, composites, thermoelectrics, ceramics DARPA’s role: Pivotal early investments that change what’s possible Distribution Statement “A” (Approved for Public Release, Distribution Unlimited) 2 Major Factors Shaping DARPA Investments Today Wide range of threats to the nation: Enemy states, non-state actors, shifting networks, WMT Peer competitions on land (Europe), at sea (Asia), and in the EM and space domains Continuous and persistent counter-terrorism and counter-insurgency operations world-wide Powerful, globally available technologies set a fast pace Distribution Statement “A” (Approved for Public Release, Distribution Unlimited) 3 DARPA’s Portfolio Multi-varied threats Peer competitor confrontations in Continuous counter-terrorism and to the nation Europe and Asia counter-insurgency operations Defend the homeland Deter and prevail against Effectively prosecute high-end adversary stabilization
    [Show full text]
  • The Pentium Chronicles: Introduction
    COVER FEATURE The Pentium Chronicles: Introduction Robert P. Colwell God tells me how the music should sound, but you stand in the way. —Arturo Toscanini, to a trumpet player n June 1990, I joined Intel Corporation’s new Ore- Intel’s lead IA-32 architect from 1992 through 2000. gon microprocessor design division as a senior com- Somewhat to my surprise, the P6 design project turned puter architect on a new project, the P6. This divi- out to be a watershed event in the history of the com- sion would eventually grow to thousands of people puter industry and the Internet; it could keep up with I but at the moment it had a population of exactly the industry’s fastest chips, especially those from one—me. I spent my first day buried in forms, picking reduced-instruction-set computer (RISC) manufactur- primary health-care providers mostly on the basis of ers, and it had enough flexibility and headroom to serve how much I liked their names. The second day, my boss as the basis for many future proliferation designs. stuck his head in my office and said, “Your job is to beat It also gave Intel a foothold in the maturing worksta- the P5 chip by a factor of two on the same process tech- tion market, and it immediately established them in the nology. Any questions?” I replied, “Three. What’s a P5? server space just as the Internet was driving up demand Can you tell me more about Intel’s process technology for inexpensive Web servers. plans? And where’s the bathroom?” The P6 project would eventually grow to over 400 P5, as it turned out, was the chip the Intel Santa Clara design and validation engineers and take 4.5 years to design team was developing, the team that had created production.
    [Show full text]
  • Beyond Moore's Technologies: Operation Principles of A
    Beyond Moore’s technologies: operation principles of a superconductor alternative Igor I. Soloviev*1, Nikolay V. Klenov1,2,3, Sergey V. Bakurskiy1, Mikhail Yu. Kupriyanov1,4, Alexander L. Gudkov5 and Anatoli S. Sidorenko4,6 Review Open Access Address: Beilstein J. Nanotechnol. 1Lomonosov Moscow State University, Skobeltsyn Institute of Nuclear doi: Physics, 119991, Moscow, Russia, 2Lomonosov Moscow State University, Physics Department, 119991, Moscow, Russia, 3Moscow Received: 26 June 2017 Technological University (MIREA), 119454, Moscow, Russia, 4Solid Accepted: 19 November 2017 State Physics Department, Kazan Federal University, 420008, Kazan, Published: Russia, 5Lukin Scientific Research Institute of Physical Problems, 124460, Zelenograd, Moscow, Russia and 6Ghitu Institute of Associate Editor: P. Leiderer Electronic Engineering and Nanotechnologies ASM, Chisinau, Moldova © Soloviev et al.; licensee Beilstein-Institut. License and terms: see end of document. Email: Igor I. Soloviev* - [email protected] * Corresponding author Keywords: energy-efficient computing; Josephson memory; superconducting computer; superconductor digital electronics; superconductor logics Abstract The predictions of Moore’s law are considered by experts to be valid until 2020 giving rise to “post-Moore’s” technologies after- wards. Energy efficiency is one of the major challenges in high-performance computing that should be answered. Superconductor digital technology is a promising post-Moore’s alternative for the development of supercomputers. In this paper, we consider opera- tion principles of an energy-efficient superconductor logic and memory circuits with a short retrospective review of their evolution. We analyze their shortcomings in respect to computer circuits design. Possible ways of further research are outlined. Introduction Intel, one of the world’s largest chipmakers, “has signaled a technology as follows [3]: “Officially Moore’s Law ends in slowing of Moore’s Law” [1].
    [Show full text]
  • The Unadbridged Pentium 4: IA32 Processor Genealogy
    world-class technical training Are your company’s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge technologies. We understand the challenges companies have when searching for quality, effective training which reduces the students’ time away from work and provides cost-effective alternatives. MindShare offers many fl exible solutions to meet those needs. Our courses are taught by highly-skilled, enthusiastic, knowledgeable and experienced instructors. We bring life to knowledge through a wide variety of learning methods and delivery options. training that fi ts your needs MindShare recognizes and addresses your company’s technical training issues with: • Scalable cost training • Customizable training options • Reducing time away from work • Just-in-time training • Overview and advanced topic courses • Training delivered effectively globally • Training in a classroom, at your cubicle or home offi ce • Concurrently delivered multiple-site training MindShare training courses expand your technical skillset 2 PCI Express 2.0 ® 2 Serial Attached SCSI (SAS) 2 Intel Core 2 Processor Architecture 2 DDR2/DDR3 DRAM Technology 2 AMD Opteron Processor Architecture 2 PC BIOS Firmware 2 Intel 64 and IA-32 Software Architecture 2 High-Speed Design 2 Intel PC and Chipset Architecture 2 Windows Internals and Drivers 2 PC Virtualization 2 Linux Fundamentals 2 USB 2.0 ... and many more. 2 Wireless USB All courses can be customized to meet your 2 Serial
    [Show full text]
  • Opportunities and Challenges for Better Than Worst-Case Design
    Opportunities and Challenges for Better Than Worst-Case Design Todd Austin, Valeria Bertacco, David Blaauw, and Trevor Mudge Advanced Computer Architecture Lab The University of Michigan [email protected] ABSTRACT noted that these new challenges add to the many challenges The progressive trend of fabrication technologies towards that architects already face in order to scale systems' per- the nanometer regime has created a number of new physical formance while meeting power and reliability budgets. design challenges for computer architects. Design complex- The ¯rst challenge of concern is design complexity. As ity, uncertainty in environmental and fabrication conditions, silicon feature sizes decrease, architects have available in- and single-event upsets all conspire to compromise system creasingly large transistor budgets. According to Moore's correctness and reliability. Recently, researchers have be- law, which has been tracked for decades by the semiconduc- gun to advocate a new design strategy, called Better Than tor industry, architects can expect to have available twice Worst-Case design, that couples a complex core component the number of transistors every 18 months. In pursuit of with a simple reliable checker mechanism. By delegating the increased system performance, they typically employ these responsibility for correctness and reliability of the design to transistors in components that contribute to increased in- the checker, it becomes possible to build correct-certi¯ed struction level parallelism and reduced operational latency. designs that e®ectively address the challenges of deep sub- While many of these transistors are assigned to regular, micron design. easy-to-verify components, such as branch predictors and In this paper, we present the concepts of Better Than caches, many others ¯nd their way into complex devices Worst-Case design and highlight two exemplary designs: the that increase the burden of veri¯cation placed on the de- DIVA checker and Razor logic.
    [Show full text]