History of NSA General Purpose Electronic Digital Computers
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Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
Solid State Drives Data Reliability and Lifetime
Solid State Drives Data Reliability and Lifetime White Paper Alan R. Olson & Denis J. Langlois April 7, 2008 Abstract The explosion of flash memory technology has dramatically increased storage capacity and decreased the cost of non-volatile semiconductor memory. The technology has fueled the proliferation of USB flash drives and is now poised to replace magnetic hard disks in some applications. A solid state drive (SSD) is a non-volatile memory system that emulates a magnetic hard disk drive (HDD). SSDs do not contain any moving parts, however, and depend on flash memory chips to store data. With proper design, an SSD is able to provide high data transfer rates, low access time, improved tolerance to shock and vibration, and reduced power consumption. For some applications, the improved performance and durability outweigh the higher cost of an SSD relative to an HDD. Using flash memory as a hard disk replacement is not without challenges. The nano-scale of the memory cell is pushing the limits of semiconductor physics. Extremely thin insulating glass layers are necessary for proper operation of the memory cells. These layers are subjected to stressful temperatures and voltages, and their insulating properties deteriorate over time. Quite simply, flash memory can wear out. Fortunately, the wear-out physics are well understood and data management strategies are used to compensate for the limited lifetime of flash memory. Floating Gate Flash Memory Cells Flash memory was invented by Dr. Fujio Masuoka while working for Toshiba in 1984. The name "flash" was suggested because the process of erasing the memory contents reminded him of the flash of a camera. -
Embedded DRAM
Embedded DRAM Raviprasad Kuloor Semiconductor Research and Development Centre, Bangalore IBM Systems and Technology Group DRAM Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example References Slide 1 Acknowledgement • John Barth, IBM SRDC for most of the slides content • Madabusi Govindarajan • Subramanian S. Iyer • Many Others Slide 2 Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example Slide 3 Memory Classification revisited Slide 4 Motivation for a memory hierarchy – infinite memory Memory store Processor Infinitely fast Infinitely large Cycles per Instruction Number of processor clock cycles (CPI) = required per instruction CPI[ ∞ cache] Finite memory speed Memory store Processor Finite speed Infinite size CPI = CPI[∞ cache] + FCP Finite cache penalty Locality of reference – spatial and temporal Temporal If you access something now you’ll need it again soon e.g: Loops Spatial If you accessed something you’ll also need its neighbor e.g: Arrays Exploit this to divide memory into hierarchy Hit L2 L1 (Slow) Processor Miss (Fast) Hit Register Cache size impacts cycles-per-instruction Access rate reduces Slower memory is sufficient Cache size impacts cycles-per-instruction For a 5GHz -
Computer Organization & Architecture Eie
COMPUTER ORGANIZATION & ARCHITECTURE EIE 411 Course Lecturer: Engr Banji Adedayo. Reg COREN. The characteristics of different computers vary considerably from category to category. Computers for data processing activities have different features than those with scientific features. Even computers configured within the same application area have variations in design. Computer architecture is the science of integrating those components to achieve a level of functionality and performance. It is logical organization or designs of the hardware that make up the computer system. The internal organization of a digital system is defined by the sequence of micro operations it performs on the data stored in its registers. The internal structure of a MICRO-PROCESSOR is called its architecture and includes the number lay out and functionality of registers, memory cell, decoders, controllers and clocks. HISTORY OF COMPUTER HARDWARE The first use of the word ‘Computer’ was recorded in 1613, referring to a person who carried out calculation or computation. A brief History: Computer as we all know 2day had its beginning with 19th century English Mathematics Professor named Chales Babage. He designed the analytical engine and it was this design that the basic frame work of the computer of today are based on. 1st Generation 1937-1946 The first electronic digital computer was built by Dr John V. Atanasoff & Berry Cliford (ABC). In 1943 an electronic computer named colossus was built for military. 1946 – The first general purpose digital computer- the Electronic Numerical Integrator and computer (ENIAC) was built. This computer weighed 30 tons and had 18,000 vacuum tubes which were used for processing. -
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 6, JUNE 2011 1495 A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H. Kim, Senior Member, IEEE Abstract—Circuit techniques for enabling a sub-0.9 V logic-com- for achieving low static power and high operating speed. patible embedded DRAM (eDRAM) are presented. A boosted 3T SRAMs have been the embedded memory of choice due to gain cell utilizes Read Word-line (RWL) preferential boosting to their logic compatibility and fast access time. Recently, em- increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense amplifier that al- bedded DRAMs (eDRAMs) have been gaining popularity in lows the Read Bit-line (RBL) to remain close to VDD. A regu- the research community due to features such as small cell size, lated bit-line write scheme for driving the Write Bit-line (WBL) is low cell leakage, and non-ratioed circuit operation. There have equipped with a steady-state storage node voltage monitor to over- been a number of successful eDRAM designs based on tradi- come the data ‘1’ write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word- tional 1T1C DRAM cells as well as logic-compatible gain cells line (WWL) over-drive. An adaptive and die-to-die adjustable read [2]–[9]. 1T1C cells are denser than gain cells, but at the cost of a reference bias generator is proposed to cope with PVT variations. -
SRAM Edram DRAM
Technology Challenges and Directions of SRAM, DRAM, and eDRAM Cell Scaling in Sub- 20nm Generations Jai-hoon Sim SK hynix, Icheon, Korea Outline 1. Nobody is perfect: Main memory & cache memory in the dilemma in sub-20nm era. 2. SRAM Scaling: Diet or Die. 6T SRAM cell scaling crisis & RDF problem. 3. DRAM Scaling: Divide and Rule. Unfinished 1T1C DRAM cell scaling and its technical direction. 4. eDRAM Story: Float like a DRAM & sting like a SRAM. Does logic based DRAM process work? 5. All for one. Reshaping DRAM with logic technology elements. 6. Conclusion. 2 Memory Hierarchy L1$ L2$ SRAM Higher Speed (< few nS) Working L3$ Better Endurance eDRAM Memory (>1x1016 cycles) Access Speed Access Stt-RAM Main Memory DRAM PcRAM ReRAM Lower Speed Bigger Size Storage Class Memory NAND Density 3 Technologies for Cache & Main Memories SRAM • 6T cell. • Non-destructive read. • Performance driven process Speed technology. eDRAM • Always very fast. • 1T-1C cell. • Destructive read and Write-back needed. • Leakage-Performance compromised process technology. Standby • Smaller than SRAM and faster than Density Power DRAM. DRAM • 1T-1C cell. • Destructive read and Write-back needed. • Leakage control driven process technology. • Not always fast. • Smallest cell and lowest cost per bit. 4 eDRAM Concept: Performance Gap Filler SRAM 20-30X Cell Size Cell eDRAM DRAM 50-100X Random Access Speed • Is there any high density & high speed memory solution that could be 100% integrated into logic SoC? 5 6T-SRAM Cell Operation VDD WL WL DVBL PU Read PG SN SN WL Icell PD BL VSS BL V SN BL BL DD SN PD Read Margin: Write PG PG V Write Margin: SS PU Time 6 DRAM’s Charge Sharing DVBL VS VBL Charge Sharing Write-back VPP WL CS CBL V BL DD 1 SN C V C V C C V S DD B 2 DD S B BL 1/2VDD Initial Charge After Charge Sharing DVBL T d 1 1 V BL SS DVBL VBL VBL VDD 1 CB / CS 2 VBBW Time 1 1 I t L RET if cell leakage included Cell select DVBL VDD 1 CB / CS 2 CS 7 DRAM Scalability Metrics BL Cell WL CS • Cell CS. -
GT-2 Launch Scheduled This Week the Launch of the Unmanned Azimuth of 105 Degrees
VOL. 4 NO. 7 MANNED SPACECRAFT CENTER, HOUSTON, TEXAS JANUARY 20, 1965 GT-2 Launch Scheduled This Week The launch of the unmanned azimuth of 105 degrees. Space- seats were not armed for ejec- additional buoyancy until the Ocmini spacecraft 2 I(JT-2). craft separation was to be fol- tion. Both seats were clamped to spacecraft could be lifted aboard _hich _as postponed December lowed by a turn-around and the seat rails to minimize vibra- the aircraft carrier by a crane. 9. x_a,_ scheduled to ha_e been maneuver to retroattitude. The tion damage to the trey, simula- The main parachute for land- launched no earlier than vcstcr- rctrorockets, though not needed tars. ing the GT-2 spacecraft is an day from Complex 19 at Cape to perform this mission, were to l'rimc recovery ship for the 84-foot-diameter ringsail chute Kenned}, Fla. be _,equencc fired 62 seconds missionis the USS l_akeCham- designed to provide stable de- The _crvo ,,alxe flange that after _,pacecraft ",eparation. plain, the aircraft carrier that scent at a vertical velocity of 30 11 cracked, causing a delay in the The panel instruments _ere to recovered A_tronaut Alan fcet per second at sea level. flight, along _ith other ,,ervo be monitored during the GT-2 Shepard's Freedom 7spacecraft. The parachute deploys and xalve,, on the Titan ll, were re mb, sion by three 16ram black May 5. 1961. supports the spacecraft verti- placcd_ilh hcaxicrandstronger and x_hite motion picture U.S. Naval forces were to be tally for 22 seconds, then the forging,, and certain modifica- camera,, mounted on the crev, deployed along the flight path single point suspension is re- 'i! tions_cre made in the hydraulic simulator pallets, with another with recovery of the spacecraft leased permitting the,,pacecraft sy,dcm, camera recording the command programmed to take place about to reposition to a two-point The modilied Ti'tan 11 booster pilot's viev_ out the left window, 800 miles east of San Juan, bridle suspension. -
F:He UNIVAC®490 Real-Time Sysf:Em
GENERAL DESCRIPTION.. f:he UNIVAC®490 Real-Time Sysf:em o • GENERAL DESCRIPTION UNIVAC 490 Real-Time Sys-tem © 1961 • SPERRY RAND CORPORATION Contents 1. UNIVAC 490 REAL-TIME SYSTEM The Real-Time Concept. ............ ........................................... 1 General Characteristics of the Real-Time System.................... ...... ... .. 2 High-Speed Communications Linkage........................................... 2 Data Storage Facilities. 2 Features and Applications ...................................................... 2 Processing Interrupt..... .......... .. ....... .. .. .. .. ... ... ... .. .... .. .. .. 2 Solid-State Design ........................................................... 3 Computer-to-Computer Configurations....................................... 3 High-Speed Random Access Storage.................... ... ............... ... 3 A "Time Conscious" System ................................................. 3 Incremental Clock...................................................... ..... 3 Incremental Interrupt Clock........................... ............ ...... ..... 3 Day Clock................................................................... 3 High Internal Computing Speeds........................................... .. 4 Equipment Enclosure..................................................... ... 4 Flexible Input-Output Facilities.......................................... ..... 4 Automatic Programming ..................................................... 4 Floating-Point Arithmetic ................................................... -
Sperry Corporation, UNIVAC Division Photographs and Audiovisual Materials 1985.261
Sperry Corporation, UNIVAC Division photographs and audiovisual materials 1985.261 This finding aid was produced using ArchivesSpace on September 14, 2021. Description is written in: English. Describing Archives: A Content Standard Audiovisual Collections PO Box 3630 Wilmington, Delaware 19807 [email protected] URL: http://www.hagley.org/library Sperry Corporation, UNIVAC Division photographs and audiovisual materials 1985.261 Table of Contents Summary Information .................................................................................................................................... 3 Historical Note ............................................................................................................................................... 4 Scope and Content ......................................................................................................................................... 5 Arrangement ................................................................................................................................................... 6 Administrative Information ............................................................................................................................ 6 Related Materials ........................................................................................................................................... 7 Controlled Access Headings .......................................................................................................................... 8 Bibliography -
6.823 Computer System Architecture
6.823 Computer System Architecture Instructors: Daniel Sanchez and Joel Emer TA: Hyun Ryong (Ryan) Lee What you’ll understand after The processor you taking 6.823 built in 6.004 September 8, 2021 MIT 6.823 Fall 2021 L01-1 Computing devices then… September 8, 2021 MIT 6.823 Fall 2021 L01-2 Computing devices now September 8, 2021 MIT 6.823 Fall 2021 L01-3 A journey through this space • What do computer architects actually do? • Illustrate via historical examples – Early days: ENIAC, EDVAC, and EDSAC – Arrival of IBM 650 and then IBM 360 – Seymour Cray – CDC 6600, Cray 1 – Microprocessors and PCs – Multicores – Cell phones • Focus on ideas, mechanisms, and principles, especially those that have withstood the test of time September 8, 2021 MIT 6.823 Fall 2021 L01-4 Abstraction layers Application Algorithm Parallel computing, Programming Language specialization, Original Operating System/Virtual Machine security, … domain of the Instruction Set Architecture (ISA) Domain of computer Microarchitecture computer architect architecture (‘90s) (‘50s-‘80s) Register-Transfer Level (RTL) Circuits Reliability, power Devices Expansion of Physics computer architecture, mid- 2000s onward. September 8, 2021 MIT 6.823 Fall 2021 L01-5 Computer Architecture is the design of abstraction layers • What do abstraction layers provide? – Environmental stability within generation – Environmental stability across generations – Consistency across a large number of units • What are the consequences? – Encouragement to create reusable foundations: • Toolchains, operating systems, libraries – Enticement for application innovation September 8, 2021 MIT 6.823 Fall 2021 L01-6 Technology is the dominant factor in computer design Technology Transistors Computers Integrated circuits VLSI (initially) Flash memories, … Technology Core memories Computers Magnetic tapes Disks Technology ROMs, RAMs VLSI Computers Packaging Low Power September 8, 2021 MIT 6.823 Fall 2021 L01-7 But Software.. -
Programming the IBM 650
RICHARD v ANDREE ASSOCIATE PROFESSOR OF MATHEMATIC S UNIVERSITY OF OKLAH O MA c - .....- If' '" .. " \ ' 0 .. N G OA t .. ........ ".•0t0l .... --\I'• .Q\; ....... -, OtU;t1Q1t•" ~ .;. ... 1<• ..,'0<" ~ut .....ucnooo ....' U .. "CO Olffhl.. Ow I • ~ 0 0 4. • 0 0 &8CMltU ~ aut\lU '-'Sfb&tJTOIt L ~ ItI~ :U· IlCII'.'" tu.II _ ife» '-'*' QHaAnoe , ...."a SfOfJ SINN no-C .~~' . '. - " ..,. I ( , I. • • • • • • • • "'f"'. ~.. • ',01 ~ IoOW1I ~ _ ....... ... ,~..- J 4«t* , no.. .., , , 't' ' \' , ,.' ~ .' ;' .. I~ MOGt£MMtO NW oa. • 0 0 • • " ,. ~ I ( ,. I 0 If • C()trl:ft.Ol ~. DGPUoy ovtut&'W ~ '''0'1 -- , , . ' I .. .. 'I O(.. IAM (O MJI ~T! " ,I,(Cu' ~I"O""¥I .. ~ .•• ~, I I I "'.' I HH;( I __ ~ S1"" I SlO'. ~ I IlUf HUT U$U l......... ' , • j ~ ~., " id , ~j ~' ·;1 ,IJ ', ',' .' • t., ." '" (, It \ t \' .. , '.3 ~: . f .. _ ... ~ .. ~ ~ . " ' . , '. \t J \' '' ':l!~ t. ','l ) '. J '\ :..' ~. , • , • • ,_ r: .. ' : ,' rW , Ii •• , ' . ~ • " f ,,;. " ,',.' • -elf!" ~-iJ~ !) , r "" ... _, _ _ .. ... .. - ".'" 't. ~" ~ _ ~ f. _ _ ." ~'f--_ _ i __ ~ '* - ;. 4 ' ~ ! /~ RICHARD V. ANDREE ASSOCIATE PROFESSOR OF MATHEMATICS UNIVERSITY OF OKLAHOMA U U U 11 ;J n I] HOLT, RINEHART AND WINSTON, INC. 383 MADISON AVENUE, NEW YORK 17, N. Y. Dedication II II I I I I I II I I I I I III I I II I 1111 " I I I I II I III I I I I III I II 10000010000010000000111000000000100000110010000001000001000000000110000000000000 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 272829 JO 313233343536 37 38 39 40414243« 45 46 47 48 49 50 5152535455565158596061626364656667686970717213747576 -
Recapping a Decade of IT Legacy Committee Accomplishments
Measuring Success = Volunteer Hours! Recapping a Decade of IT Legacy Committee Accomplishments. December 2015 ©2015, Lowell A. Benson for the VIP Club. Measuring Success = Volunteer Hours! December 6, 2015 The VIP Club's Why, What, and Who. From our constitution MISSION: The VIP CLUB is a social and service organization dedicated to enriching the lives of the members through social interaction and dissemination of information. GOALS: The CLUB shall provide an opportunity for social interaction of its members. The CLUB shall provide services and information appropriate to the interest of its members. The CLUB shall provide a mechanism for member services to the community. The CLUB shall provide a forum for information on the heritage and on-going action of the heritage companies (Twin Cities based Univac/Unisys organizations and the predecessor and successor firms). MEMBERS are former employees and their spouses of Twin-Cities- based Univac / Unisys organizations and predecessor or successor business enterprises who are retired or eligible to retire, and are at least 55 years of age - Membership is voluntary. Payment of annual dues is a condition of membership. Each membership unit (retiree and spouse) is entitled to one vote. The CLUB maintains a master file of all members. This master file is the property of the CLUB and is used for communication with members and for facility access. We dedicate this booklet/article to ‘Ole’ and our VIP Club founder, Millie Gignac. ©2015, LABenson for the VIP Club Measuring Success = Volunteer Hours! Introduction The VIP Club's Information Technology (IT) Legacy Committee started in October 2005 when LMCO's Richard 'Ole' Olson brought a Legacy committee idea to the VIP Club's board.