GENERAL DESCRIPTION..
f:he UNIVAC®490 Real-Time Sysf:em
o • GENERAL DESCRIPTION
UNIVAC 490 Real-Time Sys-tem
© 1961 • SPERRY RAND CORPORATION Contents
1. UNIVAC 490 REAL-TIME SYSTEM The Real-Time Concept...... 1 General Characteristics of the Real-Time System...... 2 High-Speed Communications Linkage...... 2 Data Storage Facilities...... 2 Features and Applications ...... 2 Processing Interrupt...... 2 Solid-State Design ...... 3 Computer-to-Computer Configurations...... 3 High-Speed Random Access Storage...... 3 A "Time Conscious" System ...... 3 Incremental Clock...... 3 Incremental Interrupt Clock...... 3 Day Clock...... 3 High Internal Computing Speeds...... 4 Equipment Enclosure...... 4 Flexible Input-Output Facilities...... 4 Automatic Programming ...... 4 Floating-Point Arithmetic ...... 4 Programming Checks...... 4 Special Programming Features...... 5 Powerful Instruction Repertoire...... 5 Absolute Efficiency ...... 5 Library of Programmed Routines...... 5 Core Storage Search ...... 5 Wired Memory...... 5 Application Versatility ...... 6
2. REAL-TIME COMPUTER Storage Section ...... 7 Octal Notation...... 7 Control Section ...... 8 Arithmetic Section...... 8 Arithmetic Registers (Operational Registers) ...... 9 Transient Registers ...... 10 Operator Console ...... 11 Computer Control Panel ...... 11 Console Keyboard and Printer ...... 11 Wired Memory...... 11 3. SYSTEM COMPONENTS AND CONFiGURATiONS Central Site Equipment ...... •..... 12 Peripheral Units...... 12 Peripheral Systems ...... •.•...... 12 Magnetic Drum Storage ...... •.....•...... 14 Magnetic Tape Storage ...•...... ••...... 15 High-Speed Card Reader...... •...... 16 Punch-Verifier Unit ...... •...... •...... •...... 16 High-Speed Printer ...... •...... 17 Transmission and Communications ...... •...... 18 Input-Output Channels ...... •.....•...... 18 Data Transfers ...... •...... •...... 18 Buffer Mode...... • ...... 18 I nput-Output Control ...... ••...... 18 External Equipment Requirements ...... 19 Remote Input-Output Devices ...... •...... 19 Keyboard Printer ...... •...... •...... 19 Uniset Console ...... •...... ••...... •...... 20 The Uniset ...... • 21 Format Control Panel ...... •...'...... • ...... • ...... 21 Communications Equipment ...... •...... 21 Communications Systems ...... 23 Party Line Network ...... , 23 Scanner - Selector ...... •...... •...... •...... 23 Party Line Communications System ...... 23 Transfer Function ...... •...•...... 24 Line Switching Network (Direct Distance Dialing) ...... •. 24 Communications Control Unit (Telegraphic Half-Duplex) ...... 24 Communications Equipment for Special Devices ...... 26
4. INSTRUCTIONS Instruction Word ...... 27 Instruction Cycle ...... •...... 27 Instruction Repertoire...... 28 Shift Instructions ...... , ...... " ...... '" ...... 28 Simple Read Instructions ...... 29 Store Instructions ...... 29 Arithmetic Read Instructions ...... 30 Comparison Instructions ...... 30 Selective Instructions ...... •...... 31 Replace Instructions ...... 31 Jump Instructions ...... 32 Special Program - Modifying Instructions ..•...... •...... 33 just as feedback is used by a computer to control a missile's path;: ....
• •• up-to-the-minute data from a UNIVAC Real-Time System can help influence the course of business curves. 1. UNIVAC 490 Real-Time System
The UNIVAC® 490 Real-Time System is a versing the direction of a business curve large-scale, general purpose digital com before it gains momentum and attains puting system specifically designed for the black-and-white finality. Up-to-the-minute dynamic organization which has diverse indications of business activity enable the operations demanding stricter control real-time user to detect the suggestion of a based on real-time computing. This new downturn and correct it immediately, in system extends valuable techniques of real much the same way as a guided missile's tinle processing, long restricted to a linlited course is adj usted as it hurtles to its target. number of special military applications If, for example, sales have dipped slightly, such as missile guidance, to the broader the Real-Time Computer will allow man field of commercial problems. agement to discover this fact immediately, instead of waiting for quarterly reports. As Remington Rand's installation of UNIVAC a result, management's remedial actions Airlines Reservation Systems at several are effectively timed. And it is the timely major airlines demonstrated the power of decision which has the greatest significance real-time processing. A centrally located in the intensified competition of business TTl\.TT1T A {'1 ...,;1", ('1n.-VV>V1>"t-",..,. ~'""".n.H;;J",,,, +1;noh+ ; ..... ~~...J !~...J .. ~./-~ __ ./-~...J ___ rn~ _~~ ..._~ ./-! ___ 1! __ ~~ ! __ \..).J..~.L l'.c:t..V.L" LH:;;-VV"LJ..J..pU.~'-'L PLVl'LU.'-''' .J...J..L.5L.J..~ LLL- a.llU 111U ut::) Ll y LVUa.y • .1. V a.t::)t::)Ul e LllllelllH~t::)t::) 111 formation in a fraction of a second to ticket organizational activities, it is necessary to offices scattered throughout the country. utilize a real-time processing system, with The well-documented success of the Airline its ability to communicate with many Reservations System proved the potential remote locations and its large storage fa of real-time processing and served as the cilities, to reflect sales, profits, costs, pro incentive for its full development. duction, and other pertinent data.
Now, with the Real-Time System, the full Thus, the real-time concept is a significant commercial potential of real-time process advance in data-processing, a field which ing can become an integral part of your heretofore employed batch processing only. business, bringing with it an efficiency and That is, master data, or information which control only approximated by other devices. is altered infrequently or in a known man In fact, just as feedback is used by a com ner, was updated at intervals, upon the ac puter to control a missile's path and coun cumulation of enough transaction data, or teract disrupting forces, up-to-the-minute information characterized by essentially data from a real-time system can help an random and unpredictable incidence. Real organization influence the course of a time processing, however, eliminates the number of its business curves as they are lag between the occurrence of transactions formed. and their postings to a master file. By up dating the master file immediately upon THE REAL-TIME CONCEPT receipt of a new transaction from a remote The real-time concept is the fulfillment of source, the Real-Time System can present management's desire for a method of re- a truly current report of the status of any
1 application-a feat impossible for the batch The many outstanding features of the processing computer with its externally UNIV AC 490 Real-Time System are par stored master data. ticularly suited to applications in which processing timeliness is vitally important, GENERAL CHARACTERISTICS OF THE perishability is a factor, or decision-making REAL-TIME SYSTEM is based on data originating simultaneously The specific design and function of the re at separate, remote points. Some of these mote input-output units of the UNIVAC features, such as solid-state components 490 Real-Time System are dictated by the and microsecond internal computing nature of the individual application. In speeds~ represent the latest design advances general, however, input units are able to in the electronic computer field. Other fea accept transaction data with speed and tures of the system, such as the ability to reliability while the output units display communicate with remote locations and to results with accuracy and clarity. The com perform both real-time and batch-process puting unit of the system is general pur ing applications, are entirely new develop pose, and therefore, ideal for all types of ments. applications. Some of the major features of the UNIVAC High-Speed Communications Linkage 490 Real-Time System are described briefly in the following paragraphs. Common carriers, such as American Tele phone and Telegraph, Western Union, Processing Interrupt American Cable and Radio, afford high An outstanding feature of the UNIVAC speed communication facilities for two-way 490 Real-Time System is its capacity to transmission of data between the central process real-time and batch-processing site Computer and the remote input-output applications concurrently. This impressive units. Transactions originating at remote data-processing innovation is made possi points are conveyed along these wires di ble through a unique feature that permits rectly to the Computer where they are im remote external units to interrupt Com mediately evaluated and processed. Then puter processing with information of high the result is returned to the originator and precedence. other appropriate distant points, the whole transaction being accomplished in seconds. With this feature the maximum process ing potential of the system is realized. For Data Storage Facilities example, when once the master data for a Since the UNIVAC 490 Real-Time System particular real-time application is recorded applies transaction data to the master file in storage, the Computer can be used to information as the transaction data occurs, process a "batch" application. Then, when the system employs extensive data-storage ever transaction data for the real-time facilities which are capable of storing en problem is entered into a remote external tire master files of information. In addition, unit, the Computer's batch-processing is these facilities are of the random access interrupted to permit handling the high type allowing immediate access to master priority real-time transaction and sending file information. the processed results to the external unit. Upon completion of the real-time process FEATURES AND APPLICATIONS ing, the Computer automatically returns to In addition to existing applications best the batch application. Further, if the real performed by this system, there is a grow time information handled during the inter ing number of vital data-processing prob rupt bears on the interrupted application, lems that depend on this type of automation the latter can be updated by the real-time -the UNIVAC 490 Real-Time System-for data, thereby assuring that all subsequent their effective solution. processing is up to date.
2 Sol id-State Design Incremental-Interrupt Clock The solid-state components and circuitry of This "program-set" clock counts up to the UNIVAC 490 Real-Time System offer 32,768 milliseconds. Upon reaching its up numerous advantages including standard per limit, the Incremental-Interrupt Clock ized production of components and the re unconditionally interrupts the Computer at duction of maintenance procedures to a few the end of the instruction being handled, relatively simple operations. In addition to regardless of the type of instruction. The ease of production and maintenance, solid clock count is maintained in core storage. state circuits also impart a high degree of The Incremental-Interrupt Clock is vital to operating reliability to the Computer while the functioning of a real-time system be reducing the power, cooling, and space re cause one of the primary uses of this clock quirements of the system. is timing subroutine operations. If a mo mentary fault arising from improper pro Computer-to-Computer Configurations gramming throws the Computer into a The UNIVAC 490 Real-Time System's abil closed loop, or if a fault occurring during ity to coordinate, through communication the execution of an instruction halts the networks, the activities of several Com Computer, the Incremental-Interrupt Clock puters located at various points, allows the restarts the Computer by means of an in user to increase his data-processing system terrupt, thus providing automatic fault to meet any sudden business expansion. recovery. The interrupt can be used to no High-Speed Random Access Storage tify maintenance personnel that a closed loop has occurred. If completing an opera To meet the extremely demanding require tion takes longer than desired, this clock is ments of real-time processing, the also used to interrupt the Computer and UNIVAC 490 Real-Time System is equipped thereby allow program attention to be di with data-storage facilities (drums, tapes) rected to items of more immediate impor that are more expansive and versatile than tance. those of most present-day computing sys tems. The Computer has an internal co:re Day Clock memory with a capacity of 32,768 or 16,384 A feature particularly suited to real-time 30-bit words. problems is the 24-hour Day Clock. As an auxiliary device, this electronic clock causes A "Time Conscious" System an external interrupt of Computer process Processing timeliness, an inherent charac ing once every minute. Thus, "keeping teristic of real-time processing, requires time" is placed completely under the pro.. the system to be extremely "time con grammer's direction. scious." Three precision electronic chro Since program control is shifted once every nometers provide the system with a timing minute to a set address in the Computer, sensitivity unmatched by other computing the Day Clock can be used to initiate a va systems. riety of subroutines. For example, by using a compare routine on the address reserved Incremental Clock for timing purposes, reports can be gener This built-in clock is used for a wide variety ated at any desired time of the day, week or of program-timing purposes. It can be used month. These reports could provide up-to to log the receipt times of aperiodic real the-minute information and analyses of time input data. Each input message and company status. Error-checking routines, its receipt time may be recorded together. trace routines, output conversions, manage This clock is also used in connection with ment report programs, maintenance rou the preparation of statistical and analyt tines, and memory dumps are some of the ical reports dealing with the frequency of many routines which can be initiated by certain transactions. the Day Clock.
3 High-Internal Computing Speeds A large number of system input-output Along with its high-speed random access channels are employed for communications storage facilities, which allow a high data between the Computer and peripheral site transmission rate between the Computer units such as high-speed printers, mass and peripheral units, the UNIVAC 490 storage units, card readers, and tape-han Real-Time System also features instruction dling units. These same channels can be execution times measured in microseconds. used to accommodate an almost unlimited Instruction access and execution time totals number of remote data-originating devices 12 microseconds for most instructions. by using a special input-output buffer mode. Two input-output channels are utilized for communications between the UNIVAC 490 Equipment Enclosure Real-Time Computer and other computers. The physical arrangement of the Computer, its peripheral units, and the operator's con trol panel demonstrate the UNIVAC 490 Automatic Programming Real-Time System's revolutionary equip The system features a very flexible compil ment enclosure concept. This modern equip ing system which allows mnemonic expres ment installation technique affords the sion of computer-oriented instructions. In operator an unrestricted view of all signifi structions and addresses to which they cant indicators and displays. It also posi refer can be given alpha-numeric names. tions the peripheral units within easy reach Program check-out can be accomplished to allow the operator to attend to them with special aids which include post mor when necessary. tem and register dumping routines. A sub routine mechanism facilities compilation Maintenance personnel, located outside the of subroutines into a final program. The operator's enclosure, have unrestricted ac compiling system also has a high-level, cess to all equipment even though it is in problem-oriented language in which com operation. Any element of the system may puter programs are written. This compiler be monitored for maintenance without in interprets general statements and auto matically generates the necessary machine terfering with operating personnel. instructions which perform the stated function. In terms of economy of installation, the equipment enclosure design concept pre sents the additional advantages of greatly Floating-Point Arithmetic reducing floor-space requirements and The UNIVAC 490 Real-Time Computer eliminating the need for expensive false floating-point format is based on a two floors. program-word information unit, one man tissa and one characteristic word. The Flexible Input-Output Facilities length of the mantissa is' 28 bits, and the length of the characteristic is 15 bits, in The UNIVAC 490 Real-Time System can cluding a sign. It is a three-address system communicate directly with a wide variety in which four index-registers are used to of commercially available input-output designate the operand and the function units and custom-designed data-originating codes. As a complete software system, it devices. The system's Computer is also includes input-output conversion and func capable of communicating directly with tion evaluation. other computers. The inherent flexibility of the system's input-output channels en ables the UNIVAC 490 Real-Time Com Programming Checks puter to perform this diversity of input An important characteristic of the output data communicating functions. UNIVAC 490 Real-Time System is operat-
4 ing reliability, a mandatory requirement of puter involve serving a large number of a system designed for real-time processing. remote peripheral units that are constantly Although the system's reliability is demanding computer attention on an im achieved through solid-state components, a mediate or near-immediate basis. number of progran1 checks and error-de Since skip and jump programming opera tection procedures also contribute to the tions are inherent in real-time processing, system's highly reliable performance. The the internal logic of the UNIVAC 490 Real system features a routine for automatic Time Computer causes these operations to restarting after an error is detected and be handled in a manner approaching abso corrected. Because transaction data in real lute efficiency. For example, because the time applications is usually independent next instruction is in "review" while the and unrelated to previously entered infor current instruction is being executed, a skip mation, the system provides a routine that instruction brings the computer-at no loss preserves the transaction data being proc of time-directly to the resumption point essed should an error occur. without leafing through intervening in structions. Jump instructions are processed SPECIAL PROGRAMMING FEATURES by the computer with similar efficiency. Special programming features enable the UNIVAC 490 Real-Time System to process Library of Programmed Routines virtually any type of commercial or scien A maj or problem often encountered in the tific data-processing application. In addi installation of a new type of computing sys tion to latest engineering advances incor tem is the large amount of programming porated into the logic of the system, a host required to put the system in operation. of special software programming features Because the UNIVAC 490 Real-Time Sys associated with the system allows the user tem evolved from prototype systems which to cut programming costs to a minimum. are now performing successfully at com mercial, government, and military installa Powerful Instruction Repertoire tions, an extensive library of proven pro The sixty-two function code values in the gramming routines, including compiler and instruction repertoire can be modified by assembly systems, is available to the user the system to provide unlimited program immediately. ming versatility. Much of the real program ming power of the computer lies in the Core Storage Search unique format of the instruction word. Of From a programming standpoint, a very the thirty bit positions in the instruction desirable and practical provision of the word, nine serve as special purpose desig UNIVAC 490 Real-Time System is the fea nators. When these designators are used in ture which allows the entire core storage, or combination with the function codes, the selected portions of it, to be searched auto computer can perform more than 25,000 matically and rapidly. Programming the basic programming operations. search operation requires the use of only two instructions. Absolute Efficiency Execution of a stored program of instruc Wired Memory tions on the Real-Time Computer proceeds A permanent memory is built into the Com in a series of steps. Very often, however, puter for program input and automatic the unique requirements of real-time prob error recovery. It consists of sixteen 30-bit lems necessitate programming a large num words of storage, and is wired to fit the ber of jump and skip operations. The prev specialized needs of the Computer user. alence of these operations arises because This storage may be accessed by a program, the processing activities of a real-time com- but can only be changed manually.
5 Application Versatility information from several sources must be interrelated for subsequent operations, the UNIVAC 490 Real-Time System can handle Designed primarily for real-time applica the application more effectively than any tions, this system can effectively handle other system. For example, if a warehouse numerous commercial and scientific batch can make known the availability and quan processing applications. Yet it is the real tity of its perishable goods, the points of time function of the system that brings a sale can order their full requirements. In significant new dimension to electronic the area of production, to cite another data-processing-fingertip access to a pow example, work-in-process control can be erful computer from man.y remote points. carefully followed and interim cost figures The ability to consult vast quantities of developed to determine the desirability of updated files in a random manner with im alternate methods of production, as well as mediate program response makes this sys optimum manufacturing quantities. The tem ideal whenever an application hinges UNIVAC 490 Real-Time System, then, has on exacting time requirements. Thus, been conceived for use on an unlimited va whenever time is of great importance as it riety of applications. Figure 1-1 shows is where perishability is involved or where some real-time data-processing areas listed customer service must be rapid or where by industry and application.
ACCOU~TS RECEIVABLE CHARGE ACCOU~TS
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COST ACCUMULATION --i~-f--+-4ir.-f--+--IHI+lHt+IIHI--f--IFRI~~-+--I--II--+-IQ:lhl--+--I--I--+--I-
SPACE CONTROL -+-ti~EB... ye.+-+---+-+-+---+-+--I---1--+--I---I--+-I=a:a4l:a..-I--tg--lI--I--
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AIRLINE COMMUNICA T IONS SHIP MILITARY
RAIL GOVERMENT NO~-FEDERAL HOTEL-CHAIN GOVERMENT FEDERAL DISTRIBUTION FAA MANUFACTURE PETROLEUM PROCESS CREDIT CARD DEPARTMENT STORE LOAN ASSOCIATION CHAIN STORE SAVINGS BANK MAIL ORDER COMMERCIAL BANK UTILITY BROKERAGE
Figure 1-1. Real-Time Data-Processing- Applications 6 2. Real-Time Computer
The Computer in the UNIVAC 490 Real STORAGE SECTION Time System is a stored program computer Internal storage of the Computer consists designed for processing large quantities of of banks of ferrite cores. Thousands of data on a real-time basis. The Computer has these cores can be mounted within a square large internal magnetic core storage, great printed-circuit frame. Each core is capable programming flexibility, and a versatile of assuming either of two stable magnetic input-output section. states: one represents binary zero; the other, binary one. The Computer forms the heart of any UNIVAC 490 Real-Time System. Its solid At the option of the user, magnetic core state arithmetic and logical circuitry per storage is available in banks of 16,384 or form tens of thousands of processing 32,768 computer words. Access to informa operations every second, in both batch tion in core storage is random since it is processing and real-time modes. independent of the address selected. Words can be inserted into or removed from any address in core storage at a rate of six c~~~ ~,,+,.,+~~;]~ ...... ~,..~+" ... ,..,., ~~ +l-.~ D,..~l IJVIUC: VU.t,,,t,a,llUJ.J.lO .1.c:a,t,U.l c;" V.1. t,UC: ~"C;a,l- microseconds per word. Figure 2-1 shows Time Computer are listed below: the basic internal data word.
Octal Notation • Access time to all core storage locations of 1.9 microseconds; ability to store and to select in Although the UNIVAC 490 Real-Time formation randomly Computer is a binary computer, the prob • 30-bit word length with a I5-bit half-word option lem of converting large decimal numbers • Repertoire of 62 basic instructions which can be into binary notation sometimes becomes modified to produce over 25,000 different instruc cumbersome. For this reason, binary nota tions tion is expressed in what is known as octal • Single address instructions with provision for form. The conversion from binary to octal address modification notation simply involves dividing the bi • Multiple program capabilities nary digits into consecutive sets of three • Ability to perform rapid data exchanges with ex from right to left, and then reading these ternal equipment without main program attention sets in decimal. For example, a full core • Real-time clock for automatically initiating various storage system requires the use of 32,768 Computer operations at predetermined times storage addresses. Representation of the • Parallel one's complement binary notation upper limit storage address in binary nota- iiiiiilllllllllllill Figure 2-1. Basic Internal Data Word
7 tion requires the use of 15 bits. This same CONTROL SECTION decimal number, however, can be repre sented by five octal digits. In addition to the magnetic core storage section, the Computer has two other sec Decimal 32,767 tions, arithmetic and control (Figure 2-2). Binary 111 111 111 111 111 The control section is responsible for the Octal 77777 operations that take place during the se quential execution of instructions. It also It should be noted that the working digits coordinates the flow of data between the in the octal system are 0 through 7. The arithmetic and storage sections. word octal means eight; therefore, when counting in octal notation, the number after seven is ten. In the Real-Time Computer, ARITHMETIC SECTION the function code values, the operand ad The arithmetic section is composed of the dress, and the operand itself (when the 15- circuits and registers used to perform bit option is used) are expressed in octal arithmetic and logical operations. These notation. operations are performed in a parallel bi-
MAIN MEMORY
PROGRAM CONTROL 16K. 32K MAGNETIC CORE U·REGISTER P·REGISTER S-REGISTER
CO REGISTER
INPUT i!·REGISTER GATES
Cl REGISTER
A·REGISTER ARITHMETIC CONTROL I~------t------...... X·REGISTER D·REGISTER ADDER Q-REGISTER
Fig'ure 2-2. Simplified Logical Diagram of the UNIVAC Real-Time Computer
8 nary mode. The arithmetic mode is one's Q-Register complement subtractive. The Q-Register is a 30-bit auxiliary arith The high internal computing speeds of the metic register. Its principal function is to Computer allow arithmetic operations to assist the A-Register in multiply, divide, be carried out at microsecond speeds. For and logical operations. Register Q has shift example, additions and subtractions are ing and logical properties, and performs performed in a maximum of 12 microsec adding or counting functions as well. onds. The ability of the computer to per The contents of the Q-Register may be form arithmetic operations simultaneously shifted right or left, in the same manner as with input-output data transfers makes it the contents of the A-Register.As shown in ideally suited to the processing of real-time Figure 2-2 all communication with the problems. Q-Register is through the X-Register. The UNIVAC 490 Real-Time Computer Logical multiplication is performed on a contains a number of registers which holds transmission path between the Q- and data during computation. These registers X-Registers. are designated by a letter or letter-nu meral combination, and they are intercon A- and Q-Registers In Combination nected by parallel transmission paths Certain instructions shift the contents of through which information flows during the A- and Q-Registers as a single 60-bit processing. register, with the A-Register representing They fall into two categories: operational the most significant half of the double and transient. Operational registers con length quantity. To illustrate, the Q-Regis tain information from one instruction to ter holds the multiplier at the beginning of another and are referred to in the opera a multiply operation. As the product is tional description of each instruction. Tran formed, by repeated additions and shifts, sient registers, on the other hand, are tem the multiplier digits are shifted to the right porary storage locations that are always and diseardedo In their plaee, the lower cleared at the end of an instruction. order digits of the double-length product are shifted into the Q-Register from the accumulator. Arithmetic Registers (Operational Registers) During a divide operation, a process essen A-Register tially the reverse of multiplication takes place. The double-length dividend is shifted The A-Register or Accumulator is the prin to the left, and the quotient bits are inserted cipal 30-bit arithmetic register. It has in the rightmost position of the Q-Register. adding and shifting properties. In most At the end of the divide sequence, the quo arithmetic operations, the result is retained tient is assembled in the Q-Register,and the in register A for use in later program steps. remainder is left in the accumulator. For example, after addition or subtraction, the sum or difference remains in the accu P-Register mulator; after multiplication the most sig The P-Register (15-bits) is the Program nificant half of the product is gathered in Address Counter. This register holds the the accumulator; after division, the re address of the next sequential instruction mainder is left there. throughout the program. As each program The contents of register A may be shifted address is transferred from the P-Register right or left, as described in the instruction to the S-Register, the contents of the repertoire. Left shifts are circular or cyclic, P-Register are increased by one. When and in a right shift the sign bit is extended Jump instructions are executed, the P-Reg by the number of bit positions shifted and ister is cleared and a new program address the lower order digits are discarded. is entered.
9 B-Register Z-Register The B-Registers (15-bits each) are Address The Z-Register (30-bits) serves as an Oper Modifying Registers generally used for in and Buffer for storage references. During dexing minor loops in a program. The con the read portion of the storage access tents of one register may be used to incre period, the Z-Register is cleared. The digit ment the operand address before execution reading amplifiers are then sampled to set of an instruction. Seven such registers are the contents of Z corresponding to bits in provided and labeled Bl through B7. The B7 the storage. During the write portion of register also serves as a counter in the re the stol'age access period, the Z-Register peat mode where a selected instruction is controls the inhibit circuits in order to executed the number of times specified write or restore the disturbed storage reg (covered later in instruction 70). ister. Input data is gated directly to the Z-Register. Transient Registers The following registers are used in the V-Register manipulation of instruction words and data The V-Register (30-bits) is the Program words during the execution of an instruc Control Register. In other words, it holds tion. These registers are not referenced in the instruction word during the execution the description of the instructions and do of an operation. The operation code and the not retain information from one operation various execution modifiers are translated to the next. from appropriate sections of this register. If an address modification is required be X-Register fore execution, the contents of the appro The X-Register (30-bits) functions as an priate B-Register are added to the contents arithmetic communication register. It has of the low order I5-bits of the V-Register. complementing, but not shifting, proper ties. The X-Register receives the operand R-Registwr from storage during all arithmetic opera The R-Register (15-bits) functions as a tions. All communication between the A communications register for all internal and Q-Registers and the rest of the opera transmissions to the B-Registers. tional registers or the adder output is via the X-Register. R1-Register K-Register The RI-Register (15-bits) functions as a communication register for all internal The K-Register (6-bits) functions as a transmission from the B-Registers. It holds shift counter for all arithmetic operations the incrementing quantity during address involving shifts. The maximum shift count modi fica tion. permitted is 60. Multiply and divide opera tions are controlled by presetting the D-Register K-Register to 30. The K-Register then counts the operational steps. The D-Register (30-bits) is the Arithmetic Register which holds the operand, for pres S-Register entation to the adder, during the execution of arithmetic operations. The S-Register (15-bits) holds the storage address during memory references. At the C-Registe1' beginning of a storage access period, the address is transferred to the S-Register. The C-Registers are communication buffer The contents of the S-Register are then registers through which computer output translated to activate the storage selection data are synchronized. There are two system. C-Registers, Co and Cl. Co is used to com-
10 municate output data to peripheral devices when initiating type-outs of interest to the on 12 different channels. Cl is used to com operators or UNIVAC Center supervisory municate output data on two different chan personnel; and in controlling the system. nels to other computers. Input data is gated There are no restrictions as to the size of directly to the Z-Register. the units of information entered by this de vice, or of the type-outs, so long as computer OPERATOR CONSOLE formats are used and program provision The UNIVAC 490 Real-Time Computer is is made. equipped with a console that includes con Wired Memory trols that allow varied manually governed operations including special modes~ Incre As mentioned earlier the purpose of the mental Clock Interrupt Disable Switch, wired memory is to provide automatic Programmed Jump Switches, and the Wired reading of new programs into the Compu :Memory Switch. ter with protection against erasing vital instructions in the wired memory. The The two-way Wired Memory Switch, located wired addresses parallel the first 16 core on the operator console, is marked "start" storage addresses (00-17, octal). Whether and "neutral." the Computer operates with words in wired or core, depends on the position of the Computer Control Panel 3-way Wired Memory Switch on the Registers found on the maintenance panel include Computer Control Panel and the two-way the following: switch on the Operator Console. 1. Co-REGISTER 8. B -REGISTER 4 The positions of this switch are: 2. C1-REGISTER 9_ Bs-REGISTER
3. Q-REGISTER 10. B6 -REGISTER 1. Automatic Recovery
4. A-REGISTER 11. B7 -REGISTER 2. Neutral 5. B1-REGISTER 12. U-REGISTER 3. Bootstrap 6. B2 -REGISTER 13. S-REGISTER When the Computer is on -and the Wired 7. Ba-REGISTER 14_ P-REGISTER Memory Switch is turned to Bootstrap, the Manual controls are provided on the Computer Con Computer starts the wired program in the trol Panel which allow: wired memory at address 00. During the 1. The execution of consecutive program steps at normal operation of the Computer, any a low rate. reference to the address between 00 and 17 2. The execution of one consecutive Computer clock phase (1,4 of a cycle) for each depression ( octal) refers to the address in the wired of a switch. memory. 3. The execution of one consecutive program step for each depression of a switch. When the switch is in Automatic Recovery, 4. Operation that is normal except that the Com and a fault interrupt occurs, the Computer puter does not stop when it executes a pro grammed stop instruction. will perform the program as wired in the 5. The Day Clock to be disconnected. Wired Memory starting at address 14. A 6. The Increment Clock to be disconnected. fault interrupt is caused when an Incre 7. The automatic recovery feature to be discon nected. mental Clock Interrupt or millisecond time out or an illegal function (00 or 77) occurs. Because of their use in programming opera A millisecond time-out occurs when, for tions, some of the indicators and manual some reason, the Incremental Clock was controls listed above are duplicated on the not updated. All other references to ad operator's console. dresses between 00 and 17 ( octal) refer Console Keyboard and Printer to words in core storage. Located at the Computer Console, the Con When the switch is in Neutral, the Compu sole Keyboard will normally be usable: dur ter ignores the wired memory and uses ing program debugging, while making address 00 through 17 (octal) in core changes to programs, schedules, or tables; storage.
11 3. System Components and Configurations
The individual components which combine Real-Time Computer, various peripheral to form a particular UNIVAC Real-Time units such as card readers, storage units, System configuration vary in number and and magnetic tape units, and communica type according to the application. Each tions equipment. Using master data main component of a UNIVAC Real-Time Sys tained at the central site, the Computer and tem, however, falls into one of the following its peripheral units process all information categories: received from input-output devices at many 1. Remote Inquiry-Answering Devices remote locations. By means of the commu 2_ Communications Equipment nications equipment, input is received by 3. Central Site Equipment the Computer and results are returned to the inquirer. Remote inquiry-answering devices situated The following paragraphs discuss the Real at many different locations have access to Time Computer and its peripheral units. the Computer and other central site equip ment through communications equipment. Conversely, the same communications Peripheral Units equipment provides the central site units The Real-Time Computer can accommodate with access to the remote units. a large variety of peripheral units. For The communications equipment is divided example, it can handle UNIVAC Solid between the remote inquiry-answering de State Subsystems equipment such as the vices and the central site equipment. In ac High-Speed Printer, the High-Speed Card tual operation, input information is entered Reader, and the Punch-Verifier Unit. Uni at a remote inquiry-answering device which servo IIA and Uniservo III tape handlers activates communications equipment at the can be connected to the system. In addition, same location. The information is trans mass-storage devices of the random access mitted via communications lines to commu type such as flying-head drums, can also be nications equipment at the central site incorporated into a Real-Time System. where it is fed into the Computer for proc essing. Output information emanating from Peripheral Systems the Computer is fed through the communi The central site peripheral systems are cations equipment to the proper inquiry listed as follows: answering device at a remote location. Flying-Head Drum Subsystem CENTRAL SITE EQUIPMENT A Channel Synchronizer Central site equipment used with a A Drum Control Unit UNIV AC Real-Time System includes a One to eight Drum Units
12 UNISET COMPUTER CONSOLE
HIGH-SPEED PRINTER
UNISET UNIVAC 490 UNISET REAL-TIME CHANNEL UNISERVO PROGRAMMER SCANNER COMPUTER SYNCH. IIA OR III
t MAGNETIC CHANNEL FH-880 SYNCH. ~ DRUM ~ CONTROL UNIT
SCANNER-SELECTOR
COMMUNICATIONS PARTY LINE CONTROL UNIT SERVICE TYPICAL LAYOUT
URTS INTERFACE (CENTRAL SITE) COMMON CARRIER SUPPLIED SUB-SETS - - - - -~ I I CCU PARTY MODEM LINE MASTFR rt- p:- COMMUNICATIONS I-- COMMUNICATIONS CONTROL UNIT I COMMON CONTROL UNIT TELEGRAPHIC - I CARRIER HALF-DUPLEX CENTRAL - - - LINES
URTS -l-t~ -- INTERFACE I
SCANNER DATA SUB-SET BUFFER I COMMON CARRIER SUPPLIED I - -1-1 I-CO~N ;;RI;- -- -- I I LINES UNISET PROGRAMMER
UNISET UNISET Figure 3-1. Typical Central' Site Layout Magnetic Tape Subsystem There are 128 6-track bands across the A Channel Synchronizer drum. Each band can store 6,144 computer A Magnetic Tape Control Unit words, allowing a total of 786,432 words to One to Twelve Magnetic Tape-Handling be recorded on the drum. Average access Units (Uniservo IIA) time to information stored on the FH 880 drum is one-half drum revolution or 17 High-Speed Printer Subsystem milliseconds. A Channel Synchronizer A High-Speed Printer Control Unit One or two High-Speed Printers
Card Equipment Subsystem A Channel Synchronizer A Card Equipment Control Unit A High-Speed Reader A Punch-Verifier Unit.
To communicate with the computer each peripheral subsystem utilizes an input-out put channel. Anyone of the peripheral systems may be connected to anyone of the 12 input-output computer channels. Thus as many as 12 peripheral sUbsystems in various combinations may be connected to the 12 Computer input-output channels.
Magnetic Drum Storage In addition to major features such as large capacity and high-speed random access these mass-storage units employ the flying head (air-floating head) technique which Read-Write Operations combines aerodynamic and pneumatic prin ciples. The read-write heads float at one The 30-bit computer words are divided into half a thousandth of an inch or less from five 6-bit groups as they are recorded on the the oxide-coated surface of the drum, on a surface of the drum. Each 6-bit group is boundary layer of air, generated by the written in parallel followed by the next rotation of the drum. The read-write heads group and so on until the word is written. are suspended in position by the opposing Each word is considered one angular ad forces of the boundary layer of air and the dress and hasa parity bit associated with it. head-positioning mechanism. When performing a read or write operation Flying-Head Drum Storage FH-880 on the flying-head drum storage, the In the FH-880 Drum Storage Unit forty computer: head blocks are positioned around the drum. Mounted in each are 22 read-write 1. Sets up a buffer mode heads, one for each recording track which 2. Sends a function word to the storage control unit revolves beneath the block. The read-write via the channel synchronizer. heads record information on the drum sur face at a density of 490 bits per inch while The function word contains the starting it revolves at 1800 rev0lutions per minute. address and a code specifying which opera Recording frequency is approximately 1 tion is to be performed. The end of the Com megacycle. puter buffer mode will stop the operation.
14 When a read is to be performed, the storage Real-Time Computer through a tape con system locates the starting address and trol unit and a channel sychronizer. reads the word at that location, and then the input request signal is sent. If an "ac knowledge" is received before the begin ning of the next word, the information can be read into the Computer as fast as it comes off the drum. This rate can be varied by integral powers of 2, starting from 16.4 microseconds up to a maximum of 262 mi croseconds. Consecutive words are read in to the Computer until the buffer mode ends.
The write operation is similar to the read operation except that the output request signal is transmitted to the Computer im mediately upon receipt of the function word. Then the storage system looks for the address and receives a word from the Computer at the same time.
Drum Search Two types of drum search are available, each using a one-word identifier. One type will locate the matching word and store its address. The other initiates a read opera tion starting with the word following the matching word.
Overflow words can be inserted at any loca The multiple control units and large storage tion preceded by an end of block which is facilities of the Computer provide for simul· represented by thirty 1-bits. These words taneous tape reading, tape writing, and will contain an address and an identifying computation. This means that a 2400-foot code. When an overflow word is reached reel of tape, containing a data-history file, during a search, the search will stop at that may be read, updated, and rewritten on an point and the overflow address is sent to output tape in the time required to read the the computer. The search can be reinitiated original file. under program control at the location speci The tape units provide fast tape-mounting fied by the overflow address. The End of and ease of operation. A switch on the front Block word can also stop a search before a panel of each unit permits interchanging of find has been made. metallic or Mylar* tape. A number of checks is incorporated into the unit to pro vide and maintain accuracy of information Magnetic Tape Storage as it is read or recorded. As many as 12 UNISERVO IIA magnetic *Mylar is a registered trademark of E. 1. du Pont de Nemours tape units may operate with a UNIVAC and Company, Inc.
15 Tape can be moved in a forward or back to a stacker. During its course through the ward direction at a speed of 100 inches per transport mechanism, a card conveys its second. Reversal time is 600 milliseconds. contents to the Computer when it is brush Data bits are recorded on the tape in par sensed at the second read station. When allel form and characters in serial form at once inserted between the rollers, a card a density of 250 or 125 bits per inch. There moves without interruption until it reaches are eight recording channels, one is used its stacker. If it were possible to halt the for parity bits, two for the zone; four, for High-Speed Reader instantaneously in the numerics; and one, for the sprocket pulse. midst of its card-cycling, the followin~ Thus, any 6-bit code plus an odd or even situation would be revealed. First of all, check bit may be employed. four cards would be committed to the system. The first card in transit from the The UNIVAC Real-Time Computer can input magazine, would be near the rollers. also accommodate UNIVAC III System Depending on the exact stopping point in magnetic-tape-handling units. a cycle, the next two cards, would be either at or approaching each of the two reading stations. The progress of the fourth card would have been suspended at some point on its way to a stacker. It is this ability to feed and read cards at the same time which enables the High-Speed Reader to reach and sustain its input speed at a maximum rate. Misfeeds, row misregistration, jams and full stacker are detected; a stacker full signal is provided. Reading at two stations pro v ide s full data -c h e c kin g .
HIGH-SPEED CARD READER The 80-column card High-Speed Reader is a fast, accurate punched card input unit capable of reading up to 600 cards per min ute. The complete accuracy of each read operation performed by the High-Speed Reader is assured through two distinct readings of each 80-column input card.
Data cards stacked in the input magazine are fed into the continuously revolving PUNCH-VERIFIER UNIT rollers that transport them through both The 80-column Punch-Verifier Unit can reading stations, after which they are sent punch up to 150 cards per minute. The unit
16 consists of an input magazine, a punch THE HIGH-SPEED PRINTER station, a post-read station, and two output The High-Speed Printer is capable of print stackers. The post-read station assures the ing output information, intermediate accuracy of information punched into results, distributed accumulations and bal cards. Verification of punched data is per ances, and final reports at a rate of 600 lines formed at the post-read station on a hole per minute. count basis.
A word-for-word check or verification may be easily programmed, eliminating the ne cessity for a complicated checking proce dure. A compact control panel, in open view, advises the operator of all conditions occur ring within the unit at any given moment.
The input magazine, or card-feed bin, holds the stack of cards into which information is to be punched. It has a holding capacity of 600 cards. There is a card-lifting lever which may be depressed to assist, in the removal of unprocessed cards. A card weight which fits over the top card in the input stack ensures a positive, uniform feed, down to and including the final card. Basically, the Printer is designed around 128 print wheels which revolve at high During the time that a card is in transit speeds. These wheels correspond to the to the punch station, the proper punches for horizontal printing positions across the that card can be set up. Electrical signals page. Each print wheel contains 26 alpha are used to energize a set of actuator mag betic, 10 numeric, and 15 special characters nets. All of the actuators are contained in a such as the period, dollar sign, ampersand, 960 magnet matrix, one for each possible colon, and semicolon. Character spacing is hole position on the card, and the energized ten to the inch across. Line spacing is six actuators correspond to the positions which to the inch vertically with variable spacing are to be punched. After the card has been options available to the programmer. punched, a cam action then opens the card stop and the card moves to the post-read In addition, the paper feed will handle station for verification. From the post-read sprocket-fed paper (including card stock, station, the cards move into the stackers. either blank or preprinted) from 4 to 27 inches in over-all width. At least four car Two output stackers, or bins, are contained bon copies can be made by using paper in a convenient hinged assembly which between 11 and 13.5 pounds in weight. swings out for maintenance. The bins are Furthermore, impression control permits designated stacker 1 and stacker O. Each variation in the strength of the printing stacker is capable of holding 850 to 1200 hammer stroke, and fine vertical adj ust cards. When either stacker is full, micro ments of the Printer in operation. The switches underneath it stop the unit, and Printer will stop automatically if it detects an indication is given on the control panel. a low paper supply.
17 TRANSMISSION AND COMMUNICATIONS the program must perform the following Input-Output Channels steps:
Communication of data between the Real 1. Activate the channel to be used for the informa Time Computer and its central site peri tion transfer, allowing the Computer to recognize pheral units, remote input-output devices, data requests on that channel. and other computers is achieved through 14 2. Load the channel's index register with the data input-output channels. These channels are control word. (The lower and upper halves of the actually plug-in cables containing various data control word contain the beginning and lines which are used to conduct and control ending address of the section of core storage involved in the transfer.) information. 3. Send the proper function word or words to the Two of these channels are reserved for com peripheral unit. munication between the Computer and other computers that may be included in a Data is then transferred between the Com UNIVAC Real-Time System. Depending on puter core storage and the peripheral the specific requirements of the applica device without main program intervention. tions to be performed and on the UNIVAC When a word is transferred to or from Real-Time System configuration, the re storage, one is added automatically to the maining 12 channels may be used as lower half of the control word. The data required with remote input-output devices transfer is terminated when the Computer and central site peripheral units. senses that the upper and lower halves of the control word are equal. Steps one and Data Transfers two above are accomplished with one of the Initiate Buffer instructions, and step three Any part of the Computer's internal core is performed by the Enter External Func storage can be used as an input-output data tion instruction. buffer storage area, with the exception of the few special core storage locations that Input-Output Control are reserved for the Incremental Clock and the interrupts. The Computer itself can Equipment external to the Computer is continue main-program processing without controlled by function words which acti constant interruption by the various input vate external function control lines. The output units. Information is transferred function word is translated into a discrete between the Computer and its external set of actions codes by the external unit. units (remote input-output devices and The use of program-generated function central site peripheral units) in "blocks" words, rather than Computer instructions, of data. A block of data is a series of words in controlling peripheral equipment allows or half-words having consecutive core the Computer logic to be independent of the memory addresses, starting with a pro characteristics of input-output units. This gram-determined first word and ending permits nearly any type of digital device vlith a program-determined last word or an to be connected to the Computer without external interrupt. modifying computer logic.
Buffer Mode Interrupt words are generated by the ex A buffer mode transfer, which occurs inde ternal units and transmitted to the Com pendent of main program control, is used puter on the input data lines to inform the to transfer blocks of data between input Computer program of the operating status output units and core storage. Before exe of the peripheral unit or its desire to ini cution of a buffer mode transfer of data, tiate or terminate a transfer. An interrupt
18 word is distinguished from data by activat REMOTE INPUT-OUTPUT DEVICES ing the external interrupt control lines. Ac Because the central site equipment can com tivation of these lines causes the Computer municate directly with nearly any type of program to jump unconditionally to a stor external digital equipment, remote inquiry age address associated with the particUlar answering devices of many different de input-output channel. From there, the Com signs can be part of a UNIVAC 490 puter will execute a subroutine which an Real-Time System. Usually, remote in alyzes the interrupt word and prescribes quiry-answering units are especially de the appropriate action to be taken (Figure signed to meet the specific requirements of 3-2) . a particular real-time application. The fol lowing paragraphs describe briefly various External Equipment Requirements remote inquiry-answering units now in use All peripheral units employed in real-time at real-time system installations. systems must have characteristics suited to both the system and the application. The Keyboard Printer following capabilities are invariably re quired of any peripheral unit in a real-time The Keyboard Printer permits keyboard system: insertion of transaction data and printed page output of computer responses at l. Ability to accept, translate, and execute function speeds of 60, 75, or 100 words per minute, words. depending upon the telegraphic service. The 2. Ability to respond to data-channel input-output keyboard and printer can be used sepa acknowledge signals. rately or in combination. Faster printing 3. Ability to produce input-output request signals. speeds are available with high-speed tele The following capabilities are almost al phone communication lines_ ways required of peripheral units in a real time system: The keyboard is the operator's basic means l. Ability to generate interrupt words. of alpha-numeric input to the system for all information, except that which can be en 2. Temporary storage to store as many bits as the peripheral unit transmits in a single transaction. tered via the data keys. The unit employs a full four-bank keyboard with 10 numeric 3. Temporary storage capable of storing the full repertoire of function codes for the specific keys, 26 alphabetic keys, 11 special char peripheral unit. acter keys, and a space bar.
NAME ORIGIN MEANING EFFECT
Output Acknowledge Computer Computer is transmitting Initiates cycle whereby output an output word unit accepts and processes output word
Output Data Request Output Unit Output unit is ready to Computer forms next output word receive next output word and sends output Acknowledge
Input Data Request Input Unit Input unit is transmitting Computer accepts input word an input word and sends input Acknowledge
Input Acknowledge Computer Computer is receiving the Initiates cycle whereby input input word unit produces next input word.
Figure 3-2. Input-Output Control Signals
19 data message are transmitted. Housing 21 to 35 pushbutton illuminators, the format control panel is used by the operator to identify specific types of transactions and data fields being entered. By observing which field buttons are illuminated, the operator is informed of transaction data items which are necessary to carry out the indicated transaction.
The basic correction facility incorporated in the UNIVAC alpha-numeric equipment operates.on a field basis. When an error is detected immediately after it occurs, as in the case of a wrong key being operated, the field-erase key is depressed, resulting in the printing of an error symbol after the faulty entry. The correct entry can then be made. If an error is not discovered until after the transaction has been entered, it can be cor rected by means of an appropriate change transaction.
The printing unit prepares a copy of all transaction data as it is typed on the key board. Computer responses are also printed Uniset Console by the printing unit. The U niset Console is a keyboard device specifically designed to meet point-of-sale The Keyboard Printer may be supplied operating requirements of an airline com with special features which make it an ex pany. Connected on-line with the Computer, tremely versatile input-output device. For this device interrogates the system for example, the unit can be used to prepare flight information by means of its key multi lith masters, multiple interleaved car board. Indicator lamps display requested bon sets, horizontal and vertical tabulation, information as well as the Computer's re as well as a large variety of printed page ply. Relevant flight information is stored on requirements. For extremely accurate feed a series of transparent cards. When in ing of forms, the unit is also available with serted in the Uniset Console by its operator, pin-feed platens. It may be used to print this information is identified to the Com payroll checks and a variety of order and puter. invoice forms, and can be programmed to extract selected portions of a transmitted message at various locations. The Computer identifies each Uniset by a four decimal digit identification number which is read from four manually settable At the option of the user, the Keyboard number switches contained within the set's Printer can be equipped with a forma~ con housing. Although developed originally for trol panel. This auxiliary device can be Airlines Reservations Systems, the Uniset used to permit greater condensation of is readily adaptable to various other gen data. It also assures that all segments of the eral applications.
20 printer provides the operator with a printed copy of input transaction data en tered on the keyboard. Employing a unique printing mechanism, the unit is quiet in operation and all printed copy can easily be seen by the Uniset operator.
Format Control Panel The format control panel is a set of 21 to 35 illuminated pushbuttons which are used by the operator to identify specific types of record transactions (for example, new rec ord, reconfirm, cancellation, and so on) and the particular fields being entered (for ex ample, name, phone, remarks, and so on). By observing which field buttons are dimly illuminated, the operator is notified of the items of information required to carry out The Uniset the transaction he has indicated. Upon de The Uniset is actually a unitive configura pression of one of the dimly illuminated tion, in a modern modular arrangement, of buttons, it "brightens." Upon depression the combined features of the Keyboard of the next desired dimly illuminated but Printer and the U niset Console. ton, that button brightens and the previous brightly illuminated butt6n extinguishes. Functioning as a general-purpose remote Thus if an operator is interrupted during input-output device, it allows rapid and a transaction the brightness of illumination accurate interrogation of the Computer. of the buttons reminds him of the stage of Basically, the Uniset comprises an alpha the entry. numeric keyboard, a format control panel, The card mount provides the operator with printer card mount, and data keys. The a convenient and fast method of limiting keyboard is the principal medium for in the inquiry to a specific area or portion of serting transaction data. The unit's four transaction data. The segment data keys bank keyboard contains 10 numeric keys, consist of three groups of keys which are 26 alphabetic keys, and 11 special character used for entering specific parts of trans keys. Careful attention to color and place action information. ment of the various elements permits operation of the Uniset quickly and accu rately, with a minimum of effort. Because COMMUNICATIONS EQUIPMENT of the assistance automatically supplied by In the UNIVAC 490 Real-Time System, the equipment during the entry of the data, remote inquiring-answering devices are the complete transaction is carried out connected to the centrally located Computer smoothly, with a minimum of delay, through through communications lines made avail the use of the format control keys. The key able by common carriers. Communications devices {)perate with a light touch, yet, like equipment located at both the central and all the Uniset components, are rugged in the remote sites converts data into a format design to assure reliable operation under that can be transmitted over the communi the heavy use to which they are exposed. cation lines. Information arriving at the central site in common carrier form is In addition to printing responses as they retranslated by other special equipment in are received from the Computer, the to a form usable by the Computer.
21 TO COMPUTER
SCANNER·SELECTOR
j
CENTRAL SITE
COMMUNICATIONS CONTROL UNIT PARTY LINE MASTER
"I I COMMUNICATIONS LINES I I j-----. I I I ADDITIONAL ~ ------...... ------~ REMOTE I I I I SITES I I I I t ~ t
CCU CCU CCU PARTY PARTY PARTY LINE LINE LINE SLAVE SLAVE SLAVE
SCANNER BUFFER
REMOTE SITE
UNISET PROGRAMMER GB Figure 3-3. Party Line Network This equipment also controls the various communication capability via a set of com communications circuits to prevent inter mon busses. Each S-S is capable of oper ference and to provide equal availability of ating with others, for building a cascaded circuits to all points having access to the "scanner complex," allowing many more system. Configurations of this equipment than the basic 16 peripheral units to share vary according to the type of communica a single computer channel pair. tions lines employed by the system.
PARTY LINE COMMUNICATIONS SYSTEM COMMUNICATIONS SYSTEMS The Party Line Communications System is Many types of communications systems a digital communications system. It con may be used to transmit information be sists of two functional types of digital tween remote input-output devices and the terminal equipments_, master and slave, centrally-located Real-Time Computer. Se connected by a communications facility. lection of a system is based upon the appli One master and a number of slave termi cation to be performed and the number of nals compose a maximum Party Line Com remote devices to be used. Configuration munications System. The master terminal of a system varies according to its type. is called a Communications Control Unit, Two of the many communications systems Party Line Master (CCU-PLM) and each which may be employed are the party line slave is called a CCU-PLS. and the line switching network (Direct Dis tance Dialing). The Party Line Communications System provides bidirectional communication be PARTY LINE NETWORK tween digital data-processing equipment at In a party line network (Figure 3-3), re the CCU-PLM location and data-handling mote input-output devices are connected to equipment at each of the CCU-PLS loca a Uniset Programmer. This unit may con tions. Direct intercommunication between nect, for example, two Keyboards plus CCU-PLS terminals is not permitted. Only Printers to a Scanner-Buffer. The Pro one CCU-PLS may communicate with the grammer provides control functions for the CCU-PLM at a given time. two remote devices sharing it. The communications facility is typically a voice-band channel with full-duplex capa Scanner-Selector bility. The channel terminations are digital The Scanner-Selector (S-S) is a device used data subsets (modem units) . Each slave terminal is electrically bridged across the for connecting up to 16 peripheral units to party line sending pair and receiving pair a single pair of UNIVAC 490 Real-Time that terminate at the master station site. Computer input-output channels. It is a simple device in that it does not attempt to Data transmission between the Central directly switch all signal lines on all 32 Processor and a remote station is initiated cables, but instead, switches a single line by selective polling (calling) of each CCU to each peripheral unit, as an indication PLS in turn. A polled CCU-PLS communi that that unit mayor may not switch those cates with the CCU-PLM as if a direct signal lines it uses. No data storage or connection existed between the two with all buffering is required.in the S-S; each other CCU-PLS units disconnected. Bidi peripheral unit provides its own computer rectional communication continues until
23 the CCU-pLS is told to "hang up" by the LINE SWITCHING NETWORK data-handling equipment at the remote site. (DIRECT DISTANCE DIALING) The "Hang Up" signal occurs at the end of The second type of communications line a message sent to the Central Processor. configuration for the Real-Time System is The message content indicates to the Cen the Line Switching Network (Figure 3-4). tral Processor that communication with This line configuration may use telegraph that station is complete. The Central Proc or voice grade facilities. Ljne switching essor then instructs the CCU-PLM to poll service is a network where connections the next CCU-PLS. are made only when communications are A polled CCU-PLS responds with data desired. when data is made available by a remote data-handling device or with a "No Data" COMMUNICATIONS CONTROL UNIT, control code. The "No Data" control code TELEGRAPHIC HALF-DUPLEX causes the CCU -PLM to poll the next The Communications Control Unit, Tele GCU-PLS. graphic Half-Duplex (CCU-THD) is a bi directional signal converter and adapter for Transfer Function use between a telegraphic channel terminal device and a character input-output regis As each Communications Control Unit be ter of a computer or remote peripheral comes ready for a one-word buffer transfer, device. It serves to relay data from the com it requests service of the Scanner-Selector puter via a telegraphic channel to the re (S-S). The S-S sequentially examines the mote device, and vice versa. The CCU -THD scanner request lines from one of the six may utilize Direct Distance Dialing to set teen stations, and, upon locating a scanner up the channel to the proper destination. request signal on one of these lines, the Operation is half-duplex; therefore, data scanner transmits a select pulse to the con moves in only one direction at any given trol circuit of that station. The control time, reversing at some other time. circuit then initiates the transfer of a data word from the character register to the Computer, or vice versa, depending upon The CCU-THD handles seven-bit serial the direction of transfer. asynchronous nine and one-half unit char acters at the telegraphic interface, and six Normally, the scanning circuit is released bit parallel characters at the computer or by terminating the scanner request signal peripheral device interface. It can be ad upon the transfer of one Computer word. justed to standard bit rates in the range of Transfer of the next word from the same 45 to 75 bits per second as well as to high Communications Control Unit is accom speed rates in the range of 600 to 750 bits plished after one complete cycle of the per second if used on voice-band channels. Scanner-Selector. For operation on high-speed channels, poll ing circuits nlay be made available to re The tagging circuit of the Communications place the dialing circuits in which case it Control Unit forms an identifier in the low is called CCU-PHD. order 15-bits of the Computer word. The identifier specifies a message buffer area in The CCU -THD may use a modified Baudot core storage. The identifier is held until the code of seven bits. The first five bits are end of the message while the data character standard Baudot code. The sixth bit is used is transferred as the upper 15 bits of the to distinguish letter codes from figure Computer word. codes. A zero (space) in the sixth bit desig-
24 TO COMPUTER
~
SCANNER·SELECTOR
J
COMMUNICATIONS CONTROL UNIT CENTRAL TELEGRAPHIC SITE HALF·DUPLEX CENTRAL l t DATA SUB-SET l t LINE SWITCHING FACILITY
COMMUNICATIONS CONTROL UNIT REMOTE TELEGRAPHIC SITE HALF-DUPLEX
SCANNER BUFFER
UNISET PROGRAMMER
UNISET UNISET
Figure 3-4. Line Switching Network nates the code as letters, while a one (mark) COMMUNICATIONS EQUIPMENT FOR designates the code as figures. The seventh SPECIAL DEVICES bit is a parity check bit added by the CCU A Communications Control Unit, Tele to data leaving the Computer, and deleted graphic Master, Simplex (CCU-TMS) is by the CCU from data entering the remote used for putting teletypewriter devices and device, and vice versa. The seventh bit is data subsets on-line with the real-time sys a one or zero as needed to maintain odd tem. It is a unidirectional signal converter parity. and adapter for use between a Computer output channel and the Scanner-Selector and telegraphic channel sending terminal. The seventh bit code appears only on the It accepts 6-bit parallel characters from the communications channel. The CCU-THD S-S, converts them to 5-bit code characters, presents an error indicating line and six and sends them to a telegraphic transmit parallel data lines to the Computer or pe ting terminal. ripheral device. A one on the error line indi Operation of the unit may be adjusted to cates the concurrent data did not meet the any standard telegraphic bit rate. The parity check when received. Conversely a CCU -TMS also generates control pulses for zero indicates it did. an exchange service telegraphic terminal unit on ten control lines at the rate of ten pulses per second, and in response to dial The CCU-THD also checks message (longi code 6-bit straight-binary characters re tudinal) parity. The transmitting CCU ceived from the Scanner-Selector. generates a message parity check code at A Communications Control Unit, Tele the end of a message which is compared graphic Slave, Simplex (CCU-TSS) is also with the message parity count at the re used with common carrier teletypewriter ceiving CCU. If they do not compare, a one equipment. It is a single direction signal is presented to the error line. converter and adapter used between a tele graphic channel receiving terminal and the Scanner-Selector. It receives 5-bit serial The CCU -THD contains an interchange coded characters from the communications able internal circuit designated a Function terminal and converts them to 6-bit codes Converter which makes its interface com for entry into the Scanner-Selector. The patible with interfaces of a wide variety of CCU-TSS can be adjusted to accept any data-handling terminal devices. standard telegraphic character rate.
26 4. Instructions
INSTRUCTION WORD and/or stored. The effect of k is different As shown in Figure 4-1, each 30-bit in for each of three instruction categories: struction word is composed of five desig read, store, and replace. nators. The operand interpretation designator also controls data transmissions during store operations. f Designator j Designator The function code designator, f, is a six-bit code that specifies the principal operation The branch-condition designator, j, is usu shift, store, add, and so on-to be performed ally a 3-bit code that may be interpreted as by a program step. Sixty-two function code a skip or jump-condition designator, a reg values constitute the UNIVAC Real-Time ister designator, or a repeat modification System repertoire of instructions. designator.
INSTRUCTION CYCLE y Designator The instruction execution cycle begins with The Y designator is a 15-bit code from a storage access period that transfers the which is derived either the address of the address of the next instruction from regis operand, or, when the k designator equals ter P to register S. Next the 15-bit contents o or 4, the operand itself. of the storage address register, (register S) are translated, activating the storage selection system, which transmits a 30-bit b Designator instruction from memory into register U. The operand address modification designa tor, b, is a 3-bit code that governs the first As soon as it enters register U, the in modification of y. This modication involves struction word assumes control over the adding to y the contents of a B-register des execution of the remaining phases of the ignated by b. program step. k Designator The instruction word function code and The operand-interpretation designator, k, various designators are then translated. If is usually a 3-bit code that controls the address modification is specified, the con procedure by which the operand is obtained tents of the designated index register are
y 129
Figure 4-1. Instruction Word
27 added to the address portion (15 low order sign bit). All other shifts are circular; that bi ts) of the instruction in register U before is, the (Y) bits that are shifted out of one execution. Now the control mechanism per end of the register appear in sequence at forms the operations designated by the the opposite end of the register (no bits are instruction word; that is, it executes the lost) . All shift instructions are Read Class program step-add, subtract, compare, and instructions. The shift instructions are as so on. follows: The instruction word remains in register U o I Shift Q Right until it is replaced by the succeeding in struction word at the beginning of the next 'T'hhdnf4tru~tion ~hifts (Q) to the right (Y) program step. bit positions. The higher-order bits are re placed with the original sign bit as the word INSTRUCTION REPERTOIRE is shifted. Only the lower-order six bits of The programming operations executed by (Y) are recognized for this instruction and the 62 function code designators are listed the maximum shift count permitted is 59. below. In describing the operations, the fol The higher-order bits of (Y) are ignored. lowing conventions are used. 02 Shift A Right ( ) the contents of the storage location or register enclosed within the parentheses. This instruction shifts (A) to the right (Y)
-? the quantity on the left is transferred to the bit positions. The higher-order bits are re storage location or register on the right. placed with the original sign bit as the word A the accumulator, a 30-bit shift register. is shifted. Only the lower-order six bits of y the operand address, a 15-bit code that denotes (Y) are recognized for this instruction and a 3~-bit storage location. Sometimes the 15 bits are the operand itself. If so, they are represented the maximum shift count permitted is 59. (Y) by (Y). The higher-order bits of (Y) are ignored. AQ the 60-bit shift register formed by using A and Q together as a single register. 03 Shift AQ Right j the 3-bit branch condition designator. (A)i the initial and final contents of register A, res This instruction shifts (A) and (Q) as one (A)f pectively. 60-bit register. The shift is to the right (Y) Q the 3~-bit quotient register. bit positions with the lower-order bits of Bj the particular B register designated by j. (A) shifting into the higher-order bit posi Cj* the particular input-output channel designated by tions of Q. The higher-order bits of (A) are j. replaced with the original sign bit as the L the logical product or bit-by-bit product of binary digits. word is shifted. Only the lower-order six )n the nth bit position of the specified register or bits of (Y) are recognized for this instruc address enclosed within the parentheses. tion and the maximum shift count per p the 15-bit program address counter register. mitted is 59. The higher-order bits of (Y) NI the next instruction to be executed. are ignored.
SHIFT INSTRUCTIONS os Shift Q Left Execution of a shift instruction shifts the This instruction shifts (Q) circularly to the word stored in a selected register by (Y) left (Y) bit positions. The lower-order bits bit positions in a specified direction (right are replaced with the higher-order bits as or left). The register selected may be 30-bit the word is shifted. Only the lower-order register A, 30-bit register Q, or 60-bit reg six bits of (Y) are recognized for this in ister AQ, formed by treating A and Q as a struction and the maximum shift count single register. Any right shift of a 30-bit permitted is 59. The higher-order bits of register (A or Q) is open-ended (that is, (Y) are ignored. the rightmost (Y) bits are lost) and pro vided with sign extension (that is, the left 06 Shift A Left most (Y) + 1 bits become duplicates of the This instruction shifts (A) circularly to the
28 left (Y) bit positions. The lower-order bits If j * = 0, 1, the instruction is a conditional are replaced with the higher-order bits as skip on an external signal line associated the word is shifted. Only the lower-order with the specified channel. The channel des six bits of (Y) are recognized for this in ignator, j * 7 is used to specify the selected struction and the maximum shift count channel. The two bits of k* are interpreted permitted is 59. The higher-order bits of as k = 0 or k =1= O. A k =1= 0 must be used for ( Y) are ignored. j* =1= 0,1. A k = 0 must be used for j* = 0, 1. If k =1= 0 the (Y) is used unmodified. 07 Shift AQ Left
This instruction shifts (A) and (Q) as one STORE INSTRUCTIONS 60-bit register. The shift is circular to the Execution of a store instruction stores a left (Y) bit positions. The lower-bits of (A) selected word at address Y. The selected are replaced with the higher bits of (Q), word may be (Q), (A), (Cj*), (A) (Q), and the lower bits of (Q) are replaced with + (A) - (Q), or L (A)· (Q). The store in the higher bits of (A). Only the lower structions are as follows: order six bits of (Y) are recognized for this instruction and the maximum shift count permitted is 59. The higher-order bits I 4 Store Q Register of (Y) are ignored. Store (Q) at the storage address Y as di rected by the operand interpretation desig SIMPLE READ INSTRUCTIONS nator k for store class instructions. (See Execution of a simple read instruction Table 3.) transfers (Y) to a selected register.- The selected register may be Q, A, Bj, or chan I 5 Store A Register nel j. The simple read instructions are as Store (A) at storage address Y as directed follows: by the operand interpretation designator k for store class instructions. (See Table 3.) 10 Enter Q-Register
Clear the Q-Register. Then transmit (Y) I 6 Sture B Register to Q. Store the contents of the selected B-Regis ter at storage address Y as directed by the II Enter A-Register operand interpretation designator k for Clear the A-Register. Then transmit (Y) store class instructions. (See Table 3.) The to A. Branch condition designator, j, is used to 12 Enter B-Register specify the selected B-Register for this in struction and is not available for its normal Clear the contents of B-Register j. Then function. transmit the 15-bits of (Y) as specified by k for read class instructions to B-Register. I 7 Store Input Channel The Branch Condition Designator, j, is used to specify the selected B-Register for this Store, in address Y, the unmodified content instruction and is not available for its nor of the channel specified by the channel des mal function. ignator, j *. An Input Acknowledge is sent on the specified channel. The k designator I 3 Enter External Function equals 3 only. Clear the contents of the Co register. Then transmit (Y) to the Co register and send an 32 Add Q and Store External Function Control signal on ex Add (Q) to the previous content of A. Then ternal function 1ine Cj*. Channels 0 and 1 store (A) at storage address Y as directed do not have external function control lines. by the operand interpretation designator k The k designator equals 3 only. for store instructions. (See Table 3.)
29 33 Subtract Q and Store 27 Q Subtract Subtract (Q) from the previous content of Shift (A) and (Q) left 30 places as a single the A-Register. Then store (A) at storage 60-bit register. Then subtract (Y) and address Y as directed by the operand inter (A), shift (A) and (Q) left 30 places as a pretation designator, k, for store class in single 60-bit register. The content of A is structions. (See Table 3.) undisturbed by this instruction. The branch condition designator, j, has special meaning 47 Store Logical Product in this instruction. (See Table 1.) Form in the X-Register the bit-by-bit prod 30 Load A Add Q uct of (A) and (Q). Then store (X) at storage address Y as directed by the oper Clear A. Then add (Q) to A. The (Y) are and interpretation designator, k, for store then added to (A). class instructions. (See Table 3.) 3 I Load A Subtract Q Clear A. Then subtract (Q) from (A). Finally add (Y) to (A). ARITHMETIC READ INSTRUCTIONS Execution of an arithmetic read instruction 40 Enter Logical Product combines (Y) with the previous content of After clearing the A-Register, form the a selected register to form a sum, differ bit-by-bit product of (Y) and (Q) in the ence, quotient, or product. The arithmetic X-Register. Then add (X) to (A). The read instructions are as follows: branch condition designator, j, is inter preted in a special way for this instruction 20 Add for values of j = 2, 3. If j = 2, skip the next Add (Y) to the previous content of the instruction if the parity of the final (A) is A-Register. even. If j = 3, skip the next instruction if the parity of the final (A) is odd. 21 Subtract 41 Add Logical Product Subtract (Y) from the previous content of the A-Register. Form in the X-Register the bit-by-bit prod uct of (Y) and (Q). Then add (X) to the 22 Multiply previous content of A. Multiply (Q) times (Y) leaving the double 42 Subtract Logical Product length product in the AQ. If the factors are Form in the X-Register the bit-by-bit prod considered as integers, the product is an uct of (Y) and (Q). Then subtract (X) from integer in AQ. the previous content of A.
23 Divide COMPARISON INSTRUCTIONS Divide (AQ) by (Y) leaving the quotient Execution of a comparison instruction in in the Q-Register and the remainder in the volves words in Y, A, and Q, but produces A-Register. The remainder bears the same no net change in these registers. The func sign as the quotient. tion of a comparison step is to determine whether a "skip" condition obtains. (This 26 Q Add point is explained further under "Branch Shift (A) and (Q) left 30 places as a single Condition Designator" below.) The com 60-bit register. Then add (Y) to (A). Shift parison instructions are as follows: (A) and (Q) left 30 places as a single 60- bit register. The content of A is undis 04 Compare turbed by this instruction. The branch con This instruction compares the signed value dition designator, j, has special meaning in of (Y) with the signed value of (A) and/ this instruction. (See Table 1.) or (Q). It does not alter either (A) or (Q).
30 The branch condition designator, j, is inter 53 Substitute preted in a special way for this instruction. Clear each of the bits of (A) where there (See Table 1.) is a corresponding I-bit in (Q) ; the remain ing bits of (A) are unaltered. Then form 43 Masked Comparison in the X-Register the bit-by-bit product of Form in the X-Register the bit-by-bit prod (Y) and (Q). Then set each of the bits of uct of (Y) and (Q). Then subtract (X) (A) to one where there is a corresponding from the previous content of A. Then per I-bit in (X) ; the remaining bits of (A) are form the branch point evaluation of skip of unaltered. This instruction has the effect of the next sequential instruction as directed replacing bits of (A) with bits of (Y) cor by the branch condition designator, j. (See responding to ones in (Q). Table 3.) Then add (X) to A. This instruc tion results in no net change in the content REPLACE INSTRUCTIONS of any operational register. Execution of a replace instruction alters (Y). The alteration consists in combining SELECTIVE INSTRUCTIONS (Y) with the contents of one or more other Execution of a selective instruction alters registers and storing the result at address selected bits of (A) without affecting the Y. The replace instructions are as follows: unselected bits of (A). The bits of (A) to be altered are determined by a 30-bit selec 24 Add Replace tion word; each bit of (A) is subject to al Add (Y) to the previous content of A. Then teration if and only if the corresponding store (A) at storage address Y. bit of the selection word is a "I". The selec 25 Subtract Replace tion word may be either (Y) or (Q) ; the alteration that is applied to each selected Subtract (Y) from the previous contents bit may be one of four types: of A. Then store (A) at storage address Y.
a. replacement by "1" 34 Replace Add Q b. complementation c. replacement by "0" Clear A. Then add (Q) to (A). Finally add d. replacement by the corresponding bit of (Y) • (Y) to (A) and store (A) at storage ad CQ) dress Y. The selective instructions are Read Class instructions and are described below: 35 Replace Subtract Q Clear A. Then subtract (Q) from (A). Finally add (Y) to (A) and store (A) at 50 Selective Set storage address Y. Set each of the bits of (A) to one where there is a corresponding I-bit in (Y) ; the 36 Replace Add One remaining bits of (A) are unaltered. Clear A. Then add one to (A). Finally add (Y) to (A) and store (A) at storage ad 51 Selective Complement dress Y. Complement each of the bits of (A) where 37 Replace Subtract One there is a corresponding I-bit in (Y) ; the remaining bits of (A) are unaltered. Clear A. Then add minus one to (A). Fi nally, add (Y) to (A) and store (A) at storage address Y. 52 Selective Clear Clear each of the bits of (A) where there 44 Replace Logical Product is a corresponding I-bit in (Y); the re Clear A. Then form in the X-Register the maining bits of (A) are unaltered. bit-by-bit product of (Y) and (Q). Finally
31 add (X) to (A) and store (A) at storage JUMP INSTRUCTIONS address Y. The branch condition designa The Computer ordinarily executes instruc tor, j, is interpreted in a special way for tions taken from consecutive memory ad this instruction for values j = 2, 3. If j = 2, dresses. It can, however, be made to branch skip the next instruction if parity of final to Y, an an out-of-sequence address deter (A) is even. If j = 3, skip the next instruc mined by other designators in the instruc tion if the parity of final (A) is odd. tion word. This operation is called a jump. A jump diverts computer operation from 45 Replace. Add Logical Product the main program to a subroutine (or an Form in the X-Register the bit-by-bit prod isolated rnain-program segment) that be uct of (Y) and (Q). Then add (X) to the gins with execution of the instruction at previous content of A and store (A) at the out-of-sequence address. A return jump storage address Y. is a special kind of jump that performs the additional function of storing the address of the next main-program instruction (the 46 Replace Subtract Logical Product instruction that would next have been exe Form in the X-Register the bit-by-bit prod cuted if the jump had not occurred) at a uct of (Y) and (Q). Then subtract (X) reference location in the portion of memory from the previous content of A and store allotted to the subroutine. When a return (A ) at storage address Y. jump is used, the subroutine that it initiates ordinarily concludes with a jump to the ad 54 Replace Selective Set dress stored in the reference location. This concluding jump causes the main-program Set each of the bits of (A) to one where operation to be resumed at the point at there is a corresponding 1-bit in (Y) and which it was interrupted. the remaining bits of (A) are unaltered. Then store (A) at storage address Y. Execution of a jump instruction (1) deter mines whether a jump condition obtains, 55 Replace Selective Complement and (2) performs the indicated jump if the jump condition is satisfied. Jump instruc Complement each of the bits of (A) where tions differ with respect to the conditions there is a corresponding 1-bit in (Y) ; the on which performance of the jump depends. remaining bits of (A) are unaltered. Then The jump instructions are as follows: store (A) at storage address Y.
60 Arithmetic Jump 56 Replace Selective Clear Execution of this instruction will cause the Clear each of the bits of (A) where there is next program instruction to be taken from a corresponding 1-bit in (Y) ; the remain (Y) under certain conditions of either the ing bits of (A) are unaltered. Then store A- or Q-register contents. The branch con- (A) at storage address Y. dition designator, j, is interpreted in a spe cial way for this instruction. (See Table 1.) 57 Replace Substitute Clear each of the bits of (A) where there 61 Manual Jump is a corresponding 1-bit in (Q) ; the remain Execution of this instruction will cause the ing bits of (A) are unaltered. Then form in next program instruction to be taken from the X-Register the bit-by-bit product of (Y) under certain conditions of manual (Y) and (Q). Next set each of the bits of Jump Key selection. Program execution (A) to one where there is a corresponding may be stopped by certain Stop Key selec 1-bit in X; the remaining bits of (A) are tions. The branch condition designator, j, unaltered. Finally, store (A) at storage is interpreted in a special way for this in address Y. struction. (See Table 2.)
32 62 Input Active Jump 67 Deactivate Output Buffer This instruction clears the prograrll ad This instruction clears the bits in the out dress register P, and enters a new program put active designator and the output moni address in P for certain conditions of the tor designator specified by the channel input active designator. The channel desig designator, j*. nator, j *, is interpreted to designate which channel status will be examined. If the in SPECIAL PROGRAM-MODIFYING put active designator is in the one state, the INSTRUCTIONS jump condition is satisfied. The two bits of A program-modifying instruction is one k* are interpreted as k = 0, 1, 2, 3. whose execution alters the normal com puter procedure of executing instructions 63 Output Active Jump from consecutive memory addresses. In This instruction clears the program address addition to the standard jump instructions register P, and enters a new program ad described above and the skip option dress in P for certain conditions of the out described under "Branch-Condition Desig put action designator. The channel desig nator" below, these three special pro nator, j *, is interpreted to designate which gram-modifying instructions are provided: channel status will be examined. If the out 'initiate repeat', 'index skip', and 'index put active designator is in the one state, jump'. the jump condition is satisfied. The hvo bits of k* are interpreted as k = 0, 1, 2, 3. Execution of an 'initiate repeaf instruction causes the next successive instruction to be 64 Arithmetic Return Jump executed (Y) times. The repeated instruc This instruction executes a return jump tion may be modified for each repetition as sequence for certain conditions of either indicated in the tabulation below (where j the A- or Q-register content. The branch is part of the 'initiate repeat' instruction condition designator is interpreted in a spe while y and b are parts of the repeated in cial way for this instruction. (See Table 2.) struction itself). If the jump condition is satisfied, the ad dress of the return jump instruction plus Execution of an 'index skip' instruction can one is stored in the address portion of (Y) cause the computer to perform a skip; that and a program jump is executed to the in is, to leave the next sequential instruction struction at address Y + 1. unexecuted and execute its successor in stead. 65 Manual Return Jump Execution of an 'index jump' instruction This instruction executes a return jump can cause the computer to perform a jump. sequence for conditions determined by manual key selections. The branch condi The special program modifying instruc tion designator, j, is interpreted in a spe tions are as follows: cial way for this instruction. (See Table 2.) 70 Initiate Repeat If the jump condition is satisfied, the ad dress of the return jump instruction plus Initiate a repeat mode of operation which one is stored in the address portion of (Y) will cause the next sequential instruction to and a program jump is executed to the in be executed (Y) times. The remaining exe struction at address Y + 1. cutions are maintained in B-Register 7. The branch condition designator, j, is inter preted in a special way for this instruction. 66 Deactivate Input Buffer (See Table 2.) This instruction clears the bits specified by the channel designator, j *, in the input ac 71 Index Skip tive designator and the input monitor If the content of the B-Register, specified designator. by the branch condition designator, j, is
33 equal to (Y), skip the next instruction and nator and the output monitor designator. clear B-Register j. If the content of B-Reg k = 2 is not permitted. A program interrupt ister j is not equal to (Y), add one to the to the instruction stored at address 00060 content of B-Register j and proceed to the + j * will occur at the termination of the next sequential instruction. output buffer. Branch-Condition Designator 72 Index Jump If the content of the B-Register, specified The branch-condition designator, J, IS a by the branch condition designator, j, is three-bit code that may be interpreted as non zero, execute a jump in program ad (1) a skip or jump-condition designator. dress to address (Y) and reduce the con (2) a register designator, or (3) a repeat tent of B-Register j by one. If the content modification designator. of B-Register j is zero proceed to the next sequential instruction. Skip and Jump Interpretations of j The most common use of j is to designate 73 Initiate Input Buffer conditions which, if satisfied, will cause the If k* = 3, store (Y), the input control word, next instruction to be skipped. The normal in storage location 00100 + j *. If k* = 1, 8kip conditions are listed below: store the lower 15-bits of (Y) in the lower order half of address 00100 + j*. Then set j=O ... Noskip j = 1 ...... Unconditional skip the input active designator bit j *. k = 2 is j = 2...... Skip if (Q) is positive not permitted. j = 3 ...... Skip if (Q) is negative j = 4 ..... Skip if (A) is zero 74 Initiate Output Buffer j = 5... . . Skip if (A) is not zero j = 6 ...... Skip if (A) is positive If k* = 3 store (Y) the output control word j = 7 ...... Skip if (A) is negative in storage location 00120 + j *. If k* = 1 The common skip interpretation of j, as store the lower 15-bits of (Y) in the lower defined by the above list, applies to instruc order half of the address 00120 + j *. Then tions in which f = 01-03, 05-11, 14, 15, 20- set the input active designator bit j *. k = 2 25, or 30-37. is not permitted. Special skip interpretations apply to 'com 75 Initiate Input Buffer with Monitor pare', 'Q add', and 'Q subtract' instructions If k* = 3, store (Y), the control word, in (f = 04, 26, 27 respectively). These inter storage location 00100 + j*. If k* = 0, store pretations are defined by the list that fol Y in the lower half of storage location lows: 00100 + j *. If k* = 1 store the lower-order f=04 f=26,27 15-bits of (Y) in the lower-order half of j=O No skip No skip address 00100 + j*. Then set the j* bit of j= 1 Unconditional skip Unconditional skip both the input active designator and the j=2 Skip if (Y) £:. (Q) Skip if (A) is positive input monitor designator. k = 2 is not per j=3 Skip if (Y) > (Q) Skip if (A) is negative j=4 Skip if (Q) ~ (Y) Skip if (Q) is zero mitted. A program interrupt to the instruc and (Y) > (A) tion stored at address 00040 + j * will occur j=5 Skip if (Y) > (Q) Skip if (Q) is not zero at the termination of the input buffer. Of (Y) L (A) Skip if (Y) £:. (A) Skip if (Q) is positive Skip if (Y) > (A) Skip if (Q) is negative 76 Initiate Output Buffer with Monitor If k* = 3, store (Y), the control word, in In jump instructions (f = 60-67), j desig storage location 00120 + j *. If k* = 0, store nates conditions that determine whether or Y in the lower-half of storage location not the indicated jumps are to be performed. 00120 + j *. If k* = 1 store in the lower Interpretations for j in jump instructions order half of address 00120 + j *. Then set are defined under "Jump Instructions" the j * bit of both the output active desig- above.
34 (The computer treats zero as a signed num ter exists; (EO) is interpreted as zero RO ber that is usually, but not necessarily, that y is not modified if b = O. positive. This fact can affect some of the interpretations of j.) Operand-Interpretation Designator The operand-interpretation designator, k, Register-Specification is a three-bit code that governs, first, the Interpretation of j or j* process whereby the operand is derived Input and output jump instructions (f = from y + (Bb), and secondly, data trans 62, 63, 66, 67), j * does not directly specify missions in store operations. The effect of k a jump condition; instead, it designates the is different for each of three instruction channel whose status (sampled or unsam categories: read, store, and replace. pled) determines the performance of the jump. Similarly, in all other instructions Interpretation of k in Read Instructions that involve a program-selected channel (f In read instructions (f = 01-13, 20-23, 26- = 13, 17, 73-76), j* designates the selected 31, 40-43, 50-53, 60-76) , the transfer of the channel. Similarly, in all instructions that operand (Y) from the X-Register to either involve a program-selected B-Register (f the A, Q, B or C Registers, is determined by = 12, 16, 71, 72), j designates the selected the particular function used. The deriva register. tion of the operand (Y) in X is determined by k in accord with the list that follows. The Repeat-Mpdification Interpretation list shows the contents of the upper and In 'repeat' instructions (f = 70), j governs lower 15 positions of X for each value of k. modification of the repeated instruction. This interpretation of j is defined under k (X)u (XlL "Special Program-Modifying Instructions" 0 Zero y+ (Bb) above. 1 Zero (y+(Bb»L Operand Address Designator 2 Zero (y+(Bb»U 3 (y + (Bb»U (y+(Bb»L As mentioned earlier, when k == 0 or 4, the 4 es y+ (Bb) 15-bit y designator is subjected to modifica 5 es (y+(Bb)h 6 ~s (y+(Bb»U tion and becomes the operand which is 7 (A)u (Ah represented by (Y). The role of the oper and in the execution of each instruction depends on f and is explained for each f In the list above, "es" for ("extended sign") under "Function-Code Designator" above. indicates that all bits of (X)u are equal to The manner in which the operand is devel the highest order bit of (X)L. This list also oped from y depends on other designators shows that y + (Bb) may, (1) become part and is explained in the paragraphs that of the operand (k = 0,4), (2) specify the ad follow. dress of part of the operand (k = 1,2,3,5,6) or (k = 7) be replaced by (A). The value Address-Modification Designator k = 7 is excluded for f = 22,23,26-31,52,53.
The address-modification designator, b, is a Interpretation of k in Store Instructions three-bit code that governs the first modifi cation to which y is subjected. This modifi In store instructions (f = 14-17,32-33,47) cation consists of adding to y the contents the contents of the A, Q, B or C Registers, of a B-Register designated by b. That is, y as determined by the particular function is modified to become y + (Bb) . No BO regis- used, is transferred to the D Register. The
35 derivation of the operand (Y) in D is deter For instructions 40 and 44-Enter Logical mined by k in accord with the list that fol Product and Replace Logical Product: lows:
k=O* (0) ~ Q j = 2 Skip next instruction if the parity of the final contents of k=l (OL) ~ YL A is even. k=2 (OL) ~ Yu j = 3 Skip next instruction if the pafity of the final contents of k=3 (0) ~ Y A is odd. k=4* (0) ~ A k=5 ** (OL)' ~ YL k=6 (OL)' ~ Yu In general Q is considered to contain the k=7 (0)' ~ Y mask for which the parity is known. Then '-, A k=O in instruction 14 causes (Q)' -+ Q and k=4 in by choosing the appropriate mask for which instruction 15, 32 and 33; (A)' -+ A. the parity is known, the parity can be calcu ** The prime mark after a parenthesis ( .... )' is defined as "take the complement of the contents of .... ". lated on any selected group of bits in the accumulator as defined by the mask. Interpretation of k in Replace Instructions Illegal Instruction Code Fault In replace instructions (f = 24-25, 34-37, 44-46, 54-57), k governs, first, the deriva Instruction Codes 00 or 77 cause a jump to tion of the operand as in read instructions, fixed address 00014 and initiation of the and secondly, the transfer of a word to ad interrupt mode. dress Y as in store instructions. (The val ues k = 0,4,7 are not used). Special Address Allocation Exceptions The allocation of the special addresses for For instructions 13, 17, 62, 63, 66, 67, 73, the control of buffers, external interrupts 74,75 and 76, the f, j*, k*, band y designa and internal interrupts are tabulated tors are as follows: below:
f j* k* b Y 00014 Fault, delta clock and millisecond time-out 29 24 23 20 19 18 17 15 14 0 interrupt. 00017 Incremental-I ncremental-I nterrupt Figure 4-2. Input-Output Instruction Word 00020-00035 External Interrupt 00040-00055 Input Internal Interrupt j* = In these instructions j designates the 00060-00075 Output Internal Interrupt input-output channels. 00100-00115 Input Buffer Control k* = In these instructions k is interpreted as "a" or not "0". 00120-00135 Output Buffer Control
j DESIGNATORS FOR *COMMANDS
04 26 or 27 _
0 No Skip No Skip No Jump Oeac. int. mode 1 Skip Skip Jump & Oeac. int. mode 2 Skip If (V) ~ (Q) Skip If (A) Pos Jump If (Q) Pos 3 Skip If (V) > (Q) Skip If (A) Neg Jump If (Q) Neg 4 Skip If (Q) ~ (V) And Skip If (Q) = 0 Jump If (A) = 0 (V) > (A) 5 Skip If (Q) < (V) Or Skip If (Q) ~ 0 Jump If (A) ~ 0 (V)~ (A) 6 Skip If (V) ~ (A) Skip If (Q) Neg Jump If (A) Pos 7 Skip If (V) > (A) Skip If (Q) Pos Jump If (A) Neg
36 TABLE 1 Relurn Jump Relurn Jump Jump If JUMP 1 Nole B Is Sel Jump If JUMP 2 Is Sel Jump If (Q) Pas Jump If JUMP 2 Nole C Is Sel Jump If JUMP 3 Is Sel Jump If (Q) Neg Jump If JUMP 3 Nole 0 Is Sel Jump And Slop Jump If (A) = 0 Jump, Slop Nole E Jump; Slop If STOP 5 Jump If (A) :I 0 Jump; Slop If Nole F Is Sel STOP 5 Is Sel Jump; STOP If STO P 6 Jump If (A) Pas Jump; Slop If Nole G Is Sel STOP 6 Is Sel Jump; Slop If STOP 7 Jump If (A) Neg Jump; Slop If Nole H Is set STOP 7 Is Sel
TABLE 2
y MODIFICATION OF REPEATED INSTRUCTION
NOTE A: IF r o =0 or 4, repeated instruction unmodi fied NOTE B: IF r o = 1 or 5, advance execution address of repeated instruction each execution except the first NOTE c: IF j'0 = 2 or 6, back execution address of repeated instruction each ex· ecution except the first o b NOTE D: IF r = 3 or 7, add (B ) of repeated instruction each execution
NOTES: E, F, G, H, are like A, B, C, D, respectively, with the added stipulation that if the repeated 6 instruction is a replace instruction, (B ) is added to the operand address lor the store portion 01 the replace instruction.
j and k DESIGNATORS
(Z)~XL' (X)~YL (Z)~XL' (X)~YL O--X O__ X u u
Skip If (Q) Pas. (Z)U-XL' (X)L-YU (Z)e-XL' (X)':-Y U O-X U O-X U
Skip If (Q) Neg. (Z)-X (X>-(Y) (Z) __ X (X) ....Y
Skip If (A) = 0 (U).:+" XL' (X)--A Nol Used Nol Used U -X 14 U
Skip If (A) " 0 (Z)L-XL' (X)'~YL (Z)L--XL' (X)~(Y)L Z .... X 14 U Z --X 14 U
Skip If (A) Pas. (Z).;-XL' (X)'L-YU (Z)~XL' (X)L.... YU Z-X Z-X 28 U 28 U
Skip If (A) Neg. (A)--X (X)'_Y Nol Used Nol Used
TABLE 3
37
DIVISION OF SPERRY RAND CORPORATION
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