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X86 Hardware Segmentation

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X86 Hardware Segmentation Want processes to co-exist Issues in sharing physical memory Protection • - A bug in one process can corrupt memory in another - Must somehow prevent process A from trashing B’s memory - Also prevent A from even observing B’s memory (ssh-agent) Transparency • - A process shouldn’t require particular memory locations Consider multiprogramming on physical memory - Processes often require large amounts of contiguous memory • (for stack, large data structures, etc.) - What happens if pintos needs to expand? Resource exhaustion - If emacs needs more memory than is on the machine?? • - If pintos has an error and writes to address 0x7100? - Programmers typically assume machine has “enough” memory - When does gcc have to know it will run at 0x4000? - Sum of sizes of all processes often greater than physical memory - What if emacs isn’t using its memory? 1/36 2/36 Virtual memory goals Virtual memory advantages Is address Can re-locate program while running • legal? - Run partially in memory, partially on disk app. virtual address Yes, phys. addr 0x30408 0x92408 Most of a process’s memory will be idle (80/20 rule). load • gcc emacs data memory kernel To fault handler No physical idle memory idle Give each program its own “virtual” address space • kernel kernel - At run time, Memory-Management Unit relocates each load, store to actual memory. App doesn’t see physical memory - Write idle parts to disk until needed Also enforce protection • - Let other processes use memory for idle part - Prevent one app from messing with another’s memory - Like CPU virtualization: when process not using CPU, switch. And allow programs to see more memory than exists When not using a page switch it to another process. • - Somehow relocate some memory accesses to disk Challenge: VM = extra layer, could be slow 3/36 • 4/36 Idea 1: load-time linking Idea 1: load-time linking Link as usual, but keep the list of references Link as usual, but keep the list of references • • Fix up process when actually executed Fix up process when actually executed • • - Determine where process will reside in memory - Determine where process will reside in memory - Adjust all references within program (using addition) - Adjust all references within program (using addition) Problems? Problems? • • - How to enforce protection - How to move once in memory (Consider: data pointers) - What if no contiguous free region fits program? 5/36 5/36 Idea 2: base + bounds register Idea 2: base + bounds register Two special privileged registers: base and bound Two special privileged registers: base and bound • • On each load/store: On each load/store: • • - Physical address = virtual address + base - Physical address = virtual address + base - Check 0 virtual address < bound, else trap to kernel - Check 0 virtual address < bound, else trap to kernel ≤ ≤ How to move process in memory? How to move process in memory? • • - Change base register - Change base register What happens on context switch? What happens on context switch? • • - OS must re-load base and bound register - OS must re-load base and bound register 6/36 6/36 Definitions Address space Programs load/store to virtual (or logical) addresses • Actual memory uses physical (or real) addresses • VM Hardware is Memory Management Unit (MMU) • - Usually part of CPU - Accessed w. privileged instructions (e.g., load bound reg) - Translates from virtual to physical addresses - Gives per-process view of memory called address space 7/36 8/36 Base+bound trade-offs Base+bound trade-offs Advantages Advantages • • - Cheap in terms of hardware: only two registers - Cheap in terms of hardware: only two registers - Cheap in terms of cycles: do add and compare in parallel - Cheap in terms of cycles: do add and compare in parallel - Examples: Cray-1 used this scheme - Examples: Cray-1 used this scheme Disadvantages Disadvantages • • - Growing a process is expensive or impossible - No way to share code or data (E.g., two copies of bochs, both running pintos) One solution: Multiple segments • - E.g., separate code, stack, data segments - Possibly multiple data segments 9/36 9/36 Segmentation Segmentation mechanics Each process has a segment table Let processes have many base/bounds regs • • Each VA indicates a segment and offset: - Address space built from many segments • - Can share/protect memory on segment granularity - Top bits of addr select segment, low bits select offset (PDP-10) - Or segment selected by instruction or operand (means you Must specify segment as part of virtual address • need wider “far” pointers to specify segment) 10/36 11/36 Segmentation example Segmentation trade-offs virtual physical Advantages • - Multiple segments per process - Allows sharing! (how?) - Don’t need entire process in memory Disadvantages • - Requires translation hardware, which could limit performance - Segments not completely transparent to program (e.g., default segment faster or uses shorter instruction) - n byte segment needs n contiguous bytes of physical memory 2-bit segment number (1st digit), 12 bit offset (last 3) • - Makes fragmentation a real problem. - Where is 0x0240? 0x1108? 0x265c? 0x3002? 0x1600? 12/36 13/36 Fragmentation Alternatives to hardware MMU Fragmentation = Inability to use free memory • ⇒ Language-level protection (Java) Over time: • • - Single address space for different modules - Variable-sized pieces = many small holes (external frag.) - Language enforces isolation - Fixed-sized pieces = no external holes, but force internal waste - Singularity OS does this [Hunt] (internal fragmentation) Software fault isolation • - Instrument compiler output - Checks before every store operation prevents modules from trashing each other - Google Native Client does this with only about 5% slowdown [Yee] 14/36 15/36 Paging Paging trade-offs Divide memory up into small pages • Map virtual pages to physical pages • - Each process has separate mapping Allow OS to gain control on certain operations • - Read-only pages trap to OS on write - Invalid pages trap to OS on read or write - OS can change mapping and resume application Eliminates external fragmentation Other features sometimes found: • • Simplifies allocation, free, and backing storage - Hardware can set “accessed” and “dirty” bits • - Control page execute permission separately from read/write (swap) - Control caching of page Average internal fragmentation of .5 pages per • “segment” 16/36 17/36 Simplified allocation Paging data structures Pages are fixed size, e.g., 4K • - Least significant 12 (log 4K) bits of address are page offset gccphysical emacs memory - Most significant bits are page number Each process has a page table Disk • - Maps virtual page numbers to physical page numbers - Also includes bits for protection, validity, etc. On memory access: Translate VPN to PPN, • then add offset Allocate any physical page to any process • Can store idle virtual pages on disk • 18/36 19/36 Example: Paging on PDP-11 x86 Paging Paging enabled by bits in a control register (%cr0) 64K virtual memory, 8K pages • • - Only privileged OS code can manipulate control registers - Separate address space for instructions & data Normally 4KB pages - I.e., can’t read your own instructions with a load • %cr3: points to 4KB page directory Entire page table stored in registers • • - See pagedir activate in Pintos - 8 Instruction page translation registers Page directory: 1024 PDEs (page directory entries) - 8 Data page translations • - Each contains physical address of a page table Swap 16 machine registers on each context switch • Page table: 1024 PTEs (page table entries) • - Each contains physical address of virtual 4K page - Page table covers 4 MB of Virtual mem See old intel manual for simplest explanation • - Also volume 2 of AMD64 Architecture docs - Also volume 3A of latest Pentium Manual 20/36 21/36 x86 page translation x86 page directory entry Linear Address 3122 2112 11 0 Directory Table O f f s et Page−Directory Entry (4−KByte Page Table) 31 1 2 11 9 8 7 6 5 4 3 2 1 0 12 4−KByte Page P P U R Page−Table Base Address A vail G P 0 A C W / / P S D T S W Page Table 10 10 Physical Address Page Directory Available for system programmer’s use Global page (Ignored) Page size (0 indicates 4 KBytes) Page−Table Entry Reserved (set to 0) 20 A c c e s se d Directory Entry Cache disabled Write−through 32* 1024 PDE 1024 PTE = 220 Pages User/Supervisor CR3 (PDBR) × R e a d /W rite P re s e n t *32 bits aligned onto a 4−KByte boundary 22/36 23/36 x86 page table entry x86 hardware segmentation x86 architecture also supports segmentation • Page−Table Ent ry (4−KByte Page) - Segment register base + pointer val = linear address 31 12 11 9 8 7 6 5 4 3 2 1 0 - Page translation happens on linear addresses P P P U R Two levels of protection and translation check Page Base Address Avail G A D A C W / / P • T D T S W - Segmentation model has four privilege levels (CPL 0–3) - Paging only two, so 0–2 = kernel, 3 = user Available for system programmer’s use Why do you want both paging and segmentation? Global Page • Page Table Attribute Index Dirty Accessed Cache Disabled Write−Through User/Supervisor Read/Write Present 24/36 25/36 x86 hardware segmentation Making paging fast x86 architecture also supports segmentation • - Segment register base + pointer val = linear address x86 PTs require 3 memory references per load/store • - Page translation happens on linear addresses - Look up page table address in page directory Two levels of protection and translation check - Look up PPN in page table • - Segmentation model has four privilege
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