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High Performance Computing : Parallel Processing Models and Architectures / Marco Vanneschi

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High Performance Computing : Parallel Processing Models and Architectures / Marco Vanneschi Marco Vanneschi High Performance Computing Parallel Processing Models and Architectures Vanneschi, Marco High performance computing : parallel processing models and architectures / Marco Vanneschi. - Pisa : Pisa university press, 2014. – (Manuali) 004.35 (22.) 1. Elaborazione parallela dei dati CIP a cura del Sistema bibliotecario dell’Università di Pisa © Copyright 2014 by Pisa University Press srl Società con socio unico Università di Pisa Capitale Sociale € 20.000,00 i.v. - Partita IVA 02047370503 Sede legale: Lungarno Pacinotti 43/44 - 56126 Pisa Tel. + 39 050 2212056 - Fax + 39 050 2212945 [email protected] www.pisauniversitypress.it ISBN 978-88-6741-372-0 Le fotocopie per uso personale del lettore possono essere effettuate nei limiti del 15% di ciascun volume/ fascicolo di periodico dietro pagamento alla SIAE del compenso previsto dall’art. 68, commi 4 e 5, della legge 22 aprile 1941 n. 633. Le riproduzioni effettuate per fi nalità di carattere professionale, economico o commerciale o comunque per uso diverso da quello personale possono essere effettuate a seguito di specifi ca autorizzazione rilasciata da AIDRO, Corso di Porta Romana, 108 – 20122 Milano, [email protected] – www.aidro.org A Giovanna Preface This book is the result of my integrated research and teaching experience in High Performance Computing at the Computer Science Department, University of Pisa. During several years, a continuous and collaborative effort has been done for properly exploiting the research experience in teaching Master Degree courses on advanced architectures, programming models and systems. At the same time, the teaching experience has often stimulated new research activities on subject matters needing a more scientific and methodological treatment, as well as a better integration of methodology and technology. This positive feedback has been enabled by the joint work with my collaborators and by a large number of Master and PhD dissertations. The book is currently used in the High Performance Computing course of the international Master Degree Program in Computer Science and Networking, a joint initiative of University of Pisa and Scuola Superiore Sant’Anna. Subject matters and goals High Performance Computing (HPC) is the ICT area that studies hardware-software architectures and applications characterized by requirements for high processing bandwidth, low response time, high efficiency and scalability, as well as availability and energy efficiency. Many scientific, commercial and technological disciplines benefit from HPC systems and tools: physics, chemistry, earth sciences, biology, medicine, engineering, environmental control, emergency management, telecommunications, software defined networking, information retrieval, big data, intelligent sensors, image and signal processing, multimedia, finance and economy, and so on. HPC is not limited to scientific supercomputing, though this is a very challenging arena. Industrial, commercial and embedded applications are perceived as quite strategic areas, which, in addition to raw performance, require modularity, portability and programmability. HPC is synonymous with parallel and distributed processing. Any HPC product is manly based on parallelism exploitation: at the process/thread level (shared memory SMP/NUMA multiprocessors, distributed memory multicomputers and heterogeenous clusters), at the instruction level (pipeline scalar and superscalar CPUs, vectorization facilities, stream processing and SIMT-GPUs). Typical HPC system configurations range from few processing elements to hundreds and thousands of processors/computers. Currently, an important technological evolution/revolution is under way: multi-/many- core components, or chip multiprocessors, will replace (are replacing) uniprocessor-based CPUs for both the scientific and the commercial market. This fact has enormous implications on technologies and applications: in some measure, all hardware-software products will be based on parallel processing. In this evolution/revolution, a fundamental role is played by high-level and portable programming tools and application development frameworks: they are becoming first- II class citizens in HPC field too, although currently a wide gap still exists between parallel architecture and parallel programming maturity. For too many years, parallel program design has been the realm of unstructured approaches based on low-level tools and specialized libraries. By now, the need for a user-friendly and solid application- architecture bridge has been widely recognized: achieving a proper trade-off in the complex interrelationships of performance, programmability and portability issues is a must. The aim of this book is: 1. to provide fundamental models and methodologies for parallel programming and parallel applications development, 2. to study parallel architectures thoroughly, at the state-of-the-art and according to the research trends, 3. to establish a strong relationship between parallel application methodologies and parallel architectures. Approach and organization of the book In this book parallel programming and parallel architectures are studied as two strongly interrelated areas in high-performance computing. Programming models and tools are characterized by a properly abstract view of the parallel architecture. At the same time, parallel architectures support such models and tools in the most effective and seamless way. Concepts and techniques, both in programming methodologies and in parallel architectures, are studied according to a uniform and structured approach. Design and implementation models and cost models (i.e. performance models) are defined for parallel programming methodologies, for parallel architectures, and for their integration. The book is organized into three Parts: 1. Parallel Processing Models and Methodology, 2. Single Instruction Stream Architectures, 3. Multiple Instruction Stream Architectures. Part 1 studies fundamental concepts and techniques in parallel computation structuring and design, including parallelization methodologies and paradigms, parallel programming models, their implementation, and related cost models. Models and methodologies of Part 1 are fundamental, not only for parallel programming and application development, but also for designing, understanding and evaluating parallel architectures and machine structures. In other words, Part1 defines also the conceptual and technical framework for the “hardware-software” integration of parallel applications and parallel architectures. Parts 2 and 3 study architectures of high-performance computing systems, including instruction level parallelism, SIMD/SIMT technologies, shared memory multiprocessors, distributed memory multicomputers, high performance interconnect structures. At the light of the strategic role played by chip multiprocessors (CMP), a large space is dedicated to CMP-based architectures: implementation and cost models for shared memory organization, processor synchronization, cache coherence, memory ordering, and communication run-time support,. All issues in parallel programming and parallel architecture are dealt with in terms of structural models, static and dynamic support to computation and programming models, III performance evaluation, capability for building complex and heterogeneous applications and/or enabling platforms. Models and methodologies precede the description of technologies and products (multi-/many-core technology, high-performance networks and interconnect technologies, parallel programming tools). Through this approach the reader will be able to understand and to critically analyze current/future products and/or to properly adapt/combine them, as well as to conceive new solutions. The book contains a large number of examples, exercises and case studies. Part 1: Parallel Processing Models and Methodology This Part deals with systematic methods and techniques for the design of high- performance parallel and distributed computations. The goal is to achieve a good trade- off between two contrasting requirements: programmability and portability, on one side, and performance and efficiency, on the other side. The methodology is based on two interrelated issues: structured parallelism paradigms and cost models. Structured parallelism paradigms aim to provide standard and effective rules for composing parallel computations in a machine-independent manner. Cost models are defined for performance evaluation and prediction, and are fundamental for reducing parallel software design complexity. Cost models will take into account application- and architecture-dependent parameters related to calculation, storage and communication. Contents: 1. HPC and structured parallel computations 2. Metrics for performance evaluation 3. Interprocess communication 4. Basic cost model for acyclic graph computations 5. Pipeline paradigm 6. Farm paradigm 7. Data parallel paradigms 8. Examples of parallel program design 9. Client-server computations Methodology of Part 1 has much wider applicability. In Parts 2 and 3 it is used for studying properties and performances of parallel architectures. Part 2: Single Instruction Stream Architectures This Part applies the general methodology of Part 1 to the firmware architecture level, i.e. structured parallel computations are implemented as collections of communicating processing units. After high-performance communication techniques, we study parallel structures for efficient cache hierarchies and for Instruction Level Parallelism (ILP) basic
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