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(12) United States Patent (10) Patent No.: US 7,676,600 B2 Davies Et Al
USOO7676600B2 (12) United States Patent (10) Patent No.: US 7,676,600 B2 Davies et al. (45) Date of Patent: Mar. 9, 2010 (54) NETWORK, STORAGE APPLIANCE, AND 4,245,344 A 1/1981 Richter METHOD FOR EXTERNALIZING AN INTERNAL AO LINK BETWEEN A SERVER AND A STORAGE CONTROLLER (Continued) INTEGRATED WITHIN THE STORAGE APPLIANCE CHASSIS FOREIGN PATENT DOCUMENTS (75) Inventors: Ian Robert Davies, Longmont, CO WO WOO21 O1573 12/2002 (US); George Alexander Kalwitz, Mead, CO (US); Victor Key Pecone, Lyons, CO (US) (Continued) (73) Assignee: Dot Hill Systems Corporation, OTHER PUBLICATIONS Longmont, CO (US) Williams, Al. “Programmable Logic & Hardware.” Dr. Dobb's Jour nal. Published May 1, 2003, downloaded from http://www.dd.com/ (*) Notice: Subject to any disclaimer, the term of this architect 184405342. pp. 1-7. patent is extended or adjusted under 35 U.S.C. 154(b) by 1546 days. (Continued) Primary Examiner Hassan Phillips (21) Appl. No.: 10/830,876 Assistant Examiner—Adam Cooney (22) Filed: Apr. 23, 2004 (74) Attorney, Agent, or Firm—Thomas J. Lavan: E. Alan pr. A5, Davis (65) Prior Publication Data (57) ABSTRACT US 2005/0027751A1 Feb. 3, 2005 Related U.S. Application Data A network Storage appliance is disclosed. The storage appli (60) Provisional application No. 60/473,355, filed on Apr. ance includes a port combiner that provides data COU1 23, 2003, provisional application No. 60/554,052, cation between at least first, second, and third I/O ports; a filed on Mar. 17, 2004. storage controller that controls storage devices and includes s the first I/O port; a server having the second I/O port; and an (51) Int. -
Making the Switch to Rapidio
QNX Software Systems Ltd. 175 Terence Matthews Crescent Ottawa, Ontario, Canada, K2M 1W8 Voice: +1 613 591-0931 1 800 676-0566 Fax: +1 613 591-3579 Email: [email protected] Web: www.qnx.com Making the Switch to RapidIO Using a Message-passing Microkernel OS to Realize the Full Potential of the RapidIO Interconnect Paul N. Leroux Technology Analyst QNX Software Systems Ltd. [email protected] Introduction Manufacturers of networking equipment have hit a bottleneck. On the one hand, they can now move traffic from one network element to another at phenomenal speeds, using line cards that transmit data at 10 Gigabits per second or higher. But, once inside the box, data moves between boards, processors, and peripherals at a much slower clip: typically a few hundred megabits per second. To break this bottleneck, equipment manufacturers are seeking a new, high-speed — and broadly supported — interconnect. In fact, many have already set their sights on RapidIO, an open-standard interconnect developed by the RapidIO Trade Association and designed for both chip-to-chip and board-to-board communications. Why RapidIO? Because it offers low latency and extremely high bandwidth, as well as a low pin count and a small silicon footprint — a RapidIO interface can easily fit Making the Switch to RapidIO into the corner of a processor, FPGA, or ASIC. Locked Out by Default: The RapidIO is also transparent to software, allowing Problem with Conventional any type of data protocol to run over the intercon- Software Architectures nect. And, last but not least, RapidIO addresses the demand for reliability by offering built-in While RapidIO provides a hardware bus that is error recovery mechanisms and a point-to-point both fast and reliable, system designers must find or architecture that helps eliminate single points develop software that can fully realize the benefits of failure. -
VME, Gig-E, Serial Rapidio (Srio) Or PCI Express (Pcie) CONTROL
Model 67C3 6U, OpenVPX, MULTI-FUNCTION I/O CARD VME, Gig-E, Serial RapidIO (sRIO) or PCI Express (PCIe) CONTROL A/D, D/A, Discrete/TTL/CMOS/Differential I/O, RTD, Synchro/Resolver/LVDT/RVDT Measurement and Simulation, Encoder/Counter ARINC 429/575, RS-422/485/232, MIL-STD-1553, CANbus FEATURES Multiple functions on a single slot 6U OpenVPX card OpenVPX Slot Profile: SLT6-BRG-4F1V2T-10.5.1 User can specify up to six different function modules Automatic background BIT testing continually checks and reports the health of each channel Control via VME or Dual Gig-E interfaces PCIe (x1) options or sRIO (1x) Front and/or Rear I/O Conduction or Convection cooled versions Commercial and Rugged applications Software Support Kit and Drivers are available Front I/O GigE Front I/O DESCRIPTION The 67C3 is a single slot 6U OpenVPX Function Function Function Function Function Function (0.8” pitch) multi-function I/O and serial Module Module Module Module Module Module # 1 # 2 # 3 # 4 # 5 # 6 communications card. With VME, Gigabit Ethernet (Gig- E) and High Speed sRIO or PCIe control interface Module Module Module Module Module Module resources resources resources resources resources resources selections, users can confidently choose to take advantage of the OpenVPX form-factor offering higher speed switched fabric communication options. Inter Module Bus The motherboard contains six independent module slots, each of which can be populated with a function- specific module, and can now be controlled by the VME, Optional Board Resources Reference Gig-E and sRIO or PCIe. This enhanced motherboard, Generator using multiple DSPs, allows for higher processing power and dedicated control for each module. -
Rapidio™: an Embedded System Component Network Architecture
February 22, 2000 RapidIOª: An Embedded System Component Network Architecture Architecture and Systems Platforms Motorola Semiconductor Product Sector 7700 West Parmer Lane, MS: PL30 Austin, TX 78729 Abstract This paper describes RapidIO, a high performance low pin count packet switched sys- tem level interconnect architecture. The interconnect architecture is intended to be an open standard which addresses the needs of a variety of applications from embedded infrastructure to desktop computing. Applications include interconnecting microproces- sors, memory, and memory mapped I/O devices in networking equipment, storage sub- systems, and general purpose computing platforms. This interconnect is intended primarily as an intra-system interface, allowing chip to chip and board to board com- munications at giga-byte per second performance levels. Supported programming mod- els include globally shared distributed memory and message-passing. In its simplest form, the interface can be implemented in an FPGA end point. The interconnect archi- tecture deÞnes a protocol independent of a physical implementation. The physical fea- tures of an implementation utilizing the interconnect are deÞned by the requirements of the implementation, such as I/O signalling levels, interconnect topology, physical layer protocol, error detection, etc. The interconnect is deÞned as a layered architecture which allows scalability and future enhancements while maintaining compatibility. 1 of 25 Introduction 1 Introduction Computer and embedded system development continues to be burdened by divergent requirements. On one hand the performance must increase at a nearly logarithmic rate, while on the other hand system cost must stay the same or decrease. Several applica- tions, such as those found in telecommunications infrastructure equipment, are also bur- dened with increasing capabilities while decreasing the board size and ultimately the ßoor space which equipment occupies. -
MVME3100 Single Board Computer Installation and Use P/N: 6806800M28H September 2019
MVME3100 Single Board Computer Installation and Use P/N: 6806800M28H September 2019 © 2019 SMART Embedded Computing™, Inc. All Rights Reserved. Trademarks The stylized "S" and "SMART" is a registered trademark of SMART Modular Technologies, Inc. and “SMART Embedded Computing” and the SMART Embedded Computing logo are trademarks of SMART Modular Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks of their respective owners. These materials are provided by SMART Embedded Computing as a service to its customers and may be used for informational purposes only. Disclaimer* SMART Embedded Computing (SMART EC) assumes no responsibility for errors or omissions in these materials. These materials are provided "AS IS" without warranty of any kind, either expressed or implied, including but not limited to, the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. SMART EC further does not warrant the accuracy or completeness of the information, text, graphics, links or other items contained within these materials. SMART EC shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. SMART EC may make changes to these materials, or to the products described therein, at any time without notice. SMART EC makes no commitment to update the information contained within these materials. Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to a SMART EC website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of SMART EC. -
MCP750HA Compactpci Single Board Computer Installation And
MCP750HA Hot Swap CompactPCI Single Board Computer Installation and Use MCP750HA/IH3 December 2000 © Copyright 2000 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc. PowerPC™ is a trademark of IBM Corporation, and is used by Motorola, Inc. under license from IBM Corporation. CompactPCI is a registered trademark of PCI Industrial Computer Manufacturers Group. All other products mentioned in this document are trademarks or registered trademarks of their respective holders. Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment. Ground the Instrument. To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes. Do Not Operate in an Explosive Atmosphere. -
CPCI 2404 PICMG PDF#82988.Indd
PMC XMCs: The popular PMC adds a fabric interface By Andy Reddig and Greg Novak raditional PMC modules have been the de facto standard for adding I/O expansion capability to Tembedded systems. The recently adopted standard for Processor PMCs enables the expansion of PMC module functionality to include processing as well as streaming I/O. As embedded systems transition from legacy parallel buses to high-speed switched serial fabrics, mezzanines are keeping pace through the XMC standard for switched fabric mezzanine cards. These new fabric-enabled mezzanine cards will allow the popular PMC form factor to continue its evolution, supporting the next generation of embedded systems with scalable, modular I/O and processing modules. Introduction VITA 39 added PCI-X capability to PMC modules. As perfor- The original PCI Mezzanine Card (PMC) standard emerged mance requirements continue to rise, traditional bus-based prod- about 10 years ago as an outgrowth of PCI Local Bus popularity. ucts will be supplanted by switched fabric architectures using With the wide availability of PCI silicon, PCI became the most open standards such as RapidIO, PCI Express, or Infiniband. The cost-effective way of implementing modular I/O, but the tradi- XMC standard supports migration of legacy PMC modules to tional PCI card did not suit the embedded marketʼs packaging or switched fabrics while maintaining backward compatibility with environmental requirements. The PMC standard repackaged the existing PMC modules and carriers. PCI electrical interface into a compact mechanical form factor, providing a low profile, rugged version of PCI that could facili- The XMC standards committee started with the PMC standard tate I/O expansion in VME and CompactPCI systems. -
Analysis and Optimisation of Communication Links for Signal Processing Applications
Analysis and Optimisation of Communication Links for Signal Processing Applications ANDREAS ÖDLING Examensarbete inom elektronik- och datorsystem, avancerad nivå, 30 hp Degree Project, in Electronic- and Computer Systems, second level School of Information and Communication Technology, ICT Royal Institute of Technology, KTH Supervisor: Johnny Öberg Examiner: Ingo Sander Stockholm, November 12, 2012 TRITA-ICT-EX-2012:287 Abstract There are lots of communication links and standards cur- rently being employed to build systems today. These meth- ods are in many way standardised, but far from everyone of them are. The trick is to select the communication method that best suit your needs. Also there is currently a trend that things have to be cheaper and have shorter time to market. That leads to more Component Off The Shelf (COTS) systems being build using commodity components. As one part of this work, Gigabit Ethernet is evaluated as a COTS-solution to building large, high-end systems. The computers used are running Windows and the pro- tocol used over Ethernet will be both TCP and UDP. In this work an attempt is also made to evaluate one of the non-standard protocols, the Link Port protocol for the TigerSHARC 20X-series, which is a narrow-bus, double- data-rate protocol, able to provide multi-gigabit-per-second performance. The studies have shown lots of interesting things, e.g. that using a standard desktop computer and network card, the theoretical throughput of TCP over Gigabit Ethernet can almost be met, reaching well over 900 Mbps. UDP performance gives on the other hand birth to a series of new questions about how to achieve good performance in a Windows environment, since it is constantly outperformed by the TCP connections. -
ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22
ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22 ISO/IEC JTC 1/SC 25 INTERCONNECTION OF INFORMATION TECHNOLOGY EQUIPMENT Secretariat: Germany (DIN) DOC TYPE: Administrative TITLE: Status of projects of SC25/WG 4, Chitose, Japan, 2004-06-22/24. SOURCE: ISO/IEC JTC 1/SC 25/WG 4 Convener PROJECT: All projects of SC 25/WG 4 STATUS: Agenda ACTION ID: FYI DUE DATE: n/a REQUESTED: For information ACTION MEDIUM: Open DISTRIBUTION: ITTF, JTC 1 Secretariat P-, L-, O-Members of SC 25 No of Pages: 08 (including cover) Page 1 of 8 Status of projects of WG 4, Chitose, Japan, 2004-06-22/24 6 Project 1.25.13.01.XX - Channel Interface Specifications: Fibre Distributed Data Interface (FDDI) 6.1. Project 1.25.13.01.03 - FDDI - Part 1: Physical Layer Protocol (PHY) [ISO 9314-1:1989] no action required 6.2. Project 1.25.13.01.04 - FDDI - Part 2: Media Access Control (MAC) [ISO 9314-2:1989] - - no action required 6.3. Project 1.25.13.01.05 - FDDI - Part 3: Physical Layer Medium Dependent (PMD) [ISO/IEC 9314-3:1990] no action required 6.4. Project 1.25.13.01.06 - FDDI - Part 4: Single-Mode Fibre Physical Layer Medium Dependent (SMF-PMD) [ISO/IEC 9314-4:1999] -- no action required 6.5. Project 1.25.13.01.07 - FDDI - Part 5: Hybrid Ring Control (HRC) [ISO/IEC 9314- 5:1995] no action required 6.6. Project 1.25.13.01.08 - FDDI - Part 6: Station Management (SMT) [ISO/IEC 9314- 6:1998] no action required 6.7. -
Serial Rapidio (SRIO)
TMS320C6472/TMS320TCI648x DSP Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13J October 2006–Revised February 2011 2 SPRUE13J–October 2006–Revised February 2011 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Preface ...................................................................................................................................... 15 1 Overview .......................................................................................................................... 16 1.1 General RapidIO System ............................................................................................. 16 1.2 RapidIO Feature Support in SRIO ................................................................................... 19 1.3 Standards ............................................................................................................... 20 1.4 External Devices Requirements ..................................................................................... 20 1.5 TI Devices Supported By This Document .......................................................................... 20 2 SRIO Functional Description ............................................................................................... 21 2.1 Overview ................................................................................................................ 21 2.2 SRIO Pins ............................................................................................................... 26 2.3 Functional Operation -
VXS, a High Speed Cu Switch Fabric Interconnect for VME
VXS, A High Speed Cu Switch Fabric Interconnect for VME Henry Wong Motorola [email protected] James Lee Fedder Tyco Electronics [email protected] James L Thompson Crane Division, Naval Surface [email protected] VME Renaissance • VME is a +20 year old technology. • VME Renaissance is an intense period of intellectual activity and technology infusion surrounding VMEbus • Many innovations, including but not limited to – Faster 2eSST parallel bus – Multi-gigabit switched serial interconnects – PCI-X chip to chip interconnect – PCI-X mezzanines – Point to point intra-connects – Point-to-point mezzanines 2 VMEbus Technology Roadmap Serial Data Parallel Serial NextNext Gen Gen Parallel Switched Fabric Plane SwitchedSwitched Switched Fabric Inter- • Ethernet, Fibre Ch • Raceway™ • Infiniband™ • HA fabric Connect • SKYchannel • Serial RapidIO™ • Mesh • 3GIO, etc. etc. etc. • Optical VME64 2eSST/PCI-X 2eSST/P2P Control VME64 2eSST/PCI-X 2eSST/P2P NextNext Gen Gen Plane VMEbusVMEbus VMEbusVMEbus VMEbusVMEbus VMEbusVMEbus Inter- • Universe II from Tundra • 8X speed improvement • 2eSST VME side Connect • Other proprietary chips • Backwards compatible • P-P Host side connect • QDR Technology • VXS – VMEbus Switched• VITA 1.5 Serial • Adds multi-gigabit per second Point-to-Point PMC PMCX Point-to-Point NextNext Gen Gen Mezzanine PMC PMCX Mezzanine switched serial links to VME Mezzanine MezzanineMezzanine Inter- Connect • Via• PCI a Mezzanine new CardsP0 connector• PCI-X Mezzanine Cards • P/S RapidIO™ • PMC & PrPMC • PMCX & PrPMCX • 3GIO • Hot plug • Dual• 64b/66MHz star based configuration• 64b/133MHz uses based one • Hypertransport • Front Access • VITA 39 • Infiniband™, etc. etc. or two switch cards Chip • MultiplePCI link technologies PointPoint-to-to-Point-Point to PCI PCIPCI-X-X Chip Connect Chip supported by structured Chip Connect Inter- • 64b/66MHz • 64b/133MHz • P/S RapidIO™ specification• Proprietary connects also • 3GIO Connect • Hypertransport • Additional power brought onto • etc. -
Serial Multiprotocol Transmission with the Latticesc FPGA
SERIAL MULTI-PROTOCOL TRANSMISSION WITH THE LatticeSC FPGA A Lattice Semiconductor White Paper February 2006 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 Serial Multi-Protocol Transmission with the LatticeSC FPGA A Lattice Semiconductor White Paper Introduction The movement towards serial chip to chip and backplane interconnects continues at a frantic pace, particularly in the communications and storage arena. Standardization forums such as the OIF, RapidIO TA, PCI-SIG, OBSAI and CPRI have solidified their work and various packet-based protocols are in the process of being adopted by system and chip vendors. In addition to these emerging protocols, there is also a broad installed base of more mature serial-based protocols such as GbE, 10G Ethernet, SONET and Fibre Channel that must be addressed as they undergo a facelift to accommodate the multi-protocol nature of the network. As the PHY and protocol layers of these new standards are being established and work continues to upgrade existing technology in the field, system vendors now have to decide how best to transmit these various protocols over existing transmission infrastructures, both inter- and intra-board. Although each protocol is unique, one thing that they all have in common is a layered protocol stack. However, all protocol stacks are not created equal: their implementation can vary greatly from one layer to the next. Typically, the physical layer consists of fixed functionality that is common to multiple packet-based protocols, while the upper layers tend to be more customizable. The dynamic of upper layer functionality is necessitated by both the natural evolution that takes place when dealing with an emerging standard as well as the desire of system vendors to create their own “value add” via proprietary functionality.