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SIMD Extensions
SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel. -
Performance of a Computer (Chapter 4) Vishwani D
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Performance of a Computer (Chapter 4) Vishwani D. Agrawal & Victor P. Nelson epartment of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 1 What is Performance? Response time: the time between the start and completion of a task. Throughput: the total amount of work done in a given time. Some performance measures: MIPS (million instructions per second). MFLOPS (million floating point operations per second), also GFLOPS, TFLOPS (1012), etc. SPEC (System Performance Evaluation Corporation) benchmarks. LINPACK benchmarks, floating point computing, used for supercomputers. Synthetic benchmarks. ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 2 Small and Large Numbers Small Large 10-3 milli m 103 kilo k 10-6 micro μ 106 mega M 10-9 nano n 109 giga G 10-12 pico p 1012 tera T 10-15 femto f 1015 peta P 10-18 atto 1018 exa 10-21 zepto 1021 zetta 10-24 yocto 1024 yotta ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 3 Computer Memory Size Number bits bytes 210 1,024 K Kb KB 220 1,048,576 M Mb MB 230 1,073,741,824 G Gb GB 240 1,099,511,627,776 T Tb TB ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 4 Units for Measuring Performance Time in seconds (s), microseconds (μs), nanoseconds (ns), or picoseconds (ps). Clock cycle Period of the hardware clock Example: one clock cycle means 1 nanosecond for a 1GHz clock frequency (or 1GHz clock rate) CPU time = (CPU clock cycles)/(clock rate) Cycles per instruction (CPI): average number of clock cycles used to execute a computer instruction. -
How Microprocessors Work E 1 of 64 ZM
How Microprocessors Work e 1 of 64 ZM How Microprocessors Work ZAHIDMEHBOOB +923215020706 [email protected] 2003 BS(IT) PRESTION UNIVERSITY How Microprocessors Work The computer you are using to read this page uses a microprocessor to do its work. The microprocessor is the heart of any normal computer, whether it is a desktop machine, a server or a laptop. The microprocessor you are using might be a Pentium, a K6, a PowerPC, a Sparc or any of the many other brands and types of microprocessors, but they all do approximately the same thing in approximately the same way. If you have ever wondered what the microprocessor in your computer is doing, or if you have ever wondered about the differences between types of microprocessors, then read on. Microprocessor History A microprocessor -- also known as a CPU or central processing unit -- is a complete computation engine that is fabricated on a single chip. The first microprocessor was the Intel [email protected] +923215020706 (2003) How Microprocessors Work e 2 of 64 ZM 4004, introduced in 1971. The 4004 was not very powerful -- all it could do was add and subtract, and it could only do that 4 bits at a time. But it was amazing that everything was on one chip. Prior to the 4004, engineers built computers either from collections of chips or from discrete components (transistors wired one at a time). The 4004 powered one of the first portable electronic calculators. The first microprocessor to make it into a home computer was the Intel 8080, a complete 8- bit computer on one chip, introduced in 1974. -
MICROPROCESSOR REPORT the INSIDERS’ GUIDE to MICROPROCESSOR HARDWARE Slot Vs
VOLUME 12, NUMBER 1 JANUARY 26, 1998 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Slot vs. Socket Battle Heats Up Intel Prepares for Transition as Competitors Boost Socket 7 A A look Look by Michael Slater ship as many parts as they hoped, especially at the highest backBack clock speeds where profits are much greater. The past year has brought a great deal The shift to 0.25-micron technology will be central to of change to the x86 microprocessor 1998’s CPU developments. Intel began shipping 0.25-micron A market, with Intel, AMD, and Cyrix processors in 3Q97; AMD followed late in 1997, IDT plans to LookA look replacing virtually their entire product join in by mid-98, and Cyrix expects to catch up in 3Q98. Ahead ahead lines with new devices. But despite high The more advanced process technology will cut power con- hopes, AMD and Cyrix struggled in vain for profits. The sumption, allowing sixth-generation CPUs to be used in financial contrast is stark: in 1997, Intel earned a record notebook systems. The smaller die sizes will enable higher $6.9 billion in net profit, while AMD lost $21 million for the production volumes and make it possible to integrate an L2 year and Cyrix lost $6 million in the six months before it was cache on the CPU chip. acquired by National. New entrant IDT added another com- The processors from Intel’s challengers have lagged in petitor to the mix but hasn’t shipped enough products to floating-point and MMX performance, which the vendors become a significant force. -
World's First High- Performance X86 With
World’s First High- Performance x86 with Integrated AI Coprocessor Linley Spring Processor Conference 2020 April 8, 2020 G Glenn Henry Dr. Parviz Palangpour Chief AI Architect AI Software Deep Dive into Centaur’s New x86 AI Coprocessor (Ncore) • Background • Motivations • Constraints • Architecture • Software • Benchmarks • Conclusion Demonstrated Working Silicon For Video-Analytics Edge Server Nov, 2019 ©2020 Centaur Technology. All Rights Reserved Centaur Technology Background • 25-year-old startup in Austin, owned by Via Technologies • We design, from scratch, low-cost x86 processors • Everything to produce a custom x86 SoC with ~100 people • Architecture, logic design and microcode • Design, verification, and layout • Physical build, fab interface, and tape-out • Shipped by IBM, HP, Dell, Samsung, Lenovo… ©2020 Centaur Technology. All Rights Reserved Genesis of the AI Coprocessor (Ncore) • Centaur was developing SoC (CHA) with new x86 cores • Targeted at edge/cloud server market (high-end x86 features) • Huge inference markets beyond hyperscale cloud, IOT and mobile • Video analytics, edge computing, on-premise servers • However, x86 isn’t efficient at inference • High-performance inference requires external accelerator • CHA has 44x PCIe to support GPUs, etc. • But adds cost, power, another point of failure, etc. ©2020 Centaur Technology. All Rights Reserved Why not integrate a coprocessor? • Very low cost • Many components already on SoC (“free” to Ncore) Caches, memory, clock, power, package, pins, busses, etc. • There often is “free” space on complex SOCs due to I/O & pins • Having many high-performance x86 cores allows flexibility • The x86 cores can do some of the work, in parallel • Didn’t have to implement all strange/new functions • Allows fast prototyping of new things • For customer: nothing extra to buy ©2020 Centaur Technology. -
MPR Article Template
CENTAUR ADDS AI TO SERVER PROCESSOR First x86 SoC to Integrate Deep-Learning Accelerator By Linley Gwennap (December 2, 2019) ................................................................................................................... Centaur is galloping back into the x86 market with Centaur Technology has designed x86 CPUs and pro- an innovative processor design that combines eight high- cessors for Via for more than 20 years, but we’ve heard little performance CPUs with a custom deep-learning accelerator from the Texan design shop since the debut of the dual-core (DLA). The company is the first to announce a server- Nano X2, which was built in a leading-edge 40nm process processor design that integrates a DLA. The new accelerator, (see MPR 1/24/11, “Via Doubles Down at CES”). Henry, called Ncore, delivers better neural-network performance who managed the company since its inception, recently than even the most powerful Xeon, but without incurring handed the reins to new president Al Loper, another long- the high cost of an external GPU card. The Via Technologies time Centaurian. Henry, boasting 50 years of CPU-design subsidiary began testing the silicon in September; we esti- experience, continues as the company’s AI architect. mate the first products based on this design could enter pro- duction in 2H20, although Via has disclosed no product One Tractor Pulling 4,096 Trailers plans. When designing the Ncore accelerator, Centaur was con- Ncore, which operates as a coprocessor, avoids the cerned that the rapid pace of neural-network evolution vogue MAC array, instead relying on a more traditional pro- grammable SIMD engine. But Centaur took the multiple in 4x DDR4 To other CHA SIMD to the extreme, designing a unit that processes 4,096 bytes in parallel to achieve peak performance of 20 trillion operations per second (TOPS) for 8-bit integers (INT8). -
Evolution Des X86befehlssatzes Und Seiner Erweiterungen
Technische Universität Dresden Evolution des x86-Befehlssatzes und seiner Erweiterungen Peter Ebert Dresden, 15.07.2009 Einführung · Überblick & Historie · Konkurrierende Befehlssatzarchitekture n · Befehlsarten · Registerstruktur · x87 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 2/24 Übersicht & Historie · IBM 1981: erster PC · x86-Architektur verwendet einen CISC-Befehlssatz · alle Prozessoren seit dem Pentium Pro sind aber hybride CISC/RISC-Prozessoren 1978 1. Gen.: 8086 1982 2. Gen.: 80286 1985 3. Gen.: 80386 IA-32 1989 4. Gen.: 80486 1993 5. Gen.: Pentium MMX 1995 6. Gen.: P2, P3 3DNow!, SSE 1999 7. Gen.: Athlon (XP), P4 SSE2 2003 8. Gen.: Opteron x86-64 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 3/24 Konkurrierende Befehlssatzarchitekturen · ARM (Acorn Risc Machine) RISC-Architektur 1983 vom englischen Computerhersteller Acorn. Einsatz vor allem im eingebetteten Bereich z.B.: Mobiltelefonen, PDAs, Routern, iPod, iPhone, Internet Tablets von Nokia und den neueren PDAs von ASUS, Konsolen wie der Nintendo DS, der GP2X und die Pandora. · PowerPC (Performance optimization with enhanced RISC Performance Chip) 1991 durch ein Konsortium aus Apple, IBM und Motorola. z.B.: Nintendo GameCube und Wii, Xbox 360 von Microsoft, Playstation 3 von Sony und in vielen eingebetteten Systemen. Auch benutzen PKW und Produkte in der Luft- und Raumfahrt · SPARC (Scalable Processor ARChitecture) Von Sun Microsystems entwickelt ab 1985 und vermarktete ab 1987, offene Architektur, 1995 64-Bit-Erweiterung (UltraSparc) 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 4/24 Befehlsarten · Transferbefehlen werden Daten innerhalb des Systems bewegt. Die Daten werden dabei nur kopiert, d. h. bleiben an ihrem Quellort unverändert. -
6IF Ver. 1.X MANUAL
5SMT / 5SMTS SiS 530 ALL-IN-ONE AT MAINBOARD OPERATION MANUAL DOC NO. UM-SMT-E4 …………………………………………………………………………………………………………… PRINTED IN TAIWAN SiS530 AT MAINBOARD TABLE OF CONTENTS CHAPTER & SECTION PAGE 1. INTRODUCTION ................................................................................... 1-1 1.1 SYSTEM OVERVIEW ...................................................................................1-1 1.2 SYSTEM BOARD LAYOUT .........................................................................1-2 2. FEATURES .............................................................................................. 2-1 2.1 2.1 MAINBOARD SPECIFICATIONS ........................................................2-1 3. HARDWARE SETUP ............................................................................. 3-1 3.1 UNPACKING...................................................................................................3-1 3.2 HARDWARE CONFIGURATION...............................................................3-2 3.2.1 CONNECTORS...................................................................................3-2 3.2.2 JUMPERS ............................................................................................3-17 3.2.3 QUICK INSTALLATION OF POPULAR CPU..............................3-23 3.2.4 INSTALLATION OF DEVICE DRIVER ........................................3-26 4. AWARD BIOS SETUP ........................................................................... 4-1 4.1 GETTING STARTED.....................................................................................4-1 -
IDT Winchip 2A Data Sheet
Preliminary Information PROCESSOR Version A Data Sheet Preliminary Information January 1999 IDT WINCHIP 2ATM PROCESSOR DATA SHEET This is Version 1.0 of the IDT WinChip 2 version A Processor data sheet. The latest versions of this data sheet may be obtained from www.winchip.com © 1999 Integrated Device Technology, Inc. All Rights Reserved Integrated Device Technology, Inc. (IDT) reserves the right to make changes in its products without notice in order to improve design or performance characteristics. This publication neither states nor implies any representations or warranties of any kind, including but not limited to any implied warranty of merchantability or fitness for a particular purpose. No license, express or implied, to any intellectual property rights is granted by this document. IDT makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. IDT disclaims responsibility for any consequences resulting from the use of the information included herein. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as components in life support or other medical devices or systems (hereinafter life support devices) unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. -
Table of Contents
Table Of Contents TABLE OF CONTENTS 1. INTRODUCTION 1.1. PREFACE ................................................................................. 1-1 1.2. KEY FEATURES ....................................................................... 1-1 1.3. PERFORMANCE LIST .............................................................. 1-3 1.4. BLOCK DIAGRAM..................................................................... 1-4 1.5. INTRODUCE THE PCI - BUS .................................................... 1-5 1.6. FEATURES ............................................................................... 1-5 1.7. What is AGP ............................................................................. 1-6 2. SPECIFICATION 2.1. HARDWARE ............................................................................. 2-1 2.2. SOFTWARE.............................................................................. 2-2 2.3. ENVIRONMENT ........................................................................ 2-2 3. HARDWARE INSTALLATION 3.1. UNPACKING............................................................................. 3-1 3.2. MAINBOARD LAYOUT.............................................................. 3-2 3.3. QUICK REFERENCE FOR JUMPERS & CONNECTORS .......... 3-3 3.4. SRAM INSTALLATION DRAM INSTALLATION.......................... 3-5 3.5. DRAM INSTALLATION.............................................................. 3-5 3.6. CPU INSTALLATION AND JUMPERS SETUP........................... 3-5 3.7. CMOS RTC & ISA CFG CMOS SRAM...................................... -
AMD's Early Processor Lines, up to the Hammer Family (Families K8
AMD’s early processor lines, up to the Hammer Family (Families K8 - K10.5h) Dezső Sima October 2018 (Ver. 1.1) Sima Dezső, 2018 AMD’s early processor lines, up to the Hammer Family (Families K8 - K10.5h) • 1. Introduction to AMD’s processor families • 2. AMD’s 32-bit x86 families • 3. Migration of 32-bit ISAs and microarchitectures to 64-bit • 4. Overview of AMD’s K8 – K10.5 (Hammer-based) families • 5. The K8 (Hammer) family • 6. The K10 Barcelona family • 7. The K10.5 Shanghai family • 8. The K10.5 Istambul family • 9. The K10.5-based Magny-Course/Lisbon family • 10. References 1. Introduction to AMD’s processor families 1. Introduction to AMD’s processor families (1) 1. Introduction to AMD’s processor families AMD’s early x86 processor history [1] AMD’s own processors Second sourced processors 1. Introduction to AMD’s processor families (2) Evolution of AMD’s early processors [2] 1. Introduction to AMD’s processor families (3) Historical remarks 1) Beyond x86 processors AMD also designed and marketed two embedded processor families; • the 2900 family of bipolar, 4-bit slice microprocessors (1975-?) used in a number of processors, such as particular DEC 11 family models, and • the 29000 family (29K family) of CMOS, 32-bit embedded microcontrollers (1987-95). In late 1995 AMD cancelled their 29K family development and transferred the related design team to the firm’s K5 effort, in order to focus on x86 processors [3]. 2) Initially, AMD designed the Am386/486 processors that were clones of Intel’s processors. -
SMBIOS Specification
1 2 Document Identifier: DSP0134 3 Date: 2019-10-31 4 Version: 3.4.0a 5 System Management BIOS (SMBIOS) Reference 6 Specification Information for Work-in-Progress version: IMPORTANT: This document is not a standard. It does not necessarily reflect the views of the DMTF or its members. Because this document is a Work in Progress, this document may still change, perhaps profoundly and without notice. This document is available for public review and comment until superseded. Provide any comments through the DMTF Feedback Portal: http://www.dmtf.org/standards/feedback 7 Supersedes: 3.3.0 8 Document Class: Normative 9 Document Status: Work in Progress 10 Document Language: en-US 11 System Management BIOS (SMBIOS) Reference Specification DSP0134 12 Copyright Notice 13 Copyright © 2000, 2002, 2004–2019 DMTF. All rights reserved. 14 DMTF is a not-for-profit association of industry members dedicated to promoting enterprise and systems 15 management and interoperability. Members and non-members may reproduce DMTF specifications and 16 documents, provided that correct attribution is given. As DMTF specifications may be revised from time to 17 time, the particular version and release date should always be noted. 18 Implementation of certain elements of this standard or proposed standard may be subject to third party 19 patent rights, including provisional patent rights (herein "patent rights"). DMTF makes no representations 20 to users of the standard as to the existence of such rights, and is not responsible to recognize, disclose, 21 or identify any or all such third party patent right, owners or claimants, nor for any incomplete or 22 inaccurate identification or disclosure of such rights, owners or claimants.