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Automated Synthesis and Optimization of Multilevel Logic Circuits

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Automated Synthesis and Optimization of Multilevel Logic Circuits Automated Synthesis and Optimization of Multilevel Logic Circuits by Lingli Wang © Copyright by Lingli Wang 2000 A thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy Napier University School of Engineering 2000 Declaration I declare that no portion of the work referred to in this thesis has been submitted in support of an application of another degree, qualification or other academic awards of this or any other university or institution of learning. Lingli Wang 11 Acknow ledgements I am deeply indebted to my research supervisor, Professor A. E. A. Almaini, School of Engineering, Napier University, for his constant guidance, encouragement, friendship, and interest to all that I did during this research. I am grateful to Professor Almaini for taking his precious time to provide regular comments and invaluable suggestions. Many ideas of this thesis were produced during our weekly meetings. He also taught me patiently the proper style of scientific writing in English and corrected my research papers and this thesis. I would like to thank Mr Alex Bystrov, a former member of the digital techniques group, for his essential support to help me learn Linux operating system and GNU C language programming environment when I started this research. Thanks are due to other members of the digital techniques group, especially Mr Yinshui Xia and Mr Belgasem Ali, for their enjoyable working environment and various discussions. I would like to thank our technician, Mr Jay Hoy for his kindly support to install Linux operating system. This project was funded by the School of Engineering (formerly the Department of Electrical, Electronic and Computing Engineering), Napier University, Edinburgh. This support is gratefully acknowledged. Finally, I would like to thank my wife, Xiaowen Zhong, for her everlasting love, under­ standing and patience throughout my research work. III Contents List of Abbreviations vi List of Figures IX List of Tables Xl Abstract xii 1 Introduction 1 1.1 A historic perspective of logic design . 1 1.2 VLSI chip design methodology based on logic synthesis . 4 1.3 Two-Level versus multilevel logic synthesis ..... 7 1.4 Reed-Muller logic based on AND /XOR operations 8 1.5 Structure of this thesis . 10 2 Conventional Multilevel Logic Synthesis 12 2.1 Algorithmic approach 12 2.2 Rule-Based approach 15 2.3 BDD approach . 16 2.4 FPGA approach 18 2.5 Several other approaches based on perturbation 20 3 Multilevel Logic Minimization Using Functional Don't Cares 22 3.1 Introduction ............. 22 3.2 Multilevel Karnaugh map technique 23 3.3 Multilevel logic synthesis for large Boolean functions 29 3.4 Experimental results 38 3.5 Summary ... 40 4 Multilevel Minimization for Multiple Output Logic Functions 41 4.1 Introduction............. 41 4.2 Review of Functional Don't Cares. 41 4.3 Simplification for single output functions 44 4.4 Multilevel minimization for multiple output functions. 46 IV 4.5 Experimental results 49 4.6 Summary . 50 5 Polarity Conversion for Single Output Boolean Functions 51 5.1 Introduction ........... 51 5.2 Basic definitions and terminology 51 5.3 Conversion of the coefficients with zero polarity 53 5.4 Conversion of the coefficients with a fixed polarity 56 5.5 Conversion algorithm for large Boolean functions 61 5.6 Algorithm and experimental results. 65 5.7 Summary .............. 70 6 Conversion Algorithm for Very Large Multiple Output Functions 71 6.1 Introduction. 71 6.2 Algorithm.. 74 6.3 Experimental Results. 76 6.4 Summary ...... 77 7 Exact Minimization of Fixed Polarity Reed-Muller Expressions 78 7.1 Introduction. 78 7.2 Background . 79 7.3 Properties of the polarities for SOP and FPRM expressions 83 7.4 Best polarity for single output functions .. 93 7.5 Best polarity for multiple output functions. 95 7.6 Experimental results 98 7.7 Summary ..... 99 8 Optimization of Reed-Muller PLA Implementations 101 8.1 Introduction ............. 101 8.2 Review of the decomposition method 103 8.3 Improved decomposition method for large single output functions 106 8.4 Generalization to multiple output functions 116 8.5 Experimental results 122 8.6 Summary ..... 123 9 Conclusions and Future Work 125 Publications 128 References and Bibliography 129 Disk Containing the Software 141 v List of Abbreviations ASIC Application Specific Integrated Circuit ATPG Automatic Test Pattern Generation BDD Binary Decision Diagram BDP Binary Decision Program BLIF Berkeley Logic Interchange Format CAD Computer Aided Design CLB Configurable Logic Block CNF Conjunction Normal Form CMOS Complementary Metal-Oxide-Semiconductor CPU Central Process Unit DAG Directed Acyclic Graph DC Don't Care DD Decision Diagram DNF Disjoint Normal Form EDA Electronic Design Automation EDIF Electronic Design Interchange Format ESOP Exclusive Sum-Of-Products EXOR(XOR) EXclusive OR operation FDD Functional Decision Diagram FPGA Field Programmable Gate Array FPLA Field Programmable Logic Array FPRM Fixed Polarity Reed-Muller GA Genetic Algorithm VI List of Abbreviations GCC GNU Compiler Collection GDB GNU DeBugger HDL Hardware Description Language IC Integrated Circuit IWLS International Workshop on Logic Synthesis KISS Keep Internal State Simple LSB Least Significant Bit LUT Look-Up Table MCNC Microelectronics Center North Carolina MIS Multilevel logic optimization system developed at Berkeley MPGA Mask Programmable Gate Array MSB Most Significant Bit MUX Multiplexer NP Nondeterministic Polynomial, Non-Polynomial NRE N on-Recurring Engineering OBDD Ordered Boolean Decision Diagram ODC Observability Don't Care OFDD Ordered Functional Decision Diagram OVAG Output Value Array Graph P &R Placement & Routing PLA Programmable Logic Array PLD Programmable Logic Device PROM Programmable Read-Only Memory PPRM Positive Polarity Reed-Muller RMPLA Reed-Muller Programmable Logic Array ROBDD Reduced Ordered Binary Decision Diagram Vll List of Abbreviations RTL Register and Transfer Level SCRL Split-level Charge Recovery Logic SDC Satisfiability Don't Care SIS Sequential Interactive System SLIF Stanford Logic Interchange Format SOC System-On-Chip SOP Sum-Of-Products SRAM Static Random Access Memory VHDL Very large scale Hardware Description Language VLSI Very Large Scale Integration XNF Xilinx Net-list Format Vlll List of Figures 1.1 Classical symbols for contacts 2 1.2 Moore's law the growth of Intel microprocessors 3 1.3 Historic perspective of logic design 4 1.4 A VLSI design model. 5 1.5 An ASIC chip design flow ..... 6 1.6 Comparison between two-level and multilevel structures 8 1. 7 Structure of this thesis . 11 2.1 DAG representation of a combinational Boolean network 13 2.2 A circuit pattern and its replacement ......... 15 2.3 BDD representation of the Boolean function in example 2.1 17 2.4 Logic circuit from fig.2.3(b) ........... 18 2.5 Typical FPGA architecture ........... 19 2.6 Different partitions for the same Boolean network 20 3.1 Comparison between two-level and multilevel K-map methods 26 3.2 Multilevel K-map method for an incompletely specified function. 29 3.3 Two examples for definition 3.3 30 3.4 Examples of theorem 3.3 ... 33 3.5 An example of procedure 3.2 38 4.1 Explanation of the functional DCs 43 4.2 Example of functional DCs 44 4.3 Results of ryy6 with 16 inputs. 46 4.4 Simplification of Boolean relation 48 5.1 Bidirectional conversion between SOP and FPRM forms 60 5.2 Conversion algorithm using multiple segment technique. 65 5.3 Bidirectional conversion algorithm for large Boolean functions 67 5.4 CPU Time versus the number of on-set coefficients for conversion 69 5.5 CPU time for parity function conversions 70 IX List of Figures 6.1 Functional decision diagrams for f = X2 EB XIXO EB X3X2XIXO 73 6.2 An example for algorithm 6.1 .............. 75 7.1 Example for a 3-variable 2-output Reed-Muller function 98 8.1 Limitation of i-majority m-cubes 104 8.2 Structures of Reed-Muller PLAs 104 8.3 Example of procedure 8.1 108 8.4 Order of ~-majority cubes .... 110 8.5 Example of procedure 8.2 112 8.6 Boolean function of example 8.4 113 8.7 Example for procedure 8.3 115 8.8 Example for procedure 8.4 117 x List of Tables 1.1 Some commercial design synthesis tools 5 2.1 Brief comparison of FPGA programming techniques 19 3.1 Comparison for single output functions run on the same PC . .. 39 4.1 Literal numbers with different encodings for table5 49 4.2 Results for multiple output functions . 49 5.1 Truth table of the criterion function gj 55 5.2 Example of multiple segment technique 64 5.3 Conversion results of some random coefficient sets . 68 5.4 Test results for conversion of parity functions 69 6.1 Distribution of dependent variables . 74 6.2 Experimental results of very large functions from IWLS'93 benchmark 76 7.1 Test results for small Boolean functions 100 7.2 Test results for large Boolean functions . 100 8.1 Comparison with ESPRESSO for general multiple output functions . 123 8.2 Comparison with ESPRESSO for very large multiple output functions 123 Xl Abstract With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multi­ level logic synthesis plays an even more important role due to its flexibility and compact­ ness. The history of symbolic logic and some typical techniques for multilevel logic synthesis are reviewed. These methods include algorithmic approach; Rule-Based approach; Binary Decision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approach and several perturbation applications. One new kind of don't cares (DCs), called functional DCs has been proposed for multi­ level logic synthesis. The conventional two-level cubes are generalized to multilevel cubes. Then functional DCs are generated based on the properties of containment.
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