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Testing and Logic Optimization Techniques for Systems on Chip Linköping Studies in Science and Technology Dissertations. No. 1490 Testing and Logic Optimization Techniques for Systems on Chip by Tomas Bengtsson Department of Computer and Information Science Linköpings universitet SE-581 83 Linköping, Sweden Linköping 2012 Copyright © 2012 Tomas Bengtsson ISBN 978917519-7425 ISSN 03457524 Printed by LiU-Tryck 2012 URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-84806 Abstract Today it is possible to integrate more than one billion transistors onto a single chip. This has enabled implementation of complex functionality in hand held gadgets, but handling such complexity is far from trivial. The challenges of handling this complexity are mostly related to the design and testing of the digital components of these chips. A number of well-researched disciplines must be employed in the efficient design of large and complex chips. These include utilization of several abstraction levels, design of appropriate architectures, several different classes of optimization methods, and development of testing techniques. This thesis contributes mainly to the areas of design optimization and testing methods. In the area of testing this thesis contributes methods for testing of on-chip links connecting different clock domains. This includes testing for defects that introduce unacceptable delay, lead to excessive crosstalk and cause glitches, which can produce errors. We show how pure digital components can be used to detect such defects and how the tests can be scheduled efficiently. To manage increasing test complexity, another contribution proposes to raise the abstraction level of fault models from logic level to system level. A set of system level fault models for a NoC-switch is proposed and evaluated to demonstrate their potential. In the area of design optimization, this thesis focuses primarily on logic optimization. Two contributions for Boolean decomposition are presented. The first one is a fast heuristic algorithm that finds non- disjoint decompositions for Boolean functions. This algorithm operates on a Binary Decision Diagram. The other contribution is a I fast algorithm for detecting whether a function is likely to benefit from optimization for architectures with a gate depth of three with an XOR-gate as the third gate. II Populärvetenskaplig sammanfattning Idag är det möjligt att integrera mer än en miljard transistorer på ett enda mikrochip. Utvecklingen av mikrochips har gjort det möjligt att implementera mycket komplexa och avancerade funktioner i små handhållna apparater. Så kallade smartphones är ett typiskt exempel. Att hantera komplexiteten i mikrochip av den här storleken är långt ifrån trivialt, i synnerhet när det gäller de digitala delarna. Resultaten från flera olika forskningsområden utnyttjas i samverkan för att på ett effektivt sätt konstruera stora komplexa mikrochip. Sådana forskningsområden behandlar hur man utnyttjar flera abstraktionsnivåer, hur man utformar bra arkitekturer, hur man optimerar konstruktioner och hur man testar de färdiga mikrochipen. Bidragen som presenteras i den här avhandlingen fokuserar dels på hur man optimerar konstruktioner dels på hur man testar de färdiga mikrochipen. Man kan ha olika klockdomäner i olika delar av ett mikrochip för att slippa distribuera en och samma klocksignal över hela mikrochipet. När det gäller test av mikrochip bidrar denna avhandling med metoder för att testa kommunikationslänkar som går mellan delar av chipet som har olika klocksignaler. Bidragen inkluderar tester för defekter som kan orsaka fel genom oacceptabel fördröjning, genom för mycket överhörning eller genom spikar. Logisk nivå är den abstraktionsnivå där en konstruktion representeras med hjälp av grindar och vippor. Det är vanligtvis utifrån en sådan representation man i detalj bestämmer hur ett mikrochip skall testas och ofta lägger man in extra grindar och vippor III i chipet för teständamål. För att hantera testkomplexiteten har denna avhandling ett bidrag som föreslår att man lyfter abstraktionsnivån för testutveckling från den logiska nivån till systemnivån. Systemnivån är en representation som beskriver vad konstruktionen skall göra utan att ange några detaljer om implementeringen. För att påvisa potentialen för utveckling av test på systemnivån föreslås och utvärderas i denna avhandling hur man på systemnivå kan modellera fel för en NoC- switch. En NoC-switch är en specifik typ av komponent som finns i vissa mikrochip. När det gäller optimeringsmetoder har denna avhandling två bidrag som fokuserar på minimering av antalet grindar i en konstruktion. Det första bidraget är en algoritm för att bryta ut delfunktioner i ett Booleskt uttryck. Den algoritmen opererar på ett så kallat Binary Decision Diagram (BDD) som är en typ av riktad graf för att representera en Boolesk funktion. Det andra bidraget är en snabb algoritm för att göra en prognos över hur mycket en funktion kommer att tjäna på en arkitektur med ett grinddjup på tre där den tredje grinden utgörs av en XOR-grind med två ingångar. IV Acknowledgment There are many people who have supported and encouraged me during my Ph.D. studies and the work with writing this thesis. I would like to give a special thank to Professor Shashi Kumar, my supervisor at Jönköping University, for always taking time to help, support and encourage me in a good way. I would also like to give a special thank to Professor Zebo Peng, my supervisor at Linköping University, for great supervision and patient guidance throughout my Ph.D. studies. A special thank I would also like to give to Professor Elena Dubrova at Royal Institute of Technology Stockholm, for good supervision, discussions and encouragement during the work with logic optimization topic which formed the basis of my licentiate thesis. I would also like to give one more thank to Professor Shashi Kumar for very useful support, encouragement and supervision also during the work taking me to licentiate degree. I would give a thank to Professor Bengt Magnhagen as well who let me be accepted as a doctoral student at Jönköping University. I am very thankful to Dr. Artur Jutman and Professor Raimund Ubar at Tallinn Technical University too for very good research collaboration with the work on electronic testing as well as for their inspiration and for their willingness to share their knowledge and experience. I am also thankful to Dr. Andrés Martinelli for good collaboration with the work with logic optimization. I am also grateful to all other colleagues at Linköping University, Royal Institute of Technology and Tallinn Technical University who have contributed in one or another way to make this work possible. I am also grateful to all other colleagues at Jönköping University who have contributed by encouraging me, participating in technical V discussions, helping me to handle obstacles or have contributed in other ways for making this work possible. A special thank to Alf Johansson, Rickard Holsmark and Dr. Adam Lagerberg. I would also like to give a thank to Brittany Shahmehri for a great work with English language correction and improvement. Finally I would like to give a great thank to my parents Ann- Louise and Klas, my sister Åsa and my girlfriend Louise for all support, understanding and encouragement. Tomas Bengtsson November 2012 VI Contents Part A. Introduction and background 1 Introduction 3 1.1 Chip design, SoC and test development .......................... 3 1.2 Addressed problems and contributions............................ 5 1.3 Thesis outline................................................................. 11 2 Digital system design and testing 13 2.1 Digital system design..................................................... 14 2.2 Core based design and systems on chips ....................... 18 2.3 Logic optimization......................................................... 22 2.4 Defects and digital system testing.................................. 31 Part B. Chip testing 3 Background and related work in SoC testing 49 3.1 SoC testing and NoC testing.......................................... 49 3.2 On chip crosstalk induced fault testing.......................... 55 3.3 Test generation at high abstraction levels...................... 69 VII 4 Testing of crosstalk induced faults in on-chip interconnects 77 4.1 Method for testing of faults causing delay errors .......... 77 4.2 Method for scheduling wires as victims ........................ 94 4.3 Method for test of crosstalk-faults causing glitches .... 100 4.4 Conclusions ................................................................. 112 5 System level fault models 113 5.1 System level faults....................................................... 113 5.2 Evaluation of system level fault models...................... 117 5.3 Conclusions ................................................................. 130 Part C. Logic optimization 6 Background and related work in Boolean decomposition 133 6.1 Decomposition of Boolean functions .......................... 134 6.2 Decision diagram based decomposition methods........ 139 6.3 Decomposition for three-levels logic synthesis........... 151 6.4 Other applications of Boolean decomposition............. 154 7 A fast algorithm for finding bound-sets 159 7.1 Basic idea of Interval-cut algorithm ............................ 159 7.2 Interval-cut algorithm and formal proof of its functionality................................................................. 161 7.3 Implementation aspects and complexity analysis........ 165 7.4 Experimental results ...................................................
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