AN43 M.2 Pinout Descriptions and Reference Designs 1/14 Printed Versions of This Document Are Not Under Revision Control
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User's Guide PN: 961Ć047Ć081
6950 Enterprise Gateway Server USER’S GUIDE """""""""""""""""""""""""""" PN: 961-047-091 Revision D September 1999 " NOTICE The information contained herein is proprietary and is provided solely for the purpose of allowing customers to operate and service Intermec manufactured equipment and is not to be released, reproduced, or used for any other purpose without written permission of Intermec. Disclaimer of Warranties. The sample source code included in this document is presented for reference only. The code does not necessarily represent complete, tested programs. The code is provided AS IS WITH ALL FAULTS." ALL WARRANTIES ARE EXPRESSLY DISCLAIMED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. We welcome your comments concerning this publication. Although every effort has been made to keep it free of errors, some may occur. When reporting a specific problem, please describe it briefly and include the book title and part number, as well as the paragraph or figure number and the page number. Send your comments to: Intermec Technologies Corporation Publications Department 550 Second Street SE Cedar Rapids, IA 52401 INTERMEC and NORAND are registered trademarks and ENTERPRISE WIRELESS LAN, UAP, and UNIVERSAL ACCESS POINT are trademarks of Intermec Technologies Corporation. 1996 Intermec Technologies Corporation. All rights reserved. Acknowledgments AS/400 and IBM are registered trademarks of International Business Machines Corporation. DEC, VAX, and VT220 are registered trademarks of Digital Equipment Corporation. UNIX is a registered trademark of UNIX System Laboratories, Inc. B CAUTION: Intermec Technologies Corporation suggests you buy cables from us to connect with other devices. Our cables are safe, meet FCC rules, and suit our products. -
VX97 User's Manual ASUS CONTACT INFORMATION Asustek COMPUTER INC
R VX97 Pentium Motherboard USER'S MANUAL USER'S NOTICE No part of this manual, including the products and softwares described in it, may be repro- duced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means, except documentation kept by the purchaser for backup pur- poses, without the express written permission of ASUSTeK COMPUTER INC. (“ASUS”). ASUS PROVIDES THIS MANUAL “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY OR FITNESS FOR A PAR- TICULAR PURPOSE. IN NO EVENT SHALL ASUS, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDEN- TAL, OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF USE OR DATA, INTERRUPTION OF BUSI- NESS AND THE LIKE), EVEN IF ASUS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING FROM ANY DEFECT OR ERROR IN THIS MANUAL OR PRODUCT. Products and corporate names appearing in this manual may or may not be registered trade- marks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. • Intel, LANDesk, and Pentium are registered trademarks of Intel Corporation. • IBM and OS/2 are registered trademarks of International Business Machines. • Symbios is a registered trademark of Symbios Logic Corporation. • Windows and MS-DOS are registered trademarks of Microsoft Corporation. • Sound Blaster AWE32 and SB16 are trademarks of Creative Technology Ltd. • Adobe and Acrobat are registered trademarks of Adobe Systems Incorporated. -
COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous Multi-Threading and Multi-Core Processors Edgar Gabriel Spring 2011
COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous multi-threading and multi-core processors Edgar Gabriel Spring 2011 Edgar Gabriel Moore’s Law • Long-term trend on the number of transistor per integrated circuit • Number of transistors double every ~18 month Source: http://en.wikipedia.org/wki/Images:Moores_law.svg COSC 6385 – Computer Architecture Edgar Gabriel 1 What do we do with that many transistors? • Optimizing the execution of a single instruction stream through – Pipelining • Overlap the execution of multiple instructions • Example: all RISC architectures; Intel x86 underneath the hood – Out-of-order execution: • Allow instructions to overtake each other in accordance with code dependencies (RAW, WAW, WAR) • Example: all commercial processors (Intel, AMD, IBM, SUN) – Branch prediction and speculative execution: • Reduce the number of stall cycles due to unresolved branches • Example: (nearly) all commercial processors COSC 6385 – Computer Architecture Edgar Gabriel What do we do with that many transistors? (II) – Multi-issue processors: • Allow multiple instructions to start execution per clock cycle • Superscalar (Intel x86, AMD, …) vs. VLIW architectures – VLIW/EPIC architectures: • Allow compilers to indicate independent instructions per issue packet • Example: Intel Itanium series – Vector units: • Allow for the efficient expression and execution of vector operations • Example: SSE, SSE2, SSE3, SSE4 instructions COSC 6385 – Computer Architecture Edgar Gabriel 2 Limitations of optimizing a single instruction -
486/25/33 EISA System Board User's Manual
PREFACE Thank you for purchasing 486EI EISA/VESA system board. This document helps configure and install the system board. The document is prepared with our best knowledge; however, we make no representation or warranty concerning the contents or use of this manual, and specifically disclaim any expressly implied warranties or merchant ability or fitness of any particular purpose. The information in this document is subject to change without notice. This document contains information protected by copyright. All rights are reserved. No part of this document may be used or reproduced in any forms or by any means, or stored in a database or retrieval system, without prior written permission. TRADEMARKS IBM, PC, XT, and AT are trademarks of International Business Machines Corp. UNIX is a trademark of AT&T Bell Labs. DOS, OS/2 and XENIX are trademarks of Microsoft Corp. 8086, 80286, i386, i486 , i486DX, i486DX2, i486DX4, i486SX, and i487SX, Intel OverDrive Processor are trademarks of Intel Corp. TECHNICAL REFERENCE . I486 Microprocessor (Intel Order No: 240440-002) . I486 Microprocessor Programmer’s Reference Manual (Intel Order No. 240486-001) . SIS 85C411 EISA System Chipset Data Book . The EISA Specification published by: BCPR Services, Incorporated . The VESA VL Bus Specification published by: Video Electronics Standard Association 486EI EISA&VESA System Board User's Manual Page 1 TABLE OF CONTENTS PREFACE CHAPTER 1: INTRODUCTION PRODUCT OVERVIEW FEATURES CPU SUPPORT CACHE MEMORY SYSTEM MEMORY DRAM SYSTEM BIOS SHADOW RAM SYSTEM CHIPSET -
M4-4X4 / M4-4X4s / M4-4X2 / M4-4X2s / PCS42P
M4-4x4 / M4-4x4S / M4-4x2 / M4-4x2S / PCS42P CHARACTERISTICS This Personal Computer line is highly modular. The different models of this product line, in fact, are the result of the combination of two different board versions (ENTRY and ENHANCED), different CPUs (i486SX, i486SX2, i486DX2 and Intel DX4) and two different cases (TIN BOX and SLIM TIN BOX). The models of this product line are listed in the following table. 4 CASE MOTHER- PROCESSOR COMMERCIAL OLIVETTI BOARD NAME PROJECT NAME TIN BOX ENTRY i486SX @ 33 MHz MODULO M4-422 KPT44 S33 i486SX2 @ 50 MHz MODULO M4-432 KPT44 S50 i486DX2 @ 50 MHz MODULO M4-452 KPT44 D50 i486SX @ 25 MHz PCS42P SX/25 E XST41 S25 i486SX @ 33 MHz PCS42P SX/33 E XST41 S33 i486SX2 @ 50 MHz PCS42P S2/50 E XST41 S50 ENHANCED i486SX @ 33 MHz MODULO M4-424 KPT45 S33 i486SX2 @ 50 MHz MODULO M4-434 KPT45 S50 i486DX2 @ 50 MHz MODULO M4-454 KPT45 D50 i486DX2 @ 66 MHz MODULO M4-464 KPT45 D66 Intel DX4 @ 100 MHz MODULO M4-484 KPT45 DX4 i486DX2 @ 50 MHz PCS42P D2/50 E XST42 D250 i486DX2 @ 66 MHz PCS42P D2/66 E XST42 D266 SLIM TIN BOX ENTRY i486SX @ 33 MHz MODULO M4-422 S KPS44 S33 i486SX2 @ 50 MHz MODULO M4-432 S KPS44 S50 i486DX2 @ 50 MHz MODULO M4-452 S KPS44 D50 i486SX @ 25 MHz PCS42P SX/25 XSS41 S25 i486SX @ 33 MHz PCS42P SX/33 XSS41 S33 i486SX2 @ 50 MHz PCS42P S2/50 XSS41 S50 ENHANCED i486SX @ 33 MHz MODULO M4-424 S KPS45 S33 i486SX2 @ 50 MHz MODULO M4-434 S KPS45 S50 i486DX2 @ 50 MHz MODULO M4-454 S KPS45 D50 i486DX2 @ 66 MHz MODULO M4-464 S KPS45 D66 Intel DX4 @ 100 MHz MODULO M4-484 S KPS45 DX4 i486DX2 @ 50 MHz -
Of 2 18/02/2010
Page 1 of 2 Support Home Search Support & Downloads OverDrive ® Processors Product Reference Table Product Ordercode Pins Socket Voltage Upgrades Name Pentium® II UBPODP66X333 387 Socket 8 3.3V 150 and 180MHz Pentium Pro OverDrive® processor based-system to Processor 300MHz. 166 and 200MHz Pentium Pro processor based-system to 333MHz. Pentium® BOXPODPMT 321 Socket 7 3.3V 75 to 150, 90 to 180MHz Pentium OverDrive 66X200 processor-based systems with MMX Processor with tech. MMX™ Technology 100 with 66MHz bus/133/166MHz Pentium processor-based systems to 200MHz with MMX tech. Pentium® BOXPODPMT 320 Socket 5 3.3V 75 to 125, 90 to 150, 100(66MHz OverDrive 66X166 321 bus) and 133 to 166MHz Pentium Processor with Socket 7 processor-based systems with MMX MMX™ tech. Technology 100(50MHz bus) to 150MHz Pentium processor-based systems with MMX tech. Pentium® PODPMT60X150 320 Socket 5 3.3V 75 to 125, 90 to 150MHz Pentium OverDrive 321 processor-based systems with MMX Processor with Socket 7 tech. MMX™ Technology Pentium® PODPMT60X180 320 Socket 5 3.3V 75 to 150, 90/120 to 180MHz, 100 OverDrive 321 (50MHz bus) to 150 Pentium Processor with Socket 7 processor-based systems with MMX MMX™ tech. For 100MHz with 66MHz bus Technology use BOXPODPMT66x166/200 Pentium® PODP3V125 320 Socket 5 3.3V 100/133MHz Pentium processor- OverDrive PODP3V150 321 based systems to 125/150/166MHz Processor PODP3V166 Socket 7 Pentium® PODP5V133 273 Socket 4 5V Upgrades 60/66MHz Pentium® OverDrive processor-based systems to Processor 120/133MHz Pentium® PODP5V83 237 Socket -
Motherboard/Processor/Memory Different Kinds of SLOTS Different
Motherboard/Processor/Memory There are different slots and sockets for CPUs, and it is necessary for a motherboard to have the appropriate slot or socket for the CPU. Most sockets are square. Several precautions are taken to ensure that both the socket and the processor are indicated to ensure proper orientation. The processor is usually marked with a dot or a notch in the corner that is intended to go into the marked corner of the socket. Sockets and slots on the motherboard are as plentiful and varied as processors. The three most popular are the Socket 5 and Socket 7, and the Single Edge Contact Card (SECC). Socket 5 and Socket 7 CPU sockets are basically flat and have several rows of holes arranged in a square. The SECC connectors are of two types: slot 1 & slot 2. Design No of Pins Pin Rows Voltage Mobo Class Processor's supported Socket 1 169 3 5 Volts 486 80486SX, 80486DX, 80486DX2, 80486DX4 Socket 2 238 4 5 Volts 486 80486SX, 80486DX, 80486DX2, 80486DX4 Socket 3 237 4 5 / 3.3 Volts 486 80486SX, 80486DX, 80486DX2, 80486DX4 Socket 4 273 4 5 Volts 1st Generation Pentium Pentium 60-66, Pentium OverDrive Socket 5 320 5 3.3 Volts Pentium Pentium 75-133 MHz, Pentium OverDrive Socket 6 235 4 3.3 Volts 486 486DX4, Pentium OverDrive Design No of Pins Pin Rows Voltage Mobo Class Processor's supported Socket 7 321 5 2.5 / 3.3Volts Pentium 75-200 MHz, OverDrive, Pentium MMX Socket 8 387 5 (dual pattern) 3.1 / 3.3Volts Pentium Pro Pentium Pro OverDrive, Pentium II OverDrive Intel Slot 1 242 N/a 2.8 / 3.3Volts Pentium Pro / Pentium II Pentium II, Pentium Pro, Celeron. -
P5 (Microarchitecture)
P5 (microarchitecture) The Intel P5 Pentium family Produced From 1993 to 1999 Common manufacturer(s) • Intel Max. CPU clock rate 60 MHz to 300 MHz FSB speeds 50 MHz to 66 MHz Min. feature size 0.8pm to 0.25pm Instruction set x86 Socket(s) • Socket 4, Socket 5, Socket 7 Core name(s) P5. P54C, P54CS, P55C, Tillamook The original Pentium microprocessor was introduced on March 22, 1993.^^ Its microarchitecture, deemed P5, was Intel's fifth-generation and first superscalar x86 microarchitecture. As a direct extension of the 80486 architecture, it included dual integer pipelines, a faster FPU, wider data bus, separate code and data caches and features for further reduced address calculation latency. In 1996, the Pentium with MMX Technology (often simply referred to as Pentium MMX) was introduced with the same basic microarchitecture complemented with an MMX instruction set, larger caches, and some other enhancements. The P5 Pentium competitors included the Motorola 68060 and the PowerPC 601 as well as the SPARC, MIPS, and Alpha microprocessor families, most of which also used a superscalar in-order dual instruction pipeline configuration at some time. Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core (P54C), augmented by multithreading, 64-bit instructions, and a 16-wide vector processing unit. T31 Intel's low-powered Bonnell [4i microarchitecture employed in Atom processor cores also uses an in-order dual pipeline similar to P5. Development The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486.^ Design work started in 1989;^ the team decided to use a superscalar architecture, with on-chip cache, floating-point, and branch prediction. -
PRIME Z370-A Series 1-1 1.1.2 Motherboard Layout Chapter 1
PRIME Z370-A Series Motherboard E13271 First Edition August 2017 Copyright© 2017 ASUSTeK COMPUTER INC. All Rights Reserved. No part of this manual, including the products and software described in it, may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means, except documentation kept by the purchaser for backup purposes, without the express written permission of ASUSTeK COMPUTER INC. (“ASUS”). Product warranty or service will not be extended if: (1) the product is repaired, modified or altered, unless such repair, modification of alteration is authorized in writing by ASUS; or (2) the serial number of the product is defaced or missing. ASUS PROVIDES THIS MANUAL “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL ASUS, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF USE OR DATA, INTERRUPTION OF BUSINESS AND THE LIKE), EVEN IF ASUS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING FROM ANY DEFECT OR ERROR IN THIS MANUAL OR PRODUCT. SPECIFICATIONS AND INFORMATION CONTAINED IN THIS MANUAL ARE FURNISHED FOR INFORMATIONAL USE ONLY, AND ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE, AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY ASUS. ASUS ASSUMES NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR INACCURACIES THAT MAY APPEAR IN THIS MANUAL, INCLUDING THE PRODUCTS AND SOFTWARE DESCRIBED IN IT. -
Socket E Slot Per
Socket e Slot per CPU Socket e Slot per CPU Socket 1 Socket 2 Socket 3 Socket 4 Socket 5 Socket 6 Socket 7 e Super Socket 7 Socket 8 Slot 1 (SC242) Slot 2 (SC330) Socket 370 (PGA-370) Slot A Socket A (Socket 462) Socket 423 Socket 478 Socket 479 Socket 775 (LGA775) Socket 603 Socket 604 PAC418 PAC611 Socket 754 Socket 939 Socket 940 Socket AM2 (Socket M2) Socket 771 (LGA771) Socket F (Socket 1207) Socket S1 A partire dai processori 486, Intel progettò e introdusse i socket per CPU che, oltre a poter ospitare diversi modelli di processori, ne consentiva anche una rapida e facile sostituzione/aggiornamento. Il nuovo socket viene definito ZIF (Zero Insertion Force ) in quanto l'inserimento della CPU non richiede alcuna forza contrariamente ai socket LIF ( Low Insertion Force ) i quali, oltre a richiedere una piccola pressione per l'inserimento del chip, richiedono anche appositi tool per la sua rimozione. Il modello di socket ZIF installato sulla motherboard è, in genere, indicato sul socket stesso. Tipi diversi di socket accettano famiglie diverse di processori. Se si conosce il tipo di zoccolo montato sulla scheda madre è possibile sapere, grosso modo, che tipo di processori può ospitare. Il condizionale è d'obbligo in quanto per sapere con precisione che tipi di processore può montare una scheda madre non basta sapere solo il socket ma bisogna tenere conto anche di altri fattori come le tensioni, il FSB, le CPU supportate dal BIOS ecc. Nel caso ci si stia apprestando ad aggiornare la CPU è meglio, dunque, attenersi alle informazioni sulla compatibilità fornite dal produttore della scheda madre. -
SMBIOS) Reference 6 Specification
1 2 Document Identifier: DSP0134 3 Date: 2018-04-26 4 Version: 3.2.0 5 System Management BIOS (SMBIOS) Reference 6 Specification 7 Supersedes: 3.1.1 8 Document Class: Normative 9 Document Status: Published 10 Document Language: en-US 11 System Management BIOS (SMBIOS) Reference Specification DSP0134 12 Copyright Notice 13 Copyright © 2000, 2002, 2004–2016 Distributed Management Task Force, Inc. (DMTF). All rights 14 reserved. 15 DMTF is a not-for-profit association of industry members dedicated to promoting enterprise and systems 16 management and interoperability. Members and non-members may reproduce DMTF specifications and 17 documents, provided that correct attribution is given. As DMTF specifications may be revised from time to 18 time, the particular version and release date should always be noted. 19 Implementation of certain elements of this standard or proposed standard may be subject to third party 20 patent rights, including provisional patent rights (herein "patent rights"). DMTF makes no representations 21 to users of the standard as to the existence of such rights, and is not responsible to recognize, disclose, 22 or identify any or all such third party patent right, owners or claimants, nor for any incomplete or 23 inaccurate identification or disclosure of such rights, owners or claimants. DMTF shall have no liability to 24 any party, in any manner or circumstance, under any legal theory whatsoever, for failure to recognize, 25 disclose, or identify any such third party patent rights, or for such party’s reliance on the standard or 26 incorporation thereof in its product, protocols or testing procedures. -
HP Z200 Workstation
HP Z200 Workstation Maintenance and Service Guide Copyright Information Warranty Trademark Credits © Copyright 2010 Hewlett-Packard Hewlett-Packard Company shall not be liable Microsoft, Windows, and XP are U.S. Development Company, L.P. for technical or editorial errors or omissions registered trademarks of Microsoft contained herein or for incidental or Corporation in the U.S. and other countries. consequential damages in connection with the furnishing, performance, or use of this Intel is a trademark of Intel Corporation in the material. The information in this document is U.S. and other countries and are used under provided “as is” without warranty of any kind, license. including, but not limited to, the implied ENERGY STAR is a U.S. registered mark of warranties of merchantability and fitness for the United States Environmental Protection a particular purpose, and is subject to change without notice. The warranties for HP Agency. products are set forth in the express limited 597849–001 warranty statements accompanying such products. First Edition, February 2010 Nothing herein should be construed as constituting and additional warranty. This document contains proprietary information that is protected by copyright. No part of this document may be photocopied, reproduced, or translated to another language without the prior written consent of Hewlett-Packard Company. About this guide This guide provides service and maintenance information for the HP Z200 Workstation. It includes these topics: Guide topics Product overview on page 1 Setting