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Embedded Systems EMBEDDED SYSTEMS Hardware, Design, and Implementation Edited by Krzysztof Iniewski CMOS Emerging Technologies Research A JOHN WILEY & SONS, INC., PUBLICATION EMBEDDED SYSTEMS EMBEDDED SYSTEMS Hardware, Design, and Implementation Edited by Krzysztof Iniewski CMOS Emerging Technologies Research A JOHN WILEY & SONS, INC., PUBLICATION Copyright © 2013 by John Wiley & Sons, Inc. All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permissions. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data: Iniewski, Krzysztof. Embedded systems : hardware, design, and implementation / by Krzysztof Iniewski. pages cm Includes bibliographical references and index. ISBN 978-1-118-35215-1 (hardback) 1. Embedded computer systems. I. Title. TK7895.E42I526 2012 006.2'2–dc23 2012034412 Printed in the United States of America 10 9 8 7 6 5 4 3 2 1 CONTENTS Preface xv Contributors xvii 1 Low Power Multicore Processors for Embedded Systems 1 Fumio Arakawa 1.1 Multicore Chip with Highly Efficient Cores 1 1.2 SuperH™ RISC Engine Family (SH) Processor Cores 5 1.2.1 History of SH Processor Cores 5 1.2.2 Highly Efficient ISA 7 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture 8 1.3 SH-X: A Highly Efficient CPU Core 9 1.3.1 Microarchitecture Selections 11 1.3.2 Improved Superpipeline Structure 12 1.3.3 Branch Prediction and Out-of-Order Branch Issue 13 1.3.4 Low Power Technologies 15 1.3.5 Performance and Efficiency Evaluations 17 1.4 SH-X FPU: A Highly Efficient FPU 20 1.4.1 FPU Architecture of SH Processors 21 1.4.2 Implementation of SH-X FPU 24 1.4.3 Performance Evaluations with 3D Graphics Benchmark 29 1.5 SH-X2: Frequency and Efficiency Enhanced Core 33 1.5.1 Frequency Enhancement 33 1.5.2 Low Power Technologies 34 1.6 SH-X3: Multicore Architecture Extension 34 1.6.1 SH-X3 Core Specifications 34 1.6.2 Symmetric and Asymmetric Multiprocessor Support 35 1.6.3 Core Snoop Sequence Optimization 36 1.6.4 Dynamic Power Management 39 1.6.5 RP-1 Prototype Chip 40 1.6.5.1 RP-1 Specifications 40 1.6.5.2 Chip Integration and Evaluations 41 v vi CONTENTS 1.6.6 RP-2 Prototype Chip 43 1.6.6.1 RP-2 Specifications 43 1.6.6.2 Power Domain and Partial Power Off 43 1.6.6.3 Synchronization Support Hardware 45 1.6.6.4 Chip Integration and Evaluations 47 1.7 SH-X4: ISA and Address Space Extension 47 1.7.1 SH-X4 Core Specifications 48 1.7.2 Efficient ISA Extension 49 1.7.3 Address Space Extension 52 1.7.4 Data Transfer Unit 53 1.7.5 RP-X Prototype Chip 54 1.7.5.1 RP-X Specifications 54 1.7.5.2 Chip Integration and Evaluations 56 References 57 2 Special-Purpose Hardware for Computational Biology 61 Siddharth Srinivasan 2.1 Molecular Dynamics Simulations on Graphics Processing Units 62 2.1.1 Molecular Mechanics Force Fields 63 2.1.1.1 Bond Term 63 2.1.1.2 Angle Term 63 2.1.1.3 Torsion Term 63 2.1.1.4 Van der Waal’s Term 64 2.1.1.5 Coulomb Term 65 2.1.2 Graphics Processing Units for MD Simulations 65 2.1.2.1 GPU Architecture Case Study: NVIDIA Fermi 66 2.1.2.2 Force Computation on GPUs 69 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations 72 2.2.1 High-Throughput Interaction Subsystem 72 2.2.1.1 Pairwise Point Interaction Modules 74 2.2.1.2 Particle Distribution Network 74 2.2.2 Hardware Description of the Flexible Subsystem 75 2.2.3 Performance and Conclusions 77 2.3 Quantum MC Applications on Field-Programmable Gate Arrays 77 2.3.1 Energy Computation and WF Kernels 78 2.3.2 Hardware Architecture 79 2.3.2.1 Binning Scheme 79 CONTENTS vii 2.3.3 PE and WF Computation Kernels 80 2.3.3.1 Distance Computation Unit (DCU) 81 2.3.3.2 Calculate Function Unit and Accumulate Function Kernels 81 2.4 Conclusions and Future Directions 82 References 82 3 Embedded GPU Design 85 Byeong-Gyu Nam and Hoi-Jun Yoo 3.1 Introduction 85 3.2 System Architecture 86 3.3 Graphics Modules Design 88 3.3.1 RISC Processor 88 3.3.2 Geometry Processor 89 3.3.2.1 Geometry Transformation 90 3.3.2.2 Unified Multifunction Unit 90 3.3.2.3 Vertex Cache 91 3.3.3 Rendering Engine 92 3.4 System Power Management 95 3.4.1 Multiple Power-Domain Management 95 3.4.2 Power Management Unit 98 3.5 Implementation Results 99 3.5.1 Chip Implementation 99 3.5.2 Comparisons 100 3.6 Conclusion 102 References 105 4 Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors 107 Tareq Hasan Khan and Khan Wahid 4.1 Introduction 107 4.2 The DVP Interface 108 4.3 The iBRIDGE-BB Architecture 109 4.3.1 Configuring the iBRIDGE-BB 110 4.3.2 Operation of the iBRIDGE-BB 110 4.3.3 Description of Internal Blocks 112 4.3.3.1 Sensor Control 112 4.3.3.2 I2C 112 4.3.3.3 Memory Addressing and Control 114 4.3.3.4 Random Access Memory (RAM) 114 4.3.3.5 Column and Row Calculator 115 viii CONTENTS 4.3.3.6 Physical Memory Address Generator 115 4.3.3.7 Clock Generator 116 4.4 Hardware Implementation 116 4.4.1 Verification in Field-Programmable Gate Array 116 4.4.2 Application in Image Compression 118 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis 121 4.5 Conclusion 123 Acknowledgments 123 References 125 5 Embedded Computing Systems on FPGAs 127 Lesley Shannon 5.1 FPGA Architecture 128 5.2 FPGA Configuration Technology 129 5.2.1 Traditional SRAM-Based FPGAs 130 5.2.1.1 DPR 130 5.2.1.2 Challenges for SRAM-Based Embedded Computing System 131 5.2.1.3 Other SRAM-Based FPGAs 132 5.2.2 Flash-Based FPGAs 133 5.3 Software Support 133 5.3.1 Synthesis and Design Tools 134 5.3.2 OSs Support 135 5.4 Final Summary of Challenges and Opportunities for Embedded Computing Design on FPGAs 135 References 136 6 FPGA-Based Emulation Support for Design Space Exploration 139 Paolo Meloni, Simone Secchi, and Luigi Raffo 6.1 Introduction 139 6.2 State of the Art 140 6.2.1 FPGA-Only Emulation Techniques 141 6.2.2 FPGA-Based Cosimulation Techniques 142 6.2.3 FPGA-Based Emulation for DSE Purposes: A Limiting Factor 144 6.3 A Tool for Energy-Aware FPGA-Based Emulation: The MADNESS Project Experience 144 6.3.1 Models for Prospective ASIC Implementation 146 6.3.2 Performance Extraction 147 CONTENTS ix 6.4 Enabling FPGA-Based DSE: Runtime-Reconfigurable Emulators 147 6.4.1 Enabling Fast NoC Topology Selection 148 6.4.1.1 WCT Definition Algorithm 148 6.4.1.2 The Extended Topology Builder 151 6.4.1.3 Hardware Support for Runtime Reconfiguration 152 6.4.1.4 Software Support for Runtime Reconfiguration 153 6.4.2 Enabling Fast ASIP Configuration Selection 154 6.4.2.1 The Reference Design Flow 155 6.4.2.2 The Extended Design Flow 156 6.4.2.3 The WCC Synthesis Algorithm 157 6.4.2.4 Hardware Support for Runtime Reconfiguration 158 6.4.2.5 Software Support for Runtime Reconfiguration 161 6.5 Use Cases 161 6.5.1 Hardware Overhead Due to Runtime Configurability 164 References 166 7 FPGA Coprocessing Solution for Real-Time Protein Identification Using Tandem Mass Spectrometry 169 Daniel Coca, István Bogdán, and Robert J.
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